Context Navigation

source: branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper.cpp @ 330

Last change on this file since 330 was 330, checked in by joannou, 11 years ago
Commented debug in dspin_local_ring_fast_c Added test on plen value in case of LL command in mem cache (vci_mem_cache and vci_mem_cache_dspin_coherence) Removed coherence handling in *CACHE_MISS_DATA_UPDT states, in vci_cc_vcache_wrapper_dspin_coherence component
File size: 227.2 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CLEANUP 0
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_INVAL",
65	"ICACHE_CC_UPDT",
66	"ICACHE_CC_BROADCAST",
67	"ICACHE_CC_SEND_WAIT",
68	};
69
70	const char *dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IT_INVAL",
90	"DCACHE_XTN_DC_FLUSH",
91	"DCACHE_XTN_DC_FLUSH_GO",
92	"DCACHE_XTN_DC_INVAL_VA",
93	"DCACHE_XTN_DC_INVAL_PA",
94	"DCACHE_XTN_DC_INVAL_END",
95	"DCACHE_XTN_DC_INVAL_GO",
96	"DCACHE_XTN_DT_INVAL",
97
98	"DCACHE_DIRTY_PTE_GET",
99	"DCACHE_DIRTY_WAIT",
100
101	"DCACHE_MISS_SELECT",
102	"DCACHE_MISS_CLEAN",
103	"DCACHE_MISS_WAIT",
104	"DCACHE_MISS_DATA_UPDT",
105	"DCACHE_MISS_DIR_UPDT",
106
107	"DCACHE_UNC_WAIT",
108	"DCACHE_LL_WAIT",
109	"DCACHE_SC_WAIT",
110
111	"DCACHE_CC_CHECK",
112	"DCACHE_CC_INVAL",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_BROADCAST",
115	"DCACHE_CC_SEND_WAIT",
116
117	"DCACHE_INVAL_TLB_SCAN",
118	};
119
120	const char *cmd_fsm_state_str[] = {
121	"CMD_IDLE",
122	"CMD_INS_MISS",
123	"CMD_INS_UNC",
124	"CMD_DATA_MISS",
125	"CMD_DATA_UNC",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char *rsp_fsm_state_str[] = {
133	"RSP_IDLE",
134	"RSP_INS_MISS",
135	"RSP_INS_UNC",
136	"RSP_DATA_MISS",
137	"RSP_DATA_UNC",
138	"RSP_DATA_LL",
139	"RSP_DATA_WRITE",
140	};
141
142	const char *cc_receive_fsm_state_str[] = {
143	"CC_RECEIVE_IDLE",
144	"CC_RECEIVE_CLACK",
145	"CC_RECEIVE_BRDCAST_HEADER",
146	"CC_RECEIVE_BRDCAST_NLINE",
147	"CC_RECEIVE_INVAL_HEADER",
148	"CC_RECEIVE_INVAL_NLINE",
149	"CC_RECEIVE_UPDT_HEADER",
150	"CC_RECEIVE_UPDT_NLINE",
151	"CC_RECEIVE_UPDT_DATA",
152	};
153
154	const char *cc_send_fsm_state_str[] = {
155	"CC_SEND_IDLE",
156	"CC_SEND_CLEANUP_1",
157	"CC_SEND_CLEANUP_2",
158	"CC_SEND_MULTI_ACK",
159	};
160	}
161
162	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t>
163
164	using soclib::common::uint32_log2;
165
166	/////////////////////////////////
167	tmpl(/**/)::VciCcVCacheWrapper(
168	sc_module_name name,
169	int proc_id,
170	const soclib::common::MappingTable &mtd,
171	const soclib::common::MappingTable &mtc,
172	const soclib::common::IntTab &initiator_index_d,
173	const soclib::common::IntTab &initiator_index_c,
174	const soclib::common::IntTab &target_index_c,
175	size_t itlb_ways,
176	size_t itlb_sets,
177	size_t dtlb_ways,
178	size_t dtlb_sets,
179	size_t icache_ways,
180	size_t icache_sets,
181	size_t icache_words,
182	size_t dcache_ways,
183	size_t dcache_sets,
184	size_t dcache_words,
185	size_t wbuf_nlines,
186	size_t wbuf_nwords,
187	size_t x_width,
188	size_t y_width,
189	uint32_t memory_cache_local_id,
190	uint32_t max_frozen_cycles,
191	uint32_t debug_start_cycle,
192	bool debug_ok)
193	: soclib::caba::BaseModule(name),
194
195	p_clk("clk"),
196	p_resetn("resetn"),
197	p_vci_ini_d("vci_ini_d"),
198	p_dspin_in("dspin_in"),
199	p_dspin_out("dspin_out"),
200
201	m_cacheability_table(mtd.getCacheabilityTable()),
202	m_segment(mtc.getSegment(target_index_c)),
203	m_srcid_d(mtd.indexForId(initiator_index_d)),
204	m_srcid_c(mtc.indexForId(initiator_index_c)),
205
206	m_itlb_ways(itlb_ways),
207	m_itlb_sets(itlb_sets),
208
209	m_dtlb_ways(dtlb_ways),
210	m_dtlb_sets(dtlb_sets),
211
212	m_icache_ways(icache_ways),
213	m_icache_sets(icache_sets),
214	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
215	m_icache_words(icache_words),
216
217	m_dcache_ways(dcache_ways),
218	m_dcache_sets(dcache_sets),
219	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
220	m_dcache_words(dcache_words),
221
222	m_x_width(x_width),
223	m_y_width(y_width),
224
225	m_memory_cache_local_id(memory_cache_local_id),
226	m_proc_id(proc_id),
227	m_max_frozen_cycles(max_frozen_cycles),
228	m_paddr_nbits(vci_param::N),
229
230	m_debug_start_cycle(debug_start_cycle),
231	m_debug_ok(debug_ok),
232
233	r_mmu_ptpr("r_mmu_ptpr"),
234	r_mmu_mode("r_mmu_mode"),
235	r_mmu_word_lo("r_mmu_word_lo"),
236	r_mmu_word_hi("r_mmu_word_hi"),
237	r_mmu_ibvar("r_mmu_ibvar"),
238	r_mmu_dbvar("r_mmu_dbvar"),
239	r_mmu_ietr("r_mmu_ietr"),
240	r_mmu_detr("r_mmu_detr"),
241
242	r_icache_fsm("r_icache_fsm"),
243	r_icache_fsm_save("r_icache_fsm_save"),
244	r_icache_vci_paddr("r_icache_vci_paddr"),
245	r_icache_vaddr_save("r_icache_vaddr_save"),
246
247	r_icache_miss_way("r_icache_miss_way"),
248	r_icache_miss_set("r_icache_miss_set"),
249	r_icache_miss_word("r_icache_miss_word"),
250	r_icache_miss_inval("r_icache_miss_inval"),
251	r_icache_miss_clack("r_icache_miss_clack"),
252
253	r_icache_cc_way("r_icache_cc_way"),
254	r_icache_cc_set("r_icache_cc_set"),
255	r_icache_cc_word("r_icache_cc_word"),
256	r_icache_cc_need_write("r_icache_cc_need_write"),
257
258	r_icache_flush_count("r_icache_flush_count"),
259
260	r_icache_miss_req("r_icache_miss_req"),
261	r_icache_unc_req("r_icache_unc_req"),
262
263	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
264	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
265
266	r_icache_cc_send_req("r_icache_cc_send_req"),
267	r_icache_cc_send_type("r_icache_cc_send_type"),
268	r_icache_cc_send_nline("r_icache_cc_send_nline"),
269	r_icache_cc_send_way("r_icache_cc_send_way"),
270	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
271
272	r_dcache_fsm("r_dcache_fsm"),
273	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
274	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
275
276	r_dcache_wbuf_req("r_dcache_wbuf_req"),
277	r_dcache_updt_req("r_dcache_updt_req"),
278	r_dcache_save_vaddr("r_dcache_save_vaddr"),
279	r_dcache_save_wdata("r_dcache_save_wdata"),
280	r_dcache_save_be("r_dcache_save_be"),
281	r_dcache_save_paddr("r_dcache_save_paddr"),
282	r_dcache_save_cacheable("r_dcache_save_cacheable"),
283	r_dcache_save_cache_way("r_dcache_save_cache_way"),
284	r_dcache_save_cache_set("r_dcache_save_cache_set"),
285	r_dcache_save_cache_word("r_dcache_save_cache_word"),
286
287	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
288	r_dcache_dirty_way("r_dcache_dirty_way"),
289	r_dcache_dirty_set("r_dcache_dirty_set"),
290
291	r_dcache_vci_paddr("r_dcache_vci_paddr"),
292	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
293	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
294	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
295	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
296	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
297	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
298	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
299	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
300	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
301
302	r_dcache_xtn_way("r_dcache_xtn_way"),
303	r_dcache_xtn_set("r_dcache_xtn_set"),
304
305	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
306
307	r_dcache_miss_type("r_dcache_miss_type"),
308	r_dcache_miss_word("r_dcache_miss_word"),
309	r_dcache_miss_way("r_dcache_miss_way"),
310	r_dcache_miss_set("r_dcache_miss_set"),
311	r_dcache_miss_inval("r_dcache_miss_inval"),
312
313	r_dcache_cc_way("r_dcache_cc_way"),
314	r_dcache_cc_set("r_dcache_cc_set"),
315	r_dcache_cc_word("r_dcache_cc_word"),
316	r_dcache_cc_need_write("r_dcache_cc_need_write"),
317
318	r_dcache_flush_count("r_dcache_flush_count"),
319
320	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
321
322	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
323	r_dcache_tlb_ins("r_dcache_tlb_ins"),
324	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
325	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
326	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
327	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
328	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
329	r_dcache_tlb_way("r_dcache_tlb_way"),
330	r_dcache_tlb_set("r_dcache_tlb_set"),
331
332	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
333	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
334
335	r_dcache_xtn_req("r_dcache_xtn_req"),
336	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
337
338	r_dcache_cc_send_req("r_dcache_cc_send_req"),
339	r_dcache_cc_send_type("r_dcache_cc_send_type"),
340	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
341	r_dcache_cc_send_way("r_dcache_cc_send_way"),
342	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
343
344	r_vci_cmd_fsm("r_vci_cmd_fsm"),
345	r_vci_cmd_min("r_vci_cmd_min"),
346	r_vci_cmd_max("r_vci_cmd_max"),
347	r_vci_cmd_cpt("r_vci_cmd_cpt"),
348	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
349
350	r_vci_rsp_fsm("r_vci_rsp_fsm"),
351	r_vci_rsp_cpt("r_vci_rsp_cpt"),
352	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
353	r_vci_rsp_data_error("r_vci_rsp_data_error"),
354	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
355	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
356
357	r_cc_send_fsm("r_cc_send_fsm"),
358	r_cc_send_last_client("r_cc_send_last_client"),
359
360	r_cc_receive_fsm("r_cc_receive_fsm"),
361	r_cc_receive_data_ins("r_cc_receive_data_ins"),
362	r_cc_receive_word_idx("r_cc_receive_word_idx"),
363	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
364	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
365	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
366
367	r_cc_receive_icache_req("r_cc_receive_icache_req"),
368	r_cc_receive_icache_type("r_cc_receive_icache_type"),
369	r_cc_receive_icache_way("r_cc_receive_icache_way"),
370	r_cc_receive_icache_set("r_cc_receive_icache_set"),
371	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
372	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
373
374	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
375	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
376	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
377	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
378	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
379	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
380
381	r_iss(this->name(), proc_id),
382	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
383	r_icache("icache", icache_ways, icache_sets, icache_words),
384	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
385	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
386	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
387	{
388	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
389	"Need more PLEN bits.");
390
391	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
392	"Need more TRDID bits.");
393
394	assert( (icache_words == dcache_words) and
395	"icache_words and dcache_words parameters must be equal");
396
397	assert( (itlb_sets == dtlb_sets) and
398	"itlb_sets and dtlb_sets parameters must be etqual");
399
400	assert( (itlb_ways == dtlb_ways) and
401	"itlb_ways and dtlb_ways parameters must be etqual");
402
403	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
404	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
405	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
406	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
407	(uint32_log2(m_icache_words<<2));
408
409	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
410
411	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
412	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
413
414	SC_METHOD(transition);
415	dont_initialize();
416	sensitive << p_clk.pos();
417
418	SC_METHOD(genMoore);
419	dont_initialize();
420	sensitive << p_clk.neg();
421
422	typename iss_t::CacheInfo cache_info;
423	cache_info.has_mmu = true;
424	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
425	cache_info.icache_assoc = icache_ways;
426	cache_info.icache_n_lines = icache_sets;
427	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
428	cache_info.dcache_assoc = dcache_ways;
429	cache_info.dcache_n_lines = dcache_sets;
430	r_iss.setCacheInfo(cache_info);
431	}
432
433	/////////////////////////////////////
434	tmpl(/**/)::~VciCcVCacheWrapper()
435	/////////////////////////////////////
436	{
437	delete [] r_dcache_in_tlb;
438	delete [] r_dcache_contains_ptd;
439	}
440
441	////////////////////////
442	tmpl(void)::print_cpi()
443	////////////////////////
444	{
445	std::cout << name() << " CPI = "
446	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
447	}
448
449	////////////////////////////////////
450	tmpl(void)::print_trace(size_t mode)
451	////////////////////////////////////
452	{
453	// b0 : write buffer trace
454	// b1 : write buffer verbose
455	// b2 : dcache trace
456	// b3 : icache trace
457	// b4 : dtlb trace
458	// b5 : itlb trace
459
460	std::cout << std::dec << "PROC " << name() << std::endl;
461
462	std::cout << " " << m_ireq << std::endl;
463	std::cout << " " << m_irsp << std::endl;
464	std::cout << " " << m_dreq << std::endl;
465	std::cout << " " << m_drsp << std::endl;
466
467	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
468	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
469	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
470	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
471	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
472	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()];
473	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
474	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
475	std::cout << std::endl;
476
477	if(mode & 0x01)
478	{
479	r_wbuf.printTrace((mode>>1)&1);
480	}
481	if(mode & 0x04)
482	{
483	std::cout << " Data Cache" << std::endl;
484	r_dcache.printTrace();
485	}
486	if(mode & 0x08)
487	{
488	std::cout << " Instruction Cache" << std::endl;
489	r_icache.printTrace();
490	}
491	if(mode & 0x10)
492	{
493	std::cout << " Data TLB" << std::endl;
494	r_dtlb.printTrace();
495	}
496	if(mode & 0x20)
497	{
498	std::cout << " Instruction TLB" << std::endl;
499	r_itlb.printTrace();
500	}
501	}
502
503	//////////////////////////////////////////
504	tmpl(void)::cache_monitor( paddr_t addr )
505	//////////////////////////////////////////
506	{
507	size_t cache_way;
508	size_t cache_set;
509	size_t cache_word;
510	uint32_t cache_rdata;
511	bool cache_hit = r_dcache.read_neutral( addr,
512	&cache_rdata,
513	&cache_way,
514	&cache_set,
515	&cache_word );
516	bool icache_hit = r_icache.read_neutral( addr,
517	&cache_rdata,
518	&cache_way,
519	&cache_set,
520	&cache_word );
521	if ( cache_hit != m_debug_previous_hit )
522	{
523	std::cout << "PROC " << name()
524	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
525	<< " for adresse " << std::hex << addr
526	<< " / HIT = " << std::dec << cache_hit << std::endl;
527	m_debug_previous_hit = cache_hit;
528	}
529	if ( icache_hit != m_idebug_previous_hit )
530	{
531	std::cout << "PROC " << name()
532	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
533	<< " for adresse " << std::hex << addr
534	<< " / HIT = " << icache_hit << std::endl;
535	m_idebug_previous_hit = icache_hit;
536	}
537	}
538
539	/*
540	////////////////////////
541	tmpl(void)::print_stats()
542	////////////////////////
543	{
544	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
545	std::cout << name() << std::endl
546	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
547	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
548	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
549	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
550	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
551	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
552	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
553	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
554	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
555	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
556	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
557	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
558	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
559	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
560	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
561	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
562	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
563	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
564	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
565	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
566	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
567	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
568	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
569	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
570	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
571	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
572	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
573	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
574	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
575	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
576	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
577	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
578	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
579	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
580	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
581	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
582	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
583	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
584	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
585	}
586
587	////////////////////////
588	tmpl(void)::clear_stats()
589	////////////////////////
590	{
591	m_cpt_dcache_data_read = 0;
592	m_cpt_dcache_data_write = 0;
593	m_cpt_dcache_dir_read = 0;
594	m_cpt_dcache_dir_write = 0;
595	m_cpt_icache_data_read = 0;
596	m_cpt_icache_data_write = 0;
597	m_cpt_icache_dir_read = 0;
598	m_cpt_icache_dir_write = 0;
599
600	m_cpt_frz_cycles = 0;
601	m_cpt_dcache_frz_cycles = 0;
602	m_cpt_total_cycles = 0;
603
604	m_cpt_read = 0;
605	m_cpt_write = 0;
606	m_cpt_data_miss = 0;
607	m_cpt_ins_miss = 0;
608	m_cpt_unc_read = 0;
609	m_cpt_write_cached = 0;
610	m_cpt_ins_read = 0;
611
612	m_cost_write_frz = 0;
613	m_cost_data_miss_frz = 0;
614	m_cost_unc_read_frz = 0;
615	m_cost_ins_miss_frz = 0;
616
617	m_cpt_imiss_transaction = 0;
618	m_cpt_dmiss_transaction = 0;
619	m_cpt_unc_transaction = 0;
620	m_cpt_write_transaction = 0;
621	m_cpt_icache_unc_transaction = 0;
622
623	m_cost_imiss_transaction = 0;
624	m_cost_dmiss_transaction = 0;
625	m_cost_unc_transaction = 0;
626	m_cost_write_transaction = 0;
627	m_cost_icache_unc_transaction = 0;
628	m_length_write_transaction = 0;
629
630	m_cpt_ins_tlb_read = 0;
631	m_cpt_ins_tlb_miss = 0;
632	m_cpt_ins_tlb_update_acc = 0;
633
634	m_cpt_data_tlb_read = 0;
635	m_cpt_data_tlb_miss = 0;
636	m_cpt_data_tlb_update_acc = 0;
637	m_cpt_data_tlb_update_dirty = 0;
638	m_cpt_ins_tlb_hit_dcache = 0;
639	m_cpt_data_tlb_hit_dcache = 0;
640	m_cpt_ins_tlb_occup_cache = 0;
641	m_cpt_data_tlb_occup_cache = 0;
642
643	m_cost_ins_tlb_miss_frz = 0;
644	m_cost_data_tlb_miss_frz = 0;
645	m_cost_ins_tlb_update_acc_frz = 0;
646	m_cost_data_tlb_update_acc_frz = 0;
647	m_cost_data_tlb_update_dirty_frz = 0;
648	m_cost_ins_tlb_occup_cache_frz = 0;
649	m_cost_data_tlb_occup_cache_frz = 0;
650
651	m_cpt_itlbmiss_transaction = 0;
652	m_cpt_itlb_ll_transaction = 0;
653	m_cpt_itlb_sc_transaction = 0;
654	m_cpt_dtlbmiss_transaction = 0;
655	m_cpt_dtlb_ll_transaction = 0;
656	m_cpt_dtlb_sc_transaction = 0;
657	m_cpt_dtlb_ll_dirty_transaction = 0;
658	m_cpt_dtlb_sc_dirty_transaction = 0;
659
660	m_cost_itlbmiss_transaction = 0;
661	m_cost_itlb_ll_transaction = 0;
662	m_cost_itlb_sc_transaction = 0;
663	m_cost_dtlbmiss_transaction = 0;
664	m_cost_dtlb_ll_transaction = 0;
665	m_cost_dtlb_sc_transaction = 0;
666	m_cost_dtlb_ll_dirty_transaction = 0;
667	m_cost_dtlb_sc_dirty_transaction = 0;
668
669	m_cpt_cc_update_data = 0;
670	m_cpt_cc_inval_ins = 0;
671	m_cpt_cc_inval_data = 0;
672	m_cpt_cc_broadcast = 0;
673
674	m_cost_updt_data_frz = 0;
675	m_cost_inval_ins_frz = 0;
676	m_cost_inval_data_frz = 0;
677	m_cost_broadcast_frz = 0;
678
679	m_cpt_cc_cleanup_data = 0;
680	m_cpt_cc_cleanup_ins = 0;
681	}
682
683	*/
684
685	/////////////////////////
686	tmpl(void)::transition()
687	/////////////////////////
688	{
689	#define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
690	if ( not p_resetn.read() )
691	{
692	r_iss.reset();
693	r_wbuf.reset();
694	r_icache.reset();
695	r_dcache.reset();
696	r_itlb.reset();
697	r_dtlb.reset();
698
699	r_dcache_fsm = DCACHE_IDLE;
700	r_icache_fsm = ICACHE_IDLE;
701	r_vci_cmd_fsm = CMD_IDLE;
702	r_vci_rsp_fsm = RSP_IDLE;
703	r_cc_receive_fsm = CC_RECEIVE_IDLE;
704	r_cc_send_fsm = CC_SEND_IDLE;
705
706	// reset dcache directory extension
707	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
708	{
709	r_dcache_in_tlb[i] = false;
710	r_dcache_contains_ptd[i] = false;
711	}
712
713	// Response FIFOs and cleanup buffer
714	r_vci_rsp_fifo_icache.init();
715	r_vci_rsp_fifo_dcache.init();
716
717	// ICACHE & DCACHE activated
718	r_mmu_mode = 0x3;
719
720	// No request from ICACHE FSM to CMD FSM
721	r_icache_miss_req = false;
722	r_icache_unc_req = false;
723
724	// No request from ICACHE_FSM to DCACHE FSM
725	r_icache_tlb_miss_req = false;
726
727	// No request from ICACHE_FSM to CC_SEND FSM
728	r_icache_cc_send_req = false;
729
730	// No pending write in pipeline
731	r_dcache_wbuf_req = false;
732	r_dcache_updt_req = false;
733
734	// No request from DCACHE_FSM to CMD_FSM
735	r_dcache_vci_miss_req = false;
736	r_dcache_vci_unc_req = false;
737	r_dcache_vci_cas_req = false;
738	r_dcache_vci_ll_req = false;
739	r_dcache_vci_sc_req = false;
740
741	// No uncacheable write pending
742	r_dcache_pending_unc_write = false;
743
744	// No processor XTN request pending
745	r_dcache_xtn_req = false;
746
747	// No request from DCACHE FSM to CC_SEND FSM
748	r_dcache_cc_send_req = false;
749
750	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
751	r_cc_receive_icache_req = false;
752	r_cc_receive_dcache_req = false;
753
754	// last cc_send client was dcache
755	r_cc_send_last_client = false;
756
757	// No pending cleanup after a replacement
758	r_icache_miss_clack = false;
759	r_dcache_miss_clack = false;
760
761	// No signalisation of a coherence request matching a pending miss
762	r_icache_miss_inval = false;
763	r_dcache_miss_inval = false;
764
765	// No signalisation of errors
766	r_vci_rsp_ins_error = false;
767	r_vci_rsp_data_error = false;
768
769	// Debug variables
770	m_debug_previous_hit = false;
771	m_idebug_previous_hit = false;
772	m_debug_dcache_fsm = false;
773	m_debug_icache_fsm = false;
774
775	// activity counters
776	m_cpt_dcache_data_read = 0;
777	m_cpt_dcache_data_write = 0;
778	m_cpt_dcache_dir_read = 0;
779	m_cpt_dcache_dir_write = 0;
780	m_cpt_icache_data_read = 0;
781	m_cpt_icache_data_write = 0;
782	m_cpt_icache_dir_read = 0;
783	m_cpt_icache_dir_write = 0;
784
785	m_cpt_frz_cycles = 0;
786	m_cpt_total_cycles = 0;
787	m_cpt_stop_simulation = 0;
788
789	m_cpt_data_miss = 0;
790	m_cpt_ins_miss = 0;
791	m_cpt_unc_read = 0;
792	m_cpt_write_cached = 0;
793	m_cpt_ins_read = 0;
794
795	m_cost_write_frz = 0;
796	m_cost_data_miss_frz = 0;
797	m_cost_unc_read_frz = 0;
798	m_cost_ins_miss_frz = 0;
799
800	m_cpt_imiss_transaction = 0;
801	m_cpt_dmiss_transaction = 0;
802	m_cpt_unc_transaction = 0;
803	m_cpt_write_transaction = 0;
804	m_cpt_icache_unc_transaction = 0;
805
806	m_cost_imiss_transaction = 0;
807	m_cost_dmiss_transaction = 0;
808	m_cost_unc_transaction = 0;
809	m_cost_write_transaction = 0;
810	m_cost_icache_unc_transaction = 0;
811	m_length_write_transaction = 0;
812
813	m_cpt_ins_tlb_read = 0;
814	m_cpt_ins_tlb_miss = 0;
815	m_cpt_ins_tlb_update_acc = 0;
816
817	m_cpt_data_tlb_read = 0;
818	m_cpt_data_tlb_miss = 0;
819	m_cpt_data_tlb_update_acc = 0;
820	m_cpt_data_tlb_update_dirty = 0;
821	m_cpt_ins_tlb_hit_dcache = 0;
822	m_cpt_data_tlb_hit_dcache = 0;
823	m_cpt_ins_tlb_occup_cache = 0;
824	m_cpt_data_tlb_occup_cache = 0;
825
826	m_cost_ins_tlb_miss_frz = 0;
827	m_cost_data_tlb_miss_frz = 0;
828	m_cost_ins_tlb_update_acc_frz = 0;
829	m_cost_data_tlb_update_acc_frz = 0;
830	m_cost_data_tlb_update_dirty_frz = 0;
831	m_cost_ins_tlb_occup_cache_frz = 0;
832	m_cost_data_tlb_occup_cache_frz = 0;
833
834	m_cpt_ins_tlb_inval = 0;
835	m_cpt_data_tlb_inval = 0;
836	m_cost_ins_tlb_inval_frz = 0;
837	m_cost_data_tlb_inval_frz = 0;
838
839	m_cpt_cc_broadcast = 0;
840
841	m_cost_updt_data_frz = 0;
842	m_cost_inval_ins_frz = 0;
843	m_cost_inval_data_frz = 0;
844	m_cost_broadcast_frz = 0;
845
846	m_cpt_cc_cleanup_data = 0;
847	m_cpt_cc_cleanup_ins = 0;
848
849	m_cpt_itlbmiss_transaction = 0;
850	m_cpt_itlb_ll_transaction = 0;
851	m_cpt_itlb_sc_transaction = 0;
852	m_cpt_dtlbmiss_transaction = 0;
853	m_cpt_dtlb_ll_transaction = 0;
854	m_cpt_dtlb_sc_transaction = 0;
855	m_cpt_dtlb_ll_dirty_transaction = 0;
856	m_cpt_dtlb_sc_dirty_transaction = 0;
857
858	m_cost_itlbmiss_transaction = 0;
859	m_cost_itlb_ll_transaction = 0;
860	m_cost_itlb_sc_transaction = 0;
861	m_cost_dtlbmiss_transaction = 0;
862	m_cost_dtlb_ll_transaction = 0;
863	m_cost_dtlb_sc_transaction = 0;
864	m_cost_dtlb_ll_dirty_transaction = 0;
865	m_cost_dtlb_sc_dirty_transaction = 0;
866	/*
867	m_cpt_dcache_frz_cycles = 0;
868	m_cpt_read = 0;
869	m_cpt_write = 0;
870	m_cpt_cc_update_data = 0;
871	m_cpt_cc_inval_ins = 0;
872	m_cpt_cc_inval_data = 0;
873	*/
874
875	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
876	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
877	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
878	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
879
880	// init the llsc reservation buffer
881	r_dcache_llsc_valid = false;
882
883	return;
884	}
885
886	// Response FIFOs default values
887	bool vci_rsp_fifo_icache_get = false;
888	bool vci_rsp_fifo_icache_put = false;
889	uint32_t vci_rsp_fifo_icache_data = 0;
890
891	bool vci_rsp_fifo_dcache_get = false;
892	bool vci_rsp_fifo_dcache_put = false;
893	uint32_t vci_rsp_fifo_dcache_data = 0;
894
895	// updt fifo
896	bool cc_receive_updt_fifo_get = false;
897	bool cc_receive_updt_fifo_put = false;
898	uint32_t cc_receive_updt_fifo_be = 0;
899	uint32_t cc_receive_updt_fifo_data = 0;
900	bool cc_receive_updt_fifo_eop = false;
901
902	#ifdef INSTRUMENTATION
903	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
904	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
905	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
906	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
907	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
908	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
909	#endif
910
911	m_cpt_total_cycles++;
912
913	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
914	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
915
916	/////////////////////////////////////////////////////////////////////
917	// Get data and instruction requests from processor
918	///////////////////////////////////////////////////////////////////////
919
920	r_iss.getRequests(m_ireq, m_dreq);
921
922	////////////////////////////////////////////////////////////////////////////////////
923	// ICACHE_FSM
924	//
925	// 1/ Coherence operations
926	// They are handled as interrupts generated by the CC_RECEIVE FSM.
927	// - There is a coherence request when r_tgt_icache_req is set.
928	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
929	// - There is a cleanup ack request when r_cleanup_icache_req is set.
930	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
931	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
932	// - For both types of requests, actions associated to the pre-empted state
933	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
934	// or CC_CLACK) to execute the requested coherence operation, and returns
935	// to the pre-empted state.
936	//
937	// 2/ Processor requests
938	// They are taken in IDLE state only. In case of cache miss, or uncacheable
939	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
940	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
941	// flip-flops are reset when the transaction starts.
942	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
943	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
944	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
945	// The availability of the missing cache line is signaled by the response fifo,
946	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
947	// and ICACHE_MISS_DIR_UPDT states.
948	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
949	// to wait the response from the RSP FSM, through the response fifo.
950	// The missing instruction is directly returned to processor in this state.
951	//
952	// 3/ TLB miss
953	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
954	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
955	// register, and goes to the ICACHE_TLB_WAIT state.
956	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
957	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
958	// to signal the completion.
959	//
960	// 4/ XTN requests
961	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
962	// using the r_dcache_xtn_req flip-flop.
963	// The request opcode and the address to be invalidated are transmitted
964	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
965	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
966	// is completed.
967	//
968	// 5/ Error Handling
969	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
970	// in a cache miss or uncacheable read VCI transaction. Nothing is written
971	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
972	////////////////////////////////////////////////////////////////////////////////////////
973
974	// default value for m_irsp
975	m_irsp.valid = false;
976	m_irsp.error = false;
977	m_irsp.instruction = 0;
978
979	switch( r_icache_fsm.read() )
980	{
981	/////////////////
982	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
983	// and coherence requests with a fixed priority:
984	// 1/ Coherence requests => ICACHE_CC_CHECK
985	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
986	// 3/ tlb miss => ICACHE_TLB_WAIT
987	// 4/ cacheable read miss => ICACHE_MISS_SELECT
988	// 5/ uncacheable read miss => ICACHE_UNC_REQ
989	{
990	// coherence interrupt
991	if ( r_cc_receive_icache_req.read() )
992	{
993	r_icache_fsm = ICACHE_CC_CHECK;
994	r_icache_fsm_save = r_icache_fsm.read();
995	break;
996	}
997
998	// XTN requests sent by DCACHE FSM
999	// These request are not executed in this IDLE state, because
1000	// they require access to icache or itlb, that are already accessed
1001	if ( r_dcache_xtn_req.read() )
1002	{
1003	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1004	{
1005	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1006	}
1007	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1008	{
1009	r_icache_flush_count = 0;
1010	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1011	}
1012	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1013	{
1014	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1015	}
1016	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1017	{
1018	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1019	}
1020	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1021	{
1022	if (sizeof(paddr_t) <= 32)
1023	{
1024	assert(r_mmu_word_hi.read() == 0 &&
1025	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1026	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1027	}
1028	else
1029	{
1030	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1031	(paddr_t)r_mmu_word_lo.read();
1032	}
1033	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1034	}
1035	else
1036	{
1037	assert( false and
1038	"undefined XTN request received by ICACHE FSM");
1039	}
1040	break;
1041	} // end if xtn_req
1042
1043	// processor request
1044	if ( m_ireq.valid )
1045	{
1046	bool cacheable;
1047	paddr_t paddr;
1048	bool tlb_hit = false;
1049	pte_info_t tlb_flags;
1050	size_t tlb_way;
1051	size_t tlb_set;
1052	paddr_t tlb_nline;
1053	uint32_t cache_inst = 0;
1054	size_t cache_way;
1055	size_t cache_set;
1056	size_t cache_word;
1057	int cache_state = CACHE_SLOT_STATE_EMPTY;
1058
1059	// We register processor request
1060	r_icache_vaddr_save = m_ireq.addr;
1061
1062	// sytematic itlb access (if activated)
1063	if ( r_mmu_mode.read() & INS_TLB_MASK )
1064	{
1065
1066	#ifdef INSTRUMENTATION
1067	m_cpt_itlb_read++;
1068	#endif
1069	tlb_hit = r_itlb.translate( m_ireq.addr,
1070	&paddr,
1071	&tlb_flags,
1072	&tlb_nline, // unused
1073	&tlb_way, // unused
1074	&tlb_set ); // unused
1075	}
1076	else
1077	{
1078	paddr = (paddr_t)m_ireq.addr;
1079	}
1080
1081	// systematic icache access (if activated)
1082	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1083	{
1084
1085
1086	#ifdef INSTRUMENTATION
1087	m_cpt_icache_data_read++;
1088	m_cpt_icache_dir_read++;
1089	#endif
1090	r_icache.read( paddr,
1091	&cache_inst,
1092	&cache_way,
1093	&cache_set,
1094	&cache_word,
1095	&cache_state );
1096	}
1097
1098	// We compute cacheability and check access rights:
1099	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1100	// and the access rights are defined by the U and X bits in the PTE.
1101	// - If MMU not activated : cacheability is defined by the segment table,
1102	// and there is no access rights checking
1103
1104	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1105	{
1106	// cacheability
1107	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1108	else cacheable = m_cacheability_table[m_ireq.addr];
1109	}
1110	else // itlb activated
1111	{
1112	if ( tlb_hit ) // ITLB hit
1113	{
1114	// cacheability
1115	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1116	else cacheable = tlb_flags.c;
1117
1118	// access rights checking
1119	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1120	{
1121	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1122	r_mmu_ibvar = m_ireq.addr;
1123	m_irsp.valid = true;
1124	m_irsp.error = true;
1125	m_irsp.instruction = 0;
1126	break;
1127	}
1128	else if ( not tlb_flags.x )
1129	{
1130	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1131	r_mmu_ibvar = m_ireq.addr;
1132	m_irsp.valid = true;
1133	m_irsp.error = true;
1134	m_irsp.instruction = 0;
1135	break;
1136	}
1137	}
1138	else // ITLB miss
1139	{
1140
1141	#ifdef INSTRUMENTATION
1142	m_cpt_itlb_miss++;
1143	#endif
1144	r_icache_fsm = ICACHE_TLB_WAIT;
1145	r_icache_tlb_miss_req = true;
1146	break;
1147	}
1148	} // end if itlb activated
1149
1150	// physical address registration
1151	r_icache_vci_paddr = paddr;
1152
1153	// Finally, we send the response to processor, and compute next state
1154	if ( cacheable )
1155	{
1156	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1157	{
1158
1159	#ifdef INSTRUMENTATION
1160	m_cpt_icache_miss++;
1161	#endif
1162	// we request a VCI transaction
1163	r_icache_fsm = ICACHE_MISS_SELECT;
1164	r_icache_miss_req = true;
1165	}
1166	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1167	{
1168	// stalled until cleanup is acknowledged
1169	r_icache_fsm = ICACHE_IDLE;
1170	}
1171	else // cache hit
1172	{
1173
1174	#ifdef INSTRUMENTATION
1175	m_cpt_ins_read++;
1176	#endif
1177	// return instruction to processor
1178	m_irsp.valid = true;
1179	m_irsp.instruction = cache_inst;
1180	r_icache_fsm = ICACHE_IDLE;
1181	}
1182	}
1183	else // non cacheable read
1184	{
1185	r_icache_unc_req = true;
1186	r_icache_fsm = ICACHE_UNC_WAIT;
1187	}
1188	} // end if m_ireq.valid
1189	break;
1190	}
1191	/////////////////////
1192	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1193	// the itlb is udated by the DCACHE FSM, as well as the
1194	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1195	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1196	// reset the r_icache_tlb_miss_req flip-flop
1197	// external coherence request are accepted in this state.
1198	{
1199	// coherence interrupt
1200	if ( r_cc_receive_icache_req.read() )
1201	{
1202	r_icache_fsm = ICACHE_CC_CHECK;
1203	r_icache_fsm_save = r_icache_fsm.read();
1204	break;
1205	}
1206
1207	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1208
1209	// DCACHE FSM signals response by reseting the request flip-flop
1210	if ( not r_icache_tlb_miss_req.read() )
1211	{
1212	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1213	{
1214	r_icache_tlb_rsp_error = false;
1215	m_irsp.error = true;
1216	m_irsp.valid = true;
1217	r_icache_fsm = ICACHE_IDLE;
1218	}
1219	else // tlb updated : return to IDLE state
1220	{
1221	r_icache_fsm = ICACHE_IDLE;
1222	}
1223	}
1224	break;
1225	}
1226	//////////////////////////
1227	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1228	{
1229	r_itlb.flush();
1230	r_dcache_xtn_req = false;
1231	r_icache_fsm = ICACHE_IDLE;
1232	break;
1233	}
1234	////////////////////////////
1235	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1236	// r_icache_flush_count as a slot counter,
1237	// looping in this state until all slots are visited.
1238	// It can require two cycles per slot:
1239	// We test here the slot state, and make the actual inval
1240	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1241	// A cleanup request is generated for each valid line
1242	{
1243	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1244	{
1245	int state;
1246	uint32_t tag;
1247	size_t way = r_icache_flush_count.read()/m_icache_sets;
1248	size_t set = r_icache_flush_count.read()%m_icache_sets;
1249
1250	#ifdef INSTRUMENTATION
1251	m_cpt_icache_dir_read++;
1252	#endif
1253	r_icache.read_dir( way,
1254	set,
1255	&tag,
1256	&state );
1257
1258	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1259	{
1260	// request cleanup
1261	r_icache_cc_send_req = true;
1262	r_icache_cc_send_nline = tag * m_icache_sets;
1263	r_icache_cc_send_way = way;
1264	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1265
1266	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1267	r_icache_miss_way = way;
1268	r_icache_miss_set = set;
1269	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1270	}
1271	else if ( r_icache_flush_count.read() ==
1272	(m_icache_sets*m_icache_ways - 1) ) // last slot
1273	{
1274	r_dcache_xtn_req = false;
1275	m_drsp.valid = true;
1276	r_icache_fsm = ICACHE_IDLE;
1277	}
1278
1279	// saturation counter, to have the same last slot condition
1280	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1281	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1282	{
1283	r_icache_flush_count = r_icache_flush_count.read() + 1;
1284	}
1285	}
1286	break;
1287	}
1288	///////////////////////////////
1289	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1290	{
1291	size_t way = r_icache_miss_way.read();
1292	size_t set = r_icache_miss_set.read();
1293
1294	#ifdef INSTRUMENTATION
1295	m_cpt_icache_dir_write++;
1296	#endif
1297
1298	r_icache.write_dir( 0,
1299	way,
1300	set,
1301	CACHE_SLOT_STATE_ZOMBI );
1302
1303	if ( r_icache_flush_count.read() ==
1304	(m_icache_sets*m_icache_ways - 1) ) // last slot
1305	{
1306	r_dcache_xtn_req = false;
1307	m_drsp.valid = true;
1308	r_icache_fsm = ICACHE_IDLE;
1309	}
1310	else
1311	{
1312	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1313	}
1314	break;
1315	}
1316
1317	//////////////////////////
1318	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1319	// stored in the r_dcache_save_wdata register
1320	{
1321	r_itlb.inval(r_dcache_save_wdata.read());
1322	r_dcache_xtn_req = false;
1323	r_icache_fsm = ICACHE_IDLE;
1324	break;
1325	}
1326	///////////////////////////////
1327	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1328	// requires 3 cycles (in case of hit on itlb and icache).
1329	// In this state, access TLB to translate virtual address
1330	// stored in the r_dcache_save_wdata register.
1331	{
1332	paddr_t paddr;
1333	bool hit;
1334
1335	// read physical address in TLB when MMU activated
1336	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1337	{
1338
1339	#ifdef INSTRUMENTATION
1340	m_cpt_itlb_read++;
1341	#endif
1342	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1343	&paddr);
1344	}
1345	else // itlb not activated
1346	{
1347	paddr = (paddr_t)r_dcache_save_wdata.read();
1348	hit = true;
1349	}
1350
1351	if ( hit ) // continue the selective inval process
1352	{
1353	r_icache_vci_paddr = paddr;
1354	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1355	}
1356	else // miss : send a request to DCACHE FSM
1357	{
1358
1359	#ifdef INSTRUMENTATION
1360	m_cpt_itlb_miss++;
1361	#endif
1362	r_icache_tlb_miss_req = true;
1363	r_icache_vaddr_save = r_dcache_save_wdata.read();
1364	r_icache_fsm = ICACHE_TLB_WAIT;
1365	}
1366	break;
1367	}
1368	///////////////////////////////
1369	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1370	// require 2 cycles. In this state, we read directory
1371	// with address stored in r_icache_vci_paddr register.
1372	{
1373	int state;
1374	size_t way;
1375	size_t set;
1376	size_t word;
1377
1378	#ifdef INSTRUMENTATION
1379	m_cpt_icache_dir_read++;
1380	#endif
1381	r_icache.read_dir(r_icache_vci_paddr.read(),
1382	&state,
1383	&way,
1384	&set,
1385	&word);
1386
1387	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1388	{
1389	r_icache_miss_way = way;
1390	r_icache_miss_set = set;
1391	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1392	}
1393	else // miss : acknowlege the XTN request and return
1394	{
1395	r_dcache_xtn_req = false;
1396	r_icache_fsm = ICACHE_IDLE;
1397	}
1398	break;
1399	}
1400	///////////////////////////////
1401	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1402	{
1403	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1404	{
1405
1406	#ifdef INSTRUMENTATION
1407	m_cpt_icache_dir_write++;
1408	#endif
1409	r_icache.write_dir( 0,
1410	r_icache_miss_way.read(),
1411	r_icache_miss_set.read(),
1412	CACHE_SLOT_STATE_ZOMBI );
1413
1414	// request cleanup
1415	r_icache_cc_send_req = true;
1416	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1417	r_icache_cc_send_way = r_icache_miss_way.read();
1418	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1419
1420	// acknowledge the XTN request and return
1421	r_dcache_xtn_req = false;
1422	r_icache_fsm = ICACHE_IDLE;
1423	}
1424	break;
1425	}
1426	////////////////////////
1427	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1428	// if previous cleanup has been sent.
1429	// Waiting in this state if no slot available.
1430	// Set the r_icache_cleanup_req flip-flop
1431	// and the r_icache_miss_clack flip-flop,
1432	// when a cleanup is required
1433	{
1434	if (m_ireq.valid) m_cost_ins_miss_frz++;
1435
1436	// coherence interrupt
1437	if ( r_cc_receive_icache_req.read() )
1438	{
1439	r_icache_fsm = ICACHE_CC_CHECK;
1440	r_icache_fsm_save = r_icache_fsm.read();
1441	break;
1442	}
1443
1444	if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
1445	{
1446	bool found;
1447	bool cleanup;
1448	size_t way;
1449	size_t set;
1450	paddr_t victim;
1451
1452	#ifdef INSTRUMENTATION
1453	m_cpt_icache_dir_read++;
1454	#endif
1455	r_icache.read_select(r_icache_vci_paddr.read(),
1456	&victim,
1457	&way,
1458	&set,
1459	&found,
1460	&cleanup );
1461	if ( found )
1462	{
1463	r_icache_miss_way = way;
1464	r_icache_miss_set = set;
1465
1466	if ( cleanup )
1467	{
1468	r_icache_fsm = ICACHE_MISS_CLEAN;
1469	r_icache_miss_clack = true;
1470	// request cleanup
1471	r_icache_cc_send_req = true;
1472	r_icache_cc_send_nline = victim;
1473	r_icache_cc_send_way = way;
1474	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1475	}
1476	else
1477	{
1478	r_icache_fsm = ICACHE_MISS_WAIT;
1479	}
1480
1481	#if DEBUG_ICACHE
1482	if ( m_debug_dcache_fsm )
1483	{
1484	std::cout << " <PROC " << name()
1485	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1486	<< " / WAY = " << way
1487	<< " / SET = " << set;
1488	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1489	else std::cout << std::endl;
1490	}
1491	#endif
1492	}
1493	}
1494	break;
1495	}
1496	///////////////////////
1497	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1498	{
1499	if (m_ireq.valid) m_cost_ins_miss_frz++;
1500
1501	// coherence interrupt
1502	if ( r_cc_receive_icache_req.read() )
1503	{
1504	r_icache_fsm = ICACHE_CC_CHECK;
1505	r_icache_fsm_save = r_icache_fsm.read();
1506	break;
1507	}
1508
1509	#ifdef INSTRUMENTATION
1510	m_cpt_icache_dir_write++;
1511	#endif
1512	r_icache.write_dir( 0,
1513	r_icache_miss_way.read(),
1514	r_icache_miss_set.read(),
1515	CACHE_SLOT_STATE_ZOMBI);
1516	#if DEBUG_ICACHE
1517	if ( m_debug_dcache_fsm )
1518	{
1519	std::cout << " <PROC " << name()
1520	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1521	<< " / WAY = " << r_icache_miss_way.read()
1522	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1523	}
1524	#endif
1525
1526	r_icache_fsm = ICACHE_MISS_WAIT;
1527	break;
1528	}
1529	//////////////////////
1530	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1531	{
1532	if (m_ireq.valid) m_cost_ins_miss_frz++;
1533
1534	// coherence interrupt
1535	if ( r_cc_receive_icache_req.read() )
1536	{
1537	r_icache_fsm = ICACHE_CC_CHECK;
1538	r_icache_fsm_save = r_icache_fsm.read();
1539	break;
1540	}
1541
1542	if ( r_vci_rsp_ins_error.read() ) // bus error
1543	{
1544	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1545	r_mmu_ibvar = r_icache_vaddr_save.read();
1546	m_irsp.valid = true;
1547	m_irsp.error = true;
1548	r_vci_rsp_ins_error = false;
1549	r_icache_fsm = ICACHE_IDLE;
1550	}
1551	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1552	{
1553	r_icache_miss_word = 0;
1554	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1555	}
1556	break;
1557	}
1558	///////////////////////////
1559	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1560	{
1561	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1562
1563	// coherence interrupt
1564	if ( r_cc_receive_icache_req.read() )
1565	{
1566	r_icache_fsm = ICACHE_CC_CHECK;
1567	r_icache_fsm_save = r_icache_fsm.read();
1568	break;
1569	}
1570
1571	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1572	{
1573
1574	#ifdef INSTRUMENTATION
1575	m_cpt_icache_data_write++;
1576	#endif
1577	r_icache.write( r_icache_miss_way.read(),
1578	r_icache_miss_set.read(),
1579	r_icache_miss_word.read(),
1580	r_vci_rsp_fifo_icache.read() );
1581	#if DEBUG_ICACHE
1582	if ( m_debug_icache_fsm )
1583	{
1584	std::cout << " <PROC " << name()
1585	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1586	<< " WDATA = " << r_vci_rsp_fifo_icache.read()
1587	<< " WAY = " << r_icache_miss_way.read()
1588	<< " SET = " << r_icache_miss_set.read()
1589	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1590	}
1591	#endif
1592	vci_rsp_fifo_icache_get = true;
1593	r_icache_miss_word = r_icache_miss_word.read() + 1;
1594
1595	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1596	{
1597	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1598	}
1599	}
1600	break;
1601	}
1602	//////////////////////////
1603	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1604	// and the cleanup ack has not been received,
1605	// as indicated by r_icache_miss_clack.
1606	// - If no matching coherence request (r_icache_miss_inval)
1607	// switch directory slot to VALID state.
1608	// - If matching coherence request, switch directory slot
1609	// to ZOMBI state, and send a cleanup request.
1610	{
1611	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1612
1613	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1614	{
1615	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1616	{
1617	if ( not r_icache_cc_send_req.read() )
1618	{
1619	r_icache_miss_inval = false;
1620	// request cleanup
1621	r_icache_cc_send_req = true;
1622	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1623	r_icache_cc_send_way = r_icache_miss_way.read();
1624	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1625
1626	#ifdef INSTRUMENTATION
1627	m_cpt_icache_dir_write++;
1628	#endif
1629	r_icache.write_dir( r_icache_vci_paddr.read(),
1630	r_icache_miss_way.read(),
1631	r_icache_miss_set.read(),
1632	CACHE_SLOT_STATE_ZOMBI );
1633	#if DEBUG_ICACHE
1634	if ( m_debug_icache_fsm )
1635	{
1636	std::cout << " <PROC " << name()
1637	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1638	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1639	<< " WAY = " << std::dec << r_icache_miss_way.read()
1640	<< " SET = " << r_icache_miss_set.read() << std::endl;
1641	}
1642	#endif
1643	}
1644	}
1645	else // Switch slot to VALID state
1646	{
1647
1648	#ifdef INSTRUMENTATION
1649	m_cpt_icache_dir_write++;
1650	#endif
1651	r_icache.write_dir( r_icache_vci_paddr.read(),
1652	r_icache_miss_way.read(),
1653	r_icache_miss_set.read(),
1654	CACHE_SLOT_STATE_VALID );
1655	#if DEBUG_ICACHE
1656	if ( m_debug_icache_fsm )
1657	{
1658	std::cout << " <PROC " << name()
1659	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1660	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1661	<< " WAY = " << std::dec << r_icache_miss_way.read()
1662	<< " SET = " << r_icache_miss_set.read() << std::endl;
1663	}
1664	#endif
1665	}
1666
1667	r_icache_fsm = ICACHE_IDLE;
1668	}
1669	break;
1670	}
1671	////////////////////
1672	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1673	{
1674	// coherence interrupt
1675	if ( r_cc_receive_icache_req.read() )
1676	{
1677	r_icache_fsm = ICACHE_CC_CHECK;
1678	r_icache_fsm_save = r_icache_fsm.read();
1679	break;
1680	}
1681
1682	if ( r_vci_rsp_ins_error.read() ) // bus error
1683	{
1684	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1685	r_mmu_ibvar = m_ireq.addr;
1686	r_vci_rsp_ins_error = false;
1687	m_irsp.valid = true;
1688	m_irsp.error = true;
1689	r_icache_fsm = ICACHE_IDLE;
1690	}
1691	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1692	{
1693	vci_rsp_fifo_icache_get = true;
1694	r_icache_fsm = ICACHE_IDLE;
1695	if ( m_ireq.valid and
1696	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1697	{
1698	m_irsp.valid = true;
1699	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1700	}
1701	}
1702	break;
1703	}
1704	/////////////////////
1705	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1706	// handling coherence requests.
1707	// if there is a matching pending miss, it is
1708	// signaled in the r_icache_miss_inval flip-flop.
1709	// The return state is defined in r_icache_fsm_save.
1710	{
1711	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1712	paddr_t mask = ~((m_icache_words<<2)-1);
1713
1714	if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK)
1715	// We switch the directory slot to EMPTY state
1716	// and reset r_icache_miss_clack if the cleanup ack
1717	// is matching a pending miss
1718	{
1719
1720	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1721
1722	#ifdef INSTRUMENTATION
1723	m_cpt_icache_dir_write++;
1724	#endif
1725	r_icache.write_dir( 0,
1726	r_cc_receive_icache_way.read(),
1727	r_cc_receive_icache_set.read(),
1728	CACHE_SLOT_STATE_EMPTY);
1729
1730	if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and
1731	(r_icache_miss_way.read() == r_cc_receive_icache_way.read()) )
1732	r_icache_miss_clack = false;
1733
1734	r_icache_fsm = r_icache_fsm_save.read() ;
1735	r_cc_receive_icache_req = false;
1736
1737	#if DEBUG_ICACHE
1738	if ( m_debug_icache_fsm )
1739	{
1740	std::cout << " <PROC " << name()
1741	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1742	<< " set = " << r_cc_receive_icache_set.read()
1743	<< " / way = " << r_cc_receive_icache_way.read() << std::endl;
1744	}
1745	#endif
1746	}
1747	else if( ((r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1748	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1749	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1750	{
1751	// signaling the matching
1752	r_icache_miss_inval = true;
1753
1754	// in case of update, go to CC_UPDT
1755	// JUST TO POP THE FIFO
1756	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1757	{
1758	r_icache_fsm = ICACHE_CC_UPDT;
1759	r_icache_cc_word = r_cc_receive_word_idx.read();
1760	// just pop the fifo , don't write in icache
1761	r_icache_cc_need_write = false;
1762	}
1763	// the request is dealt with
1764	else
1765	{
1766	r_cc_receive_icache_req = false;
1767	r_icache_fsm = r_icache_fsm_save.read();
1768	}
1769	#if DEBUG_ICACHE
1770	if ( m_debug_icache_fsm )
1771	{
1772	std::cout << " <PROC " << name()
1773	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1774	<< " PADDR = " << std::hex << paddr << std::endl;
1775	}
1776	#endif
1777	}
1778	else // no match
1779	{
1780	int state;
1781	size_t way;
1782	size_t set;
1783	size_t word;
1784
1785	#ifdef INSTRUMENTATION
1786	m_cpt_icache_dir_read++;
1787	#endif
1788	r_icache.read_dir(paddr,
1789	&state,
1790	&way,
1791	&set,
1792	&word);
1793
1794	r_icache_cc_way = way;
1795	r_icache_cc_set = set;
1796
1797	if ( state == CACHE_SLOT_STATE_VALID) // hit
1798	{
1799	// need to update the cache state
1800	r_icache_cc_need_write = true;
1801	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1802	{
1803	r_icache_fsm = ICACHE_CC_UPDT;
1804	r_icache_cc_word = r_cc_receive_word_idx.read();
1805	}
1806	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
1807	{
1808	r_icache_fsm = ICACHE_CC_INVAL;
1809	}
1810	else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
1811	{
1812	r_icache_fsm = ICACHE_CC_BROADCAST;
1813	}
1814	}
1815	else // miss
1816	{
1817	// multicast acknowledgement required in case of update
1818	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1819	{
1820	r_icache_fsm = ICACHE_CC_UPDT;
1821	r_icache_cc_word = r_cc_receive_word_idx.read();
1822	// just pop the fifo , don't write in icache
1823	r_icache_cc_need_write = false;
1824	}
1825	else // No response needed
1826	{
1827	r_cc_receive_icache_req = false;
1828	r_icache_fsm = r_icache_fsm_save.read();
1829	}
1830	}
1831	}
1832	break;
1833	}
1834	/////////////////////
1835	case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state
1836	{
1837
1838	#if DEBUG_ICACHE
1839	if ( m_debug_icache_fsm )
1840	{
1841	std::cout << " <PROC " << name()
1842	<< " ICACHE_CC_INVAL> slot returns to empty state"
1843	<< " set = " << r_icache_cc_set.read()
1844	<< " / way = " << r_icache_cc_way.read() << std::endl;
1845	}
1846	#endif
1847
1848	#ifdef INSTRUMENTATION
1849	m_cpt_icache_dir_read++;
1850	#endif
1851	if (r_icache_cc_need_write.read())
1852	{
1853	r_icache.write_dir( 0,
1854	r_icache_cc_way.read(),
1855	r_icache_cc_set.read(),
1856	CACHE_SLOT_STATE_EMPTY );
1857	// no need to write in the cache anymore
1858	r_icache_cc_need_write = false;
1859	}
1860
1861	// multicast acknowledgement
1862	// send a request to cc_send_fsm
1863	if(not r_icache_cc_send_req.read()) // cc_send is available
1864	{
1865	// coherence request completed
1866	r_cc_receive_icache_req = false;
1867	// request multicast acknowledgement
1868	r_icache_cc_send_req = true;
1869	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1870	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1871
1872	r_icache_fsm = r_icache_fsm_save.read();
1873	}
1874	//else wait for previous cc_send request to be sent
1875	break;
1876	}
1877	////////////////////
1878	case ICACHE_CC_UPDT: // hit update : write one word per cycle
1879	{
1880
1881	#if DEBUG_ICACHE
1882	if ( m_debug_icache_fsm )
1883	{
1884	std::cout << " <PROC " << name()
1885	<< " ICACHE_CC_UPDT> Write one word "
1886	<< " set = " << r_icache_cc_set.read()
1887	<< " / way = " << r_icache_cc_way.read()
1888	<< " / word = " << r_icache_cc_word.read() << std::endl;
1889	}
1890	#endif
1891
1892	#ifdef INSTRUMENTATION
1893	m_cpt_icache_data_write++;
1894	#endif
1895	size_t word = r_icache_cc_word.read();
1896	size_t way = r_icache_cc_way.read();
1897	size_t set = r_icache_cc_set.read();
1898
1899	if (r_cc_receive_updt_fifo_be.rok())
1900	{
1901	if (r_icache_cc_need_write.read())
1902	{
1903	r_icache.write( way,
1904	set,
1905	word,
1906	r_cc_receive_updt_fifo_data.read(),
1907	r_cc_receive_updt_fifo_be.read() );
1908
1909	r_icache_cc_word = word+1;
1910	}
1911	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
1912	{
1913	// no need to write in the cache anymore
1914	r_icache_cc_need_write = false;
1915	// wait to send a request to cc_send_fsm
1916	if(not r_icache_cc_send_req.read()) // cc_send is available
1917	{
1918	//consume last flit
1919	cc_receive_updt_fifo_get = true;
1920	// coherence request completed
1921	r_cc_receive_icache_req = false;
1922	// request multicast acknowledgement
1923	r_icache_cc_send_req = true;
1924	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1925	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1926
1927	r_icache_fsm = r_icache_fsm_save.read();
1928	}
1929	}
1930	else
1931	{
1932	//consume fifo if not eop
1933	cc_receive_updt_fifo_get = true;
1934	}
1935	}
1936	break;
1937	}
1938	/////////////////////////
1939	case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state
1940	// and request a cleanup
1941	{
1942
1943	#if DEBUG_ICACHE
1944	if ( m_debug_icache_fsm )
1945	{
1946	std::cout << " <PROC " << name()
1947	<< " ICACHE_CC_BROADCAST > Slot goes to zombi state "
1948	<< " set = " << r_icache_cc_set.read()
1949	<< " / way = " << r_icache_cc_way.read() << std::endl;
1950	}
1951	#endif
1952
1953	#ifdef INSTRUMENTATION
1954	m_cpt_icache_dir_write++;
1955	#endif
1956	if (r_icache_cc_need_write.read())
1957	{
1958	r_icache.write_dir( 0,
1959	r_icache_cc_way.read(),
1960	r_icache_cc_set.read(),
1961	CACHE_SLOT_STATE_ZOMBI );
1962	// no need to write in the cache anymore
1963	r_icache_cc_need_write = false;
1964	}
1965
1966	// cleanup
1967	// send a request to cc_send_fsm
1968	if(not r_icache_cc_send_req.read()) // cc_send is available
1969	{
1970	// coherence request completed
1971	r_cc_receive_icache_req = false;
1972	// request cleanup
1973	r_icache_cc_send_req = true;
1974	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1975	r_icache_cc_send_way = r_icache_cc_way.read();
1976	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1977
1978	r_icache_fsm = r_icache_fsm_save.read();
1979	}
1980	//else wait for previous cc_send request to be sent
1981	break;
1982	}
1983	} // end switch r_icache_fsm
1984
1985	////////////////////////////////////////////////////////////////////////////////////
1986	// DCACHE FSM
1987	//
1988	// 1/ Coherence operations
1989	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1990	// - There is a coherence request when r_tgt_dcache_req is set.
1991	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
1992	// and SC_WAIT states.
1993	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
1994	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
1995	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
1996	// - For both types of requests, actions associated to the pre-empted state
1997	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
1998	// or CC_CLACK) to execute the requested coherence operation, and returns
1999	// to the pre-empted state.
2000	//
2001	// 2/ TLB miss
2002	// The page tables are generally cacheable.
2003	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2004	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2005	// this sub-fsm implement the table-walk...
2006	//
2007	// 3/ processor requests
2008	// Processor requests are taken in IDLE state only.
2009	// The IDLE state implements a two stages pipe-line to handle write bursts:
2010	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2011	// - The registration in wbuf and the dcache update is done in stage P1
2012	// (if the processor request is a write).
2013	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2014	// the operations that must be done in P1 stage, and the access type
2015	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2016	// READ requests are delayed if a cache update is requested.
2017	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2018	// that is done (before handling the processor request) by a dedicated sub-fsm.
2019	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2020	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2021	//
2022	// 4/ Atomic instructions LL/SC
2023	// The LL/SC address are non cacheable (systematic access to memory).
2024	// The llsc buffer contains a registration for an active LL/SC operation
2025	// (with an address, a registration key, an aging counter and a valid bit).
2026	// - LL requests from the processor are transmitted as a one flit VCI command
2027	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2028	// be 8 as the response is 2 flits long (data and registration key)
2029	// - SC requests from the processor are systematically transmitted to the
2030	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2031	// as PKTID value). The first flit contains the registration key, the second
2032	// flit contains the data to write in case of success.
2033	// The cache is not updated, as this is done in case of success by the
2034	// coherence transaction.
2035	//
2036	// 5/ Non cacheable access:
2037	// This component implement a strong order between non cacheable access
2038	// (read or write) : A new non cacheable VCI transaction starts only when
2039	// the previous non cacheable transaction is completed. Both cacheable and
2040	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2041	// a non cacheable write transaction posted in the write buffer by setting the
2042	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2043	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2044	// pending non cacheable write transaction completes).
2045	//
2046	// 6/ Error handling:
2047	// When the MMU is not activated, Read Bus Errors are synchronous events,
2048	// but Write Bus Errors are asynchronous events (processor is not frozen).
2049	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2050	// r_vci_rsp_data_error flip-flop, without writing any data in the
2051	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2052	// by the DCACHE FSM.
2053	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2054	// the asynchronous error using the setWriteBerr() method.
2055	// When the MMU is activated bus error are rare events, as the MMU
2056	// checks the physical address before the VCI transaction starts.
2057	////////////////////////////////////////////////////////////////////////////////////////
2058
2059	// default value for m_drsp
2060	m_drsp.valid = false;
2061	m_drsp.error = false;
2062	m_drsp.rdata = 0;
2063
2064	switch ( r_dcache_fsm.read() )
2065	{
2066	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2067	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2068	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2069	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2070	// 4) XTN request (processor) => DCACHE_XTN_*
2071	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2072	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2073	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2074	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2075	// 9) LL access (processor) => DCACHE_LL_WAIT
2076	// 10) SC access (processor) => DCACHE_SC_WAIT
2077	//
2078	// There is a fixed priority to handle requests to DCACHE:
2079	// 1/ the ITLB/DTLB invalidate requests
2080	// 2/ the coherence requests,
2081	// 3/ the processor requests (including DTLB miss),
2082	// 4/ the ITLB miss requests,
2083	// The address space processor request are handled as follows:
2084	// - WRITE request is blocked if the Dirty bit mus be set.
2085	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2086	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2087	// - READ request generate a simultaneouss access to DCACHE.DATA
2088	// and DCACHE.DIR, but is delayed if DCACHE update required.
2089	//
2090	// There is 4 configurations defining the access type to
2091	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2092	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2093	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2094	// 0 / 0 / NOP / NOP / NOP /
2095	// 0 / 1 / NOP / NOP / WRITE /
2096	// 1 / 0 / READ / READ / NOP /
2097	// 1 / 1 / READ / READ / WRITE /
2098	// Those two registers are set at each cycle from the 3 signals
2099	// updt_request, wbuf_request, wbuf_write_miss.
2100	{
2101	paddr_t paddr; // physical address
2102	pte_info_t tlb_flags;
2103	size_t tlb_way;
2104	size_t tlb_set;
2105	paddr_t tlb_nline;
2106	size_t cache_way;
2107	size_t cache_set;
2108	size_t cache_word;
2109	uint32_t cache_rdata = 0;
2110	bool tlb_hit = false;
2111	int cache_state = CACHE_SLOT_STATE_EMPTY;
2112
2113	bool tlb_inval_required = false; // request TLB inval after cache update
2114	bool wbuf_write_miss = false; // miss a WBUF write request
2115	bool updt_request = false; // request DCACHE update in P1 stage
2116	bool wbuf_request = false; // request WBUF write in P1 stage
2117
2118	// physical address computation : systematic DTLB access if activated)
2119	if ( m_dreq.valid )
2120	{
2121	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2122	{
2123	tlb_hit = r_dtlb.translate( m_dreq.addr,
2124	&paddr,
2125	&tlb_flags,
2126	&tlb_nline,
2127	&tlb_way,
2128	&tlb_set );
2129	#ifdef INSTRUMENTATION
2130	m_cpt_dtlb_read++;
2131	#endif
2132	}
2133	else // identity mapping
2134	{
2135	paddr = (paddr_t)m_dreq.addr;
2136	}
2137	} // end physical address computation
2138
2139	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2140	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2141	{
2142	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2143	{
2144	r_dcache.read_dir( paddr,
2145	&cache_state,
2146	&cache_way,
2147	&cache_set,
2148	&cache_word );
2149
2150	r_dcache.write( r_dcache_save_cache_way.read(),
2151	r_dcache_save_cache_set.read(),
2152	r_dcache_save_cache_word.read(),
2153	r_dcache_save_wdata.read(),
2154	r_dcache_save_be.read() );
2155	#ifdef INSTRUMENTATION
2156	m_cpt_dcache_dir_read++;
2157	m_cpt_dcache_data_write++;
2158	#endif
2159	}
2160	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2161	{
2162	r_dcache.read( paddr,
2163	&cache_rdata,
2164	&cache_way,
2165	&cache_set,
2166	&cache_word,
2167	&cache_state );
2168	#ifdef INSTRUMENTATION
2169	m_cpt_dcache_dir_read++;
2170	m_cpt_dcache_data_read++;
2171	#endif
2172	}
2173	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2174	{
2175	r_dcache.write( r_dcache_save_cache_way.read(),
2176	r_dcache_save_cache_set.read(),
2177	r_dcache_save_cache_word.read(),
2178	r_dcache_save_wdata.read(),
2179	r_dcache_save_be.read() );
2180	#ifdef INSTRUMENTATION
2181	m_cpt_dcache_data_write++;
2182	#endif
2183	}
2184	} // end dcache access
2185
2186	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2187	if ( r_dcache_updt_req.read() )
2188	{
2189	size_t way = r_dcache_save_cache_way.read();
2190	size_t set = r_dcache_save_cache_set.read();
2191
2192	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2193	{
2194	tlb_inval_required = true;
2195	r_dcache_tlb_inval_set = 0;
2196	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2197	(uint32_log2(m_dcache_words<<2));
2198	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2199	}
2200	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2201	{
2202	r_itlb.reset();
2203	r_dtlb.reset();
2204	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2205	}
2206
2207	#if DEBUG_DCACHE
2208	if ( m_debug_dcache_fsm )
2209	{
2210	std::cout << " <PROC " << name()
2211	<< " DCACHE_IDLE> Cache update in P1 stage" << std::dec
2212	<< " / WAY = " << r_dcache_save_cache_way.read()
2213	<< " / SET = " << r_dcache_save_cache_set.read()
2214	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2215	<< " / DATA = " << r_dcache_save_wdata.read()
2216	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2217	}
2218	#endif
2219	} // end test TLB inval
2220
2221	// Try WBUF update in P1 stage
2222	// Miss if the write request is non cacheable, and there is a pending
2223	// non cacheable write, or if the write buffer is full.
2224	if ( r_dcache_wbuf_req.read() )
2225	{
2226	// miss if write not cacheable, and previous non cacheable write registered
2227	if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
2228	{
2229	wbuf_write_miss = true;
2230	}
2231	else // try a registration into write buffer
2232	{
2233	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2234	r_dcache_save_be.read(),
2235	r_dcache_save_wdata.read(),
2236	r_dcache_save_cacheable.read() );
2237	#ifdef INSTRUMENTATION
2238	m_cpt_wbuf_write++;
2239	#endif
2240	if ( not wok ) // miss if write buffer full
2241	{
2242	wbuf_write_miss = true;
2243	}
2244	else // update the write_buffer state extension
2245	{
2246	if(not r_dcache_pending_unc_write.read())
2247	r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
2248	}
2249	}
2250	} // end WBUF update
2251
2252	// Computing the response to processor,
2253	// and the next value for r_dcache_fsm
2254
2255	// itlb/dtlb invalidation self-request
2256	if ( tlb_inval_required )
2257	{
2258	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2259	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2260	}
2261
2262	// coherence request (from CC_RECEIVE FSM)
2263	else if ( r_cc_receive_dcache_req.read() )
2264	{
2265	r_dcache_fsm = DCACHE_CC_CHECK;
2266	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2267	}
2268
2269	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2270	// we don't take the processor request, and registers
2271	// are frozen in case of wbuf_write_miss
2272	else if ( m_dreq.valid and not wbuf_write_miss )
2273	{
2274	// register processor request and DCACHE response
2275	r_dcache_save_vaddr = m_dreq.addr;
2276	r_dcache_save_be = m_dreq.be;
2277	r_dcache_save_wdata = m_dreq.wdata;
2278	r_dcache_save_paddr = paddr;
2279	r_dcache_save_cache_way = cache_way;
2280	r_dcache_save_cache_set = cache_set;
2281	r_dcache_save_cache_word = cache_word;
2282
2283	// READ XTN requests from processor
2284	// They are executed in this DCACHE_IDLE state.
2285	// The processor must not be in user mode
2286	if (m_dreq.type == iss_t::XTN_READ)
2287	{
2288	int xtn_opcode = (int)m_dreq.addr/4;
2289
2290	// checking processor mode:
2291	if (m_dreq.mode == iss_t::MODE_USER)
2292	{
2293	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2294	r_mmu_dbvar = m_dreq.addr;
2295	m_drsp.valid = true;
2296	m_drsp.error = true;
2297	m_drsp.rdata = 0;
2298	r_dcache_fsm = DCACHE_IDLE;
2299	}
2300	else
2301	{
2302	switch( xtn_opcode )
2303	{
2304	case iss_t::XTN_INS_ERROR_TYPE:
2305	m_drsp.rdata = r_mmu_ietr.read();
2306	m_drsp.valid = true;
2307	m_drsp.error = false;
2308	break;
2309
2310	case iss_t::XTN_DATA_ERROR_TYPE:
2311	m_drsp.rdata = r_mmu_detr.read();
2312	m_drsp.valid = true;
2313	m_drsp.error = false;
2314	break;
2315
2316	case iss_t::XTN_INS_BAD_VADDR:
2317	m_drsp.rdata = r_mmu_ibvar.read();
2318	m_drsp.valid = true;
2319	m_drsp.error = false;
2320	break;
2321
2322	case iss_t::XTN_DATA_BAD_VADDR:
2323	m_drsp.rdata = r_mmu_dbvar.read();
2324	m_drsp.valid = true;
2325	m_drsp.error = false;
2326	break;
2327
2328	case iss_t::XTN_PTPR:
2329	m_drsp.rdata = r_mmu_ptpr.read();
2330	m_drsp.valid = true;
2331	m_drsp.error = false;
2332	break;
2333
2334	case iss_t::XTN_TLB_MODE:
2335	m_drsp.rdata = r_mmu_mode.read();
2336	m_drsp.valid = true;
2337	m_drsp.error = false;
2338	break;
2339
2340	case iss_t::XTN_MMU_PARAMS:
2341	m_drsp.rdata = r_mmu_params;
2342	m_drsp.valid = true;
2343	m_drsp.error = false;
2344	break;
2345
2346	case iss_t::XTN_MMU_RELEASE:
2347	m_drsp.rdata = r_mmu_release;
2348	m_drsp.valid = true;
2349	m_drsp.error = false;
2350	break;
2351
2352	case iss_t::XTN_MMU_WORD_LO:
2353	m_drsp.rdata = r_mmu_word_lo.read();
2354	m_drsp.valid = true;
2355	m_drsp.error = false;
2356	break;
2357
2358	case iss_t::XTN_MMU_WORD_HI:
2359	m_drsp.rdata = r_mmu_word_hi.read();
2360	m_drsp.valid = true;
2361	m_drsp.error = false;
2362	break;
2363
2364	default:
2365	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2366	r_mmu_dbvar = m_dreq.addr;
2367	m_drsp.valid = true;
2368	m_drsp.error = true;
2369	m_drsp.rdata = 0;
2370	break;
2371	} // end switch xtn_opcode
2372	} // end else
2373	} // end if XTN_READ
2374
2375	// Handling WRITE XTN requests from processor.
2376	// They are not executed in this DCACHE_IDLE state
2377	// if they require access to the caches or the TLBs
2378	// that are already accessed.
2379	// Caches can be invalidated or flushed in user mode,
2380	// and the sync instruction can be executed in user mode
2381	else if (m_dreq.type == iss_t::XTN_WRITE)
2382	{
2383	int xtn_opcode = (int)m_dreq.addr/4;
2384	r_dcache_xtn_opcode = xtn_opcode;
2385
2386	// checking processor mode:
2387	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2388	(xtn_opcode != iss_t:: XTN_SYNC) &&
2389	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2390	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2391	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2392	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2393	{
2394	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2395	r_mmu_dbvar = m_dreq.addr;
2396	m_drsp.valid = true;
2397	m_drsp.error = true;
2398	m_drsp.rdata = 0;
2399	r_dcache_fsm = DCACHE_IDLE;
2400	}
2401	else
2402	{
2403	switch( xtn_opcode )
2404	{
2405	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2406	r_dcache_xtn_req = true;
2407	r_dcache_fsm = DCACHE_XTN_SWITCH;
2408	break;
2409
2410	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2411	r_mmu_mode = m_dreq.wdata;
2412	m_drsp.valid = true;
2413	r_dcache_fsm = DCACHE_IDLE;
2414	break;
2415
2416	case iss_t::XTN_DTLB_INVAL: // dtlb access
2417	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2418	break;
2419
2420	case iss_t::XTN_ITLB_INVAL: // itlb access
2421	r_dcache_xtn_req = true;
2422	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2423	break;
2424
2425	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2426	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2427	break;
2428
2429	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2430	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2431	if (sizeof(paddr_t) <= 32)
2432	{
2433	assert(r_mmu_word_hi.read() == 0 &&
2434	"high bits should be 0 for 32bit paddr");
2435	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2436	}
2437	else
2438	{
2439	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2440	(paddr_t)r_mmu_word_lo.read();
2441	}
2442	break;
2443
2444	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2445	r_dcache_flush_count = 0;
2446	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2447	break;
2448
2449	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2450	r_dcache_xtn_req = true;
2451	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2452	break;
2453
2454	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2455	r_dcache_xtn_req = true;
2456	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2457	break;
2458
2459	case iss_t::XTN_ICACHE_FLUSH: // icache access
2460	r_dcache_xtn_req = true;
2461	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2462	break;
2463
2464	case iss_t::XTN_SYNC: // wait until write buffer empty
2465	r_dcache_fsm = DCACHE_XTN_SYNC;
2466	break;
2467
2468	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2469	r_mmu_word_lo = m_dreq.wdata;
2470	m_drsp.valid = true;
2471	r_dcache_fsm = DCACHE_IDLE;
2472	break;
2473
2474	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2475	r_mmu_word_hi = m_dreq.wdata;
2476	m_drsp.valid = true;
2477	r_dcache_fsm = DCACHE_IDLE;
2478	break;
2479
2480	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2481	r_dcache_llsc_valid = false;
2482	m_drsp.valid = true;
2483	r_dcache_fsm = DCACHE_IDLE;
2484	break;
2485
2486	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2487	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2488	m_drsp.valid = true;
2489	r_dcache_fsm = DCACHE_IDLE;
2490	break;
2491
2492	default:
2493	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2494	r_mmu_dbvar = m_dreq.addr;
2495	m_drsp.valid = true;
2496	m_drsp.error = true;
2497	r_dcache_fsm = DCACHE_IDLE;
2498	break;
2499	} // end switch xtn_opcode
2500	} // end else
2501	} // end if XTN_WRITE
2502
2503	// Handling processor requests to address space (READ/WRITE/LL/SC)
2504	// The dtlb and dcache can be activated or not.
2505	// We compute the cacheability, and check processor request validity:
2506	// - If DTLB not activated : cacheability is defined by the segment table,
2507	// and there is no access rights checking.
2508	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2509	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2510	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2511	else
2512	{
2513	bool valid_req;
2514	bool cacheable;
2515
2516	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2517	{
2518	valid_req = true;
2519
2520	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2521	else cacheable = m_cacheability_table[m_dreq.addr];
2522	}
2523	else // dtlb activated
2524	{
2525	if ( tlb_hit ) // tlb hit
2526	{
2527	// cacheability
2528	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2529	else cacheable = tlb_flags.c;
2530
2531	// access rights checking
2532	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2533	{
2534	if ( (m_dreq.type == iss_t::DATA_READ) or
2535	(m_dreq.type == iss_t::DATA_LL) )
2536	{
2537	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2538	}
2539	else
2540	{
2541	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2542	}
2543	valid_req = false;
2544	r_mmu_dbvar = m_dreq.addr;
2545	m_drsp.valid = true;
2546	m_drsp.error = true;
2547	m_drsp.rdata = 0;
2548	#if DEBUG_DCACHE
2549	if ( m_debug_dcache_fsm )
2550	{
2551	std::cout << " <PROC " << name()
2552	<< ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2553	}
2554	#endif
2555	}
2556	else if ( not tlb_flags.w and
2557	((m_dreq.type == iss_t::DATA_WRITE) or
2558	(m_dreq.type == iss_t::DATA_SC)) )
2559	{
2560	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2561	valid_req = false;
2562	r_mmu_dbvar = m_dreq.addr;
2563	m_drsp.valid = true;
2564	m_drsp.error = true;
2565	m_drsp.rdata = 0;
2566	#if DEBUG_DCACHE
2567	if ( m_debug_dcache_fsm )
2568	{
2569	std::cout << " <PROC " << name()
2570	<< ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2571	}
2572	#endif
2573	}
2574	else
2575	{
2576	valid_req = true;
2577	}
2578	}
2579	else // tlb miss
2580	{
2581	valid_req = false;
2582	r_dcache_tlb_vaddr = m_dreq.addr;
2583	r_dcache_tlb_ins = false;
2584	r_dcache_fsm = DCACHE_TLB_MISS;
2585	}
2586	} // end DTLB activated
2587
2588	if ( valid_req ) // processor request is valid after TLB check
2589	{
2590	r_dcache_save_cacheable = cacheable;
2591
2592	// READ request
2593	// The read requests are taken only if there is no cache update.
2594	// We request a VCI transaction to CMD FSM if miss or uncachable
2595	if ( ((m_dreq.type == iss_t::DATA_READ))
2596	and not r_dcache_updt_req.read() )
2597	{
2598	if ( cacheable ) // cacheable read
2599	{
2600	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2601	{
2602	#ifdef INSTRUMENTATION
2603	m_cpt_dcache_miss++;
2604	#endif
2605	// request a VCI DMISS transaction
2606	r_dcache_vci_paddr = paddr;
2607	r_dcache_vci_miss_req = true;
2608	r_dcache_miss_type = PROC_MISS;
2609	r_dcache_fsm = DCACHE_MISS_SELECT;
2610	#if DEBUG_DCACHE
2611	if ( m_debug_dcache_fsm )
2612	{
2613	std::cout << " <PROC " << name()
2614	<< ".DCACHE_IDLE> READ MISS in dcache" << std::endl;
2615	}
2616	#endif
2617	}
2618	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2619	{
2620	// stalled until cleanup is acknowledged
2621	r_dcache_fsm = DCACHE_IDLE;
2622	}
2623	else // cache hit
2624	{
2625	#ifdef INSTRUMENTATION
2626	m_cpt_data_read++;
2627	#endif
2628	// returns data to processor
2629	m_drsp.valid = true;
2630	m_drsp.error = false;
2631	m_drsp.rdata = cache_rdata;
2632	#if DEBUG_DCACHE
2633	if ( m_debug_dcache_fsm )
2634	{
2635	std::cout << " <PROC " << name()
2636	<< ".DCACHE_IDLE> READ HIT in dcache" << std::endl;
2637	}
2638	#endif
2639	}
2640	}
2641	else // uncacheable read
2642	{
2643	r_dcache_vci_paddr = paddr;
2644	r_dcache_vci_unc_be = m_dreq.be;
2645	r_dcache_vci_unc_req = true;
2646	r_dcache_fsm = DCACHE_UNC_WAIT;
2647	#if DEBUG_DCACHE
2648	if ( m_debug_dcache_fsm )
2649	{
2650	std::cout << " <PROC " << name()
2651	<< ".DCACHE_IDLE> READ UNCACHEABLE in dcache" << std::endl;
2652	}
2653	#endif
2654	}
2655	} // end READ
2656
2657	// LL request (non cachable)
2658	// We request a VCI LL transaction to CMD FSM and register
2659	// the LL/SC operation in llsc buffer.
2660	else if (m_dreq.type == iss_t::DATA_LL)
2661	{
2662	// register paddr in LLSC buffer
2663	r_dcache_llsc_paddr = paddr;
2664	r_dcache_llsc_count = LLSC_TIMEOUT;
2665	r_dcache_llsc_valid = true;
2666
2667	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2668	r_dcache_vci_ll_req = true;
2669	r_dcache_vci_paddr = paddr;
2670	r_dcache_ll_rsp_count = 0;
2671	r_dcache_fsm = DCACHE_LL_WAIT;
2672
2673	}// end LL
2674
2675	// WRITE request:
2676	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2677	// the processor and set the Dirty bit before handling the write request,
2678	// going to the DCACHE_DIRTY_GT_PTE state.
2679	// If we don't need to set the Dirty bit, we can acknowledge
2680	// the processor request, as the write arguments (including the
2681	// physical address) are registered in r_dcache_save registers,
2682	// and the write will be done in the P1 pipeline stage.
2683	else if ( m_dreq.type == iss_t::DATA_WRITE )
2684	{
2685	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2686	and not tlb_flags.d ) // Dirty bit must be set
2687	{
2688	// The PTE physical address is obtained from the nline value (dtlb),
2689	// and from the virtual address (word index)
2690	if ( tlb_flags.b ) // PTE1
2691	{
2692	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2693	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2694	}
2695	else // PTE2
2696	{
2697	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2698	(paddr_t)((m_dreq.addr>>9) & 0x38);
2699	}
2700	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2701	}
2702	else // Write request accepted
2703	{
2704	#ifdef INSTRUMENTATION
2705	m_cpt_data_write++;
2706	#endif
2707	// cleaning llsc buffer if address matching
2708	if ( paddr == r_dcache_llsc_paddr.read() )
2709	r_dcache_llsc_valid = false;
2710
2711	// response to processor
2712	m_drsp.valid = true;
2713
2714	// activating P1 stage
2715	wbuf_request = true;
2716	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2717	}
2718	} // end WRITE
2719
2720	// SC request:
2721	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2722	// the processor and set the Dirty bit before handling the write request,
2723	// going to the DCACHE_DIRTY_GT_PTE state.
2724	// If we don't need to set the Dirty bit, we test the llsc buffer:
2725	// If failure, we send a negative response to processor.
2726	// If success, we request a SC transaction to CMD FSM and go
2727	// to DCACHE_SC_WAIT state.
2728	// We don't check a possible write hit in dcache, as the cache update
2729	// is done by the coherence transaction induced by the SC...
2730	else if ( m_dreq.type == iss_t::DATA_SC )
2731	{
2732	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2733	and not tlb_flags.d ) // Dirty bit must be set
2734	{
2735	// The PTE physical address is obtained from the nline value (dtlb),
2736	// and the word index (virtual address)
2737	if ( tlb_flags.b ) // PTE1
2738	{
2739	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2740	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2741	}
2742	else // PTE2
2743	{
2744	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2745	(paddr_t)((m_dreq.addr>>9) & 0x38);
2746	}
2747	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2748	m_drsp.valid = false;
2749	m_drsp.error = false;
2750	m_drsp.rdata = 0;
2751	}
2752	else // SC request accepted
2753	{
2754	#ifdef INSTRUMENTATION
2755	m_cpt_data_sc++;
2756	#endif
2757	// checking local success
2758	if( r_dcache_llsc_valid.read() and
2759	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2760	{
2761	// request an SC CMD and go to DCACHE_SC_WAIT state
2762	r_dcache_vci_paddr = paddr;
2763	r_dcache_vci_sc_req = true;
2764	r_dcache_vci_sc_data = m_dreq.wdata;
2765	r_dcache_fsm = DCACHE_SC_WAIT;
2766	}
2767	else // local fail
2768	{
2769	m_drsp.valid = true;
2770	m_drsp.error = false;
2771	m_drsp.rdata = 0x1;
2772	}
2773	}
2774	} // end SC
2775	} // end valid_req
2776	} // end if read/write/ll/sc request
2777	} // end processor request
2778
2779	// itlb miss request
2780	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2781	{
2782	r_dcache_tlb_ins = true;
2783	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2784	r_dcache_fsm = DCACHE_TLB_MISS;
2785	}
2786
2787	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2788	r_dcache_updt_req = updt_request;
2789	r_dcache_wbuf_req = wbuf_request or
2790	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2791	break;
2792	}
2793	/////////////////////
2794	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2795	// Input arguments are:
2796	// - r_dcache_tlb_vaddr
2797	// - r_dcache_tlb_ins (true when itlb miss)
2798	// The sub-fsm access the dcache to find the missing TLB entry,
2799	// and activates the cache miss procedure in case of miss.
2800	// It bypass the first level page table access if possible.
2801	// It uses atomic access to update the R/L access bits
2802	// in the page table if required.
2803	// It directly updates the itlb or dtlb, and writes into the
2804	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2805	{
2806	uint32_t ptba = 0;
2807	bool bypass;
2808	paddr_t pte_paddr;
2809
2810	// evaluate bypass in order to skip first level page table access
2811	if ( r_dcache_tlb_ins.read() ) // itlb miss
2812	{
2813	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2814	}
2815	else // dtlb miss
2816	{
2817	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2818	}
2819
2820	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2821	{
2822	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2823	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2824	r_dcache_tlb_paddr = pte_paddr;
2825	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2826	}
2827	else // Try to read PTE2 in dcache
2828	{
2829	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2830	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2831	r_dcache_tlb_paddr = pte_paddr;
2832	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2833	}
2834
2835	#if DEBUG_DCACHE
2836	if ( m_debug_dcache_fsm )
2837	{
2838	if ( r_dcache_tlb_ins.read() )
2839	{
2840	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
2841	}
2842	else
2843	{
2844	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
2845	}
2846	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2847	<< " / BYPASS = " << bypass
2848	<< " / PTE_ADR = " << pte_paddr << std::endl;
2849	}
2850	#endif
2851
2852	break;
2853	}
2854	/////////////////////////
2855	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2856	{
2857	uint32_t entry;
2858	size_t way;
2859	size_t set;
2860	size_t word;
2861
2862	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2863	&entry,
2864	&way,
2865	&set,
2866	&word );
2867	#ifdef INSTRUMENTATION
2868	m_cpt_dcache_data_read++;
2869	m_cpt_dcache_dir_read++;
2870	#endif
2871	if ( hit ) // hit in dcache
2872	{
2873	if ( not (entry & PTE_V_MASK) ) // unmapped
2874	{
2875	if ( r_dcache_tlb_ins.read() )
2876	{
2877	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2878	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2879	r_icache_tlb_miss_req = false;
2880	r_icache_tlb_rsp_error = true;
2881	}
2882	else
2883	{
2884	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2885	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2886	m_drsp.valid = true;
2887	m_drsp.error = true;
2888	}
2889	r_dcache_fsm = DCACHE_IDLE;
2890
2891	#if DEBUG_DCACHE
2892	if ( m_debug_dcache_fsm )
2893	{
2894	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2895	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2896	<< std::dec << " / way = " << way
2897	<< std::dec << " / set = " << set
2898	<< std::dec << " / word = " << word
2899	<< std::hex << " / PTE1 = " << entry << std::endl;
2900	}
2901	#endif
2902
2903	}
2904	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2905	{
2906	// mark the cache line ac containing a PTD
2907	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2908
2909	// register bypass
2910	if ( r_dcache_tlb_ins.read() ) // itlb
2911	{
2912	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2913	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2914	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
2915	}
2916	else // dtlb
2917	{
2918	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2919	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2920	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
2921	}
2922	r_dcache_tlb_paddr =
2923	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2924	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2925	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2926
2927	#if DEBUG_DCACHE
2928	if ( m_debug_dcache_fsm )
2929	{
2930	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2931	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2932	<< std::dec << " / way = " << way
2933	<< std::dec << " / set = " << set
2934	<< std::dec << " / word = " << word
2935	<< std::hex << " / PTD = " << entry << std::endl;
2936	}
2937	#endif
2938	}
2939	else // PTE1 : we must update the TLB
2940	{
2941	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2942	r_dcache_tlb_pte_flags = entry;
2943	r_dcache_tlb_cache_way = way;
2944	r_dcache_tlb_cache_set = set;
2945	r_dcache_tlb_cache_word = word;
2946	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2947
2948	#if DEBUG_DCACHE
2949	if ( m_debug_dcache_fsm )
2950	{
2951	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2952	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2953	<< std::dec << " / way = " << way
2954	<< std::dec << " / set = " << set
2955	<< std::dec << " / word = " << word
2956	<< std::hex << " / PTE1 = " << entry << std::endl;
2957	}
2958	#endif
2959	}
2960	}
2961	else // we must load the missing cache line in dcache
2962	{
2963	r_dcache_vci_miss_req = true;
2964	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2965	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
2966	r_dcache_miss_type = PTE1_MISS;
2967	r_dcache_fsm = DCACHE_MISS_SELECT;
2968
2969	#if DEBUG_DCACHE
2970	if ( m_debug_dcache_fsm )
2971	{
2972	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
2973	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2974	}
2975	#endif
2976	}
2977	break;
2978	}
2979	////////////////////////////
2980	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2981	{
2982	size_t way;
2983	size_t set;
2984
2985	if ( r_dcache_tlb_ins.read() )
2986	{
2987	r_itlb.select( r_dcache_tlb_vaddr.read(),
2988	true, // PTE1
2989	&way,
2990	&set );
2991	#ifdef INSTRUMENTATION
2992	m_cpt_itlb_read++;
2993	#endif
2994	}
2995	else
2996	{
2997	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2998	true, // PTE1
2999	&way,
3000	&set );
3001	#ifdef INSTRUMENTATION
3002	m_cpt_dtlb_read++;
3003	#endif
3004	}
3005	r_dcache_tlb_way = way;
3006	r_dcache_tlb_set = set;
3007	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3008
3009	#if DEBUG_DCACHE
3010	if ( m_debug_dcache_fsm )
3011	{
3012	if ( r_dcache_tlb_ins.read() )
3013	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3014	else
3015	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3016	std::cout << " way = " << std::dec << way
3017	<< " / set = " << set << std::endl;
3018	}
3019	#endif
3020	break;
3021	}
3022	//////////////////////////
3023	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3024	// - if L/R bit already set, exit the sub-fsm.
3025	// - if not, we update the page table but we dont write
3026	// neither in DCACHE, nor in TLB, as this will be done by
3027	// the coherence mechanism.
3028	{
3029	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3030	uint32_t pte = r_dcache_tlb_pte_flags.read();
3031	bool pt_updt = false;
3032	bool local = true;
3033
3034	// We should compute the access locality:
3035	// The PPN MSB bits define the destination cluster index.
3036	// The m_srcid_d MSB bits define the source cluster index.
3037	// The number of bits to compare depends on the number of clusters,
3038	// and can be obtained in the mapping table.
3039	// As long as this computation is not done, all access are local.
3040
3041	if ( local ) // local access
3042	{
3043	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3044	{
3045	pt_updt = true;
3046	r_dcache_vci_cas_old = pte;
3047	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3048	pte = pte \| PTE_L_MASK;
3049	r_dcache_tlb_pte_flags = pte;
3050	}
3051	}
3052	else // remote access
3053	{
3054	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3055	{
3056	pt_updt = true;
3057	r_dcache_vci_cas_old = pte;
3058	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3059	pte = pte \| PTE_R_MASK;
3060	r_dcache_tlb_pte_flags = pte;
3061	}
3062	}
3063
3064	if ( not pt_updt ) // update TLB and return
3065	{
3066	if ( r_dcache_tlb_ins.read() )
3067	{
3068	r_itlb.write( true, // 2M page
3069	pte,
3070	0, // argument unused for a PTE1
3071	r_dcache_tlb_vaddr.read(),
3072	r_dcache_tlb_way.read(),
3073	r_dcache_tlb_set.read(),
3074	nline );
3075	#ifdef INSTRUMENTATION
3076	m_cpt_itlb_write++;
3077	#endif
3078
3079	#if DEBUG_DCACHE
3080	if ( m_debug_dcache_fsm )
3081	{
3082	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3083	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3084	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3085	r_itlb.printTrace();
3086	}
3087	#endif
3088	}
3089	else
3090	{
3091	r_dtlb.write( true, // 2M page
3092	pte,
3093	0, // argument unused for a PTE1
3094	r_dcache_tlb_vaddr.read(),
3095	r_dcache_tlb_way.read(),
3096	r_dcache_tlb_set.read(),
3097	nline );
3098	#ifdef INSTRUMENTATION
3099	m_cpt_dtlb_write++;
3100	#endif
3101
3102	#if DEBUG_DCACHE
3103	if ( m_debug_dcache_fsm )
3104	{
3105	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3106	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3107	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3108	r_dtlb.printTrace();
3109	}
3110	#endif
3111	}
3112	r_dcache_fsm = DCACHE_TLB_RETURN;
3113	}
3114	else // update page table but not TLB
3115	{
3116	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3117
3118	#if DEBUG_DCACHE
3119	if ( m_debug_dcache_fsm )
3120	{
3121	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3122	<< std::endl;
3123	}
3124	#endif
3125	}
3126	break;
3127	}
3128	/////////////////////////
3129	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3130	{
3131	uint32_t pte_flags;
3132	uint32_t pte_ppn;
3133	size_t way;
3134	size_t set;
3135	size_t word;
3136
3137	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
3138	&pte_flags,
3139	&pte_ppn,
3140	&way,
3141	&set,
3142	&word );
3143	#ifdef INSTRUMENTATION
3144	m_cpt_dcache_data_read++;
3145	m_cpt_dcache_dir_read++;
3146	#endif
3147	if ( hit ) // request hits in dcache
3148	{
3149	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3150	{
3151	if ( r_dcache_tlb_ins.read() )
3152	{
3153	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3154	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3155	r_icache_tlb_miss_req = false;
3156	r_icache_tlb_rsp_error = true;
3157	}
3158	else
3159	{
3160	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3161	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3162	m_drsp.valid = true;
3163	m_drsp.error = true;
3164	}
3165	r_dcache_fsm = DCACHE_IDLE;
3166
3167	#if DEBUG_DCACHE
3168	if ( m_debug_dcache_fsm )
3169	{
3170	std::cout << " <PROC " << name()
3171	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3172	<< " PTE_FLAGS = " << std::hex << pte_flags
3173	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3174	}
3175	#endif
3176	}
3177	else // mapped : we must update the TLB
3178	{
3179	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3180	r_dcache_tlb_pte_flags = pte_flags;
3181	r_dcache_tlb_pte_ppn = pte_ppn;
3182	r_dcache_tlb_cache_way = way;
3183	r_dcache_tlb_cache_set = set;
3184	r_dcache_tlb_cache_word = word;
3185	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3186
3187	#if DEBUG_DCACHE
3188	if ( m_debug_dcache_fsm )
3189	{
3190	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
3191	<< " PTE_FLAGS = " << std::hex << pte_flags
3192	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3193	}
3194	#endif
3195	}
3196	}
3197	else // we must load the missing cache line in dcache
3198	{
3199	r_dcache_fsm = DCACHE_MISS_SELECT;
3200	r_dcache_vci_miss_req = true;
3201	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3202	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3203	r_dcache_miss_type = PTE2_MISS;
3204
3205	#if DEBUG_DCACHE
3206	if ( m_debug_dcache_fsm )
3207	{
3208	std::cout << " <PROC " << name()
3209	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3210	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3211	}
3212	#endif
3213	}
3214	break;
3215	}
3216	////////////////////////////
3217	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3218	{
3219	size_t way;
3220	size_t set;
3221
3222	if ( r_dcache_tlb_ins.read() )
3223	{
3224	r_itlb.select( r_dcache_tlb_vaddr.read(),
3225	false, // PTE2
3226	&way,
3227	&set );
3228	#ifdef INSTRUMENTATION
3229	m_cpt_itlb_read++;
3230	#endif
3231	}
3232	else
3233	{
3234	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3235	false, // PTE2
3236	&way,
3237	&set );
3238	#ifdef INSTRUMENTATION
3239	m_cpt_dtlb_read++;
3240	#endif
3241	}
3242
3243	#if DEBUG_DCACHE
3244	if ( m_debug_dcache_fsm )
3245	{
3246	if ( r_dcache_tlb_ins.read() )
3247	std::cout << " <PROC " << name()
3248	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3249	else
3250	std::cout << " <PROC " << name()
3251	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3252	std::cout << " way = " << std::dec << way
3253	<< " / set = " << set << std::endl;
3254	}
3255	#endif
3256	r_dcache_tlb_way = way;
3257	r_dcache_tlb_set = set;
3258	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3259	break;
3260	}
3261	//////////////////////////
3262	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3263	// - if L/R bit already set, exit the sub-fsm.
3264	// - if not, we update the page table but we dont write
3265	// neither in DCACHE, nor in TLB, as this will be done by
3266	// the coherence mechanism.
3267	{
3268	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3269	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3270	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3271	bool pt_updt = false;
3272	bool local = true;
3273
3274	// We should compute the access locality:
3275	// The PPN MSB bits define the destination cluster index.
3276	// The m_srcid_d MSB bits define the source cluster index.
3277	// The number of bits to compare depends on the number of clusters,
3278	// and can be obtained in the mapping table.
3279	// As long as this computation is not done, all access are local.
3280
3281	if ( local ) // local access
3282	{
3283	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3284	{
3285	pt_updt = true;
3286	r_dcache_vci_cas_old = pte_flags;
3287	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3288	pte_flags = pte_flags \| PTE_L_MASK;
3289	r_dcache_tlb_pte_flags = pte_flags;
3290	}
3291	}
3292	else // remote access
3293	{
3294	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3295	{
3296	pt_updt = true;
3297	r_dcache_vci_cas_old = pte_flags;
3298	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3299	pte_flags = pte_flags \| PTE_R_MASK;
3300	r_dcache_tlb_pte_flags = pte_flags;
3301	}
3302	}
3303
3304	if ( not pt_updt ) // update TLB
3305	{
3306	if ( r_dcache_tlb_ins.read() )
3307	{
3308	r_itlb.write( false, // 4K page
3309	pte_flags,
3310	pte_ppn,
3311	r_dcache_tlb_vaddr.read(),
3312	r_dcache_tlb_way.read(),
3313	r_dcache_tlb_set.read(),
3314	nline );
3315	#ifdef INSTRUMENTATION
3316	m_cpt_itlb_write++;
3317	#endif
3318
3319	#if DEBUG_DCACHE
3320	if ( m_debug_dcache_fsm )
3321	{
3322	std::cout << " <PROC " << name()
3323	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3324	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3325	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3326	r_itlb.printTrace();
3327	}
3328	#endif
3329	}
3330	else
3331	{
3332	r_dtlb.write( false, // 4K page
3333	pte_flags,
3334	pte_ppn,
3335	r_dcache_tlb_vaddr.read(),
3336	r_dcache_tlb_way.read(),
3337	r_dcache_tlb_set.read(),
3338	nline );
3339	#ifdef INSTRUMENTATION
3340	m_cpt_dtlb_write++;
3341	#endif
3342
3343	#if DEBUG_DCACHE
3344	if ( m_debug_dcache_fsm )
3345	{
3346	std::cout << " <PROC " << name()
3347	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3348	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3349	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3350	r_dtlb.printTrace();
3351	}
3352	#endif
3353
3354	}
3355	r_dcache_fsm = DCACHE_TLB_RETURN;
3356	}
3357	else // update page table but not TLB
3358	{
3359	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3360
3361	#if DEBUG_DCACHE
3362	if ( m_debug_dcache_fsm )
3363	{
3364	std::cout << " <PROC " << name()
3365	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3366	}
3367	#endif
3368	}
3369	break;
3370	}
3371	////////////////////////
3372	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3373	{
3374	#if DEBUG_DCACHE
3375	if ( m_debug_dcache_fsm )
3376	{
3377	std::cout << " <PROC " << name()
3378	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3379	}
3380	#endif
3381	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3382	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3383
3384	// checking llsc reservation buffer
3385	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3386	r_dcache_llsc_valid = false;
3387
3388	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3389	r_dcache_vci_cas_req = true;
3390	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3391	break;
3392	}
3393	////////////////////////
3394	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3395	// We consume the response in rsp FIFO,
3396	// and exit the sub-fsm, but we don't
3397	// analyse the response, because we don't
3398	// care if the L/R bit update is not done.
3399	// We must take the coherence requests because
3400	// there is a risk of dead-lock
3401
3402	{
3403	// coherence request (from CC_RECEIVE FSM)
3404	if ( r_cc_receive_dcache_req.read() )
3405	{
3406	r_dcache_fsm = DCACHE_CC_CHECK;
3407	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3408	break;
3409	}
3410
3411	if ( r_vci_rsp_data_error.read() ) // bus error
3412	{
3413	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3414	std::cout << "This should not happen in this state" << std::endl;
3415	exit(0);
3416	}
3417	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3418	{
3419	#if DEBUG_DCACHE
3420	if ( m_debug_dcache_fsm )
3421	{
3422	std::cout << " <PROC " << name()
3423	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3424	}
3425	#endif
3426	vci_rsp_fifo_dcache_get = true;
3427	r_dcache_fsm = DCACHE_TLB_RETURN;
3428	}
3429	break;
3430	}
3431	///////////////////////
3432	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3433	{
3434	#if DEBUG_DCACHE
3435	if ( m_debug_dcache_fsm )
3436	{
3437	std::cout << " <PROC " << name()
3438	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3439	}
3440	#endif
3441	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3442	r_dcache_fsm = DCACHE_IDLE;
3443	break;
3444	}
3445	///////////////////////
3446	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3447	// and both itlb and dtlb must be flushed.
3448	// Caution : the itlb miss requests must be taken
3449	// to avoid dead-lock in case of simultaneous ITLB miss
3450	{
3451	// itlb miss request
3452	if ( r_icache_tlb_miss_req.read() )
3453	{
3454	r_dcache_tlb_ins = true;
3455	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3456	r_dcache_fsm = DCACHE_TLB_MISS;
3457	break;
3458	}
3459
3460	if ( not r_dcache_xtn_req.read() )
3461	{
3462	r_dtlb.flush();
3463	r_mmu_ptpr = m_dreq.wdata;
3464	r_dcache_fsm = DCACHE_IDLE;
3465	m_drsp.valid = true;
3466	}
3467	break;
3468	}
3469	/////////////////////
3470	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3471	// The coherence request must be taken
3472	// as there is a risk of dead-lock
3473	{
3474	// coherence request (from CC_RECEIVE FSM)
3475	if ( r_cc_receive_dcache_req.read() )
3476	{
3477	r_dcache_fsm = DCACHE_CC_CHECK;
3478	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3479	}
3480
3481	if ( r_wbuf.empty() )
3482	{
3483	m_drsp.valid = true;
3484	r_dcache_fsm = DCACHE_IDLE;
3485	}
3486	break;
3487	}
3488	////////////////////////
3489	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3490	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3491	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3492	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3493	// and because it can exist a simultaneous ITLB miss
3494	{
3495	// coherence request (from CC_RECEIVE FSM)
3496	if ( r_cc_receive_dcache_req.read() )
3497	{
3498	r_dcache_fsm = DCACHE_CC_CHECK;
3499	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3500	break;
3501	}
3502
3503	// itlb miss request
3504	if ( r_icache_tlb_miss_req.read() )
3505	{
3506	r_dcache_tlb_ins = true;
3507	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3508	r_dcache_fsm = DCACHE_TLB_MISS;
3509	break;
3510	}
3511
3512	// test if XTN request to icache completed
3513	if ( not r_dcache_xtn_req.read() )
3514	{
3515	r_dcache_fsm = DCACHE_IDLE;
3516	m_drsp.valid = true;
3517	}
3518	break;
3519	}
3520	/////////////////////////
3521	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3522	// r_dcache_flush_count as a slot counter,
3523	// looping in this state until all slots have been visited.
3524	// It can require two cycles per slot:
3525	// We test here the slot state, and make the actual inval
3526	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3527	// A cleanup request is generated for each valid line.
3528	// returns to IDLE and flush TLBs when last slot
3529	{
3530	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3531	{
3532	int state;
3533	uint32_t tag;
3534	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3535	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3536
3537	#ifdef INSTRUMENTATION
3538	m_cpt_dcache_dir_read++;
3539	#endif
3540	r_dcache.read_dir( way,
3541	set,
3542	&tag,
3543	&state );
3544
3545	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3546	{
3547	// request cleanup
3548	r_dcache_cc_send_req = true;
3549	r_dcache_cc_send_nline = tag * m_dcache_sets;
3550	r_dcache_cc_send_way = way;
3551	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3552
3553	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3554	r_dcache_miss_way = way;
3555	r_dcache_miss_set = set;
3556	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3557	}
3558	else if ( r_dcache_flush_count.read() ==
3559	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3560	{
3561	r_dtlb.reset();
3562	r_itlb.reset();
3563	r_dcache_fsm = DCACHE_IDLE;
3564	m_drsp.valid = true;
3565	}
3566
3567	// saturation counter
3568	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3569	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3570	}
3571	break;
3572	}
3573	////////////////////////////
3574	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3575	// and reset directory extension.
3576	// returns to IDLE and flush TLBs when last slot
3577	{
3578	size_t way = r_dcache_miss_way.read();
3579	size_t set = r_dcache_miss_set.read();
3580
3581	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3582	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3583
3584	#ifdef INSTRUMENTATION
3585	m_cpt_dcache_dir_write++;
3586	#endif
3587	r_dcache.write_dir( 0,
3588	way,
3589	set,
3590	CACHE_SLOT_STATE_ZOMBI );
3591
3592	if ( r_dcache_flush_count.read() ==
3593	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3594	{
3595	r_dtlb.reset();
3596	r_itlb.reset();
3597	r_dcache_fsm = DCACHE_IDLE;
3598	m_drsp.valid = true;
3599	}
3600	else
3601	{
3602	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3603	}
3604	break;
3605	}
3606	/////////////////////////
3607	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3608	{
3609	r_dtlb.inval(r_dcache_save_wdata.read());
3610	r_dcache_fsm = DCACHE_IDLE;
3611	m_drsp.valid = true;
3612	break;
3613	}
3614	////////////////////////////
3615	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3616	// requires 3 cycles: access tlb, read cache, inval cache
3617	// we compute the physical address in this state
3618	{
3619	paddr_t paddr;
3620	bool hit;
3621
3622	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3623	{
3624
3625	#ifdef INSTRUMENTATION
3626	m_cpt_dtlb_read++;
3627	#endif
3628	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3629	&paddr );
3630	}
3631	else // dtlb not activated
3632	{
3633	paddr = (paddr_t)r_dcache_save_wdata.read();
3634	hit = true;
3635	}
3636
3637	if ( hit ) // tlb hit
3638	{
3639	r_dcache_save_paddr = paddr;
3640	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3641	}
3642	else // tlb miss
3643	{
3644
3645	#ifdef INSTRUMENTATION
3646	m_cpt_dtlb_miss++;
3647	#endif
3648	r_dcache_tlb_ins = false; // dtlb
3649	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3650	r_dcache_fsm = DCACHE_TLB_MISS;
3651	}
3652
3653	#if DEBUG_DCACHE
3654	if ( m_debug_dcache_fsm )
3655	{
3656	std::cout << " <PROC " << name()
3657	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3658	<< " / VADDR = " << r_dcache_save_wdata.read()
3659	<< " / PADDR = " << paddr << std::endl;
3660	}
3661	#endif
3662
3663	break;
3664	}
3665	////////////////////////////
3666	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3667	// requires 2 cycles: read cache / inval cache
3668	// In this state we read dcache.
3669	{
3670	size_t way;
3671	size_t set;
3672	size_t word;
3673	int state;
3674
3675	#ifdef INSTRUMENTATION
3676	m_cpt_dcache_dir_read++;
3677	#endif
3678	r_dcache.read_dir( r_dcache_save_paddr.read(),
3679	&state,
3680	&way,
3681	&set,
3682	&word );
3683
3684	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3685	{
3686	r_dcache_xtn_way = way;
3687	r_dcache_xtn_set = set;
3688	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3689	}
3690	else // miss : nothing to do
3691	{
3692	r_dcache_fsm = DCACHE_IDLE;
3693	m_drsp.valid = true;
3694	}
3695
3696	#if DEBUG_DCACHE
3697	if ( m_debug_dcache_fsm )
3698	{
3699	std::cout << " <PROC " << name()
3700	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3701	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3702	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3703	<< " / SET = " << set
3704	<< " / WAY = " << way << std::endl;
3705	}
3706	#endif
3707	break;
3708	}
3709	////////////////////////////
3710	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3711	// Blocked if previous cleanup not completed
3712	// Test if itlb or dtlb inval is required
3713	{
3714	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3715	{
3716	size_t way = r_dcache_xtn_way.read();
3717	size_t set = r_dcache_xtn_set.read();
3718	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3719
3720	#ifdef INSTRUMENTATION
3721	m_cpt_dcache_dir_write++;
3722	#endif
3723	r_dcache.write_dir( 0,
3724	way,
3725	set,
3726	CACHE_SLOT_STATE_EMPTY );
3727
3728	// request cleanup
3729	r_dcache_cc_send_req = true;
3730	r_dcache_cc_send_nline = nline;
3731	r_dcache_cc_send_way = way;
3732	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3733
3734	// possible itlb & dtlb invalidate
3735	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3736	{
3737	r_dcache_tlb_inval_line = nline;
3738	r_dcache_tlb_inval_set = 0;
3739	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3740	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3741	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3742	}
3743	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3744	{
3745	r_itlb.reset();
3746	r_dtlb.reset();
3747	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3748	r_dcache_fsm = DCACHE_IDLE;
3749	m_drsp.valid = true;
3750	}
3751	else
3752	{
3753	r_dcache_fsm = DCACHE_IDLE;
3754	m_drsp.valid = true;
3755	}
3756
3757	#if DEBUG_DCACHE
3758	if ( m_debug_dcache_fsm )
3759	{
3760	std::cout << " <PROC " << name()
3761	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3762	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3763	}
3764	#endif
3765	}
3766	break;
3767	}
3768	//////////////////////////////
3769	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3770	{
3771	r_dcache_fsm = DCACHE_IDLE;
3772	m_drsp.valid = true;
3773	break;
3774	}
3775	////////////////////////
3776	case DCACHE_MISS_SELECT: // Try to select a slot in associative set
3777	// if previous cleanup has been sent.
3778	// Waiting in this state if no slot available
3779	// Set the r_dcache_cleanup_req flip-flop
3780	// and the r_dcache_miss_clack flip-flop
3781	// when a cleanup is required
3782	{
3783	if ( m_dreq.valid) m_cost_data_miss_frz++;
3784
3785	// coherence request (from CC_RECEIVE FSM)
3786	if ( r_cc_receive_dcache_req.read() )
3787	{
3788	r_dcache_fsm = DCACHE_CC_CHECK;
3789	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3790	break;
3791	}
3792
3793	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3794	{
3795	bool found;
3796	bool cleanup;
3797	size_t way;
3798	size_t set;
3799	paddr_t victim;
3800
3801	#ifdef INSTRUMENTATION
3802	m_cpt_dcache_dir_read++;
3803	#endif
3804	r_dcache.read_select( r_dcache_save_paddr.read(),
3805	&victim,
3806	&way,
3807	&set,
3808	&found,
3809	&cleanup );
3810	if ( found )
3811	{
3812	r_dcache_miss_way = way;
3813	r_dcache_miss_set = set;
3814
3815	if ( cleanup )
3816	{
3817	r_dcache_miss_clack = true;
3818	r_dcache_fsm = DCACHE_MISS_CLEAN;
3819	// request cleanup
3820	r_dcache_cc_send_req = true;
3821	r_dcache_cc_send_nline = victim;
3822	r_dcache_cc_send_way = way;
3823	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3824	}
3825	else
3826	{
3827	r_dcache_fsm = DCACHE_MISS_WAIT;
3828	}
3829
3830	#if DEBUG_DCACHE
3831	if ( m_debug_dcache_fsm )
3832	{
3833	std::cout << " <PROC " << name()
3834	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
3835	<< " / WAY = " << way
3836	<< " / SET = " << set
3837	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
3838	if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
3839	else std::cout << std::endl;
3840	}
3841	#endif
3842	} // end found
3843	}
3844	break;
3845	}
3846	///////////////////////
3847	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
3848	// and possibly request itlb or dtlb invalidate
3849	{
3850	if ( m_dreq.valid) m_cost_data_miss_frz++;
3851
3852	// coherence request (from CC_RECEIVE FSM)
3853	if ( r_cc_receive_dcache_req.read() )
3854	{
3855	r_dcache_fsm = DCACHE_CC_CHECK;
3856	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3857	break;
3858	}
3859
3860	size_t way = r_dcache_miss_way.read();
3861	size_t set = r_dcache_miss_set.read();
3862	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3863
3864	#ifdef INSTRUMENTATION
3865	m_cpt_dcache_dir_read++;
3866	#endif
3867	r_dcache.write_dir( 0,
3868	way,
3869	set,
3870	CACHE_SLOT_STATE_ZOMBI );
3871	#if DEBUG_DCACHE
3872	if ( m_debug_dcache_fsm )
3873	{
3874	std::cout << " <PROC " << name()
3875	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
3876	<< " / way = " << way
3877	<< " / set = " << set << std::endl;
3878	}
3879	#endif
3880	// if selective itlb & dtlb invalidate are required
3881	// the miss response is not handled before invalidate completed
3882	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3883	{
3884	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3885	r_dcache_tlb_inval_line = nline;
3886	r_dcache_tlb_inval_set = 0;
3887	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3888	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3889	}
3890	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3891	{
3892	r_itlb.reset();
3893	r_dtlb.reset();
3894	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3895	r_dcache_fsm = DCACHE_MISS_WAIT;
3896	}
3897	else
3898	{
3899	r_dcache_fsm = DCACHE_MISS_WAIT;
3900	}
3901	break;
3902	}
3903	//////////////////////
3904	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3905	// This state is in charge of error signaling
3906	// There is 5 types of error depending on the requester
3907	{
3908	if ( m_dreq.valid) m_cost_data_miss_frz++;
3909
3910	// coherence request (from CC_RECEIVE FSM)
3911	if ( r_cc_receive_dcache_req.read() )
3912	{
3913	r_dcache_fsm = DCACHE_CC_CHECK;
3914	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3915	break;
3916	}
3917
3918	if ( r_vci_rsp_data_error.read() ) // bus error
3919	{
3920	switch ( r_dcache_miss_type.read() )
3921	{
3922	case PROC_MISS:
3923	{
3924	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3925	r_mmu_dbvar = r_dcache_save_vaddr.read();
3926	m_drsp.valid = true;
3927	m_drsp.error = true;
3928	r_dcache_fsm = DCACHE_IDLE;
3929	break;
3930	}
3931	case PTE1_MISS:
3932	{
3933	if ( r_dcache_tlb_ins.read() )
3934	{
3935	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3936	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3937	r_icache_tlb_miss_req = false;
3938	r_icache_tlb_rsp_error = true;
3939	}
3940	else
3941	{
3942	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3943	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3944	m_drsp.valid = true;
3945	m_drsp.error = true;
3946	}
3947	r_dcache_fsm = DCACHE_IDLE;
3948	break;
3949	}
3950	case PTE2_MISS:
3951	{
3952	if ( r_dcache_tlb_ins.read() )
3953	{
3954	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3955	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3956	r_icache_tlb_miss_req = false;
3957	r_icache_tlb_rsp_error = true;
3958	}
3959	else
3960	{
3961	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3962	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3963	m_drsp.valid = true;
3964	m_drsp.error = true;
3965	}
3966	r_dcache_fsm = DCACHE_IDLE;
3967	break;
3968	}
3969	} // end switch type
3970	r_vci_rsp_data_error = false;
3971	}
3972	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3973	{
3974	r_dcache_miss_word = 0;
3975	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
3976	}
3977	break;
3978	}
3979	//////////////////////////
3980	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
3981	{
3982	if ( m_dreq.valid) m_cost_data_miss_frz++;
3983
3984	// coherence request (from CC_RECEIVE FSM)
3985	if ( r_cc_receive_dcache_req.read() )
3986	{
3987	r_dcache_fsm = DCACHE_CC_CHECK;
3988	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3989	break;
3990	}
3991
3992	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3993	{
3994	#ifdef INSTRUMENTATION
3995	m_cpt_dcache_data_write++;
3996	#endif
3997	r_dcache.write( r_dcache_miss_way.read(),
3998	r_dcache_miss_set.read(),
3999	r_dcache_miss_word.read(),
4000	r_vci_rsp_fifo_dcache.read() );
4001	#if DEBUG_DCACHE
4002	if ( m_debug_dcache_fsm )
4003	{
4004	std::cout << " <PROC " << name()
4005	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4006	<< " / DATA = " << r_vci_rsp_fifo_dcache.read()
4007	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4008	<< " / SET = " << r_dcache_miss_set.read()
4009	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4010	}
4011	#endif
4012	vci_rsp_fifo_dcache_get = true;
4013	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4014
4015	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4016	{
4017	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4018	}
4019	}
4020	break;
4021	}
4022	//////////////////////////
4023	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4024	// and the cleanup ack has not been received,
4025	// as indicated by the r_dcache_miss clack.
4026	// - If no matching coherence request (r_dcache_inval_miss)
4027	// switch directory slot to VALID state.
4028	// - If matching coherence request, switch directory slot
4029	// to ZOMBI state, and send a cleanup request.
4030	{
4031	if ( m_dreq.valid) m_cost_data_miss_frz++;
4032
4033	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4034	{
4035	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4036	{
4037	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
4038	{
4039	r_dcache_miss_inval = false;
4040	// request cleanup
4041	r_dcache_cc_send_req = true;
4042	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4043	r_dcache_cc_send_way = r_dcache_miss_way.read();
4044	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4045
4046	#ifdef INSTRUMENTATION
4047	m_cpt_dcache_dir_write++;
4048	#endif
4049	r_dcache.write_dir( r_dcache_save_paddr.read(),
4050	r_dcache_miss_way.read(),
4051	r_dcache_miss_set.read(),
4052	CACHE_SLOT_STATE_ZOMBI );
4053	#if DEBUG_DCACHE
4054	if ( m_debug_dcache_fsm )
4055	{
4056	std::cout << " <PROC " << name()
4057	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4058	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4059	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4060	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4061	}
4062	#endif
4063	}
4064	}
4065	else // switch slot to VALID state
4066	{
4067
4068	#ifdef INSTRUMENTATION
4069	m_cpt_dcache_dir_write++;
4070	#endif
4071	r_dcache.write_dir( r_dcache_save_paddr.read(),
4072	r_dcache_miss_way.read(),
4073	r_dcache_miss_set.read(),
4074	CACHE_SLOT_STATE_VALID );
4075
4076	#if DEBUG_DCACHE
4077	if ( m_debug_dcache_fsm )
4078	{
4079	std::cout << " <PROC " << name()
4080	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4081	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4082	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4083	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4084
4085	r_dcache.printTrace();
4086
4087
4088	}
4089	#endif
4090	// reset directory extension
4091	size_t way = r_dcache_miss_way.read();
4092	size_t set = r_dcache_miss_set.read();
4093	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4094	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4095	}
4096
4097	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4098	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4099	else r_dcache_fsm = DCACHE_IDLE;
4100	}
4101	break;
4102	}
4103	/////////////////////
4104	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4105	{
4106	// coherence request (from CC_RECEIVE FSM)
4107	if ( r_cc_receive_dcache_req.read() )
4108	{
4109	r_dcache_fsm = DCACHE_CC_CHECK;
4110	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4111	break;
4112	}
4113
4114	if ( r_vci_rsp_data_error.read() ) // bus error
4115	{
4116	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4117	r_mmu_dbvar = m_dreq.addr;
4118	r_vci_rsp_data_error = false;
4119	m_drsp.error = true;
4120	m_drsp.valid = true;
4121	r_dcache_fsm = DCACHE_IDLE;
4122	break;
4123	}
4124	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4125	{
4126	// consume data
4127	vci_rsp_fifo_dcache_get = true;
4128	r_dcache_fsm = DCACHE_IDLE;
4129
4130	// acknowledge the processor request if it has not been modified
4131	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4132	{
4133	m_drsp.valid = true;
4134	m_drsp.error = false;
4135	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4136	}
4137	}
4138	break;
4139	}
4140	/////////////////////
4141	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4142	{
4143	// coherence request (from CC_RECEIVE FSM)
4144	if ( r_cc_receive_dcache_req.read() )
4145	{
4146	r_dcache_fsm = DCACHE_CC_CHECK;
4147	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4148	break;
4149	}
4150
4151	if ( r_vci_rsp_data_error.read() ) // bus error
4152	{
4153	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4154	r_mmu_dbvar = m_dreq.addr;
4155	r_vci_rsp_data_error = false;
4156	m_drsp.error = true;
4157	m_drsp.valid = true;
4158	r_dcache_fsm = DCACHE_IDLE;
4159	break;
4160	}
4161	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4162	{
4163	// consume data
4164	vci_rsp_fifo_dcache_get = true;
4165
4166	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4167	{
4168	// set key value in llsc reservation buffer
4169	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4170	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4171	}
4172	else // last flit
4173	{
4174	// acknowledge the processor request if it has not been modified
4175	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4176	{
4177	m_drsp.valid = true;
4178	m_drsp.error = false;
4179	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4180	}
4181	r_dcache_fsm = DCACHE_IDLE;
4182	}
4183	}
4184	break;
4185	}
4186	////////////////////
4187	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4188	{
4189	// coherence request (from CC_RECEIVE FSM)
4190	if ( r_cc_receive_dcache_req.read() )
4191	{
4192	r_dcache_fsm = DCACHE_CC_CHECK;
4193	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4194	break;
4195	}
4196
4197	if ( r_vci_rsp_data_error.read() ) // bus error
4198	{
4199	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4200	r_mmu_dbvar = m_dreq.addr;
4201	r_vci_rsp_data_error = false;
4202	m_drsp.error = true;
4203	m_drsp.valid = true;
4204	r_dcache_fsm = DCACHE_IDLE;
4205	break;
4206	}
4207	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4208	{
4209	// consume response
4210	vci_rsp_fifo_dcache_get = true;
4211	m_drsp.valid = true;
4212	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4213	r_dcache_fsm = DCACHE_IDLE;
4214	}
4215	break;
4216	}
4217	//////////////////////////
4218	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4219	// before handling a processor WRITE or SC request
4220	// Input argument is r_dcache_dirty_paddr
4221	// In this first state, we get PTE value in dcache
4222	// and post a CAS request to CMD FSM
4223	{
4224	// get PTE in dcache
4225	uint32_t pte;
4226	size_t way;
4227	size_t set;
4228	size_t word; // unused
4229	int state;
4230
4231	#ifdef INSTRUMENTATION
4232	m_cpt_dcache_data_read++;
4233	m_cpt_dcache_dir_read++;
4234	#endif
4235	r_dcache.read( r_dcache_dirty_paddr.read(),
4236	&pte,
4237	&way,
4238	&set,
4239	&word,
4240	&state );
4241
4242	assert( (state == CACHE_SLOT_STATE_VALID) and
4243	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4244
4245	// request CAS transaction to CMD_FSM
4246	r_dcache_dirty_way = way;
4247	r_dcache_dirty_set = set;
4248
4249	// check llsc reservation buffer
4250	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4251	r_dcache_llsc_valid = false;
4252
4253	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4254	r_dcache_vci_cas_req = true;
4255	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4256	r_dcache_vci_cas_old = pte;
4257	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4258	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4259
4260	#if DEBUG_DCACHE
4261	if ( m_debug_dcache_fsm )
4262	{
4263	std::cout << " <PROC " << name()
4264	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4265	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4266	<< " / PTE_VALUE = " << pte << std::dec
4267	<< " / SET = " << set
4268	<< " / WAY = " << way << std::endl;
4269	}
4270	#endif
4271	break;
4272	}
4273	///////////////////////
4274	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4275	// and return to IDLE state when response is received.
4276	// we don't care if the CAS is a failure:
4277	// - if the CAS is a success, the coherence mechanism
4278	// updates the local copy.
4279	// - if the CAS is a failure, we just retry the write.
4280	{
4281	// coherence request (from CC_RECEIVE FSM)
4282	if ( r_cc_receive_dcache_req.read() )
4283	{
4284	r_dcache_fsm = DCACHE_CC_CHECK;
4285	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4286	break;
4287	}
4288
4289	if ( r_vci_rsp_data_error.read() ) // bus error
4290	{
4291	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4292	std::cout << "This should not happen in this state" << std::endl;
4293	exit(0);
4294	}
4295	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4296	{
4297	vci_rsp_fifo_dcache_get = true;
4298	r_dcache_fsm = DCACHE_IDLE;
4299
4300	#if DEBUG_DCACHE
4301	if ( m_debug_dcache_fsm )
4302	{
4303	std::cout << " <PROC " << name()
4304	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4305	}
4306	#endif
4307	}
4308	break;
4309	}
4310	/////////////////////
4311	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4312	// handling coherence requests for DCACHE.
4313	// If there is a matching pending miss on the modified cache
4314	// line this is signaled in the r_dcache_miss inval flip-flop.
4315	// If the updated (or invalidated) cache line has copies in TLBs
4316	// these TLB copies are invalidated.
4317	// The return state is defined in r_dcache_fsm_cc_save
4318	{
4319	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4320	paddr_t mask = ~((m_dcache_words<<2)-1);
4321
4322
4323	if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK)
4324	// We switch the directory slot to EMPTY state
4325	// and reset r_icache_miss_clack if the cleanup ack
4326	// is matching a pending miss.
4327	{
4328
4329	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4330
4331	#ifdef INSTRUMENTATION
4332	m_cpt_dcache_dir_write++;
4333	#endif
4334	r_dcache.write_dir( 0,
4335	r_cc_receive_dcache_way.read(),
4336	r_cc_receive_dcache_set.read(),
4337	CACHE_SLOT_STATE_EMPTY);
4338
4339	if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and
4340	(r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) )
4341	r_dcache_miss_clack = false;
4342
4343	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4344	r_cc_receive_dcache_req = false;
4345	#if DEBUG_DCACHE
4346	if ( m_debug_dcache_fsm )
4347	{
4348	std::cout << " <PROC " << name()
4349	<< " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
4350	<< " set = " << r_cc_receive_dcache_set.read()
4351	<< " / way = " << r_cc_receive_dcache_way.read() << std::endl;
4352	}
4353	#endif
4354	}
4355	else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4356	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4357	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
4358	{
4359	// signaling matching
4360	r_dcache_miss_inval = true;
4361
4362	// in case of update, go to CC_UPDT
4363	// JUST TO POP THE FIFO
4364	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4365	{
4366	r_dcache_fsm = DCACHE_CC_UPDT;
4367	r_dcache_cc_word = r_cc_receive_word_idx.read();
4368	// just pop the fifo , don't write in icache
4369	r_dcache_cc_need_write = false;
4370	}
4371	// the request is dealt with
4372	else
4373	{
4374	r_cc_receive_dcache_req = false;
4375	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4376	}
4377
4378	#if DEBUG_DCACHE
4379	if ( m_debug_dcache_fsm )
4380	{
4381	std::cout << " <PROC " << name()
4382	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4383	<< " PADDR = " << std::hex << paddr << std::endl;
4384	}
4385	#endif
4386
4387	}
4388	else // no match
4389	{
4390	int state;
4391	size_t way;
4392	size_t set;
4393	size_t word;
4394
4395	#ifdef INSTRUMENTATION
4396	m_cpt_dcache_dir_read++;
4397	#endif
4398	r_dcache.read_dir( paddr,
4399	&state,
4400	&way,
4401	&set,
4402	&word ); // unused
4403
4404	r_dcache_cc_way = way;
4405	r_dcache_cc_set = set;
4406
4407	if ( state == CACHE_SLOT_STATE_VALID) // hit
4408	{
4409	// need to update the cache state
4410	r_dcache_cc_need_write = true;
4411	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4412	{
4413	r_dcache_fsm = DCACHE_CC_UPDT;
4414	r_dcache_cc_word = r_cc_receive_word_idx.read();
4415	}
4416	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4417	{
4418	r_dcache_fsm = DCACHE_CC_INVAL;
4419	}
4420	else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
4421	{
4422	r_dcache_fsm = DCACHE_CC_BROADCAST;
4423	}
4424	}
4425	else // miss
4426	{
4427	// multicast acknowledgement required in case of update
4428	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4429	{
4430	r_dcache_fsm = DCACHE_CC_UPDT;
4431	r_dcache_cc_word = r_cc_receive_word_idx.read();
4432	// just pop the fifo , don't write in icache
4433	r_dcache_cc_need_write = false;
4434	}
4435	else // No response needed
4436	{
4437	r_cc_receive_dcache_req = false;
4438	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4439	}
4440	}
4441
4442	#if DEBUG_DCACHE
4443	if ( m_debug_dcache_fsm )
4444	{
4445	std::cout << " <PROC " << name()
4446	<< " DCACHE_CC_CHECK> Coherence request received:"
4447	<< " PADDR = " << std::hex << paddr
4448	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4449	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4450	}
4451	#endif
4452	}
4453	break;
4454	}
4455	/////////////////////
4456	case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state,
4457	// after possible invalidation of copies in TLBs
4458	{
4459	size_t way = r_dcache_cc_way.read();
4460	size_t set = r_dcache_cc_set.read();
4461
4462	if (r_dcache_cc_need_write.read())
4463	{
4464	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4465	{
4466	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4467	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4468	r_dcache_tlb_inval_set = 0;
4469	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4470	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4471	break;
4472	}
4473	else
4474	{
4475	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4476	{
4477	r_itlb.reset();
4478	r_dtlb.reset();
4479	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4480
4481	#if DEBUG_DCACHE
4482	if ( m_debug_dcache_fsm )
4483	{
4484	std::cout << " <PROC " << name()
4485	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4486	}
4487	#endif
4488	}
4489
4490	r_dcache.write_dir( 0,
4491	way,
4492	set,
4493	CACHE_SLOT_STATE_EMPTY );
4494
4495	r_dcache_cc_need_write = false;
4496
4497	#if DEBUG_DCACHE
4498	if ( m_debug_dcache_fsm )
4499	{
4500	std::cout << " <PROC " << name()
4501	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4502	<< " / WAY = " << way
4503	<< " / SET = " << set << std::endl;
4504	}
4505	#endif
4506	}
4507	}
4508	// multicast acknowledgement
4509	// send a request to cc_send_fsm
4510	if(not r_dcache_cc_send_req.read()) // cc_send is available
4511	{
4512	// coherence request completed
4513	r_cc_receive_dcache_req = false;
4514	// request multicast acknowledgement
4515	r_dcache_cc_send_req = true;
4516	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4517	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4518
4519	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4520	}
4521	//else wait for previous cc_send request to be sent
4522	break;
4523	}
4524	///////////////////
4525	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4526	// after possible invalidation of copies in TLBs
4527	{
4528	size_t word = r_dcache_cc_word.read();
4529	size_t way = r_dcache_cc_way.read();
4530	size_t set = r_dcache_cc_set.read();
4531
4532	if (r_cc_receive_updt_fifo_be.rok())
4533	{
4534	if (r_dcache_cc_need_write.read())
4535	{
4536	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4537	{
4538	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4539	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4540	r_dcache_tlb_inval_set = 0;
4541	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4542	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4543	break;
4544	}
4545
4546	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4547	{
4548	r_itlb.reset();
4549	r_dtlb.reset();
4550	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4551
4552	#if DEBUG_DCACHE
4553	if ( m_debug_dcache_fsm )
4554	{
4555	std::cout << " <PROC " << name()
4556	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4557	}
4558	#endif
4559	}
4560
4561	#ifdef INSTRUMENTATION
4562	m_cpt_dcache_data_write++;
4563	#endif
4564	r_dcache.write( way,
4565	set,
4566	word,
4567	r_cc_receive_updt_fifo_data.read(),
4568	r_cc_receive_updt_fifo_be.read() );
4569
4570	r_dcache_cc_word = word + 1;
4571
4572	#if DEBUG_DCACHE
4573	if ( m_debug_dcache_fsm )
4574	{
4575	std::cout << " <PROC " << name()
4576	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4577	<< " / WAY = " << way
4578	<< " / SET = " << set
4579	<< " / WORD = " << word
4580	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4581	}
4582	#endif
4583	}
4584
4585	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4586	{
4587	// no need to write in the cache anymore
4588	r_dcache_cc_need_write = false;
4589
4590	// wait to send a request to cc_send_fsm
4591	if(not r_icache_cc_send_req.read())
4592	// cc_send is available
4593	{
4594	//consume last fifo flit if eop and request to cc_send possible
4595	cc_receive_updt_fifo_get = true;
4596
4597	// coherence request completed
4598	r_cc_receive_dcache_req = false;
4599
4600	// request multicast acknowledgement
4601	r_dcache_cc_send_req = true;
4602	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4603	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4604
4605	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4606	}
4607	}
4608	else
4609	{
4610	//consume fifo if not eop
4611	cc_receive_updt_fifo_get = true;
4612	}
4613	}
4614	break;
4615	}
4616	/////////////////////////
4617	case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state
4618	// and request a cleanup, after possible
4619	// invalidation of copies in TLBs
4620	{
4621	size_t way = r_dcache_cc_way.read();
4622	size_t set = r_dcache_cc_set.read();
4623	paddr_t nline = r_cc_receive_dcache_nline.read();
4624
4625	if (r_dcache_cc_need_write.read())
4626	{
4627	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4628	{
4629	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4630	r_dcache_tlb_inval_line = nline;
4631	r_dcache_tlb_inval_set = 0;
4632	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4633	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4634	break;
4635	}
4636	else
4637	{
4638	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4639	{
4640	r_itlb.reset();
4641	r_dtlb.reset();
4642	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4643
4644	#if DEBUG_DCACHE
4645	if ( m_debug_dcache_fsm )
4646	{
4647	std::cout << " <PROC " << name()
4648	<< " DCACHE_CC_BROADCAST> Flush DTLB & ITLB" << std::endl;
4649	}
4650	#endif
4651	}
4652
4653	#ifdef INSTRUMENTATION
4654	m_cpt_dcache_dir_write++;
4655	#endif
4656	r_dcache.write_dir( 0,
4657	way,
4658	set,
4659	CACHE_SLOT_STATE_ZOMBI );
4660
4661	r_dcache_cc_need_write = false;
4662	#if DEBUG_DCACHE
4663	if ( m_debug_dcache_fsm )
4664	{
4665	std::cout << " <PROC " << name()
4666	<< " DCACHE_CC_BROADCAST > Slot goes to ZOMBI state "
4667	<< " SET = " << set
4668	<< " / WAY = " << way << std::endl;
4669	}
4670	#endif
4671	}
4672	}
4673	// cleanup
4674	// send a request to cc_send_fsm
4675	if(not r_dcache_cc_send_req.read()) // cc_send is available
4676	{
4677	// coherence request completed
4678	r_cc_receive_dcache_req = false;
4679	// request cleanup
4680	r_dcache_cc_send_req = true;
4681	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4682	r_dcache_cc_send_way = r_dcache_cc_way.read();
4683	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4684
4685	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4686	}
4687	//else wait for previous cc_send request to be sent
4688	break;
4689	}
4690	///////////////////////////
4691	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4692	// It makes assumption: m_itlb_sets == m_dtlb_sets
4693	// All ways are handled in parallel.
4694	// We enter this state when a DCACHE line is modified,
4695	// and there is a copy in itlb or dtlb.
4696	// It can be caused by:
4697	// - a coherence inval or updt transaction,
4698	// - a line inval caused by a cache miss
4699	// - a processor XTN inval request,
4700	// - a WRITE hit,
4701	// - a Dirty bit update
4702	// Input arguments are:
4703	// - r_dcache_tlb_inval_line
4704	// - r_dcache_tlb_inval_set
4705	// - r_dcache_fsm_scan_save
4706	{
4707	paddr_t line = r_dcache_tlb_inval_line.read();
4708	size_t set = r_dcache_tlb_inval_set.read();
4709	size_t way;
4710	bool ok;
4711
4712	for ( way = 0 ; way < m_itlb_ways ; way++ )
4713	{
4714	ok = r_itlb.inval( line, way, set );
4715
4716	#if DEBUG_DCACHE
4717	if ( m_debug_dcache_fsm and ok )
4718	{
4719	std::cout << " <PROC " << name()
4720	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4721	<< " line = " << line << std::dec
4722	<< " / set = " << set
4723	<< " / way = " << way << std::endl;
4724	}
4725	#endif
4726	}
4727
4728	for ( way = 0 ; way < m_dtlb_ways ; way++ )
4729	{
4730	ok = r_dtlb.inval( line, way, set );
4731
4732	#if DEBUG_DCACHE
4733	if ( m_debug_dcache_fsm and ok )
4734	{
4735	std::cout << " <PROC " << name()
4736	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4737	<< " line = " << line << std::dec
4738	<< " / set = " << set
4739	<< " / way = " << way << std::endl;
4740	}
4741	#endif
4742	}
4743
4744	// return to the calling state when TLB inval completed
4745	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
4746	{
4747	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4748	}
4749	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
4750	break;
4751	}
4752	} // end switch r_dcache_fsm
4753
4754	///////////////// wbuf update ///////////////////////////////////////////////////////
4755	r_wbuf.update();
4756
4757	///////////////// llsc update ///////////////////////////////////////////////////////
4758	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
4759	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
4760
4761	//////////////// test processor frozen //////////////////////////////////////////////
4762	// The simulation exit if the number of consecutive frozen cycles
4763	// is larger than the m_max_frozen_cycles (constructor parameter)
4764	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4765	{
4766	m_cpt_frz_cycles++; // used for instrumentation
4767	m_cpt_stop_simulation++; // used for debug
4768	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4769	{
4770	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4771	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4772	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4773	<< std::endl;
4774	r_iss.dump();
4775	exit(1);
4776	}
4777	}
4778	else
4779	{
4780	m_cpt_stop_simulation = 0;
4781	}
4782
4783	/////////// execute one iss cycle /////////////////////////////////
4784	{
4785	uint32_t it = 0;
4786	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4787	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4788	}
4789
4790	////////////////////////////////////////////////////////////////////////////
4791	// The VCI_CMD FSM controls the following ressources:
4792	// - r_vci_cmd_fsm
4793	// - r_vci_cmd_min
4794	// - r_vci_cmd_max
4795	// - r_vci_cmd_cpt
4796	// - r_vci_cmd_imiss_prio
4797	// - wbuf (reset)
4798	// - r_icache_miss_req (reset)
4799	// - r_icache_unc_req (reset)
4800	// - r_dcache_vci_miss_req (reset)
4801	// - r_dcache_vci_unc_req (reset)
4802	// - r_dcache_vci_ll_req (reset)
4803	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4804	// - r_dcache_vci_cas_req (reset)
4805	//
4806	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4807	// There are 8 request types, with the following priorities :
4808	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4809	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4810	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4811	// 4 - Instruction Uncachable : r_icache_unc_req
4812	// 5 - Data Write : r_wbuf.rok()
4813	// 6 - Data Linked Load : r_dcache_vci_ll_req
4814	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4815	// 8 - Compare And Swap : r_dcache_vci_cas_req
4816	//
4817	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4818	// and the VCI_RSP_FSM are fully desynchronized.
4819	//
4820	// VCI formats:
4821	// According to the VCI advanced specification, all read requests packets
4822	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4823	// are one word packets.
4824	// For write burst packets, all words are in the same cache line,
4825	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4826	// The sc command packet implements actually a compare-and-swap mechanism
4827	// and the packet contains two flits.
4828	////////////////////////////////////////////////////////////////////////////////////
4829
4830	switch ( r_vci_cmd_fsm.read() )
4831	{
4832	//////////////
4833	case CMD_IDLE:
4834	{
4835	// DDACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
4836	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
4837	// to check a possible pending write on the same cache line.
4838	// As there is only one possible access per cycle to write buffer, we implement
4839	// a round-robin priority between DCACHE and ICACHE for this access,
4840	// using the r_vci_cmd_imiss_prio flip-flop.
4841
4842	size_t wbuf_min;
4843	size_t wbuf_max;
4844
4845	bool dcache_unc_req = r_dcache_vci_unc_req.read() and
4846	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4847
4848	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
4849	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4850
4851	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
4852	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4853
4854	bool icache_miss_req = r_icache_miss_req.read() and
4855	( not (r_dcache_vci_miss_req.read() or
4856	r_dcache_vci_ll_req.read() or
4857	r_dcache_vci_unc_req.read())
4858	or r_vci_cmd_imiss_prio.read() ) ;
4859
4860	// 1 - Data Read Miss
4861	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4862	{
4863	r_vci_cmd_fsm = CMD_DATA_MISS;
4864	r_dcache_vci_miss_req = false;
4865	r_vci_cmd_imiss_prio = true;
4866	// m_cpt_dmiss_transaction++;
4867	}
4868	// 2 - Data Read Uncachable
4869	else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4870	{
4871	r_vci_cmd_fsm = CMD_DATA_UNC;
4872	r_dcache_vci_unc_req = false;
4873	// m_cpt_dunc_transaction++;
4874	}
4875	// 3 - Data Linked Load
4876	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4877	{
4878	r_dcache_vci_ll_req = false;
4879	r_vci_cmd_fsm = CMD_DATA_LL;
4880	// m_cpt_ll_transaction++;
4881	}
4882	// 4 - Instruction Miss
4883	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4884	{
4885	r_vci_cmd_fsm = CMD_INS_MISS;
4886	r_icache_miss_req = false;
4887	r_vci_cmd_imiss_prio = false;
4888	// m_cpt_imiss_transaction++;
4889	}
4890	// 5 - Instruction Uncachable
4891	else if ( r_icache_unc_req.read() )
4892	{
4893	r_vci_cmd_fsm = CMD_INS_UNC;
4894	r_icache_unc_req = false;
4895	// m_cpt_iunc_transaction++;
4896	}
4897	// 6 - Data Write
4898	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4899	{
4900	r_vci_cmd_fsm = CMD_DATA_WRITE;
4901	r_vci_cmd_cpt = wbuf_min;
4902	r_vci_cmd_min = wbuf_min;
4903	r_vci_cmd_max = wbuf_max;
4904	// m_cpt_write_transaction++;
4905	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4906	}
4907	// 7 - Data Store Conditionnal
4908	else if ( r_dcache_vci_sc_req.read() )
4909	{
4910	r_dcache_vci_sc_req = false;
4911	r_vci_cmd_cpt = 0;
4912	r_vci_cmd_fsm = CMD_DATA_SC;
4913	// m_cpt_sc_transaction++;
4914	}
4915	// 8 - Compare And Swap
4916	else if ( r_dcache_vci_cas_req.read() )
4917	{
4918	r_vci_cmd_fsm = CMD_DATA_CAS;
4919	r_dcache_vci_cas_req = false;
4920	r_vci_cmd_cpt = 0;
4921	// m_cpt_cas_transaction++;
4922	}
4923	break;
4924	}
4925	////////////////////
4926	case CMD_DATA_WRITE:
4927	{
4928	if ( p_vci_ini_d.cmdack.read() )
4929	{
4930	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4931	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4932	{
4933	r_vci_cmd_fsm = CMD_IDLE ;
4934	r_wbuf.sent() ;
4935	}
4936	}
4937	break;
4938	}
4939	/////////////////
4940	case CMD_DATA_SC:
4941	case CMD_DATA_CAS:
4942	{
4943	// The CAS and SC VCI commands contain two flits
4944	if ( p_vci_ini_d.cmdack.read() )
4945	{
4946	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4947	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4948	}
4949	break;
4950	}
4951	//////////////////
4952	case CMD_INS_MISS:
4953	case CMD_INS_UNC:
4954	case CMD_DATA_MISS:
4955	case CMD_DATA_UNC:
4956	case CMD_DATA_LL:
4957	{
4958	// all read VCI commands contain one single flit
4959	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4960	break;
4961	}
4962
4963	} // end switch r_vci_cmd_fsm
4964
4965	//////////////////////////////////////////////////////////////////////////
4966	// The VCI_RSP FSM controls the following ressources:
4967	// - r_vci_rsp_fsm:
4968	// - r_vci_rsp_fifo_icache (push)
4969	// - r_vci_rsp_fifo_dcache (push)
4970	// - r_vci_rsp_data_error (set)
4971	// - r_vci_rsp_ins_error (set)
4972	// - r_vci_rsp_cpt
4973	// - r_dcache_vci_sc_req (reset when SC response recieved)
4974	//
4975	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4976	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
4977	// to identify the transactions.
4978	//
4979	// VCI vormat:
4980	// This component checks the response packet length and accepts only
4981	// single word packets for write response packets.
4982	//
4983	// Error handling:
4984	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
4985	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
4986	// flip_flop and the error is signaled by the DCACHE FSM.
4987	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
4988	// flip_flop and the error is signaled by the ICACHE FSM.
4989	// In case of Cleanup Error, the simulation stops with an error message...
4990	//////////////////////////////////////////////////////////////////////////
4991
4992	switch ( r_vci_rsp_fsm.read() )
4993	{
4994	//////////////
4995	case RSP_IDLE:
4996	{
4997	if ( p_vci_ini_d.rspval.read() )
4998	{
4999	r_vci_rsp_cpt = 0;
5000
5001	if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
5002	{
5003	r_vci_rsp_fsm = RSP_DATA_UNC;
5004	}
5005	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5006	{
5007	r_vci_rsp_fsm = RSP_DATA_MISS;
5008	}
5009	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5010	{
5011	r_vci_rsp_fsm = RSP_INS_UNC;
5012	}
5013	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5014	{
5015	r_vci_rsp_fsm = RSP_INS_MISS;
5016	}
5017	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_WRITE )
5018	{
5019	r_vci_rsp_fsm = RSP_DATA_WRITE;
5020	}
5021	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_CAS )
5022	{
5023	r_vci_rsp_fsm = RSP_DATA_UNC;
5024	}
5025	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_LL )
5026	{
5027	r_vci_rsp_fsm = RSP_DATA_LL;
5028	}
5029	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_SC )
5030	{
5031	r_vci_rsp_fsm = RSP_DATA_UNC;
5032	}
5033	else
5034	{
5035	assert(false and "Unexpected VCI response");
5036	}
5037	}
5038	break;
5039	}
5040	//////////////////
5041	case RSP_INS_MISS:
5042	{
5043	if ( p_vci_ini_d.rspval.read() )
5044	{
5045	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5046	{
5047	r_vci_rsp_ins_error = true;
5048	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5049	}
5050	else // no error reported
5051	{
5052	if ( r_vci_rsp_fifo_icache.wok() )
5053	{
5054	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
5055	"The VCI response packet for instruction miss is too long" );
5056
5057	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5058	vci_rsp_fifo_icache_put = true,
5059	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
5060	if ( p_vci_ini_d.reop.read() )
5061	{
5062	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
5063	"The VCI response packet for instruction miss is too short");
5064
5065	r_vci_rsp_fsm = RSP_IDLE;
5066	}
5067	}
5068	}
5069	}
5070	break;
5071	}
5072	/////////////////
5073	case RSP_INS_UNC:
5074	{
5075	if (p_vci_ini_d.rspval.read() )
5076	{
5077	assert( p_vci_ini_d.reop.read() and
5078	"illegal VCI response packet for uncachable instruction");
5079
5080	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5081	{
5082	r_vci_rsp_ins_error = true;
5083	r_vci_rsp_fsm = RSP_IDLE;
5084	}
5085	else // no error reported
5086	{
5087	if ( r_vci_rsp_fifo_icache.wok())
5088	{
5089	vci_rsp_fifo_icache_put = true;
5090	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
5091	r_vci_rsp_fsm = RSP_IDLE;
5092	}
5093	}
5094	}
5095	break;
5096	}
5097	///////////////////
5098	case RSP_DATA_MISS:
5099	{
5100	if ( p_vci_ini_d.rspval.read() )
5101	{
5102	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5103	{
5104	r_vci_rsp_data_error = true;
5105	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5106	}
5107	else // no error reported
5108	{
5109	if ( r_vci_rsp_fifo_dcache.wok() )
5110	{
5111	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5112	"The VCI response packet for data miss is too long");
5113
5114	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5115	vci_rsp_fifo_dcache_put = true,
5116	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5117	if ( p_vci_ini_d.reop.read() )
5118	{
5119	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5120	"The VCI response packet for data miss is too short");
5121
5122	r_vci_rsp_fsm = RSP_IDLE;
5123	}
5124	}
5125	}
5126	}
5127	break;
5128	}
5129	//////////////////
5130	case RSP_DATA_UNC:
5131	{
5132	if (p_vci_ini_d.rspval.read() )
5133	{
5134	assert( p_vci_ini_d.reop.read() and
5135	"illegal VCI response packet for uncachable read data");
5136
5137	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5138	{
5139	r_vci_rsp_data_error = true;
5140	r_vci_rsp_fsm = RSP_IDLE;
5141	}
5142	else // no error reported
5143	{
5144	if ( r_vci_rsp_fifo_dcache.wok())
5145	{
5146	vci_rsp_fifo_dcache_put = true;
5147	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5148	r_vci_rsp_fsm = RSP_IDLE;
5149	}
5150	}
5151	}
5152	break;
5153	}
5154	////////////////////
5155	case RSP_DATA_LL:
5156	{
5157	if ( p_vci_ini_d.rspval.read() )
5158	{
5159	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5160	{
5161	r_vci_rsp_data_error = true;
5162	r_vci_rsp_fsm = RSP_IDLE;
5163	}
5164	if (r_vci_rsp_cpt.read() == 0) //first flit
5165	{
5166	if(r_vci_rsp_fifo_dcache.wok())
5167	{
5168	assert(!p_vci_ini_d.reop.read() &&
5169	"illegal VCI response packet for LL");
5170	vci_rsp_fifo_dcache_put = true;
5171	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5172	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5173	}
5174	break;
5175	}
5176	else // last flit
5177	{
5178	if(r_vci_rsp_fifo_dcache.wok())
5179	{
5180	assert(p_vci_ini_d.reop.read() &&
5181	"illegal VCI response packet for LL");
5182	vci_rsp_fifo_dcache_put = true;
5183	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5184	r_vci_rsp_fsm = RSP_IDLE;
5185	}
5186	break;
5187	}
5188	}
5189	break;
5190	}
5191	////////////////////
5192	case RSP_DATA_WRITE:
5193	{
5194	if (p_vci_ini_d.rspval.read())
5195	{
5196	assert( p_vci_ini_d.reop.read() and
5197	"a VCI response packet must contain one flit for a write transaction");
5198
5199	r_vci_rsp_fsm = RSP_IDLE;
5200	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read();
5201	bool cacheable = r_wbuf.completed(wbuf_index);
5202	if ( not cacheable ) r_dcache_pending_unc_write = false;
5203	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5204	}
5205	break;
5206	}
5207	} // end switch r_vci_rsp_fsm
5208
5209	/////////////////////////////////////////////////////////////////////////////////////
5210	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5211	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5212	// and ICACHE FSM) that are served with a round-robin priority.
5213	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5214	// soon as the request has been sent.
5215	/////////////////////////////////////////////////////////////////////////////////////
5216	switch ( r_cc_send_fsm.read() )
5217	{
5218	///////////////////////////
5219	case CC_SEND_IDLE:
5220	{
5221	///////////////////////////////////////////////////////
5222	// handling round robin between icache and dcache : //
5223	// we first check for the last client and listen for //
5224	// a request of the other, then update the client //
5225	///////////////////////////////////////////////////////
5226	// r_cc_send_last_client : 0 dcache 1 icache
5227	bool update_last_client;
5228	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5229	{
5230	if(r_icache_cc_send_req.read()) // request from icache
5231	update_last_client = 1; // update last client to icache
5232	}
5233	else // last client was icache
5234	{
5235	if(r_dcache_cc_send_req.read()) // request from dcache
5236	update_last_client = 0; // update last client to dcache
5237	}
5238	r_cc_send_last_client = update_last_client;
5239
5240	// if there is an actual request
5241	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5242	{
5243	// test if the new client is dcache and has a cleanup request
5244	if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5245	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5246	// test if the new client is dcache and has a multi acknowledgement request
5247	else if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5248	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5249	// test if the new client is icache and has a cleanup request
5250	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5251	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5252	// test if the new client is icache and has a multi acknowledgement request
5253	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5254	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5255	}
5256	break;
5257	}
5258	///////////////////////////
5259	case CC_SEND_CLEANUP_1:
5260	{
5261	// wait for the first flit to be consumed
5262	if(p_dspin_out.read.read())
5263	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5264
5265	break;
5266	}
5267	///////////////////////////
5268	case CC_SEND_CLEANUP_2:
5269	{
5270	assert( p_dspin_out.read.read() and
5271	"The interconnect should accept the second cleanup flit instantly" );
5272
5273	// wait for the second flit to be consumed
5274	if(p_dspin_out.read.read())
5275	{
5276	if(r_cc_send_last_client.read() == 0) // dcache active request
5277	r_dcache_cc_send_req = false; // reset dcache request
5278	else // icache active request
5279	r_icache_cc_send_req = false; // reset icache request
5280
5281	// go back to idle state
5282	r_cc_send_fsm = CC_SEND_IDLE;
5283	}
5284	break;
5285	}
5286	///////////////////////////
5287	case CC_SEND_MULTI_ACK:
5288	{
5289	// wait for the flit to be consumed
5290	if(p_dspin_out.read.read())
5291	{
5292	if(r_cc_send_last_client.read() == 0) // dcache active request
5293	r_dcache_cc_send_req = false; // reset dcache request
5294	else // icache active request
5295	r_icache_cc_send_req = false; // reset icache request
5296	// go back to idle state
5297	r_cc_send_fsm = CC_SEND_IDLE;
5298	}
5299	break;
5300	}
5301	} // end switch CC_SEND FSM
5302
5303	///////////////////////////////////////////////////////////////////////////////
5304	// C_RECEIVE FSM
5305	// This FSM receive all coherence packets on a DSPIN40 port.
5306	// There is 4 packet types:
5307	// - CC_DATA_INVAL : DCACHE invalidate request
5308	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5309	// - CC_INST_INVAL : ICACHE invalidate request
5310	// - CC_INST_UPDT : ICACHE update request (multi-words)
5311	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5312	// - CC_DATA_CLACK : DCACHE cleanup acknowledge
5313	// - CC_INST_CLACK : ICACHE cleanup acknowledge
5314	//////////////////////////////////////////////////////////////////////////////
5315	switch( r_cc_receive_fsm.read() )
5316	{
5317	/////////////////////
5318	case CC_RECEIVE_IDLE:
5319	{
5320	// a coherence request has arrived
5321	if (p_dspin_in.write.read())
5322	{
5323	// initialize dspin received data
5324	uint64_t receive_data = p_dspin_in.data.read();
5325	// initialize coherence packet type
5326	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_TYPE);
5327	// initialize data/ins flip_flop (0 data / 1 ins)
5328	r_cc_receive_data_ins = (bool)(receive_type & 0x1);
5329	// test for a broadcast
5330	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_BC))
5331	{
5332	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5333	}
5334	// test for a CLACK
5335	else if ((receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_DATA) or
5336	(receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_INST))
5337	{
5338	r_cc_receive_fsm = CC_RECEIVE_CLACK;
5339	}
5340	// test for a multi updt
5341	else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or
5342	(receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST))
5343	{
5344	r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER;
5345	}
5346	// test for a multi inval
5347	else
5348	{
5349	r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER;
5350	}
5351	}
5352	break;
5353	}
5354	//////////////////////
5355	case CC_RECEIVE_CLACK:
5356	{
5357	// initialize dspin received data
5358	uint64_t receive_data = p_dspin_in.data.read();
5359
5360	// for data CLACK, wait for dcache to take the request
5361	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5362	{
5363	// request dcache to handle the CLACK
5364	r_cc_receive_dcache_req = true;
5365	r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
5366	r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5367	r_cc_receive_dcache_type = CC_TYPE_CLACK;
5368	// get back to idle state
5369	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5370	break;
5371	}
5372	// for ins CLACK, wait for icache to take the request
5373	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5374	{
5375	// request icache to handle the CLACK
5376	r_cc_receive_icache_req = true;
5377	r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5378	r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_icache_ways)))-1);
5379	r_cc_receive_icache_type = CC_TYPE_CLACK;
5380	// get back to idle state
5381	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5382	break;
5383	}
5384	// keep waiting for the correct cache to accept the request
5385	break;
5386	}
5387	///////////////////////////////
5388	case CC_RECEIVE_BRDCAST_HEADER:
5389	{
5390	// no actual data in the HEADER, just skip to second flit
5391	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5392	break;
5393	}
5394	//////////////////////////////
5395	case CC_RECEIVE_BRDCAST_NLINE:
5396	{
5397	// initialize dspin received data
5398	uint64_t receive_data = p_dspin_in.data.read();
5399	// wait for both dcache and icache to take the request
5400	// TODO maybe we need to wait for both only to leave the state, but
5401	// not to actually post a request to an available cache => need a
5402	// flip_flop to check that ?
5403	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
5404	{
5405	// request dcache to handle the BROADCAST
5406	r_cc_receive_dcache_req = true;
5407	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5408	r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
5409	// request icache to handle the BROADCAST
5410	r_cc_receive_icache_req = true;
5411	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5412	r_cc_receive_icache_type = CC_TYPE_BRDCAST;
5413	// get back to idle state
5414	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5415	break;
5416	}
5417	// keep waiting for the caches to accept the request
5418	break;
5419	}
5420	/////////////////////////////
5421	case CC_RECEIVE_INVAL_HEADER:
5422	{
5423	// sample updt tab index in the HEADER, than skip to second flit
5424	uint64_t receive_data = p_dspin_in.data.read();
5425	// for data INVAL, wait for dcache to take the request
5426	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5427	{
5428	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5429	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5430	break;
5431	}
5432	// for ins INVAL, wait for icache to take the request
5433	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5434	{
5435	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5436	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5437	break;
5438	}
5439	// keep waiting for the correct cache to accept the request
5440	break;
5441	}
5442	////////////////////////////
5443	case CC_RECEIVE_INVAL_NLINE:
5444	{
5445	// sample nline in the second flit
5446	uint64_t receive_data = p_dspin_in.data.read();
5447	// for data INVAL, wait for dcache to take the request
5448	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5449	{
5450	// request dcache to handle the INVAL
5451	r_cc_receive_dcache_req = true;
5452	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5453	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5454	// get back to idle state
5455	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5456	break;
5457	}
5458	// for ins INVAL, wait for icache to take the request
5459	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5460	{
5461	// request icache to handle the INVAL
5462	r_cc_receive_icache_req = true;
5463	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5464	r_cc_receive_icache_type = CC_TYPE_INVAL;
5465	// get back to idle state
5466	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5467	break;
5468	}
5469	// we should never get there
5470	assert ( false && "CC_RECEIVE_INVAL_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req\n");
5471	}
5472	////////////////////////////
5473	case CC_RECEIVE_UPDT_HEADER:
5474	{
5475	// sample updt tab index in the HEADER, than skip to second flit
5476	uint64_t receive_data = p_dspin_in.data.read();
5477	// for data INVAL, wait for dcache to take the request and fifo to
5478	// be empty
5479	if ((r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())
5480	{
5481	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5482	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5483	break;
5484	}
5485	// for ins INVAL, wait for icache to take the request and fifo to be
5486	// empty
5487	if ((r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())
5488	{
5489	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5490	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5491	break;
5492	}
5493	// keep waiting for the correct cache to accept the request
5494	break;
5495	}
5496	///////////////////////////
5497	case CC_RECEIVE_UPDT_NLINE:
5498	{
5499	// sample nline and word index in the second flit
5500	uint64_t receive_data = p_dspin_in.data.read();
5501	// for data INVAL, wait for dcache to take the request and fifo to
5502	// be empty
5503	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty())
5504	{
5505	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5506	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5507	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5508	// get back to idle state
5509	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5510	break;
5511	}
5512	// for ins INVAL, wait for icache to take the request and fifo to be
5513	// empty
5514	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty())
5515	{
5516	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5517	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5518	r_cc_receive_icache_type = CC_TYPE_UPDT;
5519	// get back to idle state
5520	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5521	break;
5522	}
5523	// we should never get there
5524	assert ( false && "CC_RECEIVE_UPDT_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req or r_cc_receive_fifo\n");
5525	break;
5526	}
5527	//////////////////////////
5528	case CC_RECEIVE_UPDT_DATA:
5529	{
5530	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5531	r_cc_receive_dcache_req = true;
5532	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5533	r_cc_receive_icache_req = true;
5534
5535	// sample data, be and eop
5536	uint64_t receive_data = p_dspin_in.data.read();
5537	// wait for the fifo
5538	if (r_cc_receive_updt_fifo_be.wok())
5539	{
5540	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5541	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5542	// sample eop to test for state exit
5543	bool flit_eop = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_EOP);
5544	cc_receive_updt_fifo_eop = flit_eop;
5545	cc_receive_updt_fifo_put = true;
5546	if(flit_eop)
5547	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5548	}
5549	break;
5550	}
5551	} // end switch CC_RECEIVE FSM
5552
5553	///////////////// Response FIFOs update //////////////////////
5554	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5555	vci_rsp_fifo_icache_put,
5556	vci_rsp_fifo_icache_data);
5557
5558	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5559	vci_rsp_fifo_dcache_put,
5560	vci_rsp_fifo_dcache_data);
5561	///////////////// updt FIFO update //////////////////////
5562	//TODO check this
5563	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5564	cc_receive_updt_fifo_put,
5565	cc_receive_updt_fifo_be);
5566	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5567	cc_receive_updt_fifo_put,
5568	cc_receive_updt_fifo_data);
5569	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5570	cc_receive_updt_fifo_put,
5571	cc_receive_updt_fifo_eop);
5572
5573	} // end transition()
5574
5575	///////////////////////
5576	tmpl(void)::genMoore()
5577	///////////////////////
5578	{
5579
5580	// VCI initiator command on the direct network
5581	// it depends on the CMD FSM state
5582
5583	p_vci_ini_d.pktid = 0;
5584	p_vci_ini_d.srcid = m_srcid_d;
5585	p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_CAS);
5586	p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_CAS);
5587	p_vci_ini_d.wrap = false;
5588	p_vci_ini_d.clen = 0;
5589	p_vci_ini_d.cfixed = false;
5590
5591	switch ( r_vci_cmd_fsm.read() ) {
5592
5593	case CMD_IDLE:
5594	p_vci_ini_d.cmdval = false;
5595	p_vci_ini_d.address = 0;
5596	p_vci_ini_d.wdata = 0;
5597	p_vci_ini_d.be = 0;
5598	p_vci_ini_d.trdid = 0;
5599	p_vci_ini_d.pktid = 0;
5600	p_vci_ini_d.plen = 0;
5601	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5602	p_vci_ini_d.eop = false;
5603	break;
5604
5605	case CMD_INS_MISS:
5606	p_vci_ini_d.cmdval = true;
5607	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5608	p_vci_ini_d.wdata = 0;
5609	p_vci_ini_d.be = 0xF;
5610	p_vci_ini_d.trdid = 0;
5611	p_vci_ini_d.pktid = TYPE_READ_INS_MISS;
5612	p_vci_ini_d.plen = m_icache_words<<2;
5613	p_vci_ini_d.cmd = vci_param::CMD_READ;
5614	p_vci_ini_d.eop = true;
5615	break;
5616
5617	case CMD_INS_UNC:
5618	p_vci_ini_d.cmdval = true;
5619	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
5620	p_vci_ini_d.wdata = 0;
5621	p_vci_ini_d.be = 0xF;
5622	p_vci_ini_d.trdid = 0;
5623	p_vci_ini_d.pktid = TYPE_READ_INS_UNC;
5624	p_vci_ini_d.plen = 4;
5625	p_vci_ini_d.cmd = vci_param::CMD_READ;
5626	p_vci_ini_d.eop = true;
5627	break;
5628
5629	case CMD_DATA_MISS:
5630	p_vci_ini_d.cmdval = true;
5631	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5632	p_vci_ini_d.wdata = 0;
5633	p_vci_ini_d.be = 0xF;
5634	p_vci_ini_d.trdid = 0;
5635	p_vci_ini_d.pktid = TYPE_READ_DATA_MISS;
5636	p_vci_ini_d.plen = m_dcache_words << 2;
5637	p_vci_ini_d.cmd = vci_param::CMD_READ;
5638	p_vci_ini_d.eop = true;
5639	break;
5640
5641	case CMD_DATA_UNC:
5642	p_vci_ini_d.cmdval = true;
5643	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5644	p_vci_ini_d.wdata = 0;
5645	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
5646	p_vci_ini_d.trdid = 0;
5647	p_vci_ini_d.pktid = TYPE_READ_DATA_UNC;
5648	p_vci_ini_d.plen = 4;
5649	p_vci_ini_d.cmd = vci_param::CMD_READ;
5650	p_vci_ini_d.eop = true;
5651	break;
5652
5653	case CMD_DATA_WRITE:
5654	p_vci_ini_d.cmdval = true;
5655	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5656	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5657	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5658	p_vci_ini_d.trdid = r_wbuf.getIndex();
5659	p_vci_ini_d.pktid = TYPE_WRITE;
5660	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5661	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
5662	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5663	break;
5664
5665	case CMD_DATA_LL:
5666	p_vci_ini_d.cmdval = true;
5667	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5668	p_vci_ini_d.wdata = 0;
5669	p_vci_ini_d.be = 0xF;
5670	p_vci_ini_d.trdid = 0;
5671	p_vci_ini_d.pktid = TYPE_LL;
5672	p_vci_ini_d.plen = 8;
5673	p_vci_ini_d.cmd = vci_param::CMD_LOCKED_READ;
5674	p_vci_ini_d.eop = true;
5675	break;
5676
5677	case CMD_DATA_SC:
5678	p_vci_ini_d.cmdval = true;
5679	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5680	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_llsc_key.read();
5681	else p_vci_ini_d.wdata = r_dcache_vci_sc_data.read();
5682	p_vci_ini_d.be = 0xF;
5683	p_vci_ini_d.trdid = 0;
5684	p_vci_ini_d.pktid = TYPE_SC;
5685	p_vci_ini_d.plen = 8;
5686	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5687	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
5688	break;
5689
5690	case CMD_DATA_CAS:
5691	p_vci_ini_d.cmdval = true;
5692	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5693	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_cas_old.read();
5694	else p_vci_ini_d.wdata = r_dcache_vci_cas_new.read();
5695	p_vci_ini_d.be = 0xF;
5696	p_vci_ini_d.trdid = 0;
5697	p_vci_ini_d.pktid = TYPE_CAS;
5698	p_vci_ini_d.plen = 8;
5699	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5700	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
5701	break;
5702	} // end switch r_vci_cmd_fsm
5703
5704	// VCI initiator response on the direct network
5705	// it depends on the VCI RSP state
5706
5707	switch (r_vci_rsp_fsm.read() )
5708	{
5709	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
5710	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
5711	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
5712	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5713	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5714	case RSP_DATA_LL : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5715	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
5716	} // end switch r_vci_rsp_fsm
5717
5718	/////////////////
5719	// CC_SEND FSM //
5720	/////////////////
5721	uint64_t dspin_send_data = 0;
5722	switch ( r_cc_send_fsm.read() )
5723	{
5724	///////////////////////////
5725	case CC_SEND_IDLE:
5726	{
5727	p_dspin_out.write = false;
5728	break;
5729	}
5730	///////////////////////////
5731	case CC_SEND_CLEANUP_1:
5732	{
5733	// initialize dspin send data
5734	DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_EOP);
5735	DspinDhccpParam::dspin_set(dspin_send_data,m_srcid_c,DspinDhccpParam::CLEANUP_SRCID);
5736	DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_BC);
5737	// dcache active request
5738	if(r_cc_send_last_client.read() == 0)
5739	{
5740	// compute global id
5741	uint32_t nline_size = vci_param::N - (uint32_log2(m_dcache_words)) - (uint32_log2(vci_param::B));
5742	uint64_t global_id = (uint64_t) r_dcache_cc_send_nline.read();
5743	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5744
5745	DspinDhccpParam::dspin_set(dspin_send_data,
5746	global_id,
5747	DspinDhccpParam::CLEANUP_DEST);
5748
5749	DspinDhccpParam::dspin_set(dspin_send_data,
5750	r_dcache_cc_send_nline.read() & 0x300000000ULL,
5751	DspinDhccpParam::CLEANUP_NLINE_MSB);
5752
5753	DspinDhccpParam::dspin_set(dspin_send_data,
5754	r_dcache_cc_send_way.read(),
5755	DspinDhccpParam::CLEANUP_WAY_INDEX);
5756
5757	DspinDhccpParam::dspin_set(dspin_send_data,
5758	DspinDhccpParam::TYPE_CLEANUP_DATA,
5759	DspinDhccpParam::FROM_L1_TYPE);
5760	}
5761	// icache active request
5762	else
5763	{
5764	// compute global id
5765	uint32_t nline_size = vci_param::N - (uint32_log2(m_icache_words)) - (uint32_log2(vci_param::B));
5766	uint64_t global_id = (uint64_t) r_icache_cc_send_nline.read();
5767	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5768
5769	DspinDhccpParam::dspin_set(dspin_send_data,
5770	global_id,
5771	DspinDhccpParam::CLEANUP_DEST);
5772
5773	DspinDhccpParam::dspin_set(dspin_send_data,
5774	r_icache_cc_send_nline.read() & 0x300000000ULL,
5775	DspinDhccpParam::CLEANUP_NLINE_MSB);
5776
5777	DspinDhccpParam::dspin_set(dspin_send_data,
5778	r_icache_cc_send_way.read(),
5779	DspinDhccpParam::CLEANUP_WAY_INDEX);
5780
5781	DspinDhccpParam::dspin_set(dspin_send_data,
5782	DspinDhccpParam::TYPE_CLEANUP_INST,
5783	DspinDhccpParam::FROM_L1_TYPE);
5784	}
5785	// send flit
5786	p_dspin_out.data = dspin_send_data;
5787	p_dspin_out.write = true;
5788	break;
5789	}
5790	///////////////////////////
5791	case CC_SEND_CLEANUP_2:
5792	{
5793	// initialize dspin send data
5794	DspinDhccpParam::dspin_set(dspin_send_data,1,DspinDhccpParam::FROM_L1_EOP);
5795	// dcache active request
5796	if(r_cc_send_last_client.read() == 0)
5797	{
5798	DspinDhccpParam::dspin_set(dspin_send_data,
5799	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
5800	DspinDhccpParam::CLEANUP_NLINE_LSB);
5801	}
5802	// icache active request
5803	else
5804	{
5805	DspinDhccpParam::dspin_set(dspin_send_data,
5806	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
5807	DspinDhccpParam::CLEANUP_NLINE_LSB);
5808	}
5809	// send flit
5810	p_dspin_out.data = dspin_send_data;
5811	p_dspin_out.write = true;
5812	break;
5813	}
5814	///////////////////////////
5815	case CC_SEND_MULTI_ACK:
5816	{
5817	// initialize dspin send data
5818	DspinDhccpParam::dspin_set(dspin_send_data,1,DspinDhccpParam::FROM_L1_EOP);
5819	DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_BC);
5820	DspinDhccpParam::dspin_set(dspin_send_data,
5821	DspinDhccpParam::TYPE_MULTI_ACK,
5822	DspinDhccpParam::FROM_L1_TYPE);
5823	// dcache active request
5824	if(r_cc_send_last_client.read() == 0)
5825	{
5826	// compute global id
5827	uint32_t nline_size = vci_param::N - (uint32_log2(m_dcache_words)) - (uint32_log2(vci_param::B));
5828	uint64_t global_id = (uint64_t) r_dcache_cc_send_nline.read();
5829	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5830
5831	DspinDhccpParam::dspin_set(dspin_send_data,
5832	global_id,
5833	DspinDhccpParam::MULTI_ACK_DEST);
5834
5835	DspinDhccpParam::dspin_set(dspin_send_data,
5836	r_dcache_cc_send_updt_tab_idx.read(),
5837	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5838	}
5839	// icache active request
5840	else
5841	{
5842	// compute global id
5843	uint32_t nline_size = vci_param::N - (uint32_log2(m_icache_words)) - (uint32_log2(vci_param::B));
5844	uint64_t global_id = (uint64_t) r_icache_cc_send_nline.read();
5845	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5846
5847	DspinDhccpParam::dspin_set(dspin_send_data,
5848	global_id,
5849	DspinDhccpParam::MULTI_ACK_DEST);
5850
5851	DspinDhccpParam::dspin_set(dspin_send_data,
5852	r_icache_cc_send_updt_tab_idx.read(),
5853	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5854	}
5855	// send flit
5856	p_dspin_out.data = dspin_send_data;
5857	p_dspin_out.write = true;
5858	break;
5859	}
5860	} // end switch CC_SEND FSM
5861
5862	////////////////////
5863	// CC_RECEIVE FSM //
5864	////////////////////
5865	switch( r_cc_receive_fsm.read() )
5866	{
5867	/////////////////////
5868	case CC_RECEIVE_IDLE:
5869	{
5870	p_dspin_in.read = false;
5871	break;
5872	}
5873	//////////////////////
5874	case CC_RECEIVE_CLACK:
5875	{
5876	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5877	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5878	p_dspin_in.read = true;
5879	else
5880	p_dspin_in.read = false;
5881	break;
5882	}
5883	///////////////////////////////
5884	case CC_RECEIVE_BRDCAST_HEADER:
5885	{
5886	p_dspin_in.read = true;
5887	break;
5888	}
5889	//////////////////////////////
5890	case CC_RECEIVE_BRDCAST_NLINE:
5891	{
5892	// TODO maybe we need to wait for both only to leave the state, but
5893	// not to actually post a request to an available cache => need a
5894	// flip_flop to check that ?
5895	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
5896	p_dspin_in.read = true;
5897	else
5898	p_dspin_in.read = false;
5899	break;
5900	}
5901	/////////////////////////////
5902	case CC_RECEIVE_INVAL_HEADER:
5903	{
5904	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5905	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5906	p_dspin_in.read = true;
5907	else
5908	p_dspin_in.read = false;
5909	break;
5910	}
5911	////////////////////////////
5912	case CC_RECEIVE_INVAL_NLINE:
5913	{
5914	p_dspin_in.read = true;
5915	break;
5916	}
5917	////////////////////////////
5918	case CC_RECEIVE_UPDT_HEADER:
5919	{
5920	if (((r_cc_receive_data_ins.read() == 0) and
5921	not r_cc_receive_dcache_req.read() and
5922	r_cc_receive_updt_fifo_be.empty())
5923	or
5924	((r_cc_receive_data_ins.read() == 1) and
5925	not r_cc_receive_icache_req.read()) and
5926	r_cc_receive_updt_fifo_be.empty())
5927	p_dspin_in.read = true;
5928	else
5929	p_dspin_in.read = false;
5930	break;
5931	}
5932	///////////////////////////
5933	case CC_RECEIVE_UPDT_NLINE:
5934	{
5935	if (((r_cc_receive_data_ins.read() == 0) and
5936	not (r_cc_receive_dcache_req.read()) and
5937	r_cc_receive_updt_fifo_be.empty())
5938	or
5939	((r_cc_receive_data_ins.read() == 1) and
5940	not (r_cc_receive_icache_req.read()) and
5941	r_cc_receive_updt_fifo_be.empty()))
5942	p_dspin_in.read = true;
5943	else
5944	p_dspin_in.read = false;
5945	break;
5946	}
5947	//////////////////////////
5948	case CC_RECEIVE_UPDT_DATA:
5949	{
5950	if (r_cc_receive_updt_fifo_be.wok())
5951	p_dspin_in.read = true;
5952	else
5953	p_dspin_in.read = false;
5954	break;
5955	}
5956	} // end switch CC_RECEIVE FSM
5957
5958	} // end genMoore
5959
5960	}}
5961
5962	// Local Variables:
5963	// tab-width: 4
5964	// c-basic-offset: 4
5965	// c-file-offsets:((innamespace . 0)(inline-open . 0))
5966	// indent-tabs-mode: nil
5967	// End:
5968
5969	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
Plural-Forms: nplurals=2; plural=(n != 1)
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Generated-By: Babel 2.8.0