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source: branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper_dspin_coherence.cpp @ 338

Last change on this file since 338 was 338, checked in by joannou, 11 years ago
In vci_cc_vcache_wrapper_dspin_coherence, modified both states DCACHE_TLB_PTE1_GET and DCACHE_TLB_PTE2_GET to take into account the zombi state of a chache line In vci_mem_cache_dspin_coherence, added so traces
File size: 230.8 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper_dspin_coherence.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CLEANUP 0
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_INVAL",
65	"ICACHE_CC_UPDT",
66	"ICACHE_CC_BROADCAST",
67	"ICACHE_CC_SEND_WAIT",
68	};
69
70	const char *dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IT_INVAL",
90	"DCACHE_XTN_DC_FLUSH",
91	"DCACHE_XTN_DC_FLUSH_GO",
92	"DCACHE_XTN_DC_INVAL_VA",
93	"DCACHE_XTN_DC_INVAL_PA",
94	"DCACHE_XTN_DC_INVAL_END",
95	"DCACHE_XTN_DC_INVAL_GO",
96	"DCACHE_XTN_DT_INVAL",
97
98	"DCACHE_DIRTY_PTE_GET",
99	"DCACHE_DIRTY_WAIT",
100
101	"DCACHE_MISS_SELECT",
102	"DCACHE_MISS_CLEAN",
103	"DCACHE_MISS_WAIT",
104	"DCACHE_MISS_DATA_UPDT",
105	"DCACHE_MISS_DIR_UPDT",
106
107	"DCACHE_UNC_WAIT",
108	"DCACHE_LL_WAIT",
109	"DCACHE_SC_WAIT",
110
111	"DCACHE_CC_CHECK",
112	"DCACHE_CC_INVAL",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_BROADCAST",
115	"DCACHE_CC_SEND_WAIT",
116
117	"DCACHE_INVAL_TLB_SCAN",
118	};
119
120	const char *cmd_fsm_state_str[] = {
121	"CMD_IDLE",
122	"CMD_INS_MISS",
123	"CMD_INS_UNC",
124	"CMD_DATA_MISS",
125	"CMD_DATA_UNC",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char *rsp_fsm_state_str[] = {
133	"RSP_IDLE",
134	"RSP_INS_MISS",
135	"RSP_INS_UNC",
136	"RSP_DATA_MISS",
137	"RSP_DATA_UNC",
138	"RSP_DATA_LL",
139	"RSP_DATA_WRITE",
140	};
141
142	const char *cc_receive_fsm_state_str[] = {
143	"CC_RECEIVE_IDLE",
144	"CC_RECEIVE_CLACK",
145	"CC_RECEIVE_BRDCAST_HEADER",
146	"CC_RECEIVE_BRDCAST_NLINE",
147	"CC_RECEIVE_INVAL_HEADER",
148	"CC_RECEIVE_INVAL_NLINE",
149	"CC_RECEIVE_UPDT_HEADER",
150	"CC_RECEIVE_UPDT_NLINE",
151	"CC_RECEIVE_UPDT_DATA",
152	};
153
154	const char *cc_send_fsm_state_str[] = {
155	"CC_SEND_IDLE",
156	"CC_SEND_CLEANUP_1",
157	"CC_SEND_CLEANUP_2",
158	"CC_SEND_MULTI_ACK",
159	};
160	}
161
162	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t>
163
164	using soclib::common::uint32_log2;
165
166	/////////////////////////////////
167	tmpl(/**/)::VciCcVCacheWrapper(
168	sc_module_name name,
169	int proc_id,
170	const soclib::common::MappingTable &mtd,
171	const soclib::common::MappingTable &mtc,
172	const soclib::common::IntTab &initiator_index_d,
173	const soclib::common::IntTab &initiator_index_c,
174	const soclib::common::IntTab &target_index_c,
175	size_t itlb_ways,
176	size_t itlb_sets,
177	size_t dtlb_ways,
178	size_t dtlb_sets,
179	size_t icache_ways,
180	size_t icache_sets,
181	size_t icache_words,
182	size_t dcache_ways,
183	size_t dcache_sets,
184	size_t dcache_words,
185	size_t wbuf_nlines,
186	size_t wbuf_nwords,
187	size_t x_width,
188	size_t y_width,
189	uint32_t memory_cache_local_id,
190	uint32_t max_frozen_cycles,
191	uint32_t debug_start_cycle,
192	bool debug_ok)
193	: soclib::caba::BaseModule(name),
194
195	p_clk("clk"),
196	p_resetn("resetn"),
197	p_vci_ini_d("vci_ini_d"),
198	p_dspin_in("dspin_in"),
199	p_dspin_out("dspin_out"),
200
201	m_cacheability_table(mtd.getCacheabilityTable()),
202	m_segment(mtc.getSegment(target_index_c)),
203	m_srcid_d(mtd.indexForId(initiator_index_d)),
204	m_srcid_c(mtc.indexForId(initiator_index_c)),
205
206	m_itlb_ways(itlb_ways),
207	m_itlb_sets(itlb_sets),
208
209	m_dtlb_ways(dtlb_ways),
210	m_dtlb_sets(dtlb_sets),
211
212	m_icache_ways(icache_ways),
213	m_icache_sets(icache_sets),
214	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
215	m_icache_words(icache_words),
216
217	m_dcache_ways(dcache_ways),
218	m_dcache_sets(dcache_sets),
219	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
220	m_dcache_words(dcache_words),
221
222	m_x_width(x_width),
223	m_y_width(y_width),
224
225	m_memory_cache_local_id(memory_cache_local_id),
226	m_proc_id(proc_id),
227	m_max_frozen_cycles(max_frozen_cycles),
228	m_paddr_nbits(vci_param::N),
229
230	m_debug_start_cycle(debug_start_cycle),
231	m_debug_ok(debug_ok),
232
233	r_mmu_ptpr("r_mmu_ptpr"),
234	r_mmu_mode("r_mmu_mode"),
235	r_mmu_word_lo("r_mmu_word_lo"),
236	r_mmu_word_hi("r_mmu_word_hi"),
237	r_mmu_ibvar("r_mmu_ibvar"),
238	r_mmu_dbvar("r_mmu_dbvar"),
239	r_mmu_ietr("r_mmu_ietr"),
240	r_mmu_detr("r_mmu_detr"),
241
242	r_icache_fsm("r_icache_fsm"),
243	r_icache_fsm_save("r_icache_fsm_save"),
244	r_icache_vci_paddr("r_icache_vci_paddr"),
245	r_icache_vaddr_save("r_icache_vaddr_save"),
246
247	r_icache_miss_way("r_icache_miss_way"),
248	r_icache_miss_set("r_icache_miss_set"),
249	r_icache_miss_word("r_icache_miss_word"),
250	r_icache_miss_inval("r_icache_miss_inval"),
251	r_icache_miss_clack("r_icache_miss_clack"),
252
253	r_icache_cc_way("r_icache_cc_way"),
254	r_icache_cc_set("r_icache_cc_set"),
255	r_icache_cc_word("r_icache_cc_word"),
256	r_icache_cc_need_write("r_icache_cc_need_write"),
257
258	r_icache_flush_count("r_icache_flush_count"),
259
260	r_icache_miss_req("r_icache_miss_req"),
261	r_icache_unc_req("r_icache_unc_req"),
262
263	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
264	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
265
266	r_icache_cc_send_req("r_icache_cc_send_req"),
267	r_icache_cc_send_type("r_icache_cc_send_type"),
268	r_icache_cc_send_nline("r_icache_cc_send_nline"),
269	r_icache_cc_send_way("r_icache_cc_send_way"),
270	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
271
272	r_dcache_fsm("r_dcache_fsm"),
273	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
274	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
275
276	r_dcache_wbuf_req("r_dcache_wbuf_req"),
277	r_dcache_updt_req("r_dcache_updt_req"),
278	r_dcache_save_vaddr("r_dcache_save_vaddr"),
279	r_dcache_save_wdata("r_dcache_save_wdata"),
280	r_dcache_save_be("r_dcache_save_be"),
281	r_dcache_save_paddr("r_dcache_save_paddr"),
282	r_dcache_save_cacheable("r_dcache_save_cacheable"),
283	r_dcache_save_cache_way("r_dcache_save_cache_way"),
284	r_dcache_save_cache_set("r_dcache_save_cache_set"),
285	r_dcache_save_cache_word("r_dcache_save_cache_word"),
286
287	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
288	r_dcache_dirty_way("r_dcache_dirty_way"),
289	r_dcache_dirty_set("r_dcache_dirty_set"),
290
291	r_dcache_vci_paddr("r_dcache_vci_paddr"),
292	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
293	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
294	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
295	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
296	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
297	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
298	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
299	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
300	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
301
302	r_dcache_xtn_way("r_dcache_xtn_way"),
303	r_dcache_xtn_set("r_dcache_xtn_set"),
304
305	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
306
307	r_dcache_miss_type("r_dcache_miss_type"),
308	r_dcache_miss_word("r_dcache_miss_word"),
309	r_dcache_miss_way("r_dcache_miss_way"),
310	r_dcache_miss_set("r_dcache_miss_set"),
311	r_dcache_miss_inval("r_dcache_miss_inval"),
312
313	r_dcache_cc_way("r_dcache_cc_way"),
314	r_dcache_cc_set("r_dcache_cc_set"),
315	r_dcache_cc_word("r_dcache_cc_word"),
316	r_dcache_cc_need_write("r_dcache_cc_need_write"),
317
318	r_dcache_flush_count("r_dcache_flush_count"),
319
320	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
321
322	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
323	r_dcache_tlb_ins("r_dcache_tlb_ins"),
324	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
325	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
326	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
327	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
328	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
329	r_dcache_tlb_way("r_dcache_tlb_way"),
330	r_dcache_tlb_set("r_dcache_tlb_set"),
331
332	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
333	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
334
335	r_dcache_xtn_req("r_dcache_xtn_req"),
336	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
337
338	r_dcache_cc_send_req("r_dcache_cc_send_req"),
339	r_dcache_cc_send_type("r_dcache_cc_send_type"),
340	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
341	r_dcache_cc_send_way("r_dcache_cc_send_way"),
342	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
343
344	r_vci_cmd_fsm("r_vci_cmd_fsm"),
345	r_vci_cmd_min("r_vci_cmd_min"),
346	r_vci_cmd_max("r_vci_cmd_max"),
347	r_vci_cmd_cpt("r_vci_cmd_cpt"),
348	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
349
350	r_vci_rsp_fsm("r_vci_rsp_fsm"),
351	r_vci_rsp_cpt("r_vci_rsp_cpt"),
352	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
353	r_vci_rsp_data_error("r_vci_rsp_data_error"),
354	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
355	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
356
357	r_cc_send_fsm("r_cc_send_fsm"),
358	r_cc_send_last_client("r_cc_send_last_client"),
359
360	r_cc_receive_fsm("r_cc_receive_fsm"),
361	r_cc_receive_data_ins("r_cc_receive_data_ins"),
362	r_cc_receive_word_idx("r_cc_receive_word_idx"),
363	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
364	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
365	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
366
367	r_cc_receive_icache_req("r_cc_receive_icache_req"),
368	r_cc_receive_icache_type("r_cc_receive_icache_type"),
369	r_cc_receive_icache_way("r_cc_receive_icache_way"),
370	r_cc_receive_icache_set("r_cc_receive_icache_set"),
371	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
372	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
373
374	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
375	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
376	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
377	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
378	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
379	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
380
381	r_iss(this->name(), proc_id),
382	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
383	r_icache("icache", icache_ways, icache_sets, icache_words),
384	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
385	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
386	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
387	{
388	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
389	"Need more PLEN bits.");
390
391	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
392	"Need more TRDID bits.");
393
394	assert( (icache_words == dcache_words) and
395	"icache_words and dcache_words parameters must be equal");
396
397	assert( (itlb_sets == dtlb_sets) and
398	"itlb_sets and dtlb_sets parameters must be etqual");
399
400	assert( (itlb_ways == dtlb_ways) and
401	"itlb_ways and dtlb_ways parameters must be etqual");
402
403	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
404	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
405	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
406	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
407	(uint32_log2(m_icache_words<<2));
408
409	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
410
411	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
412	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
413
414	SC_METHOD(transition);
415	dont_initialize();
416	sensitive << p_clk.pos();
417
418	SC_METHOD(genMoore);
419	dont_initialize();
420	sensitive << p_clk.neg();
421
422	typename iss_t::CacheInfo cache_info;
423	cache_info.has_mmu = true;
424	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
425	cache_info.icache_assoc = icache_ways;
426	cache_info.icache_n_lines = icache_sets;
427	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
428	cache_info.dcache_assoc = dcache_ways;
429	cache_info.dcache_n_lines = dcache_sets;
430	r_iss.setCacheInfo(cache_info);
431	}
432
433	/////////////////////////////////////
434	tmpl(/**/)::~VciCcVCacheWrapper()
435	/////////////////////////////////////
436	{
437	delete [] r_dcache_in_tlb;
438	delete [] r_dcache_contains_ptd;
439	}
440
441	////////////////////////
442	tmpl(void)::print_cpi()
443	////////////////////////
444	{
445	std::cout << name() << " CPI = "
446	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
447	}
448
449	////////////////////////////////////
450	tmpl(void)::print_trace(size_t mode)
451	////////////////////////////////////
452	{
453	// b0 : write buffer trace
454	// b1 : write buffer verbose
455	// b2 : dcache trace
456	// b3 : icache trace
457	// b4 : dtlb trace
458	// b5 : itlb trace
459
460	std::cout << std::dec << "PROC " << name() << std::endl;
461
462	std::cout << " " << m_ireq << std::endl;
463	std::cout << " " << m_irsp << std::endl;
464	std::cout << " " << m_dreq << std::endl;
465	std::cout << " " << m_drsp << std::endl;
466
467	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
468	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
469	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
470	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
471	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
472	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()];
473	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
474	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
475	std::cout << std::endl;
476
477	if(mode & 0x01)
478	{
479	r_wbuf.printTrace((mode>>1)&1);
480	}
481	if(mode & 0x04)
482	{
483	std::cout << " Data Cache" << std::endl;
484	r_dcache.printTrace();
485	}
486	if(mode & 0x08)
487	{
488	std::cout << " Instruction Cache" << std::endl;
489	r_icache.printTrace();
490	}
491	if(mode & 0x10)
492	{
493	std::cout << " Data TLB" << std::endl;
494	r_dtlb.printTrace();
495	}
496	if(mode & 0x20)
497	{
498	std::cout << " Instruction TLB" << std::endl;
499	r_itlb.printTrace();
500	}
501	}
502
503	//////////////////////////////////////////
504	tmpl(void)::cache_monitor( paddr_t addr )
505	//////////////////////////////////////////
506	{
507	size_t cache_way;
508	size_t cache_set;
509	size_t cache_word;
510	uint32_t cache_rdata;
511	bool cache_hit = r_dcache.read_neutral( addr,
512	&cache_rdata,
513	&cache_way,
514	&cache_set,
515	&cache_word );
516	bool icache_hit = r_icache.read_neutral( addr,
517	&cache_rdata,
518	&cache_way,
519	&cache_set,
520	&cache_word );
521	if ( cache_hit != m_debug_previous_hit )
522	{
523	std::cout << "PROC " << name()
524	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
525	<< " for adresse " << std::hex << addr
526	<< " / HIT = " << std::dec << cache_hit << std::endl;
527	m_debug_previous_hit = cache_hit;
528	}
529	if ( icache_hit != m_idebug_previous_hit )
530	{
531	std::cout << "PROC " << name()
532	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
533	<< " for adresse " << std::hex << addr
534	<< " / HIT = " << icache_hit << std::endl;
535	m_idebug_previous_hit = icache_hit;
536	}
537	}
538
539	/*
540	////////////////////////
541	tmpl(void)::print_stats()
542	////////////////////////
543	{
544	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
545	std::cout << name() << std::endl
546	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
547	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
548	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
549	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
550	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
551	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
552	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
553	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
554	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
555	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
556	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
557	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
558	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
559	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
560	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
561	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
562	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
563	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
564	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
565	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
566	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
567	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
568	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
569	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
570	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
571	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
572	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
573	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
574	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
575	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
576	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
577	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
578	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
579	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
580	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
581	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
582	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
583	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
584	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
585	}
586
587	////////////////////////
588	tmpl(void)::clear_stats()
589	////////////////////////
590	{
591	m_cpt_dcache_data_read = 0;
592	m_cpt_dcache_data_write = 0;
593	m_cpt_dcache_dir_read = 0;
594	m_cpt_dcache_dir_write = 0;
595	m_cpt_icache_data_read = 0;
596	m_cpt_icache_data_write = 0;
597	m_cpt_icache_dir_read = 0;
598	m_cpt_icache_dir_write = 0;
599
600	m_cpt_frz_cycles = 0;
601	m_cpt_dcache_frz_cycles = 0;
602	m_cpt_total_cycles = 0;
603
604	m_cpt_read = 0;
605	m_cpt_write = 0;
606	m_cpt_data_miss = 0;
607	m_cpt_ins_miss = 0;
608	m_cpt_unc_read = 0;
609	m_cpt_write_cached = 0;
610	m_cpt_ins_read = 0;
611
612	m_cost_write_frz = 0;
613	m_cost_data_miss_frz = 0;
614	m_cost_unc_read_frz = 0;
615	m_cost_ins_miss_frz = 0;
616
617	m_cpt_imiss_transaction = 0;
618	m_cpt_dmiss_transaction = 0;
619	m_cpt_unc_transaction = 0;
620	m_cpt_write_transaction = 0;
621	m_cpt_icache_unc_transaction = 0;
622
623	m_cost_imiss_transaction = 0;
624	m_cost_dmiss_transaction = 0;
625	m_cost_unc_transaction = 0;
626	m_cost_write_transaction = 0;
627	m_cost_icache_unc_transaction = 0;
628	m_length_write_transaction = 0;
629
630	m_cpt_ins_tlb_read = 0;
631	m_cpt_ins_tlb_miss = 0;
632	m_cpt_ins_tlb_update_acc = 0;
633
634	m_cpt_data_tlb_read = 0;
635	m_cpt_data_tlb_miss = 0;
636	m_cpt_data_tlb_update_acc = 0;
637	m_cpt_data_tlb_update_dirty = 0;
638	m_cpt_ins_tlb_hit_dcache = 0;
639	m_cpt_data_tlb_hit_dcache = 0;
640	m_cpt_ins_tlb_occup_cache = 0;
641	m_cpt_data_tlb_occup_cache = 0;
642
643	m_cost_ins_tlb_miss_frz = 0;
644	m_cost_data_tlb_miss_frz = 0;
645	m_cost_ins_tlb_update_acc_frz = 0;
646	m_cost_data_tlb_update_acc_frz = 0;
647	m_cost_data_tlb_update_dirty_frz = 0;
648	m_cost_ins_tlb_occup_cache_frz = 0;
649	m_cost_data_tlb_occup_cache_frz = 0;
650
651	m_cpt_itlbmiss_transaction = 0;
652	m_cpt_itlb_ll_transaction = 0;
653	m_cpt_itlb_sc_transaction = 0;
654	m_cpt_dtlbmiss_transaction = 0;
655	m_cpt_dtlb_ll_transaction = 0;
656	m_cpt_dtlb_sc_transaction = 0;
657	m_cpt_dtlb_ll_dirty_transaction = 0;
658	m_cpt_dtlb_sc_dirty_transaction = 0;
659
660	m_cost_itlbmiss_transaction = 0;
661	m_cost_itlb_ll_transaction = 0;
662	m_cost_itlb_sc_transaction = 0;
663	m_cost_dtlbmiss_transaction = 0;
664	m_cost_dtlb_ll_transaction = 0;
665	m_cost_dtlb_sc_transaction = 0;
666	m_cost_dtlb_ll_dirty_transaction = 0;
667	m_cost_dtlb_sc_dirty_transaction = 0;
668
669	m_cpt_cc_update_data = 0;
670	m_cpt_cc_inval_ins = 0;
671	m_cpt_cc_inval_data = 0;
672	m_cpt_cc_broadcast = 0;
673
674	m_cost_updt_data_frz = 0;
675	m_cost_inval_ins_frz = 0;
676	m_cost_inval_data_frz = 0;
677	m_cost_broadcast_frz = 0;
678
679	m_cpt_cc_cleanup_data = 0;
680	m_cpt_cc_cleanup_ins = 0;
681	}
682
683	*/
684
685	/////////////////////////
686	tmpl(void)::transition()
687	/////////////////////////
688	{
689	#define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
690	if ( not p_resetn.read() )
691	{
692	r_iss.reset();
693	r_wbuf.reset();
694	r_icache.reset();
695	r_dcache.reset();
696	r_itlb.reset();
697	r_dtlb.reset();
698
699	r_dcache_fsm = DCACHE_IDLE;
700	r_icache_fsm = ICACHE_IDLE;
701	r_vci_cmd_fsm = CMD_IDLE;
702	r_vci_rsp_fsm = RSP_IDLE;
703	r_cc_receive_fsm = CC_RECEIVE_IDLE;
704	r_cc_send_fsm = CC_SEND_IDLE;
705
706	// reset dcache directory extension
707	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
708	{
709	r_dcache_in_tlb[i] = false;
710	r_dcache_contains_ptd[i] = false;
711	}
712
713	// Response FIFOs and cleanup buffer
714	r_vci_rsp_fifo_icache.init();
715	r_vci_rsp_fifo_dcache.init();
716
717	// ICACHE & DCACHE activated
718	r_mmu_mode = 0x3;
719
720	// No request from ICACHE FSM to CMD FSM
721	r_icache_miss_req = false;
722	r_icache_unc_req = false;
723
724	// No request from ICACHE_FSM to DCACHE FSM
725	r_icache_tlb_miss_req = false;
726
727	// No request from ICACHE_FSM to CC_SEND FSM
728	r_icache_cc_send_req = false;
729
730	// No pending write in pipeline
731	r_dcache_wbuf_req = false;
732	r_dcache_updt_req = false;
733
734	// No request from DCACHE_FSM to CMD_FSM
735	r_dcache_vci_miss_req = false;
736	r_dcache_vci_unc_req = false;
737	r_dcache_vci_cas_req = false;
738	r_dcache_vci_ll_req = false;
739	r_dcache_vci_sc_req = false;
740
741	// No uncacheable write pending
742	r_dcache_pending_unc_write = false;
743
744	// No processor XTN request pending
745	r_dcache_xtn_req = false;
746
747	// No request from DCACHE FSM to CC_SEND FSM
748	r_dcache_cc_send_req = false;
749
750	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
751	r_cc_receive_icache_req = false;
752	r_cc_receive_dcache_req = false;
753
754	// last cc_send client was dcache
755	r_cc_send_last_client = false;
756
757	// No pending cleanup after a replacement
758	r_icache_miss_clack = false;
759	r_dcache_miss_clack = false;
760
761	// No signalisation of a coherence request matching a pending miss
762	r_icache_miss_inval = false;
763	r_dcache_miss_inval = false;
764
765	// No signalisation of errors
766	r_vci_rsp_ins_error = false;
767	r_vci_rsp_data_error = false;
768
769	// Debug variables
770	m_debug_previous_hit = false;
771	m_idebug_previous_hit = false;
772	m_debug_dcache_fsm = false;
773	m_debug_icache_fsm = false;
774
775	// activity counters
776	m_cpt_dcache_data_read = 0;
777	m_cpt_dcache_data_write = 0;
778	m_cpt_dcache_dir_read = 0;
779	m_cpt_dcache_dir_write = 0;
780	m_cpt_icache_data_read = 0;
781	m_cpt_icache_data_write = 0;
782	m_cpt_icache_dir_read = 0;
783	m_cpt_icache_dir_write = 0;
784
785	m_cpt_frz_cycles = 0;
786	m_cpt_total_cycles = 0;
787	m_cpt_stop_simulation = 0;
788
789	m_cpt_data_miss = 0;
790	m_cpt_ins_miss = 0;
791	m_cpt_unc_read = 0;
792	m_cpt_write_cached = 0;
793	m_cpt_ins_read = 0;
794
795	m_cost_write_frz = 0;
796	m_cost_data_miss_frz = 0;
797	m_cost_unc_read_frz = 0;
798	m_cost_ins_miss_frz = 0;
799
800	m_cpt_imiss_transaction = 0;
801	m_cpt_dmiss_transaction = 0;
802	m_cpt_unc_transaction = 0;
803	m_cpt_write_transaction = 0;
804	m_cpt_icache_unc_transaction = 0;
805
806	m_cost_imiss_transaction = 0;
807	m_cost_dmiss_transaction = 0;
808	m_cost_unc_transaction = 0;
809	m_cost_write_transaction = 0;
810	m_cost_icache_unc_transaction = 0;
811	m_length_write_transaction = 0;
812
813	m_cpt_ins_tlb_read = 0;
814	m_cpt_ins_tlb_miss = 0;
815	m_cpt_ins_tlb_update_acc = 0;
816
817	m_cpt_data_tlb_read = 0;
818	m_cpt_data_tlb_miss = 0;
819	m_cpt_data_tlb_update_acc = 0;
820	m_cpt_data_tlb_update_dirty = 0;
821	m_cpt_ins_tlb_hit_dcache = 0;
822	m_cpt_data_tlb_hit_dcache = 0;
823	m_cpt_ins_tlb_occup_cache = 0;
824	m_cpt_data_tlb_occup_cache = 0;
825
826	m_cost_ins_tlb_miss_frz = 0;
827	m_cost_data_tlb_miss_frz = 0;
828	m_cost_ins_tlb_update_acc_frz = 0;
829	m_cost_data_tlb_update_acc_frz = 0;
830	m_cost_data_tlb_update_dirty_frz = 0;
831	m_cost_ins_tlb_occup_cache_frz = 0;
832	m_cost_data_tlb_occup_cache_frz = 0;
833
834	m_cpt_ins_tlb_inval = 0;
835	m_cpt_data_tlb_inval = 0;
836	m_cost_ins_tlb_inval_frz = 0;
837	m_cost_data_tlb_inval_frz = 0;
838
839	m_cpt_cc_broadcast = 0;
840
841	m_cost_updt_data_frz = 0;
842	m_cost_inval_ins_frz = 0;
843	m_cost_inval_data_frz = 0;
844	m_cost_broadcast_frz = 0;
845
846	m_cpt_cc_cleanup_data = 0;
847	m_cpt_cc_cleanup_ins = 0;
848
849	m_cpt_itlbmiss_transaction = 0;
850	m_cpt_itlb_ll_transaction = 0;
851	m_cpt_itlb_sc_transaction = 0;
852	m_cpt_dtlbmiss_transaction = 0;
853	m_cpt_dtlb_ll_transaction = 0;
854	m_cpt_dtlb_sc_transaction = 0;
855	m_cpt_dtlb_ll_dirty_transaction = 0;
856	m_cpt_dtlb_sc_dirty_transaction = 0;
857
858	m_cost_itlbmiss_transaction = 0;
859	m_cost_itlb_ll_transaction = 0;
860	m_cost_itlb_sc_transaction = 0;
861	m_cost_dtlbmiss_transaction = 0;
862	m_cost_dtlb_ll_transaction = 0;
863	m_cost_dtlb_sc_transaction = 0;
864	m_cost_dtlb_ll_dirty_transaction = 0;
865	m_cost_dtlb_sc_dirty_transaction = 0;
866	/*
867	m_cpt_dcache_frz_cycles = 0;
868	m_cpt_read = 0;
869	m_cpt_write = 0;
870	m_cpt_cc_update_data = 0;
871	m_cpt_cc_inval_ins = 0;
872	m_cpt_cc_inval_data = 0;
873	*/
874
875	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
876	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
877	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
878	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
879
880	// init the llsc reservation buffer
881	r_dcache_llsc_valid = false;
882
883	return;
884	}
885
886	// Response FIFOs default values
887	bool vci_rsp_fifo_icache_get = false;
888	bool vci_rsp_fifo_icache_put = false;
889	uint32_t vci_rsp_fifo_icache_data = 0;
890
891	bool vci_rsp_fifo_dcache_get = false;
892	bool vci_rsp_fifo_dcache_put = false;
893	uint32_t vci_rsp_fifo_dcache_data = 0;
894
895	// updt fifo
896	bool cc_receive_updt_fifo_get = false;
897	bool cc_receive_updt_fifo_put = false;
898	uint32_t cc_receive_updt_fifo_be = 0;
899	uint32_t cc_receive_updt_fifo_data = 0;
900	bool cc_receive_updt_fifo_eop = false;
901
902	#ifdef INSTRUMENTATION
903	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
904	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
905	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
906	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
907	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
908	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
909	#endif
910
911	m_cpt_total_cycles++;
912
913	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
914	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
915
916	/////////////////////////////////////////////////////////////////////
917	// Get data and instruction requests from processor
918	///////////////////////////////////////////////////////////////////////
919
920	r_iss.getRequests(m_ireq, m_dreq);
921
922	////////////////////////////////////////////////////////////////////////////////////
923	// ICACHE_FSM
924	//
925	// 1/ Coherence operations
926	// They are handled as interrupts generated by the CC_RECEIVE FSM.
927	// - There is a coherence request when r_tgt_icache_req is set.
928	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
929	// - There is a cleanup ack request when r_cleanup_icache_req is set.
930	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
931	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
932	// - For both types of requests, actions associated to the pre-empted state
933	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
934	// or CC_CLACK) to execute the requested coherence operation, and returns
935	// to the pre-empted state.
936	//
937	// 2/ Processor requests
938	// They are taken in IDLE state only. In case of cache miss, or uncacheable
939	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
940	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
941	// flip-flops are reset when the transaction starts.
942	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
943	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
944	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
945	// The availability of the missing cache line is signaled by the response fifo,
946	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
947	// and ICACHE_MISS_DIR_UPDT states.
948	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
949	// to wait the response from the RSP FSM, through the response fifo.
950	// The missing instruction is directly returned to processor in this state.
951	//
952	// 3/ TLB miss
953	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
954	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
955	// register, and goes to the ICACHE_TLB_WAIT state.
956	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
957	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
958	// to signal the completion.
959	//
960	// 4/ XTN requests
961	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
962	// using the r_dcache_xtn_req flip-flop.
963	// The request opcode and the address to be invalidated are transmitted
964	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
965	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
966	// is completed.
967	//
968	// 5/ Error Handling
969	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
970	// in a cache miss or uncacheable read VCI transaction. Nothing is written
971	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
972	////////////////////////////////////////////////////////////////////////////////////////
973
974	// default value for m_irsp
975	m_irsp.valid = false;
976	m_irsp.error = false;
977	m_irsp.instruction = 0;
978
979	switch( r_icache_fsm.read() )
980	{
981	/////////////////
982	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
983	// and coherence requests with a fixed priority:
984	// 1/ Coherence requests => ICACHE_CC_CHECK
985	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
986	// 3/ tlb miss => ICACHE_TLB_WAIT
987	// 4/ cacheable read miss => ICACHE_MISS_SELECT
988	// 5/ uncacheable read miss => ICACHE_UNC_REQ
989	{
990	// coherence interrupt
991	if ( r_cc_receive_icache_req.read() )
992	{
993	r_icache_fsm = ICACHE_CC_CHECK;
994	r_icache_fsm_save = r_icache_fsm.read();
995	break;
996	}
997
998	// XTN requests sent by DCACHE FSM
999	// These request are not executed in this IDLE state, because
1000	// they require access to icache or itlb, that are already accessed
1001	if ( r_dcache_xtn_req.read() )
1002	{
1003	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1004	{
1005	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1006	}
1007	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1008	{
1009	r_icache_flush_count = 0;
1010	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1011	}
1012	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1013	{
1014	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1015	}
1016	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1017	{
1018	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1019	}
1020	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1021	{
1022	if (sizeof(paddr_t) <= 32)
1023	{
1024	assert(r_mmu_word_hi.read() == 0 &&
1025	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1026	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1027	}
1028	else
1029	{
1030	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1031	(paddr_t)r_mmu_word_lo.read();
1032	}
1033	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1034	}
1035	else
1036	{
1037	assert( false and
1038	"undefined XTN request received by ICACHE FSM");
1039	}
1040	break;
1041	} // end if xtn_req
1042
1043	// processor request
1044	if ( m_ireq.valid )
1045	{
1046	bool cacheable;
1047	paddr_t paddr;
1048	bool tlb_hit = false;
1049	pte_info_t tlb_flags;
1050	size_t tlb_way;
1051	size_t tlb_set;
1052	paddr_t tlb_nline;
1053	uint32_t cache_inst = 0;
1054	size_t cache_way;
1055	size_t cache_set;
1056	size_t cache_word;
1057	int cache_state = CACHE_SLOT_STATE_EMPTY;
1058
1059	// We register processor request
1060	r_icache_vaddr_save = m_ireq.addr;
1061
1062	// sytematic itlb access (if activated)
1063	if ( r_mmu_mode.read() & INS_TLB_MASK )
1064	{
1065
1066	#ifdef INSTRUMENTATION
1067	m_cpt_itlb_read++;
1068	#endif
1069	tlb_hit = r_itlb.translate( m_ireq.addr,
1070	&paddr,
1071	&tlb_flags,
1072	&tlb_nline, // unused
1073	&tlb_way, // unused
1074	&tlb_set ); // unused
1075	}
1076	else
1077	{
1078	paddr = (paddr_t)m_ireq.addr;
1079	}
1080
1081	// systematic icache access (if activated)
1082	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1083	{
1084
1085
1086	#ifdef INSTRUMENTATION
1087	m_cpt_icache_data_read++;
1088	m_cpt_icache_dir_read++;
1089	#endif
1090	r_icache.read( paddr,
1091	&cache_inst,
1092	&cache_way,
1093	&cache_set,
1094	&cache_word,
1095	&cache_state );
1096	}
1097
1098	// We compute cacheability and check access rights:
1099	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1100	// and the access rights are defined by the U and X bits in the PTE.
1101	// - If MMU not activated : cacheability is defined by the segment table,
1102	// and there is no access rights checking
1103
1104	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1105	{
1106	// cacheability
1107	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1108	else cacheable = m_cacheability_table[m_ireq.addr];
1109	}
1110	else // itlb activated
1111	{
1112	if ( tlb_hit ) // ITLB hit
1113	{
1114	// cacheability
1115	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1116	else cacheable = tlb_flags.c;
1117
1118	// access rights checking
1119	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1120	{
1121	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1122	r_mmu_ibvar = m_ireq.addr;
1123	m_irsp.valid = true;
1124	m_irsp.error = true;
1125	m_irsp.instruction = 0;
1126	break;
1127	}
1128	else if ( not tlb_flags.x )
1129	{
1130	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1131	r_mmu_ibvar = m_ireq.addr;
1132	m_irsp.valid = true;
1133	m_irsp.error = true;
1134	m_irsp.instruction = 0;
1135	break;
1136	}
1137	}
1138	else // ITLB miss
1139	{
1140
1141	#ifdef INSTRUMENTATION
1142	m_cpt_itlb_miss++;
1143	#endif
1144	r_icache_fsm = ICACHE_TLB_WAIT;
1145	r_icache_tlb_miss_req = true;
1146	break;
1147	}
1148	} // end if itlb activated
1149
1150	// physical address registration
1151	r_icache_vci_paddr = paddr;
1152
1153	// Finally, we send the response to processor, and compute next state
1154	if ( cacheable )
1155	{
1156	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1157	{
1158
1159	#ifdef INSTRUMENTATION
1160	m_cpt_icache_miss++;
1161	#endif
1162	// we request a VCI transaction
1163	r_icache_fsm = ICACHE_MISS_SELECT;
1164	r_icache_miss_req = true;
1165	}
1166	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1167	{
1168	// stalled until cleanup is acknowledged
1169	r_icache_fsm = ICACHE_IDLE;
1170	}
1171	else // cache hit
1172	{
1173
1174	#ifdef INSTRUMENTATION
1175	m_cpt_ins_read++;
1176	#endif
1177	// return instruction to processor
1178	m_irsp.valid = true;
1179	m_irsp.instruction = cache_inst;
1180	r_icache_fsm = ICACHE_IDLE;
1181	}
1182	}
1183	else // non cacheable read
1184	{
1185	r_icache_unc_req = true;
1186	r_icache_fsm = ICACHE_UNC_WAIT;
1187	}
1188	} // end if m_ireq.valid
1189	break;
1190	}
1191	/////////////////////
1192	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1193	// the itlb is udated by the DCACHE FSM, as well as the
1194	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1195	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1196	// reset the r_icache_tlb_miss_req flip-flop
1197	// external coherence request are accepted in this state.
1198	{
1199	// coherence interrupt
1200	if ( r_cc_receive_icache_req.read() )
1201	{
1202	r_icache_fsm = ICACHE_CC_CHECK;
1203	r_icache_fsm_save = r_icache_fsm.read();
1204	break;
1205	}
1206
1207	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1208
1209	// DCACHE FSM signals response by reseting the request flip-flop
1210	if ( not r_icache_tlb_miss_req.read() )
1211	{
1212	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1213	{
1214	r_icache_tlb_rsp_error = false;
1215	m_irsp.error = true;
1216	m_irsp.valid = true;
1217	r_icache_fsm = ICACHE_IDLE;
1218	}
1219	else // tlb updated : return to IDLE state
1220	{
1221	r_icache_fsm = ICACHE_IDLE;
1222	}
1223	}
1224	break;
1225	}
1226	//////////////////////////
1227	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1228	{
1229	r_itlb.flush();
1230	r_dcache_xtn_req = false;
1231	r_icache_fsm = ICACHE_IDLE;
1232	break;
1233	}
1234	////////////////////////////
1235	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1236	// r_icache_flush_count as a slot counter,
1237	// looping in this state until all slots are visited.
1238	// It can require two cycles per slot:
1239	// We test here the slot state, and make the actual inval
1240	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1241	// A cleanup request is generated for each valid line
1242	{
1243	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1244	{
1245	int state;
1246	uint32_t tag;
1247	size_t way = r_icache_flush_count.read()/m_icache_sets;
1248	size_t set = r_icache_flush_count.read()%m_icache_sets;
1249
1250	#ifdef INSTRUMENTATION
1251	m_cpt_icache_dir_read++;
1252	#endif
1253	r_icache.read_dir( way,
1254	set,
1255	&tag,
1256	&state );
1257
1258	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1259	{
1260	// request cleanup
1261	r_icache_cc_send_req = true;
1262	r_icache_cc_send_nline = tag * m_icache_sets;
1263	r_icache_cc_send_way = way;
1264	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1265
1266	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1267	r_icache_miss_way = way;
1268	r_icache_miss_set = set;
1269	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1270	}
1271	else if ( r_icache_flush_count.read() ==
1272	(m_icache_sets*m_icache_ways - 1) ) // last slot
1273	{
1274	r_dcache_xtn_req = false;
1275	m_drsp.valid = true;
1276	r_icache_fsm = ICACHE_IDLE;
1277	}
1278
1279	// saturation counter, to have the same last slot condition
1280	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1281	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1282	{
1283	r_icache_flush_count = r_icache_flush_count.read() + 1;
1284	}
1285	}
1286	break;
1287	}
1288	///////////////////////////////
1289	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1290	{
1291	size_t way = r_icache_miss_way.read();
1292	size_t set = r_icache_miss_set.read();
1293
1294	#ifdef INSTRUMENTATION
1295	m_cpt_icache_dir_write++;
1296	#endif
1297
1298	r_icache.write_dir( 0,
1299	way,
1300	set,
1301	CACHE_SLOT_STATE_ZOMBI );
1302
1303	if ( r_icache_flush_count.read() ==
1304	(m_icache_sets*m_icache_ways - 1) ) // last slot
1305	{
1306	r_dcache_xtn_req = false;
1307	m_drsp.valid = true;
1308	r_icache_fsm = ICACHE_IDLE;
1309	}
1310	else
1311	{
1312	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1313	}
1314	break;
1315	}
1316
1317	//////////////////////////
1318	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1319	// stored in the r_dcache_save_wdata register
1320	{
1321	r_itlb.inval(r_dcache_save_wdata.read());
1322	r_dcache_xtn_req = false;
1323	r_icache_fsm = ICACHE_IDLE;
1324	break;
1325	}
1326	///////////////////////////////
1327	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1328	// requires 3 cycles (in case of hit on itlb and icache).
1329	// In this state, access TLB to translate virtual address
1330	// stored in the r_dcache_save_wdata register.
1331	{
1332	paddr_t paddr;
1333	bool hit;
1334
1335	// read physical address in TLB when MMU activated
1336	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1337	{
1338
1339	#ifdef INSTRUMENTATION
1340	m_cpt_itlb_read++;
1341	#endif
1342	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1343	&paddr);
1344	}
1345	else // itlb not activated
1346	{
1347	paddr = (paddr_t)r_dcache_save_wdata.read();
1348	hit = true;
1349	}
1350
1351	if ( hit ) // continue the selective inval process
1352	{
1353	r_icache_vci_paddr = paddr;
1354	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1355	}
1356	else // miss : send a request to DCACHE FSM
1357	{
1358
1359	#ifdef INSTRUMENTATION
1360	m_cpt_itlb_miss++;
1361	#endif
1362	r_icache_tlb_miss_req = true;
1363	r_icache_vaddr_save = r_dcache_save_wdata.read();
1364	r_icache_fsm = ICACHE_TLB_WAIT;
1365	}
1366	break;
1367	}
1368	///////////////////////////////
1369	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1370	// require 2 cycles. In this state, we read directory
1371	// with address stored in r_icache_vci_paddr register.
1372	{
1373	int state;
1374	size_t way;
1375	size_t set;
1376	size_t word;
1377
1378	#ifdef INSTRUMENTATION
1379	m_cpt_icache_dir_read++;
1380	#endif
1381	r_icache.read_dir(r_icache_vci_paddr.read(),
1382	&state,
1383	&way,
1384	&set,
1385	&word);
1386
1387	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1388	{
1389	r_icache_miss_way = way;
1390	r_icache_miss_set = set;
1391	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1392	}
1393	else // miss : acknowlege the XTN request and return
1394	{
1395	r_dcache_xtn_req = false;
1396	r_icache_fsm = ICACHE_IDLE;
1397	}
1398	break;
1399	}
1400	///////////////////////////////
1401	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1402	{
1403	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1404	{
1405
1406	#ifdef INSTRUMENTATION
1407	m_cpt_icache_dir_write++;
1408	#endif
1409	r_icache.write_dir( 0,
1410	r_icache_miss_way.read(),
1411	r_icache_miss_set.read(),
1412	CACHE_SLOT_STATE_ZOMBI );
1413
1414	// request cleanup
1415	r_icache_cc_send_req = true;
1416	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1417	r_icache_cc_send_way = r_icache_miss_way.read();
1418	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1419
1420	// acknowledge the XTN request and return
1421	r_dcache_xtn_req = false;
1422	r_icache_fsm = ICACHE_IDLE;
1423	}
1424	break;
1425	}
1426	////////////////////////
1427	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1428	// if previous cleanup has been sent.
1429	// Waiting in this state if no slot available.
1430	// Set the r_icache_cleanup_req flip-flop
1431	// and the r_icache_miss_clack flip-flop,
1432	// when a cleanup is required
1433	{
1434	if (m_ireq.valid) m_cost_ins_miss_frz++;
1435
1436	// coherence interrupt
1437	if ( r_cc_receive_icache_req.read() )
1438	{
1439	r_icache_fsm = ICACHE_CC_CHECK;
1440	r_icache_fsm_save = r_icache_fsm.read();
1441	break;
1442	}
1443
1444	if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
1445	{
1446	bool found;
1447	bool cleanup;
1448	size_t way;
1449	size_t set;
1450	paddr_t victim;
1451
1452	#ifdef INSTRUMENTATION
1453	m_cpt_icache_dir_read++;
1454	#endif
1455	r_icache.read_select(r_icache_vci_paddr.read(),
1456	&victim,
1457	&way,
1458	&set,
1459	&found,
1460	&cleanup );
1461	if ( found )
1462	{
1463	r_icache_miss_way = way;
1464	r_icache_miss_set = set;
1465
1466	if ( cleanup )
1467	{
1468	r_icache_fsm = ICACHE_MISS_CLEAN;
1469	r_icache_miss_clack = true;
1470	// request cleanup
1471	r_icache_cc_send_req = true;
1472	r_icache_cc_send_nline = victim;
1473	r_icache_cc_send_way = way;
1474	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1475	}
1476	else
1477	{
1478	r_icache_fsm = ICACHE_MISS_WAIT;
1479	}
1480
1481	#if DEBUG_ICACHE
1482	if ( m_debug_dcache_fsm )
1483	{
1484	std::cout << " <PROC " << name()
1485	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1486	<< " / WAY = " << way
1487	<< " / SET = " << set;
1488	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1489	else std::cout << std::endl;
1490	}
1491	#endif
1492	}
1493	}
1494	break;
1495	}
1496	///////////////////////
1497	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1498	{
1499	if (m_ireq.valid) m_cost_ins_miss_frz++;
1500
1501	// coherence interrupt
1502	if ( r_cc_receive_icache_req.read() )
1503	{
1504	r_icache_fsm = ICACHE_CC_CHECK;
1505	r_icache_fsm_save = r_icache_fsm.read();
1506	break;
1507	}
1508
1509	#ifdef INSTRUMENTATION
1510	m_cpt_icache_dir_write++;
1511	#endif
1512	r_icache.write_dir( 0,
1513	r_icache_miss_way.read(),
1514	r_icache_miss_set.read(),
1515	CACHE_SLOT_STATE_ZOMBI);
1516	#if DEBUG_ICACHE
1517	if ( m_debug_dcache_fsm )
1518	{
1519	std::cout << " <PROC " << name()
1520	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1521	<< " / WAY = " << r_icache_miss_way.read()
1522	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1523	}
1524	#endif
1525
1526	r_icache_fsm = ICACHE_MISS_WAIT;
1527	break;
1528	}
1529	//////////////////////
1530	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1531	{
1532	if (m_ireq.valid) m_cost_ins_miss_frz++;
1533
1534	// coherence interrupt
1535	if ( r_cc_receive_icache_req.read() )
1536	{
1537	r_icache_fsm = ICACHE_CC_CHECK;
1538	r_icache_fsm_save = r_icache_fsm.read();
1539	break;
1540	}
1541
1542	if ( r_vci_rsp_ins_error.read() ) // bus error
1543	{
1544	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1545	r_mmu_ibvar = r_icache_vaddr_save.read();
1546	m_irsp.valid = true;
1547	m_irsp.error = true;
1548	r_vci_rsp_ins_error = false;
1549	r_icache_fsm = ICACHE_IDLE;
1550	}
1551	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1552	{
1553	r_icache_miss_word = 0;
1554	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1555	}
1556	break;
1557	}
1558	///////////////////////////
1559	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1560	{
1561	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1562
1563	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1564	{
1565
1566	#ifdef INSTRUMENTATION
1567	m_cpt_icache_data_write++;
1568	#endif
1569	r_icache.write( r_icache_miss_way.read(),
1570	r_icache_miss_set.read(),
1571	r_icache_miss_word.read(),
1572	r_vci_rsp_fifo_icache.read() );
1573	#if DEBUG_ICACHE
1574	if ( m_debug_icache_fsm )
1575	{
1576	std::cout << " <PROC " << name()
1577	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1578	<< " WDATA = " << r_vci_rsp_fifo_icache.read()
1579	<< " WAY = " << r_icache_miss_way.read()
1580	<< " SET = " << r_icache_miss_set.read()
1581	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1582	}
1583	#endif
1584	vci_rsp_fifo_icache_get = true;
1585	r_icache_miss_word = r_icache_miss_word.read() + 1;
1586
1587	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1588	{
1589	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1590	}
1591	}
1592	break;
1593	}
1594	//////////////////////////
1595	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1596	// and the cleanup ack has not been received,
1597	// as indicated by r_icache_miss_clack.
1598	// - If no matching coherence request (r_icache_miss_inval)
1599	// switch directory slot to VALID state.
1600	// - If matching coherence request, switch directory slot
1601	// to ZOMBI state, and send a cleanup request.
1602	{
1603	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1604
1605	// coherence interrupt
1606	if ( r_cc_receive_icache_req.read() )
1607	{
1608	r_icache_fsm = ICACHE_CC_CHECK;
1609	r_icache_fsm_save = r_icache_fsm.read();
1610	break;
1611	}
1612
1613	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1614	{
1615	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1616	{
1617	if ( not r_icache_cc_send_req.read() )
1618	{
1619	r_icache_miss_inval = false;
1620	// request cleanup
1621	r_icache_cc_send_req = true;
1622	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1623	r_icache_cc_send_way = r_icache_miss_way.read();
1624	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1625
1626	#ifdef INSTRUMENTATION
1627	m_cpt_icache_dir_write++;
1628	#endif
1629	r_icache.write_dir( r_icache_vci_paddr.read(),
1630	r_icache_miss_way.read(),
1631	r_icache_miss_set.read(),
1632	CACHE_SLOT_STATE_ZOMBI );
1633	#if DEBUG_ICACHE
1634	if ( m_debug_icache_fsm )
1635	{
1636	std::cout << " <PROC " << name()
1637	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1638	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1639	<< " WAY = " << std::dec << r_icache_miss_way.read()
1640	<< " SET = " << r_icache_miss_set.read() << std::endl;
1641	}
1642	#endif
1643	}
1644	else
1645	break;
1646	}
1647	else // Switch slot to VALID state
1648	{
1649
1650	#ifdef INSTRUMENTATION
1651	m_cpt_icache_dir_write++;
1652	#endif
1653	r_icache.write_dir( r_icache_vci_paddr.read(),
1654	r_icache_miss_way.read(),
1655	r_icache_miss_set.read(),
1656	CACHE_SLOT_STATE_VALID );
1657	#if DEBUG_ICACHE
1658	if ( m_debug_icache_fsm )
1659	{
1660	std::cout << " <PROC " << name()
1661	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1662	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1663	<< " WAY = " << std::dec << r_icache_miss_way.read()
1664	<< " SET = " << r_icache_miss_set.read() << std::endl;
1665	}
1666	#endif
1667	}
1668
1669	r_icache_fsm = ICACHE_IDLE;
1670	}
1671	break;
1672	}
1673	////////////////////
1674	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1675	{
1676	// coherence interrupt
1677	if ( r_cc_receive_icache_req.read() )
1678	{
1679	r_icache_fsm = ICACHE_CC_CHECK;
1680	r_icache_fsm_save = r_icache_fsm.read();
1681	break;
1682	}
1683
1684	if ( r_vci_rsp_ins_error.read() ) // bus error
1685	{
1686	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1687	r_mmu_ibvar = m_ireq.addr;
1688	r_vci_rsp_ins_error = false;
1689	m_irsp.valid = true;
1690	m_irsp.error = true;
1691	r_icache_fsm = ICACHE_IDLE;
1692	}
1693	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1694	{
1695	vci_rsp_fifo_icache_get = true;
1696	r_icache_fsm = ICACHE_IDLE;
1697	if ( m_ireq.valid and
1698	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1699	{
1700	m_irsp.valid = true;
1701	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1702	}
1703	}
1704	break;
1705	}
1706	/////////////////////
1707	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1708	// handling coherence requests.
1709	// if there is a matching pending miss, it is
1710	// signaled in the r_icache_miss_inval flip-flop.
1711	// The return state is defined in r_icache_fsm_save.
1712	{
1713	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1714	paddr_t mask = ~((m_icache_words<<2)-1);
1715
1716	if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK)
1717	// We switch the directory slot to EMPTY state
1718	// and reset r_icache_miss_clack if the cleanup ack
1719	// is matching a pending miss
1720	{
1721
1722	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1723
1724	#ifdef INSTRUMENTATION
1725	m_cpt_icache_dir_write++;
1726	#endif
1727	r_icache.write_dir( 0,
1728	r_cc_receive_icache_way.read(),
1729	r_cc_receive_icache_set.read(),
1730	CACHE_SLOT_STATE_EMPTY);
1731
1732	if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and
1733	(r_icache_miss_way.read() == r_cc_receive_icache_way.read()) )
1734	r_icache_miss_clack = false;
1735
1736	r_icache_fsm = r_icache_fsm_save.read() ;
1737	r_cc_receive_icache_req = false;
1738
1739	#if DEBUG_ICACHE
1740	if ( m_debug_icache_fsm )
1741	{
1742	std::cout << " <PROC " << name()
1743	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1744	<< " set = " << r_cc_receive_icache_set.read()
1745	<< " / way = " << r_cc_receive_icache_way.read() << std::endl;
1746	}
1747	#endif
1748	}
1749	else if( ((r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1750	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1751	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1752	{
1753	// signaling the matching
1754	r_icache_miss_inval = true;
1755
1756	// in case of update, go to CC_UPDT
1757	// JUST TO POP THE FIFO
1758	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1759	{
1760	r_icache_fsm = ICACHE_CC_UPDT;
1761	r_icache_cc_word = r_cc_receive_word_idx.read();
1762	// just pop the fifo , don't write in icache
1763	r_icache_cc_need_write = false;
1764	}
1765	// the request is dealt with
1766	else
1767	{
1768	r_cc_receive_icache_req = false;
1769	r_icache_fsm = r_icache_fsm_save.read();
1770	}
1771	#if DEBUG_ICACHE
1772	if ( m_debug_icache_fsm )
1773	{
1774	std::cout << " <PROC " << name()
1775	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1776	<< " PADDR = " << std::hex << paddr << std::endl;
1777	}
1778	#endif
1779	}
1780	else // no match
1781	{
1782	int state;
1783	size_t way;
1784	size_t set;
1785	size_t word;
1786
1787	#ifdef INSTRUMENTATION
1788	m_cpt_icache_dir_read++;
1789	#endif
1790	r_icache.read_dir(paddr,
1791	&state,
1792	&way,
1793	&set,
1794	&word);
1795
1796	r_icache_cc_way = way;
1797	r_icache_cc_set = set;
1798
1799	if ( state == CACHE_SLOT_STATE_VALID) // hit
1800	{
1801	// need to update the cache state
1802	r_icache_cc_need_write = true;
1803	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1804	{
1805	r_icache_fsm = ICACHE_CC_UPDT;
1806	r_icache_cc_word = r_cc_receive_word_idx.read();
1807	}
1808	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
1809	{
1810	r_icache_fsm = ICACHE_CC_INVAL;
1811	}
1812	else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
1813	{
1814	r_icache_fsm = ICACHE_CC_BROADCAST;
1815	}
1816	}
1817	else // miss
1818	{
1819	// multicast acknowledgement required in case of update
1820	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1821	{
1822	r_icache_fsm = ICACHE_CC_UPDT;
1823	r_icache_cc_word = r_cc_receive_word_idx.read();
1824	// just pop the fifo , don't write in icache
1825	r_icache_cc_need_write = false;
1826	}
1827	else // No response needed
1828	{
1829	r_cc_receive_icache_req = false;
1830	r_icache_fsm = r_icache_fsm_save.read();
1831	}
1832	}
1833	}
1834	break;
1835	}
1836	/////////////////////
1837	case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state
1838	{
1839
1840	#if DEBUG_ICACHE
1841	if ( m_debug_icache_fsm )
1842	{
1843	std::cout << " <PROC " << name()
1844	<< " ICACHE_CC_INVAL> slot returns to empty state"
1845	<< " set = " << r_icache_cc_set.read()
1846	<< " / way = " << r_icache_cc_way.read() << std::endl;
1847	}
1848	#endif
1849
1850	#ifdef INSTRUMENTATION
1851	m_cpt_icache_dir_read++;
1852	#endif
1853	if (r_icache_cc_need_write.read())
1854	{
1855	r_icache.write_dir( 0,
1856	r_icache_cc_way.read(),
1857	r_icache_cc_set.read(),
1858	CACHE_SLOT_STATE_EMPTY );
1859	// no need to write in the cache anymore
1860	r_icache_cc_need_write = false;
1861	}
1862
1863	// multicast acknowledgement
1864	// send a request to cc_send_fsm
1865	if(not r_icache_cc_send_req.read()) // cc_send is available
1866	{
1867	// coherence request completed
1868	r_cc_receive_icache_req = false;
1869	// request multicast acknowledgement
1870	r_icache_cc_send_req = true;
1871	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1872	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1873
1874	r_icache_fsm = r_icache_fsm_save.read();
1875	}
1876	//else wait for previous cc_send request to be sent
1877	break;
1878	}
1879	////////////////////
1880	case ICACHE_CC_UPDT: // hit update : write one word per cycle
1881	{
1882
1883	#if DEBUG_ICACHE
1884	if ( m_debug_icache_fsm )
1885	{
1886	std::cout << " <PROC " << name()
1887	<< " ICACHE_CC_UPDT> Write one word "
1888	<< " set = " << r_icache_cc_set.read()
1889	<< " / way = " << r_icache_cc_way.read()
1890	<< " / word = " << r_icache_cc_word.read() << std::endl;
1891	}
1892	#endif
1893
1894	#ifdef INSTRUMENTATION
1895	m_cpt_icache_data_write++;
1896	#endif
1897	size_t word = r_icache_cc_word.read();
1898	size_t way = r_icache_cc_way.read();
1899	size_t set = r_icache_cc_set.read();
1900
1901	if (r_cc_receive_updt_fifo_be.rok())
1902	{
1903	if (r_icache_cc_need_write.read())
1904	{
1905	r_icache.write( way,
1906	set,
1907	word,
1908	r_cc_receive_updt_fifo_data.read(),
1909	r_cc_receive_updt_fifo_be.read() );
1910
1911	r_icache_cc_word = word+1;
1912	}
1913	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
1914	{
1915	// no need to write in the cache anymore
1916	r_icache_cc_need_write = false;
1917	// wait to send a request to cc_send_fsm
1918	if(not r_icache_cc_send_req.read()) // cc_send is available
1919	{
1920	//consume last flit
1921	cc_receive_updt_fifo_get = true;
1922	// coherence request completed
1923	r_cc_receive_icache_req = false;
1924	// request multicast acknowledgement
1925	r_icache_cc_send_req = true;
1926	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1927	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1928
1929	r_icache_fsm = r_icache_fsm_save.read();
1930	}
1931	}
1932	else
1933	{
1934	//consume fifo if not eop
1935	cc_receive_updt_fifo_get = true;
1936	}
1937	}
1938	break;
1939	}
1940	/////////////////////////
1941	case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state
1942	// and request a cleanup
1943	{
1944
1945	#if DEBUG_ICACHE
1946	if ( m_debug_icache_fsm )
1947	{
1948	std::cout << " <PROC " << name()
1949	<< " ICACHE_CC_BROADCAST > Slot goes to zombi state "
1950	<< " set = " << r_icache_cc_set.read()
1951	<< " / way = " << r_icache_cc_way.read() << std::endl;
1952	}
1953	#endif
1954
1955	#ifdef INSTRUMENTATION
1956	m_cpt_icache_dir_write++;
1957	#endif
1958	if (r_icache_cc_need_write.read())
1959	{
1960	r_icache.write_dir( 0,
1961	r_icache_cc_way.read(),
1962	r_icache_cc_set.read(),
1963	CACHE_SLOT_STATE_ZOMBI );
1964	// no need to write in the cache anymore
1965	r_icache_cc_need_write = false;
1966	}
1967
1968	// cleanup
1969	// send a request to cc_send_fsm
1970	if(not r_icache_cc_send_req.read()) // cc_send is available
1971	{
1972	// coherence request completed
1973	r_cc_receive_icache_req = false;
1974	// request cleanup
1975	r_icache_cc_send_req = true;
1976	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1977	r_icache_cc_send_way = r_icache_cc_way.read();
1978	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1979
1980	r_icache_fsm = r_icache_fsm_save.read();
1981	}
1982	//else wait for previous cc_send request to be sent
1983	break;
1984	}
1985	} // end switch r_icache_fsm
1986
1987	////////////////////////////////////////////////////////////////////////////////////
1988	// DCACHE FSM
1989	//
1990	// 1/ Coherence operations
1991	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1992	// - There is a coherence request when r_tgt_dcache_req is set.
1993	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
1994	// and SC_WAIT states.
1995	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
1996	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
1997	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
1998	// - For both types of requests, actions associated to the pre-empted state
1999	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2000	// or CC_CLACK) to execute the requested coherence operation, and returns
2001	// to the pre-empted state.
2002	//
2003	// 2/ TLB miss
2004	// The page tables are generally cacheable.
2005	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2006	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2007	// this sub-fsm implement the table-walk...
2008	//
2009	// 3/ processor requests
2010	// Processor requests are taken in IDLE state only.
2011	// The IDLE state implements a two stages pipe-line to handle write bursts:
2012	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2013	// - The registration in wbuf and the dcache update is done in stage P1
2014	// (if the processor request is a write).
2015	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2016	// the operations that must be done in P1 stage, and the access type
2017	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2018	// READ requests are delayed if a cache update is requested.
2019	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2020	// that is done (before handling the processor request) by a dedicated sub-fsm.
2021	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2022	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2023	//
2024	// 4/ Atomic instructions LL/SC
2025	// The LL/SC address are non cacheable (systematic access to memory).
2026	// The llsc buffer contains a registration for an active LL/SC operation
2027	// (with an address, a registration key, an aging counter and a valid bit).
2028	// - LL requests from the processor are transmitted as a one flit VCI command
2029	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2030	// be 8 as the response is 2 flits long (data and registration key)
2031	// - SC requests from the processor are systematically transmitted to the
2032	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2033	// as PKTID value). The first flit contains the registration key, the second
2034	// flit contains the data to write in case of success.
2035	// The cache is not updated, as this is done in case of success by the
2036	// coherence transaction.
2037	//
2038	// 5/ Non cacheable access:
2039	// This component implement a strong order between non cacheable access
2040	// (read or write) : A new non cacheable VCI transaction starts only when
2041	// the previous non cacheable transaction is completed. Both cacheable and
2042	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2043	// a non cacheable write transaction posted in the write buffer by setting the
2044	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2045	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2046	// pending non cacheable write transaction completes).
2047	//
2048	// 6/ Error handling:
2049	// When the MMU is not activated, Read Bus Errors are synchronous events,
2050	// but Write Bus Errors are asynchronous events (processor is not frozen).
2051	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2052	// r_vci_rsp_data_error flip-flop, without writing any data in the
2053	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2054	// by the DCACHE FSM.
2055	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2056	// the asynchronous error using the setWriteBerr() method.
2057	// When the MMU is activated bus error are rare events, as the MMU
2058	// checks the physical address before the VCI transaction starts.
2059	////////////////////////////////////////////////////////////////////////////////////////
2060
2061	// default value for m_drsp
2062	m_drsp.valid = false;
2063	m_drsp.error = false;
2064	m_drsp.rdata = 0;
2065
2066	switch ( r_dcache_fsm.read() )
2067	{
2068	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2069	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2070	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2071	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2072	// 4) XTN request (processor) => DCACHE_XTN_*
2073	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2074	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2075	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2076	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2077	// 9) LL access (processor) => DCACHE_LL_WAIT
2078	// 10) SC access (processor) => DCACHE_SC_WAIT
2079	//
2080	// There is a fixed priority to handle requests to DCACHE:
2081	// 1/ the ITLB/DTLB invalidate requests
2082	// 2/ the coherence requests,
2083	// 3/ the processor requests (including DTLB miss),
2084	// 4/ the ITLB miss requests,
2085	// The address space processor request are handled as follows:
2086	// - WRITE request is blocked if the Dirty bit mus be set.
2087	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2088	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2089	// - READ request generate a simultaneouss access to DCACHE.DATA
2090	// and DCACHE.DIR, but is delayed if DCACHE update required.
2091	//
2092	// There is 4 configurations defining the access type to
2093	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2094	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2095	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2096	// 0 / 0 / NOP / NOP / NOP /
2097	// 0 / 1 / NOP / NOP / WRITE /
2098	// 1 / 0 / READ / READ / NOP /
2099	// 1 / 1 / READ / READ / WRITE /
2100	// Those two registers are set at each cycle from the 3 signals
2101	// updt_request, wbuf_request, wbuf_write_miss.
2102	{
2103	paddr_t paddr; // physical address
2104	pte_info_t tlb_flags;
2105	size_t tlb_way;
2106	size_t tlb_set;
2107	paddr_t tlb_nline;
2108	size_t cache_way;
2109	size_t cache_set;
2110	size_t cache_word;
2111	uint32_t cache_rdata = 0;
2112	bool tlb_hit = false;
2113	int cache_state = CACHE_SLOT_STATE_EMPTY;
2114
2115	bool tlb_inval_required = false; // request TLB inval after cache update
2116	bool wbuf_write_miss = false; // miss a WBUF write request
2117	bool updt_request = false; // request DCACHE update in P1 stage
2118	bool wbuf_request = false; // request WBUF write in P1 stage
2119
2120	// physical address computation : systematic DTLB access if activated)
2121	if ( m_dreq.valid )
2122	{
2123	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2124	{
2125	tlb_hit = r_dtlb.translate( m_dreq.addr,
2126	&paddr,
2127	&tlb_flags,
2128	&tlb_nline,
2129	&tlb_way,
2130	&tlb_set );
2131	#ifdef INSTRUMENTATION
2132	m_cpt_dtlb_read++;
2133	#endif
2134	}
2135	else // identity mapping
2136	{
2137	paddr = (paddr_t)m_dreq.addr;
2138	}
2139	} // end physical address computation
2140
2141	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2142	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2143	{
2144	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2145	{
2146	r_dcache.read_dir( paddr,
2147	&cache_state,
2148	&cache_way,
2149	&cache_set,
2150	&cache_word );
2151
2152	r_dcache.write( r_dcache_save_cache_way.read(),
2153	r_dcache_save_cache_set.read(),
2154	r_dcache_save_cache_word.read(),
2155	r_dcache_save_wdata.read(),
2156	r_dcache_save_be.read() );
2157	#ifdef INSTRUMENTATION
2158	m_cpt_dcache_dir_read++;
2159	m_cpt_dcache_data_write++;
2160	#endif
2161	}
2162	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2163	{
2164	r_dcache.read( paddr,
2165	&cache_rdata,
2166	&cache_way,
2167	&cache_set,
2168	&cache_word,
2169	&cache_state );
2170	#ifdef INSTRUMENTATION
2171	m_cpt_dcache_dir_read++;
2172	m_cpt_dcache_data_read++;
2173	#endif
2174	}
2175	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2176	{
2177	r_dcache.write( r_dcache_save_cache_way.read(),
2178	r_dcache_save_cache_set.read(),
2179	r_dcache_save_cache_word.read(),
2180	r_dcache_save_wdata.read(),
2181	r_dcache_save_be.read() );
2182	#ifdef INSTRUMENTATION
2183	m_cpt_dcache_data_write++;
2184	#endif
2185	}
2186	} // end dcache access
2187
2188	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2189	if ( r_dcache_updt_req.read() )
2190	{
2191	size_t way = r_dcache_save_cache_way.read();
2192	size_t set = r_dcache_save_cache_set.read();
2193
2194	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2195	{
2196	tlb_inval_required = true;
2197	r_dcache_tlb_inval_set = 0;
2198	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2199	(uint32_log2(m_dcache_words<<2));
2200	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2201	}
2202	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2203	{
2204	r_itlb.reset();
2205	r_dtlb.reset();
2206	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2207	}
2208
2209	#if DEBUG_DCACHE
2210	if ( m_debug_dcache_fsm )
2211	{
2212	std::cout << " <PROC " << name()
2213	<< " DCACHE_IDLE> Cache update in P1 stage" << std::dec
2214	<< " / WAY = " << r_dcache_save_cache_way.read()
2215	<< " / SET = " << r_dcache_save_cache_set.read()
2216	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2217	<< " / DATA = " << r_dcache_save_wdata.read()
2218	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2219	}
2220	#endif
2221	} // end test TLB inval
2222
2223	// Try WBUF update in P1 stage
2224	// Miss if the write request is non cacheable, and there is a pending
2225	// non cacheable write, or if the write buffer is full.
2226	if ( r_dcache_wbuf_req.read() )
2227	{
2228	// miss if write not cacheable, and previous non cacheable write registered
2229	if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
2230	{
2231	wbuf_write_miss = true;
2232	}
2233	else // try a registration into write buffer
2234	{
2235	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2236	r_dcache_save_be.read(),
2237	r_dcache_save_wdata.read(),
2238	r_dcache_save_cacheable.read() );
2239	#ifdef INSTRUMENTATION
2240	m_cpt_wbuf_write++;
2241	#endif
2242	if ( not wok ) // miss if write buffer full
2243	{
2244	wbuf_write_miss = true;
2245	}
2246	else // update the write_buffer state extension
2247	{
2248	if(not r_dcache_pending_unc_write.read())
2249	r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
2250	}
2251	}
2252	} // end WBUF update
2253
2254	// Computing the response to processor,
2255	// and the next value for r_dcache_fsm
2256
2257	// itlb/dtlb invalidation self-request
2258	if ( tlb_inval_required )
2259	{
2260	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2261	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2262	}
2263
2264	// coherence request (from CC_RECEIVE FSM)
2265	else if ( r_cc_receive_dcache_req.read() )
2266	{
2267	r_dcache_fsm = DCACHE_CC_CHECK;
2268	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2269	}
2270
2271	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2272	// we don't take the processor request, and registers
2273	// are frozen in case of wbuf_write_miss
2274	else if ( m_dreq.valid and not wbuf_write_miss )
2275	{
2276	// register processor request and DCACHE response
2277	r_dcache_save_vaddr = m_dreq.addr;
2278	r_dcache_save_be = m_dreq.be;
2279	r_dcache_save_wdata = m_dreq.wdata;
2280	r_dcache_save_paddr = paddr;
2281	r_dcache_save_cache_way = cache_way;
2282	r_dcache_save_cache_set = cache_set;
2283	r_dcache_save_cache_word = cache_word;
2284
2285	// READ XTN requests from processor
2286	// They are executed in this DCACHE_IDLE state.
2287	// The processor must not be in user mode
2288	if (m_dreq.type == iss_t::XTN_READ)
2289	{
2290	int xtn_opcode = (int)m_dreq.addr/4;
2291
2292	// checking processor mode:
2293	if (m_dreq.mode == iss_t::MODE_USER)
2294	{
2295	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2296	r_mmu_dbvar = m_dreq.addr;
2297	m_drsp.valid = true;
2298	m_drsp.error = true;
2299	m_drsp.rdata = 0;
2300	r_dcache_fsm = DCACHE_IDLE;
2301	}
2302	else
2303	{
2304	switch( xtn_opcode )
2305	{
2306	case iss_t::XTN_INS_ERROR_TYPE:
2307	m_drsp.rdata = r_mmu_ietr.read();
2308	m_drsp.valid = true;
2309	m_drsp.error = false;
2310	break;
2311
2312	case iss_t::XTN_DATA_ERROR_TYPE:
2313	m_drsp.rdata = r_mmu_detr.read();
2314	m_drsp.valid = true;
2315	m_drsp.error = false;
2316	break;
2317
2318	case iss_t::XTN_INS_BAD_VADDR:
2319	m_drsp.rdata = r_mmu_ibvar.read();
2320	m_drsp.valid = true;
2321	m_drsp.error = false;
2322	break;
2323
2324	case iss_t::XTN_DATA_BAD_VADDR:
2325	m_drsp.rdata = r_mmu_dbvar.read();
2326	m_drsp.valid = true;
2327	m_drsp.error = false;
2328	break;
2329
2330	case iss_t::XTN_PTPR:
2331	m_drsp.rdata = r_mmu_ptpr.read();
2332	m_drsp.valid = true;
2333	m_drsp.error = false;
2334	break;
2335
2336	case iss_t::XTN_TLB_MODE:
2337	m_drsp.rdata = r_mmu_mode.read();
2338	m_drsp.valid = true;
2339	m_drsp.error = false;
2340	break;
2341
2342	case iss_t::XTN_MMU_PARAMS:
2343	m_drsp.rdata = r_mmu_params;
2344	m_drsp.valid = true;
2345	m_drsp.error = false;
2346	break;
2347
2348	case iss_t::XTN_MMU_RELEASE:
2349	m_drsp.rdata = r_mmu_release;
2350	m_drsp.valid = true;
2351	m_drsp.error = false;
2352	break;
2353
2354	case iss_t::XTN_MMU_WORD_LO:
2355	m_drsp.rdata = r_mmu_word_lo.read();
2356	m_drsp.valid = true;
2357	m_drsp.error = false;
2358	break;
2359
2360	case iss_t::XTN_MMU_WORD_HI:
2361	m_drsp.rdata = r_mmu_word_hi.read();
2362	m_drsp.valid = true;
2363	m_drsp.error = false;
2364	break;
2365
2366	default:
2367	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2368	r_mmu_dbvar = m_dreq.addr;
2369	m_drsp.valid = true;
2370	m_drsp.error = true;
2371	m_drsp.rdata = 0;
2372	break;
2373	} // end switch xtn_opcode
2374	} // end else
2375	} // end if XTN_READ
2376
2377	// Handling WRITE XTN requests from processor.
2378	// They are not executed in this DCACHE_IDLE state
2379	// if they require access to the caches or the TLBs
2380	// that are already accessed.
2381	// Caches can be invalidated or flushed in user mode,
2382	// and the sync instruction can be executed in user mode
2383	else if (m_dreq.type == iss_t::XTN_WRITE)
2384	{
2385	int xtn_opcode = (int)m_dreq.addr/4;
2386	r_dcache_xtn_opcode = xtn_opcode;
2387
2388	// checking processor mode:
2389	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2390	(xtn_opcode != iss_t:: XTN_SYNC) &&
2391	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2392	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2393	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2394	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2395	{
2396	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2397	r_mmu_dbvar = m_dreq.addr;
2398	m_drsp.valid = true;
2399	m_drsp.error = true;
2400	m_drsp.rdata = 0;
2401	r_dcache_fsm = DCACHE_IDLE;
2402	}
2403	else
2404	{
2405	switch( xtn_opcode )
2406	{
2407	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2408	r_dcache_xtn_req = true;
2409	r_dcache_fsm = DCACHE_XTN_SWITCH;
2410	break;
2411
2412	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2413	r_mmu_mode = m_dreq.wdata;
2414	m_drsp.valid = true;
2415	r_dcache_fsm = DCACHE_IDLE;
2416	break;
2417
2418	case iss_t::XTN_DTLB_INVAL: // dtlb access
2419	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2420	break;
2421
2422	case iss_t::XTN_ITLB_INVAL: // itlb access
2423	r_dcache_xtn_req = true;
2424	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2425	break;
2426
2427	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2428	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2429	break;
2430
2431	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2432	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2433	if (sizeof(paddr_t) <= 32)
2434	{
2435	assert(r_mmu_word_hi.read() == 0 &&
2436	"high bits should be 0 for 32bit paddr");
2437	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2438	}
2439	else
2440	{
2441	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2442	(paddr_t)r_mmu_word_lo.read();
2443	}
2444	break;
2445
2446	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2447	r_dcache_flush_count = 0;
2448	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2449	break;
2450
2451	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2452	r_dcache_xtn_req = true;
2453	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2454	break;
2455
2456	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2457	r_dcache_xtn_req = true;
2458	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2459	break;
2460
2461	case iss_t::XTN_ICACHE_FLUSH: // icache access
2462	r_dcache_xtn_req = true;
2463	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2464	break;
2465
2466	case iss_t::XTN_SYNC: // wait until write buffer empty
2467	r_dcache_fsm = DCACHE_XTN_SYNC;
2468	break;
2469
2470	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2471	r_mmu_word_lo = m_dreq.wdata;
2472	m_drsp.valid = true;
2473	r_dcache_fsm = DCACHE_IDLE;
2474	break;
2475
2476	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2477	r_mmu_word_hi = m_dreq.wdata;
2478	m_drsp.valid = true;
2479	r_dcache_fsm = DCACHE_IDLE;
2480	break;
2481
2482	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2483	r_dcache_llsc_valid = false;
2484	m_drsp.valid = true;
2485	r_dcache_fsm = DCACHE_IDLE;
2486	break;
2487
2488	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2489	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2490	m_drsp.valid = true;
2491	r_dcache_fsm = DCACHE_IDLE;
2492	break;
2493
2494	default:
2495	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2496	r_mmu_dbvar = m_dreq.addr;
2497	m_drsp.valid = true;
2498	m_drsp.error = true;
2499	r_dcache_fsm = DCACHE_IDLE;
2500	break;
2501	} // end switch xtn_opcode
2502	} // end else
2503	} // end if XTN_WRITE
2504
2505	// Handling processor requests to address space (READ/WRITE/LL/SC)
2506	// The dtlb and dcache can be activated or not.
2507	// We compute the cacheability, and check processor request validity:
2508	// - If DTLB not activated : cacheability is defined by the segment table,
2509	// and there is no access rights checking.
2510	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2511	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2512	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2513	else
2514	{
2515	bool valid_req;
2516	bool cacheable;
2517
2518	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2519	{
2520	valid_req = true;
2521
2522	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2523	else cacheable = m_cacheability_table[m_dreq.addr];
2524	}
2525	else // dtlb activated
2526	{
2527	if ( tlb_hit ) // tlb hit
2528	{
2529	// cacheability
2530	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2531	else cacheable = tlb_flags.c;
2532
2533	// access rights checking
2534	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2535	{
2536	if ( (m_dreq.type == iss_t::DATA_READ) or
2537	(m_dreq.type == iss_t::DATA_LL) )
2538	{
2539	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2540	}
2541	else
2542	{
2543	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2544	}
2545	valid_req = false;
2546	r_mmu_dbvar = m_dreq.addr;
2547	m_drsp.valid = true;
2548	m_drsp.error = true;
2549	m_drsp.rdata = 0;
2550	#if DEBUG_DCACHE
2551	if ( m_debug_dcache_fsm )
2552	{
2553	std::cout << " <PROC " << name()
2554	<< ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2555	}
2556	#endif
2557	}
2558	else if ( not tlb_flags.w and
2559	((m_dreq.type == iss_t::DATA_WRITE) or
2560	(m_dreq.type == iss_t::DATA_SC)) )
2561	{
2562	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2563	valid_req = false;
2564	r_mmu_dbvar = m_dreq.addr;
2565	m_drsp.valid = true;
2566	m_drsp.error = true;
2567	m_drsp.rdata = 0;
2568	#if DEBUG_DCACHE
2569	if ( m_debug_dcache_fsm )
2570	{
2571	std::cout << " <PROC " << name()
2572	<< ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2573	}
2574	#endif
2575	}
2576	else
2577	{
2578	valid_req = true;
2579	}
2580	}
2581	else // tlb miss
2582	{
2583	valid_req = false;
2584	r_dcache_tlb_vaddr = m_dreq.addr;
2585	r_dcache_tlb_ins = false;
2586	r_dcache_fsm = DCACHE_TLB_MISS;
2587	}
2588	} // end DTLB activated
2589
2590	if ( valid_req ) // processor request is valid after TLB check
2591	{
2592	r_dcache_save_cacheable = cacheable;
2593
2594	// READ request
2595	// The read requests are taken only if there is no cache update.
2596	// We request a VCI transaction to CMD FSM if miss or uncachable
2597	if ( ((m_dreq.type == iss_t::DATA_READ))
2598	and not r_dcache_updt_req.read() )
2599	{
2600	if ( cacheable ) // cacheable read
2601	{
2602	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2603	{
2604	#ifdef INSTRUMENTATION
2605	m_cpt_dcache_miss++;
2606	#endif
2607	// request a VCI DMISS transaction
2608	r_dcache_vci_paddr = paddr;
2609	r_dcache_vci_miss_req = true;
2610	r_dcache_miss_type = PROC_MISS;
2611	r_dcache_fsm = DCACHE_MISS_SELECT;
2612	#if DEBUG_DCACHE
2613	if ( m_debug_dcache_fsm )
2614	{
2615	std::cout << " <PROC " << name()
2616	<< ".DCACHE_IDLE> READ MISS in dcache" << std::endl;
2617	}
2618	#endif
2619	}
2620	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2621	{
2622	// stalled until cleanup is acknowledged
2623	r_dcache_fsm = DCACHE_IDLE;
2624	}
2625	else // cache hit
2626	{
2627	#ifdef INSTRUMENTATION
2628	m_cpt_data_read++;
2629	#endif
2630	// returns data to processor
2631	m_drsp.valid = true;
2632	m_drsp.error = false;
2633	m_drsp.rdata = cache_rdata;
2634	#if DEBUG_DCACHE
2635	if ( m_debug_dcache_fsm )
2636	{
2637	std::cout << " <PROC " << name()
2638	<< ".DCACHE_IDLE> READ HIT in dcache" << std::endl;
2639	}
2640	#endif
2641	}
2642	}
2643	else // uncacheable read
2644	{
2645	r_dcache_vci_paddr = paddr;
2646	r_dcache_vci_unc_be = m_dreq.be;
2647	r_dcache_vci_unc_req = true;
2648	r_dcache_fsm = DCACHE_UNC_WAIT;
2649	#if DEBUG_DCACHE
2650	if ( m_debug_dcache_fsm )
2651	{
2652	std::cout << " <PROC " << name()
2653	<< ".DCACHE_IDLE> READ UNCACHEABLE in dcache" << std::endl;
2654	}
2655	#endif
2656	}
2657	} // end READ
2658
2659	// LL request (non cachable)
2660	// We request a VCI LL transaction to CMD FSM and register
2661	// the LL/SC operation in llsc buffer.
2662	else if (m_dreq.type == iss_t::DATA_LL)
2663	{
2664	// register paddr in LLSC buffer
2665	r_dcache_llsc_paddr = paddr;
2666	r_dcache_llsc_count = LLSC_TIMEOUT;
2667	r_dcache_llsc_valid = true;
2668
2669	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2670	r_dcache_vci_ll_req = true;
2671	r_dcache_vci_paddr = paddr;
2672	r_dcache_ll_rsp_count = 0;
2673	r_dcache_fsm = DCACHE_LL_WAIT;
2674
2675	}// end LL
2676
2677	// WRITE request:
2678	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2679	// the processor and set the Dirty bit before handling the write request,
2680	// going to the DCACHE_DIRTY_GT_PTE state.
2681	// If we don't need to set the Dirty bit, we can acknowledge
2682	// the processor request, as the write arguments (including the
2683	// physical address) are registered in r_dcache_save registers,
2684	// and the write will be done in the P1 pipeline stage.
2685	else if ( m_dreq.type == iss_t::DATA_WRITE )
2686	{
2687	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2688	and not tlb_flags.d ) // Dirty bit must be set
2689	{
2690	// The PTE physical address is obtained from the nline value (dtlb),
2691	// and from the virtual address (word index)
2692	if ( tlb_flags.b ) // PTE1
2693	{
2694	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2695	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2696	}
2697	else // PTE2
2698	{
2699	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2700	(paddr_t)((m_dreq.addr>>9) & 0x38);
2701	}
2702	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2703	}
2704	else // Write request accepted
2705	{
2706	#ifdef INSTRUMENTATION
2707	m_cpt_data_write++;
2708	#endif
2709	// cleaning llsc buffer if address matching
2710	if ( paddr == r_dcache_llsc_paddr.read() )
2711	r_dcache_llsc_valid = false;
2712
2713	// response to processor
2714	m_drsp.valid = true;
2715
2716	// activating P1 stage
2717	wbuf_request = true;
2718	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2719	}
2720	} // end WRITE
2721
2722	// SC request:
2723	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2724	// the processor and set the Dirty bit before handling the write request,
2725	// going to the DCACHE_DIRTY_GT_PTE state.
2726	// If we don't need to set the Dirty bit, we test the llsc buffer:
2727	// If failure, we send a negative response to processor.
2728	// If success, we request a SC transaction to CMD FSM and go
2729	// to DCACHE_SC_WAIT state.
2730	// We don't check a possible write hit in dcache, as the cache update
2731	// is done by the coherence transaction induced by the SC...
2732	else if ( m_dreq.type == iss_t::DATA_SC )
2733	{
2734	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2735	and not tlb_flags.d ) // Dirty bit must be set
2736	{
2737	// The PTE physical address is obtained from the nline value (dtlb),
2738	// and the word index (virtual address)
2739	if ( tlb_flags.b ) // PTE1
2740	{
2741	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2742	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2743	}
2744	else // PTE2
2745	{
2746	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2747	(paddr_t)((m_dreq.addr>>9) & 0x38);
2748	}
2749	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2750	m_drsp.valid = false;
2751	m_drsp.error = false;
2752	m_drsp.rdata = 0;
2753	}
2754	else // SC request accepted
2755	{
2756	#ifdef INSTRUMENTATION
2757	m_cpt_data_sc++;
2758	#endif
2759	// checking local success
2760	if( r_dcache_llsc_valid.read() and
2761	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2762	{
2763	// request an SC CMD and go to DCACHE_SC_WAIT state
2764	r_dcache_vci_paddr = paddr;
2765	r_dcache_vci_sc_req = true;
2766	r_dcache_vci_sc_data = m_dreq.wdata;
2767	r_dcache_fsm = DCACHE_SC_WAIT;
2768	}
2769	else // local fail
2770	{
2771	m_drsp.valid = true;
2772	m_drsp.error = false;
2773	m_drsp.rdata = 0x1;
2774	}
2775	}
2776	} // end SC
2777	} // end valid_req
2778	} // end if read/write/ll/sc request
2779	} // end processor request
2780
2781	// itlb miss request
2782	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2783	{
2784	r_dcache_tlb_ins = true;
2785	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2786	r_dcache_fsm = DCACHE_TLB_MISS;
2787	}
2788
2789	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2790	r_dcache_updt_req = updt_request;
2791	r_dcache_wbuf_req = wbuf_request or
2792	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2793	break;
2794	}
2795	/////////////////////
2796	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2797	// Input arguments are:
2798	// - r_dcache_tlb_vaddr
2799	// - r_dcache_tlb_ins (true when itlb miss)
2800	// The sub-fsm access the dcache to find the missing TLB entry,
2801	// and activates the cache miss procedure in case of miss.
2802	// It bypass the first level page table access if possible.
2803	// It uses atomic access to update the R/L access bits
2804	// in the page table if required.
2805	// It directly updates the itlb or dtlb, and writes into the
2806	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2807	{
2808	uint32_t ptba = 0;
2809	bool bypass;
2810	paddr_t pte_paddr;
2811
2812	// evaluate bypass in order to skip first level page table access
2813	if ( r_dcache_tlb_ins.read() ) // itlb miss
2814	{
2815	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2816	}
2817	else // dtlb miss
2818	{
2819	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2820	}
2821
2822	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2823	{
2824	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2825	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2826	r_dcache_tlb_paddr = pte_paddr;
2827	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2828	}
2829	else // Try to read PTE2 in dcache
2830	{
2831	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2832	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2833	r_dcache_tlb_paddr = pte_paddr;
2834	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2835	}
2836
2837	#if DEBUG_DCACHE
2838	if ( m_debug_dcache_fsm )
2839	{
2840	if ( r_dcache_tlb_ins.read() )
2841	{
2842	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
2843	}
2844	else
2845	{
2846	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
2847	}
2848	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2849	<< " / BYPASS = " << bypass
2850	<< " / PTE_ADR = " << pte_paddr << std::endl;
2851	}
2852	#endif
2853
2854	break;
2855	}
2856	/////////////////////////
2857	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2858	{
2859	uint32_t entry;
2860	size_t way;
2861	size_t set;
2862	size_t word;
2863	int cache_state;
2864	r_dcache.read( r_dcache_tlb_paddr.read(),
2865	&entry,
2866	&way,
2867	&set,
2868	&word,
2869	&cache_state );
2870	#ifdef INSTRUMENTATION
2871	m_cpt_dcache_data_read++;
2872	m_cpt_dcache_dir_read++;
2873	#endif
2874	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
2875	{
2876	if ( not (entry & PTE_V_MASK) ) // unmapped
2877	{
2878	if ( r_dcache_tlb_ins.read() )
2879	{
2880	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2881	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2882	r_icache_tlb_miss_req = false;
2883	r_icache_tlb_rsp_error = true;
2884	}
2885	else
2886	{
2887	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2888	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2889	m_drsp.valid = true;
2890	m_drsp.error = true;
2891	}
2892	r_dcache_fsm = DCACHE_IDLE;
2893
2894	#if DEBUG_DCACHE
2895	if ( m_debug_dcache_fsm )
2896	{
2897	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2898	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2899	<< std::dec << " / way = " << way
2900	<< std::dec << " / set = " << set
2901	<< std::dec << " / word = " << word
2902	<< std::hex << " / PTE1 = " << entry << std::endl;
2903	}
2904	#endif
2905
2906	}
2907	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2908	{
2909	// mark the cache line ac containing a PTD
2910	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2911
2912	// register bypass
2913	if ( r_dcache_tlb_ins.read() ) // itlb
2914	{
2915	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2916	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2917	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
2918	}
2919	else // dtlb
2920	{
2921	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2922	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2923	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
2924	}
2925	r_dcache_tlb_paddr =
2926	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2927	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2928	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2929
2930	#if DEBUG_DCACHE
2931	if ( m_debug_dcache_fsm )
2932	{
2933	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2934	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2935	<< std::dec << " / way = " << way
2936	<< std::dec << " / set = " << set
2937	<< std::dec << " / word = " << word
2938	<< std::hex << " / PTD = " << entry << std::endl;
2939	}
2940	#endif
2941	}
2942	else // PTE1 : we must update the TLB
2943	{
2944	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2945	r_dcache_tlb_pte_flags = entry;
2946	r_dcache_tlb_cache_way = way;
2947	r_dcache_tlb_cache_set = set;
2948	r_dcache_tlb_cache_word = word;
2949	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2950
2951	#if DEBUG_DCACHE
2952	if ( m_debug_dcache_fsm )
2953	{
2954	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2955	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2956	<< std::dec << " / way = " << way
2957	<< std::dec << " / set = " << set
2958	<< std::dec << " / word = " << word
2959	<< std::hex << " / PTE1 = " << entry << std::endl;
2960	}
2961	#endif
2962	}
2963	}
2964	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2965	{
2966	// stalled until cleanup is acknowledged
2967	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2968	}
2969	else // we must load the missing cache line in dcache
2970	{
2971	r_dcache_vci_miss_req = true;
2972	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2973	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
2974	r_dcache_miss_type = PTE1_MISS;
2975	r_dcache_fsm = DCACHE_MISS_SELECT;
2976
2977	#if DEBUG_DCACHE
2978	if ( m_debug_dcache_fsm )
2979	{
2980	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
2981	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2982	}
2983	#endif
2984	}
2985	break;
2986	}
2987	////////////////////////////
2988	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2989	{
2990	size_t way;
2991	size_t set;
2992
2993	if ( r_dcache_tlb_ins.read() )
2994	{
2995	r_itlb.select( r_dcache_tlb_vaddr.read(),
2996	true, // PTE1
2997	&way,
2998	&set );
2999	#ifdef INSTRUMENTATION
3000	m_cpt_itlb_read++;
3001	#endif
3002	}
3003	else
3004	{
3005	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3006	true, // PTE1
3007	&way,
3008	&set );
3009	#ifdef INSTRUMENTATION
3010	m_cpt_dtlb_read++;
3011	#endif
3012	}
3013	r_dcache_tlb_way = way;
3014	r_dcache_tlb_set = set;
3015	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3016
3017	#if DEBUG_DCACHE
3018	if ( m_debug_dcache_fsm )
3019	{
3020	if ( r_dcache_tlb_ins.read() )
3021	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3022	else
3023	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3024	std::cout << " way = " << std::dec << way
3025	<< " / set = " << set << std::endl;
3026	}
3027	#endif
3028	break;
3029	}
3030	//////////////////////////
3031	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3032	// - if L/R bit already set, exit the sub-fsm.
3033	// - if not, we update the page table but we dont write
3034	// neither in DCACHE, nor in TLB, as this will be done by
3035	// the coherence mechanism.
3036	{
3037	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3038	uint32_t pte = r_dcache_tlb_pte_flags.read();
3039	bool pt_updt = false;
3040	bool local = true;
3041
3042	// We should compute the access locality:
3043	// The PPN MSB bits define the destination cluster index.
3044	// The m_srcid_d MSB bits define the source cluster index.
3045	// The number of bits to compare depends on the number of clusters,
3046	// and can be obtained in the mapping table.
3047	// As long as this computation is not done, all access are local.
3048
3049	if ( local ) // local access
3050	{
3051	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3052	{
3053	pt_updt = true;
3054	r_dcache_vci_cas_old = pte;
3055	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3056	pte = pte \| PTE_L_MASK;
3057	r_dcache_tlb_pte_flags = pte;
3058	}
3059	}
3060	else // remote access
3061	{
3062	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3063	{
3064	pt_updt = true;
3065	r_dcache_vci_cas_old = pte;
3066	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3067	pte = pte \| PTE_R_MASK;
3068	r_dcache_tlb_pte_flags = pte;
3069	}
3070	}
3071
3072	if ( not pt_updt ) // update TLB and return
3073	{
3074	if ( r_dcache_tlb_ins.read() )
3075	{
3076	r_itlb.write( true, // 2M page
3077	pte,
3078	0, // argument unused for a PTE1
3079	r_dcache_tlb_vaddr.read(),
3080	r_dcache_tlb_way.read(),
3081	r_dcache_tlb_set.read(),
3082	nline );
3083	#ifdef INSTRUMENTATION
3084	m_cpt_itlb_write++;
3085	#endif
3086
3087	#if DEBUG_DCACHE
3088	if ( m_debug_dcache_fsm )
3089	{
3090	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3091	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3092	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3093	r_itlb.printTrace();
3094	}
3095	#endif
3096	}
3097	else
3098	{
3099	r_dtlb.write( true, // 2M page
3100	pte,
3101	0, // argument unused for a PTE1
3102	r_dcache_tlb_vaddr.read(),
3103	r_dcache_tlb_way.read(),
3104	r_dcache_tlb_set.read(),
3105	nline );
3106	#ifdef INSTRUMENTATION
3107	m_cpt_dtlb_write++;
3108	#endif
3109
3110	#if DEBUG_DCACHE
3111	if ( m_debug_dcache_fsm )
3112	{
3113	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3114	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3115	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3116	r_dtlb.printTrace();
3117	}
3118	#endif
3119	}
3120	r_dcache_fsm = DCACHE_TLB_RETURN;
3121	}
3122	else // update page table but not TLB
3123	{
3124	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3125
3126	#if DEBUG_DCACHE
3127	if ( m_debug_dcache_fsm )
3128	{
3129	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3130	<< std::endl;
3131	}
3132	#endif
3133	}
3134	break;
3135	}
3136	/////////////////////////
3137	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3138	{
3139	uint32_t pte_flags;
3140	uint32_t pte_ppn;
3141	size_t way;
3142	size_t set;
3143	size_t word;
3144	int cache_state;
3145
3146	r_dcache.read( r_dcache_tlb_paddr.read(),
3147	&pte_flags,
3148	&pte_ppn,
3149	&way,
3150	&set,
3151	&word,
3152	&cache_state );
3153	#ifdef INSTRUMENTATION
3154	m_cpt_dcache_data_read++;
3155	m_cpt_dcache_dir_read++;
3156	#endif
3157	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
3158	{
3159	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3160	{
3161	if ( r_dcache_tlb_ins.read() )
3162	{
3163	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3164	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3165	r_icache_tlb_miss_req = false;
3166	r_icache_tlb_rsp_error = true;
3167	}
3168	else
3169	{
3170	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3171	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3172	m_drsp.valid = true;
3173	m_drsp.error = true;
3174	}
3175	r_dcache_fsm = DCACHE_IDLE;
3176
3177	#if DEBUG_DCACHE
3178	if ( m_debug_dcache_fsm )
3179	{
3180	std::cout << " <PROC " << name()
3181	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3182	<< " PTE_FLAGS = " << std::hex << pte_flags
3183	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3184	}
3185	#endif
3186	}
3187	else // mapped : we must update the TLB
3188	{
3189	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3190	r_dcache_tlb_pte_flags = pte_flags;
3191	r_dcache_tlb_pte_ppn = pte_ppn;
3192	r_dcache_tlb_cache_way = way;
3193	r_dcache_tlb_cache_set = set;
3194	r_dcache_tlb_cache_word = word;
3195	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3196
3197	#if DEBUG_DCACHE
3198	if ( m_debug_dcache_fsm )
3199	{
3200	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
3201	<< " PTE_FLAGS = " << std::hex << pte_flags
3202	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3203	}
3204	#endif
3205	}
3206	}
3207	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3208	{
3209	// stalled until cleanup is acknowledged
3210	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3211	}
3212	else // we must load the missing cache line in dcache
3213	{
3214	r_dcache_fsm = DCACHE_MISS_SELECT;
3215	r_dcache_vci_miss_req = true;
3216	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3217	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3218	r_dcache_miss_type = PTE2_MISS;
3219
3220	#if DEBUG_DCACHE
3221	if ( m_debug_dcache_fsm )
3222	{
3223	std::cout << " <PROC " << name()
3224	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3225	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3226	}
3227	#endif
3228	}
3229	break;
3230	}
3231	////////////////////////////
3232	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3233	{
3234	size_t way;
3235	size_t set;
3236
3237	if ( r_dcache_tlb_ins.read() )
3238	{
3239	r_itlb.select( r_dcache_tlb_vaddr.read(),
3240	false, // PTE2
3241	&way,
3242	&set );
3243	#ifdef INSTRUMENTATION
3244	m_cpt_itlb_read++;
3245	#endif
3246	}
3247	else
3248	{
3249	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3250	false, // PTE2
3251	&way,
3252	&set );
3253	#ifdef INSTRUMENTATION
3254	m_cpt_dtlb_read++;
3255	#endif
3256	}
3257
3258	#if DEBUG_DCACHE
3259	if ( m_debug_dcache_fsm )
3260	{
3261	if ( r_dcache_tlb_ins.read() )
3262	std::cout << " <PROC " << name()
3263	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3264	else
3265	std::cout << " <PROC " << name()
3266	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3267	std::cout << " way = " << std::dec << way
3268	<< " / set = " << set << std::endl;
3269	}
3270	#endif
3271	r_dcache_tlb_way = way;
3272	r_dcache_tlb_set = set;
3273	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3274	break;
3275	}
3276	//////////////////////////
3277	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3278	// - if L/R bit already set, exit the sub-fsm.
3279	// - if not, we update the page table but we dont write
3280	// neither in DCACHE, nor in TLB, as this will be done by
3281	// the coherence mechanism.
3282	{
3283	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3284	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3285	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3286	bool pt_updt = false;
3287	bool local = true;
3288
3289	// We should compute the access locality:
3290	// The PPN MSB bits define the destination cluster index.
3291	// The m_srcid_d MSB bits define the source cluster index.
3292	// The number of bits to compare depends on the number of clusters,
3293	// and can be obtained in the mapping table.
3294	// As long as this computation is not done, all access are local.
3295
3296	if ( local ) // local access
3297	{
3298	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3299	{
3300	pt_updt = true;
3301	r_dcache_vci_cas_old = pte_flags;
3302	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3303	pte_flags = pte_flags \| PTE_L_MASK;
3304	r_dcache_tlb_pte_flags = pte_flags;
3305	}
3306	}
3307	else // remote access
3308	{
3309	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3310	{
3311	pt_updt = true;
3312	r_dcache_vci_cas_old = pte_flags;
3313	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3314	pte_flags = pte_flags \| PTE_R_MASK;
3315	r_dcache_tlb_pte_flags = pte_flags;
3316	}
3317	}
3318
3319	if ( not pt_updt ) // update TLB
3320	{
3321	if ( r_dcache_tlb_ins.read() )
3322	{
3323	r_itlb.write( false, // 4K page
3324	pte_flags,
3325	pte_ppn,
3326	r_dcache_tlb_vaddr.read(),
3327	r_dcache_tlb_way.read(),
3328	r_dcache_tlb_set.read(),
3329	nline );
3330	#ifdef INSTRUMENTATION
3331	m_cpt_itlb_write++;
3332	#endif
3333
3334	#if DEBUG_DCACHE
3335	if ( m_debug_dcache_fsm )
3336	{
3337	std::cout << " <PROC " << name()
3338	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3339	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3340	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3341	r_itlb.printTrace();
3342	}
3343	#endif
3344	}
3345	else
3346	{
3347	r_dtlb.write( false, // 4K page
3348	pte_flags,
3349	pte_ppn,
3350	r_dcache_tlb_vaddr.read(),
3351	r_dcache_tlb_way.read(),
3352	r_dcache_tlb_set.read(),
3353	nline );
3354	#ifdef INSTRUMENTATION
3355	m_cpt_dtlb_write++;
3356	#endif
3357
3358	#if DEBUG_DCACHE
3359	if ( m_debug_dcache_fsm )
3360	{
3361	std::cout << " <PROC " << name()
3362	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3363	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3364	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3365	r_dtlb.printTrace();
3366	}
3367	#endif
3368
3369	}
3370	r_dcache_fsm = DCACHE_TLB_RETURN;
3371	}
3372	else // update page table but not TLB
3373	{
3374	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3375
3376	#if DEBUG_DCACHE
3377	if ( m_debug_dcache_fsm )
3378	{
3379	std::cout << " <PROC " << name()
3380	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3381	}
3382	#endif
3383	}
3384	break;
3385	}
3386	////////////////////////
3387	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3388	{
3389	#if DEBUG_DCACHE
3390	if ( m_debug_dcache_fsm )
3391	{
3392	std::cout << " <PROC " << name()
3393	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3394	}
3395	#endif
3396	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3397	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3398
3399	// checking llsc reservation buffer
3400	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3401	r_dcache_llsc_valid = false;
3402
3403	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3404	r_dcache_vci_cas_req = true;
3405	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3406	break;
3407	}
3408	////////////////////////
3409	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3410	// We consume the response in rsp FIFO,
3411	// and exit the sub-fsm, but we don't
3412	// analyse the response, because we don't
3413	// care if the L/R bit update is not done.
3414	// We must take the coherence requests because
3415	// there is a risk of dead-lock
3416
3417	{
3418	// coherence request (from CC_RECEIVE FSM)
3419	if ( r_cc_receive_dcache_req.read() )
3420	{
3421	r_dcache_fsm = DCACHE_CC_CHECK;
3422	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3423	break;
3424	}
3425
3426	if ( r_vci_rsp_data_error.read() ) // bus error
3427	{
3428	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3429	std::cout << "This should not happen in this state" << std::endl;
3430	exit(0);
3431	}
3432	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3433	{
3434	#if DEBUG_DCACHE
3435	if ( m_debug_dcache_fsm )
3436	{
3437	std::cout << " <PROC " << name()
3438	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3439	}
3440	#endif
3441	vci_rsp_fifo_dcache_get = true;
3442	r_dcache_fsm = DCACHE_TLB_RETURN;
3443	}
3444	break;
3445	}
3446	///////////////////////
3447	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3448	{
3449	#if DEBUG_DCACHE
3450	if ( m_debug_dcache_fsm )
3451	{
3452	std::cout << " <PROC " << name()
3453	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3454	}
3455	#endif
3456	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3457	r_dcache_fsm = DCACHE_IDLE;
3458	break;
3459	}
3460	///////////////////////
3461	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3462	// and both itlb and dtlb must be flushed.
3463	// Caution : the itlb miss requests must be taken
3464	// to avoid dead-lock in case of simultaneous ITLB miss
3465	{
3466	// itlb miss request
3467	if ( r_icache_tlb_miss_req.read() )
3468	{
3469	r_dcache_tlb_ins = true;
3470	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3471	r_dcache_fsm = DCACHE_TLB_MISS;
3472	break;
3473	}
3474
3475	if ( not r_dcache_xtn_req.read() )
3476	{
3477	r_dtlb.flush();
3478	r_mmu_ptpr = m_dreq.wdata;
3479	r_dcache_fsm = DCACHE_IDLE;
3480	m_drsp.valid = true;
3481	}
3482	break;
3483	}
3484	/////////////////////
3485	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3486	// The coherence request must be taken
3487	// as there is a risk of dead-lock
3488	{
3489	// coherence request (from CC_RECEIVE FSM)
3490	if ( r_cc_receive_dcache_req.read() )
3491	{
3492	r_dcache_fsm = DCACHE_CC_CHECK;
3493	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3494	}
3495
3496	if ( r_wbuf.empty() )
3497	{
3498	m_drsp.valid = true;
3499	r_dcache_fsm = DCACHE_IDLE;
3500	}
3501	break;
3502	}
3503	////////////////////////
3504	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3505	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3506	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3507	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3508	// and because it can exist a simultaneous ITLB miss
3509	{
3510	// coherence request (from CC_RECEIVE FSM)
3511	if ( r_cc_receive_dcache_req.read() )
3512	{
3513	r_dcache_fsm = DCACHE_CC_CHECK;
3514	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3515	break;
3516	}
3517
3518	// itlb miss request
3519	if ( r_icache_tlb_miss_req.read() )
3520	{
3521	r_dcache_tlb_ins = true;
3522	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3523	r_dcache_fsm = DCACHE_TLB_MISS;
3524	break;
3525	}
3526
3527	// test if XTN request to icache completed
3528	if ( not r_dcache_xtn_req.read() )
3529	{
3530	r_dcache_fsm = DCACHE_IDLE;
3531	m_drsp.valid = true;
3532	}
3533	break;
3534	}
3535	/////////////////////////
3536	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3537	// r_dcache_flush_count as a slot counter,
3538	// looping in this state until all slots have been visited.
3539	// It can require two cycles per slot:
3540	// We test here the slot state, and make the actual inval
3541	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3542	// A cleanup request is generated for each valid line.
3543	// returns to IDLE and flush TLBs when last slot
3544	{
3545	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3546	{
3547	int state;
3548	uint32_t tag;
3549	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3550	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3551
3552	#ifdef INSTRUMENTATION
3553	m_cpt_dcache_dir_read++;
3554	#endif
3555	r_dcache.read_dir( way,
3556	set,
3557	&tag,
3558	&state );
3559
3560	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3561	{
3562	// request cleanup
3563	r_dcache_cc_send_req = true;
3564	r_dcache_cc_send_nline = tag * m_dcache_sets;
3565	r_dcache_cc_send_way = way;
3566	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3567
3568	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3569	r_dcache_miss_way = way;
3570	r_dcache_miss_set = set;
3571	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3572	}
3573	else if ( r_dcache_flush_count.read() ==
3574	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3575	{
3576	r_dtlb.reset();
3577	r_itlb.reset();
3578	r_dcache_fsm = DCACHE_IDLE;
3579	m_drsp.valid = true;
3580	}
3581
3582	// saturation counter
3583	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3584	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3585	}
3586	break;
3587	}
3588	////////////////////////////
3589	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3590	// and reset directory extension.
3591	// returns to IDLE and flush TLBs when last slot
3592	{
3593	size_t way = r_dcache_miss_way.read();
3594	size_t set = r_dcache_miss_set.read();
3595
3596	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3597	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3598
3599	#ifdef INSTRUMENTATION
3600	m_cpt_dcache_dir_write++;
3601	#endif
3602	r_dcache.write_dir( 0,
3603	way,
3604	set,
3605	CACHE_SLOT_STATE_ZOMBI );
3606
3607	if ( r_dcache_flush_count.read() ==
3608	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3609	{
3610	r_dtlb.reset();
3611	r_itlb.reset();
3612	r_dcache_fsm = DCACHE_IDLE;
3613	m_drsp.valid = true;
3614	}
3615	else
3616	{
3617	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3618	}
3619	break;
3620	}
3621	/////////////////////////
3622	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3623	{
3624	r_dtlb.inval(r_dcache_save_wdata.read());
3625	r_dcache_fsm = DCACHE_IDLE;
3626	m_drsp.valid = true;
3627	break;
3628	}
3629	////////////////////////////
3630	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3631	// requires 3 cycles: access tlb, read cache, inval cache
3632	// we compute the physical address in this state
3633	{
3634	paddr_t paddr;
3635	bool hit;
3636
3637	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3638	{
3639
3640	#ifdef INSTRUMENTATION
3641	m_cpt_dtlb_read++;
3642	#endif
3643	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3644	&paddr );
3645	}
3646	else // dtlb not activated
3647	{
3648	paddr = (paddr_t)r_dcache_save_wdata.read();
3649	hit = true;
3650	}
3651
3652	if ( hit ) // tlb hit
3653	{
3654	r_dcache_save_paddr = paddr;
3655	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3656	}
3657	else // tlb miss
3658	{
3659
3660	#ifdef INSTRUMENTATION
3661	m_cpt_dtlb_miss++;
3662	#endif
3663	r_dcache_tlb_ins = false; // dtlb
3664	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3665	r_dcache_fsm = DCACHE_TLB_MISS;
3666	}
3667
3668	#if DEBUG_DCACHE
3669	if ( m_debug_dcache_fsm )
3670	{
3671	std::cout << " <PROC " << name()
3672	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3673	<< " / VADDR = " << r_dcache_save_wdata.read()
3674	<< " / PADDR = " << paddr << std::endl;
3675	}
3676	#endif
3677
3678	break;
3679	}
3680	////////////////////////////
3681	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3682	// requires 2 cycles: read cache / inval cache
3683	// In this state we read dcache.
3684	{
3685	size_t way;
3686	size_t set;
3687	size_t word;
3688	int state;
3689
3690	#ifdef INSTRUMENTATION
3691	m_cpt_dcache_dir_read++;
3692	#endif
3693	r_dcache.read_dir( r_dcache_save_paddr.read(),
3694	&state,
3695	&way,
3696	&set,
3697	&word );
3698
3699	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3700	{
3701	r_dcache_xtn_way = way;
3702	r_dcache_xtn_set = set;
3703	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3704	}
3705	else // miss : nothing to do
3706	{
3707	r_dcache_fsm = DCACHE_IDLE;
3708	m_drsp.valid = true;
3709	}
3710
3711	#if DEBUG_DCACHE
3712	if ( m_debug_dcache_fsm )
3713	{
3714	std::cout << " <PROC " << name()
3715	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3716	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3717	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3718	<< " / SET = " << set
3719	<< " / WAY = " << way << std::endl;
3720	}
3721	#endif
3722	break;
3723	}
3724	////////////////////////////
3725	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3726	// Blocked if previous cleanup not completed
3727	// Test if itlb or dtlb inval is required
3728	{
3729	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3730	{
3731	size_t way = r_dcache_xtn_way.read();
3732	size_t set = r_dcache_xtn_set.read();
3733	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3734
3735	#ifdef INSTRUMENTATION
3736	m_cpt_dcache_dir_write++;
3737	#endif
3738	r_dcache.write_dir( 0,
3739	way,
3740	set,
3741	CACHE_SLOT_STATE_EMPTY );
3742
3743	// request cleanup
3744	r_dcache_cc_send_req = true;
3745	r_dcache_cc_send_nline = nline;
3746	r_dcache_cc_send_way = way;
3747	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3748
3749	// possible itlb & dtlb invalidate
3750	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3751	{
3752	r_dcache_tlb_inval_line = nline;
3753	r_dcache_tlb_inval_set = 0;
3754	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3755	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3756	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3757	}
3758	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3759	{
3760	r_itlb.reset();
3761	r_dtlb.reset();
3762	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3763	r_dcache_fsm = DCACHE_IDLE;
3764	m_drsp.valid = true;
3765	}
3766	else
3767	{
3768	r_dcache_fsm = DCACHE_IDLE;
3769	m_drsp.valid = true;
3770	}
3771
3772	#if DEBUG_DCACHE
3773	if ( m_debug_dcache_fsm )
3774	{
3775	std::cout << " <PROC " << name()
3776	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3777	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3778	}
3779	#endif
3780	}
3781	break;
3782	}
3783	//////////////////////////////
3784	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3785	{
3786	r_dcache_fsm = DCACHE_IDLE;
3787	m_drsp.valid = true;
3788	break;
3789	}
3790	////////////////////////
3791	case DCACHE_MISS_SELECT: // Try to select a slot in associative set
3792	// if previous cleanup has been sent.
3793	// Waiting in this state if no slot available
3794	// Set the r_dcache_cleanup_req flip-flop
3795	// and the r_dcache_miss_clack flip-flop
3796	// when a cleanup is required
3797	{
3798	if ( m_dreq.valid) m_cost_data_miss_frz++;
3799
3800	// coherence request (from CC_RECEIVE FSM)
3801	if ( r_cc_receive_dcache_req.read() )
3802	{
3803	r_dcache_fsm = DCACHE_CC_CHECK;
3804	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3805	break;
3806	}
3807
3808	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3809	{
3810	bool found;
3811	bool cleanup;
3812	size_t way;
3813	size_t set;
3814	paddr_t victim;
3815
3816	#ifdef INSTRUMENTATION
3817	m_cpt_dcache_dir_read++;
3818	#endif
3819	r_dcache.read_select( r_dcache_save_paddr.read(),
3820	&victim,
3821	&way,
3822	&set,
3823	&found,
3824	&cleanup );
3825	if ( found )
3826	{
3827	r_dcache_miss_way = way;
3828	r_dcache_miss_set = set;
3829
3830	if ( cleanup )
3831	{
3832	r_dcache_miss_clack = true;
3833	r_dcache_fsm = DCACHE_MISS_CLEAN;
3834	// request cleanup
3835	r_dcache_cc_send_req = true;
3836	r_dcache_cc_send_nline = victim;
3837	r_dcache_cc_send_way = way;
3838	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3839	}
3840	else
3841	{
3842	r_dcache_fsm = DCACHE_MISS_WAIT;
3843	}
3844
3845	#if DEBUG_DCACHE
3846	if ( m_debug_dcache_fsm )
3847	{
3848	std::cout << " <PROC " << name()
3849	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
3850	<< " / WAY = " << way
3851	<< " / SET = " << set
3852	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
3853	if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
3854	else std::cout << std::endl;
3855	}
3856	#endif
3857	} // end found
3858	}
3859	break;
3860	}
3861	///////////////////////
3862	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
3863	// and possibly request itlb or dtlb invalidate
3864	{
3865	if ( m_dreq.valid) m_cost_data_miss_frz++;
3866
3867	// coherence request (from CC_RECEIVE FSM)
3868	if ( r_cc_receive_dcache_req.read() )
3869	{
3870	r_dcache_fsm = DCACHE_CC_CHECK;
3871	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3872	break;
3873	}
3874
3875	size_t way = r_dcache_miss_way.read();
3876	size_t set = r_dcache_miss_set.read();
3877	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3878
3879	#ifdef INSTRUMENTATION
3880	m_cpt_dcache_dir_read++;
3881	#endif
3882	r_dcache.write_dir( 0,
3883	way,
3884	set,
3885	CACHE_SLOT_STATE_ZOMBI );
3886	#if DEBUG_DCACHE
3887	if ( m_debug_dcache_fsm )
3888	{
3889	std::cout << " <PROC " << name()
3890	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
3891	<< " / way = " << way
3892	<< " / set = " << set << std::endl;
3893	}
3894	#endif
3895	// if selective itlb & dtlb invalidate are required
3896	// the miss response is not handled before invalidate completed
3897	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3898	{
3899	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3900	r_dcache_tlb_inval_line = nline;
3901	r_dcache_tlb_inval_set = 0;
3902	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3903	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3904	}
3905	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3906	{
3907	r_itlb.reset();
3908	r_dtlb.reset();
3909	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3910	r_dcache_fsm = DCACHE_MISS_WAIT;
3911	}
3912	else
3913	{
3914	r_dcache_fsm = DCACHE_MISS_WAIT;
3915	}
3916	break;
3917	}
3918	//////////////////////
3919	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3920	// This state is in charge of error signaling
3921	// There is 5 types of error depending on the requester
3922	{
3923	if ( m_dreq.valid) m_cost_data_miss_frz++;
3924
3925	/**/
3926	#if DEBUG_DCACHE
3927	if ( m_debug_dcache_fsm )
3928	{
3929	std::cout << " <PROC " << name()
3930	<< " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
3931	std::cout << " <PROC " << name()
3932	<< " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
3933	}
3934	#endif
3935
3936	// coherence request (from CC_RECEIVE FSM)
3937	if ( r_cc_receive_dcache_req.read() )
3938	{
3939	r_dcache_fsm = DCACHE_CC_CHECK;
3940	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3941	break;
3942	}
3943
3944	if ( r_vci_rsp_data_error.read() ) // bus error
3945	{
3946	switch ( r_dcache_miss_type.read() )
3947	{
3948	case PROC_MISS:
3949	{
3950	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3951	r_mmu_dbvar = r_dcache_save_vaddr.read();
3952	m_drsp.valid = true;
3953	m_drsp.error = true;
3954	r_dcache_fsm = DCACHE_IDLE;
3955	break;
3956	}
3957	case PTE1_MISS:
3958	{
3959	if ( r_dcache_tlb_ins.read() )
3960	{
3961	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3962	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3963	r_icache_tlb_miss_req = false;
3964	r_icache_tlb_rsp_error = true;
3965	}
3966	else
3967	{
3968	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3969	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3970	m_drsp.valid = true;
3971	m_drsp.error = true;
3972	}
3973	r_dcache_fsm = DCACHE_IDLE;
3974	break;
3975	}
3976	case PTE2_MISS:
3977	{
3978	if ( r_dcache_tlb_ins.read() )
3979	{
3980	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3981	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3982	r_icache_tlb_miss_req = false;
3983	r_icache_tlb_rsp_error = true;
3984	}
3985	else
3986	{
3987	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3988	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3989	m_drsp.valid = true;
3990	m_drsp.error = true;
3991	}
3992	r_dcache_fsm = DCACHE_IDLE;
3993	break;
3994	}
3995	} // end switch type
3996	r_vci_rsp_data_error = false;
3997	}
3998	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3999	{
4000	r_dcache_miss_word = 0;
4001	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
4002	}
4003	break;
4004	}
4005	//////////////////////////
4006	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4007	{
4008	if ( m_dreq.valid) m_cost_data_miss_frz++;
4009
4010	/**/
4011	#if DEBUG_DCACHE
4012	if ( m_debug_dcache_fsm )
4013	{
4014	std::cout << " <PROC " << name()
4015	<< " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
4016	std::cout << " <PROC " << name()
4017	<< " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
4018	}
4019	#endif
4020
4021	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
4022	{
4023	#ifdef INSTRUMENTATION
4024	m_cpt_dcache_data_write++;
4025	#endif
4026	r_dcache.write( r_dcache_miss_way.read(),
4027	r_dcache_miss_set.read(),
4028	r_dcache_miss_word.read(),
4029	r_vci_rsp_fifo_dcache.read() );
4030	#if DEBUG_DCACHE
4031	if ( m_debug_dcache_fsm )
4032	{
4033	std::cout << " <PROC " << name()
4034	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4035	<< " / DATA = " << r_vci_rsp_fifo_dcache.read()
4036	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4037	<< " / SET = " << r_dcache_miss_set.read()
4038	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4039	}
4040	#endif
4041	vci_rsp_fifo_dcache_get = true;
4042	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4043
4044	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4045	{
4046	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4047	}
4048	}
4049	break;
4050	}
4051	//////////////////////////
4052	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4053	// and the cleanup ack has not been received,
4054	// as indicated by the r_dcache_miss clack.
4055	// - If no matching coherence request (r_dcache_inval_miss)
4056	// switch directory slot to VALID state.
4057	// - If matching coherence request, switch directory slot
4058	// to ZOMBI state, and send a cleanup request.
4059	{
4060	if ( m_dreq.valid) m_cost_data_miss_frz++;
4061
4062	/**/
4063	#if DEBUG_DCACHE
4064	if ( m_debug_dcache_fsm )
4065	{
4066	std::cout << " <PROC " << name()
4067	<< " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
4068	std::cout << " <PROC " << name()
4069	<< " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
4070	}
4071	#endif
4072
4073	// coherence request (from CC_RECEIVE FSM)
4074	if ( r_cc_receive_dcache_req.read() )
4075	{
4076	r_dcache_fsm = DCACHE_CC_CHECK;
4077	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4078	break;
4079	}
4080
4081	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4082	{
4083	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4084	{
4085	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
4086	{
4087	r_dcache_miss_inval = false;
4088	// request cleanup
4089	r_dcache_cc_send_req = true;
4090	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4091	r_dcache_cc_send_way = r_dcache_miss_way.read();
4092	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4093
4094	#ifdef INSTRUMENTATION
4095	m_cpt_dcache_dir_write++;
4096	#endif
4097	r_dcache.write_dir( r_dcache_save_paddr.read(),
4098	r_dcache_miss_way.read(),
4099	r_dcache_miss_set.read(),
4100	CACHE_SLOT_STATE_ZOMBI );
4101	#if DEBUG_DCACHE
4102	if ( m_debug_dcache_fsm )
4103	{
4104	std::cout << " <PROC " << name()
4105	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4106	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4107	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4108	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4109	}
4110	#endif
4111	}
4112	else
4113	break;
4114	}
4115	else // switch slot to VALID state
4116	{
4117
4118	#ifdef INSTRUMENTATION
4119	m_cpt_dcache_dir_write++;
4120	#endif
4121	r_dcache.write_dir( r_dcache_save_paddr.read(),
4122	r_dcache_miss_way.read(),
4123	r_dcache_miss_set.read(),
4124	CACHE_SLOT_STATE_VALID );
4125
4126	#if DEBUG_DCACHE
4127	if ( m_debug_dcache_fsm )
4128	{
4129	std::cout << " <PROC " << name()
4130	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4131	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4132	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4133	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4134
4135	r_dcache.printTrace();
4136
4137
4138	}
4139	#endif
4140	// reset directory extension
4141	size_t way = r_dcache_miss_way.read();
4142	size_t set = r_dcache_miss_set.read();
4143	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4144	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4145	}
4146	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4147	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4148	else r_dcache_fsm = DCACHE_IDLE;
4149	}
4150	break;
4151	}
4152	/////////////////////
4153	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4154	{
4155	// coherence request (from CC_RECEIVE FSM)
4156	if ( r_cc_receive_dcache_req.read() )
4157	{
4158	r_dcache_fsm = DCACHE_CC_CHECK;
4159	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4160	break;
4161	}
4162
4163	if ( r_vci_rsp_data_error.read() ) // bus error
4164	{
4165	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4166	r_mmu_dbvar = m_dreq.addr;
4167	r_vci_rsp_data_error = false;
4168	m_drsp.error = true;
4169	m_drsp.valid = true;
4170	r_dcache_fsm = DCACHE_IDLE;
4171	break;
4172	}
4173	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4174	{
4175	// consume data
4176	vci_rsp_fifo_dcache_get = true;
4177	r_dcache_fsm = DCACHE_IDLE;
4178
4179	// acknowledge the processor request if it has not been modified
4180	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4181	{
4182	m_drsp.valid = true;
4183	m_drsp.error = false;
4184	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4185	}
4186	}
4187	break;
4188	}
4189	/////////////////////
4190	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4191	{
4192	// coherence request (from CC_RECEIVE FSM)
4193	if ( r_cc_receive_dcache_req.read() )
4194	{
4195	r_dcache_fsm = DCACHE_CC_CHECK;
4196	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4197	break;
4198	}
4199
4200	if ( r_vci_rsp_data_error.read() ) // bus error
4201	{
4202	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4203	r_mmu_dbvar = m_dreq.addr;
4204	r_vci_rsp_data_error = false;
4205	m_drsp.error = true;
4206	m_drsp.valid = true;
4207	r_dcache_fsm = DCACHE_IDLE;
4208	break;
4209	}
4210	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4211	{
4212	// consume data
4213	vci_rsp_fifo_dcache_get = true;
4214
4215	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4216	{
4217	// set key value in llsc reservation buffer
4218	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4219	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4220	}
4221	else // last flit
4222	{
4223	// acknowledge the processor request if it has not been modified
4224	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4225	{
4226	m_drsp.valid = true;
4227	m_drsp.error = false;
4228	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4229	}
4230	r_dcache_fsm = DCACHE_IDLE;
4231	}
4232	}
4233	break;
4234	}
4235	////////////////////
4236	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4237	{
4238	// coherence request (from CC_RECEIVE FSM)
4239	if ( r_cc_receive_dcache_req.read() )
4240	{
4241	r_dcache_fsm = DCACHE_CC_CHECK;
4242	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4243	break;
4244	}
4245
4246	if ( r_vci_rsp_data_error.read() ) // bus error
4247	{
4248	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4249	r_mmu_dbvar = m_dreq.addr;
4250	r_vci_rsp_data_error = false;
4251	m_drsp.error = true;
4252	m_drsp.valid = true;
4253	r_dcache_fsm = DCACHE_IDLE;
4254	break;
4255	}
4256	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4257	{
4258	// consume response
4259	vci_rsp_fifo_dcache_get = true;
4260	m_drsp.valid = true;
4261	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4262	r_dcache_fsm = DCACHE_IDLE;
4263	}
4264	break;
4265	}
4266	//////////////////////////
4267	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4268	// before handling a processor WRITE or SC request
4269	// Input argument is r_dcache_dirty_paddr
4270	// In this first state, we get PTE value in dcache
4271	// and post a CAS request to CMD FSM
4272	{
4273	// get PTE in dcache
4274	uint32_t pte;
4275	size_t way;
4276	size_t set;
4277	size_t word; // unused
4278	int state;
4279
4280	#ifdef INSTRUMENTATION
4281	m_cpt_dcache_data_read++;
4282	m_cpt_dcache_dir_read++;
4283	#endif
4284	r_dcache.read( r_dcache_dirty_paddr.read(),
4285	&pte,
4286	&way,
4287	&set,
4288	&word,
4289	&state );
4290
4291	assert( (state == CACHE_SLOT_STATE_VALID) and
4292	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4293
4294	// request CAS transaction to CMD_FSM
4295	r_dcache_dirty_way = way;
4296	r_dcache_dirty_set = set;
4297
4298	// check llsc reservation buffer
4299	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4300	r_dcache_llsc_valid = false;
4301
4302	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4303	r_dcache_vci_cas_req = true;
4304	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4305	r_dcache_vci_cas_old = pte;
4306	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4307	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4308
4309	#if DEBUG_DCACHE
4310	if ( m_debug_dcache_fsm )
4311	{
4312	std::cout << " <PROC " << name()
4313	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4314	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4315	<< " / PTE_VALUE = " << pte << std::dec
4316	<< " / SET = " << set
4317	<< " / WAY = " << way << std::endl;
4318	}
4319	#endif
4320	break;
4321	}
4322	///////////////////////
4323	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4324	// and return to IDLE state when response is received.
4325	// we don't care if the CAS is a failure:
4326	// - if the CAS is a success, the coherence mechanism
4327	// updates the local copy.
4328	// - if the CAS is a failure, we just retry the write.
4329	{
4330	// coherence request (from CC_RECEIVE FSM)
4331	if ( r_cc_receive_dcache_req.read() )
4332	{
4333	r_dcache_fsm = DCACHE_CC_CHECK;
4334	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4335	break;
4336	}
4337
4338	if ( r_vci_rsp_data_error.read() ) // bus error
4339	{
4340	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4341	std::cout << "This should not happen in this state" << std::endl;
4342	exit(0);
4343	}
4344	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4345	{
4346	vci_rsp_fifo_dcache_get = true;
4347	r_dcache_fsm = DCACHE_IDLE;
4348
4349	#if DEBUG_DCACHE
4350	if ( m_debug_dcache_fsm )
4351	{
4352	std::cout << " <PROC " << name()
4353	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4354	}
4355	#endif
4356	}
4357	break;
4358	}
4359	/////////////////////
4360	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4361	// handling coherence requests for DCACHE.
4362	// If there is a matching pending miss on the modified cache
4363	// line this is signaled in the r_dcache_miss inval flip-flop.
4364	// If the updated (or invalidated) cache line has copies in TLBs
4365	// these TLB copies are invalidated.
4366	// The return state is defined in r_dcache_fsm_cc_save
4367	{
4368	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4369	paddr_t mask = ~((m_dcache_words<<2)-1);
4370
4371	#if DEBUG_DCACHE
4372	if ( m_debug_dcache_fsm )
4373	{
4374	std::cout << " <PROC " << name()
4375	<< " DCACHE_CC_CHECK> paddr = " << paddr
4376	<< " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
4377	<< " mask = " << mask
4378	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
4379	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
4380	<< " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
4381	<<std::endl;
4382	}
4383	#endif
4384
4385	if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK)
4386	// We switch the directory slot to EMPTY state
4387	// and reset r_icache_miss_clack if the cleanup ack
4388	// is matching a pending miss.
4389	{
4390
4391	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4392
4393	#ifdef INSTRUMENTATION
4394	m_cpt_dcache_dir_write++;
4395	#endif
4396	r_dcache.write_dir( 0,
4397	r_cc_receive_dcache_way.read(),
4398	r_cc_receive_dcache_set.read(),
4399	CACHE_SLOT_STATE_EMPTY);
4400
4401	if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and
4402	(r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) )
4403	r_dcache_miss_clack = false;
4404
4405	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4406	r_cc_receive_dcache_req = false;
4407	#if DEBUG_DCACHE
4408	if ( m_debug_dcache_fsm )
4409	{
4410	std::cout << " <PROC " << name()
4411	<< " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
4412	<< " set = " << r_cc_receive_dcache_set.read()
4413	<< " / way = " << r_cc_receive_dcache_way.read() << std::endl;
4414	}
4415	#endif
4416	}
4417	else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4418	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4419	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
4420	{
4421	// signaling matching
4422	r_dcache_miss_inval = true;
4423
4424	// in case of update, go to CC_UPDT
4425	// JUST TO POP THE FIFO
4426	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4427	{
4428	r_dcache_fsm = DCACHE_CC_UPDT;
4429	r_dcache_cc_word = r_cc_receive_word_idx.read();
4430	// just pop the fifo , don't write in icache
4431	r_dcache_cc_need_write = false;
4432	}
4433	// the request is dealt with
4434	else
4435	{
4436	r_cc_receive_dcache_req = false;
4437	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4438	}
4439
4440	#if DEBUG_DCACHE
4441	if ( m_debug_dcache_fsm )
4442	{
4443	std::cout << " <PROC " << name()
4444	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4445	<< " PADDR = " << std::hex << paddr << std::endl;
4446	}
4447	#endif
4448
4449	}
4450	else // no match
4451	{
4452	int state;
4453	size_t way;
4454	size_t set;
4455	size_t word;
4456
4457	#ifdef INSTRUMENTATION
4458	m_cpt_dcache_dir_read++;
4459	#endif
4460	r_dcache.read_dir( paddr,
4461	&state,
4462	&way,
4463	&set,
4464	&word ); // unused
4465
4466	r_dcache_cc_way = way;
4467	r_dcache_cc_set = set;
4468
4469	if ( state == CACHE_SLOT_STATE_VALID) // hit
4470	{
4471	// need to update the cache state
4472	r_dcache_cc_need_write = true;
4473	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4474	{
4475	r_dcache_fsm = DCACHE_CC_UPDT;
4476	r_dcache_cc_word = r_cc_receive_word_idx.read();
4477	}
4478	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4479	{
4480	r_dcache_fsm = DCACHE_CC_INVAL;
4481	}
4482	else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
4483	{
4484	r_dcache_fsm = DCACHE_CC_BROADCAST;
4485	}
4486	}
4487	else // miss
4488	{
4489	// multicast acknowledgement required in case of update
4490	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4491	{
4492	r_dcache_fsm = DCACHE_CC_UPDT;
4493	r_dcache_cc_word = r_cc_receive_word_idx.read();
4494	// just pop the fifo , don't write in icache
4495	r_dcache_cc_need_write = false;
4496	}
4497	else // No response needed
4498	{
4499	r_cc_receive_dcache_req = false;
4500	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4501	}
4502	}
4503
4504	#if DEBUG_DCACHE
4505	if ( m_debug_dcache_fsm )
4506	{
4507	std::cout << " <PROC " << name()
4508	<< " DCACHE_CC_CHECK> Coherence request received:"
4509	<< " PADDR = " << std::hex << paddr
4510	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4511	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4512	}
4513	#endif
4514	}
4515	break;
4516	}
4517	/////////////////////
4518	case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state,
4519	// after possible invalidation of copies in TLBs
4520	{
4521	size_t way = r_dcache_cc_way.read();
4522	size_t set = r_dcache_cc_set.read();
4523
4524	if (r_dcache_cc_need_write.read())
4525	{
4526	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4527	{
4528	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4529	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4530	r_dcache_tlb_inval_set = 0;
4531	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4532	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4533	break;
4534	}
4535	else
4536	{
4537	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4538	{
4539	r_itlb.reset();
4540	r_dtlb.reset();
4541	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4542
4543	#if DEBUG_DCACHE
4544	if ( m_debug_dcache_fsm )
4545	{
4546	std::cout << " <PROC " << name()
4547	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4548	}
4549	#endif
4550	}
4551
4552	r_dcache.write_dir( 0,
4553	way,
4554	set,
4555	CACHE_SLOT_STATE_EMPTY );
4556
4557	r_dcache_cc_need_write = false;
4558
4559	#if DEBUG_DCACHE
4560	if ( m_debug_dcache_fsm )
4561	{
4562	std::cout << " <PROC " << name()
4563	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4564	<< " / WAY = " << way
4565	<< " / SET = " << set << std::endl;
4566	}
4567	#endif
4568	}
4569	}
4570	// multicast acknowledgement
4571	// send a request to cc_send_fsm
4572	if(not r_dcache_cc_send_req.read()) // cc_send is available
4573	{
4574	// coherence request completed
4575	r_cc_receive_dcache_req = false;
4576	// request multicast acknowledgement
4577	r_dcache_cc_send_req = true;
4578	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4579	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4580
4581	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4582	}
4583	//else wait for previous cc_send request to be sent
4584	break;
4585	}
4586	///////////////////
4587	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4588	// after possible invalidation of copies in TLBs
4589	{
4590	size_t word = r_dcache_cc_word.read();
4591	size_t way = r_dcache_cc_way.read();
4592	size_t set = r_dcache_cc_set.read();
4593
4594	if (r_cc_receive_updt_fifo_be.rok())
4595	{
4596	if (r_dcache_cc_need_write.read())
4597	{
4598	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4599	{
4600	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4601	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4602	r_dcache_tlb_inval_set = 0;
4603	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4604	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4605	break;
4606	}
4607
4608	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4609	{
4610	r_itlb.reset();
4611	r_dtlb.reset();
4612	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4613
4614	#if DEBUG_DCACHE
4615	if ( m_debug_dcache_fsm )
4616	{
4617	std::cout << " <PROC " << name()
4618	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4619	}
4620	#endif
4621	}
4622
4623	#ifdef INSTRUMENTATION
4624	m_cpt_dcache_data_write++;
4625	#endif
4626	r_dcache.write( way,
4627	set,
4628	word,
4629	r_cc_receive_updt_fifo_data.read(),
4630	r_cc_receive_updt_fifo_be.read() );
4631
4632	r_dcache_cc_word = word + 1;
4633
4634	#if DEBUG_DCACHE
4635	if ( m_debug_dcache_fsm )
4636	{
4637	std::cout << " <PROC " << name()
4638	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4639	<< " / WAY = " << way
4640	<< " / SET = " << set
4641	<< " / WORD = " << word
4642	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4643	}
4644	#endif
4645	}
4646
4647	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4648	{
4649	// no need to write in the cache anymore
4650	r_dcache_cc_need_write = false;
4651
4652	// wait to send a request to cc_send_fsm
4653	if(not r_icache_cc_send_req.read())
4654	// cc_send is available
4655	{
4656	//consume last fifo flit if eop and request to cc_send possible
4657	cc_receive_updt_fifo_get = true;
4658
4659	// coherence request completed
4660	r_cc_receive_dcache_req = false;
4661
4662	// request multicast acknowledgement
4663	r_dcache_cc_send_req = true;
4664	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4665	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4666
4667	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4668	}
4669	}
4670	else
4671	{
4672	//consume fifo if not eop
4673	cc_receive_updt_fifo_get = true;
4674	}
4675	}
4676	break;
4677	}
4678	/////////////////////////
4679	case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state
4680	// and request a cleanup, after possible
4681	// invalidation of copies in TLBs
4682	{
4683	size_t way = r_dcache_cc_way.read();
4684	size_t set = r_dcache_cc_set.read();
4685	paddr_t nline = r_cc_receive_dcache_nline.read();
4686
4687	if (r_dcache_cc_need_write.read())
4688	{
4689	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4690	{
4691	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4692	r_dcache_tlb_inval_line = nline;
4693	r_dcache_tlb_inval_set = 0;
4694	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4695	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4696	break;
4697	}
4698	else
4699	{
4700	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4701	{
4702	r_itlb.reset();
4703	r_dtlb.reset();
4704	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4705
4706	#if DEBUG_DCACHE
4707	if ( m_debug_dcache_fsm )
4708	{
4709	std::cout << " <PROC " << name()
4710	<< " DCACHE_CC_BROADCAST> Flush DTLB & ITLB" << std::endl;
4711	}
4712	#endif
4713	}
4714
4715	#ifdef INSTRUMENTATION
4716	m_cpt_dcache_dir_write++;
4717	#endif
4718	r_dcache.write_dir( 0,
4719	way,
4720	set,
4721	CACHE_SLOT_STATE_ZOMBI );
4722
4723	r_dcache_cc_need_write = false;
4724	#if DEBUG_DCACHE
4725	if ( m_debug_dcache_fsm )
4726	{
4727	std::cout << " <PROC " << name()
4728	<< " DCACHE_CC_BROADCAST > Slot goes to ZOMBI state "
4729	<< " SET = " << set
4730	<< " / WAY = " << way << std::endl;
4731	}
4732	#endif
4733	}
4734	}
4735	// cleanup
4736	// send a request to cc_send_fsm
4737	if(not r_dcache_cc_send_req.read()) // cc_send is available
4738	{
4739	// coherence request completed
4740	r_cc_receive_dcache_req = false;
4741	// request cleanup
4742	r_dcache_cc_send_req = true;
4743	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4744	r_dcache_cc_send_way = r_dcache_cc_way.read();
4745	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4746
4747	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4748	}
4749	//else wait for previous cc_send request to be sent
4750	break;
4751	}
4752	///////////////////////////
4753	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4754	// It makes assumption: m_itlb_sets == m_dtlb_sets
4755	// All ways are handled in parallel.
4756	// We enter this state when a DCACHE line is modified,
4757	// and there is a copy in itlb or dtlb.
4758	// It can be caused by:
4759	// - a coherence inval or updt transaction,
4760	// - a line inval caused by a cache miss
4761	// - a processor XTN inval request,
4762	// - a WRITE hit,
4763	// - a Dirty bit update
4764	// Input arguments are:
4765	// - r_dcache_tlb_inval_line
4766	// - r_dcache_tlb_inval_set
4767	// - r_dcache_fsm_scan_save
4768	{
4769	paddr_t line = r_dcache_tlb_inval_line.read();
4770	size_t set = r_dcache_tlb_inval_set.read();
4771	size_t way;
4772	bool ok;
4773
4774	for ( way = 0 ; way < m_itlb_ways ; way++ )
4775	{
4776	ok = r_itlb.inval( line, way, set );
4777
4778	#if DEBUG_DCACHE
4779	if ( m_debug_dcache_fsm and ok )
4780	{
4781	std::cout << " <PROC " << name()
4782	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4783	<< " line = " << line << std::dec
4784	<< " / set = " << set
4785	<< " / way = " << way << std::endl;
4786	}
4787	#endif
4788	}
4789
4790	for ( way = 0 ; way < m_dtlb_ways ; way++ )
4791	{
4792	ok = r_dtlb.inval( line, way, set );
4793
4794	#if DEBUG_DCACHE
4795	if ( m_debug_dcache_fsm and ok )
4796	{
4797	std::cout << " <PROC " << name()
4798	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4799	<< " line = " << line << std::dec
4800	<< " / set = " << set
4801	<< " / way = " << way << std::endl;
4802	}
4803	#endif
4804	}
4805
4806	// return to the calling state when TLB inval completed
4807	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
4808	{
4809	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4810	}
4811	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
4812	break;
4813	}
4814	} // end switch r_dcache_fsm
4815
4816	///////////////// wbuf update ///////////////////////////////////////////////////////
4817	r_wbuf.update();
4818
4819	///////////////// llsc update ///////////////////////////////////////////////////////
4820	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
4821	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
4822
4823	//////////////// test processor frozen //////////////////////////////////////////////
4824	// The simulation exit if the number of consecutive frozen cycles
4825	// is larger than the m_max_frozen_cycles (constructor parameter)
4826	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4827	{
4828	m_cpt_frz_cycles++; // used for instrumentation
4829	m_cpt_stop_simulation++; // used for debug
4830	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4831	{
4832	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4833	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4834	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4835	<< std::endl;
4836	r_iss.dump();
4837	exit(1);
4838	}
4839	}
4840	else
4841	{
4842	m_cpt_stop_simulation = 0;
4843	}
4844
4845	/////////// execute one iss cycle /////////////////////////////////
4846	{
4847	uint32_t it = 0;
4848	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4849	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4850	}
4851
4852	////////////////////////////////////////////////////////////////////////////
4853	// The VCI_CMD FSM controls the following ressources:
4854	// - r_vci_cmd_fsm
4855	// - r_vci_cmd_min
4856	// - r_vci_cmd_max
4857	// - r_vci_cmd_cpt
4858	// - r_vci_cmd_imiss_prio
4859	// - wbuf (reset)
4860	// - r_icache_miss_req (reset)
4861	// - r_icache_unc_req (reset)
4862	// - r_dcache_vci_miss_req (reset)
4863	// - r_dcache_vci_unc_req (reset)
4864	// - r_dcache_vci_ll_req (reset)
4865	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4866	// - r_dcache_vci_cas_req (reset)
4867	//
4868	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4869	// There are 8 request types, with the following priorities :
4870	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4871	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4872	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4873	// 4 - Instruction Uncachable : r_icache_unc_req
4874	// 5 - Data Write : r_wbuf.rok()
4875	// 6 - Data Linked Load : r_dcache_vci_ll_req
4876	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4877	// 8 - Compare And Swap : r_dcache_vci_cas_req
4878	//
4879	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4880	// and the VCI_RSP_FSM are fully desynchronized.
4881	//
4882	// VCI formats:
4883	// According to the VCI advanced specification, all read requests packets
4884	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4885	// are one word packets.
4886	// For write burst packets, all words are in the same cache line,
4887	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4888	// The sc command packet implements actually a compare-and-swap mechanism
4889	// and the packet contains two flits.
4890	////////////////////////////////////////////////////////////////////////////////////
4891
4892	switch ( r_vci_cmd_fsm.read() )
4893	{
4894	//////////////
4895	case CMD_IDLE:
4896	{
4897	// DDACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
4898	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
4899	// to check a possible pending write on the same cache line.
4900	// As there is only one possible access per cycle to write buffer, we implement
4901	// a round-robin priority between DCACHE and ICACHE for this access,
4902	// using the r_vci_cmd_imiss_prio flip-flop.
4903
4904	size_t wbuf_min;
4905	size_t wbuf_max;
4906
4907	bool dcache_unc_req = r_dcache_vci_unc_req.read() and
4908	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4909
4910	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
4911	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4912
4913	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
4914	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4915
4916	bool icache_miss_req = r_icache_miss_req.read() and
4917	( not (r_dcache_vci_miss_req.read() or
4918	r_dcache_vci_ll_req.read() or
4919	r_dcache_vci_unc_req.read())
4920	or r_vci_cmd_imiss_prio.read() ) ;
4921
4922	// 1 - Data Read Miss
4923	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4924	{
4925	r_vci_cmd_fsm = CMD_DATA_MISS;
4926	r_dcache_vci_miss_req = false;
4927	r_vci_cmd_imiss_prio = true;
4928	// m_cpt_dmiss_transaction++;
4929	}
4930	// 2 - Data Read Uncachable
4931	else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4932	{
4933	r_vci_cmd_fsm = CMD_DATA_UNC;
4934	r_dcache_vci_unc_req = false;
4935	// m_cpt_dunc_transaction++;
4936	}
4937	// 3 - Data Linked Load
4938	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4939	{
4940	r_dcache_vci_ll_req = false;
4941	r_vci_cmd_fsm = CMD_DATA_LL;
4942	// m_cpt_ll_transaction++;
4943	}
4944	// 4 - Instruction Miss
4945	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4946	{
4947	r_vci_cmd_fsm = CMD_INS_MISS;
4948	r_icache_miss_req = false;
4949	r_vci_cmd_imiss_prio = false;
4950	// m_cpt_imiss_transaction++;
4951	}
4952	// 5 - Instruction Uncachable
4953	else if ( r_icache_unc_req.read() )
4954	{
4955	r_vci_cmd_fsm = CMD_INS_UNC;
4956	r_icache_unc_req = false;
4957	// m_cpt_iunc_transaction++;
4958	}
4959	// 6 - Data Write
4960	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4961	{
4962	r_vci_cmd_fsm = CMD_DATA_WRITE;
4963	r_vci_cmd_cpt = wbuf_min;
4964	r_vci_cmd_min = wbuf_min;
4965	r_vci_cmd_max = wbuf_max;
4966	// m_cpt_write_transaction++;
4967	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4968	}
4969	// 7 - Data Store Conditionnal
4970	else if ( r_dcache_vci_sc_req.read() )
4971	{
4972	r_dcache_vci_sc_req = false;
4973	r_vci_cmd_cpt = 0;
4974	r_vci_cmd_fsm = CMD_DATA_SC;
4975	// m_cpt_sc_transaction++;
4976	}
4977	// 8 - Compare And Swap
4978	else if ( r_dcache_vci_cas_req.read() )
4979	{
4980	r_vci_cmd_fsm = CMD_DATA_CAS;
4981	r_dcache_vci_cas_req = false;
4982	r_vci_cmd_cpt = 0;
4983	// m_cpt_cas_transaction++;
4984	}
4985	break;
4986	}
4987	////////////////////
4988	case CMD_DATA_WRITE:
4989	{
4990	if ( p_vci_ini_d.cmdack.read() )
4991	{
4992	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4993	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4994	{
4995	r_vci_cmd_fsm = CMD_IDLE ;
4996	r_wbuf.sent() ;
4997	}
4998	}
4999	break;
5000	}
5001	/////////////////
5002	case CMD_DATA_SC:
5003	case CMD_DATA_CAS:
5004	{
5005	// The CAS and SC VCI commands contain two flits
5006	if ( p_vci_ini_d.cmdack.read() )
5007	{
5008	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5009	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
5010	}
5011	break;
5012	}
5013	//////////////////
5014	case CMD_INS_MISS:
5015	case CMD_INS_UNC:
5016	case CMD_DATA_MISS:
5017	case CMD_DATA_UNC:
5018	case CMD_DATA_LL:
5019	{
5020	// all read VCI commands contain one single flit
5021	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
5022	break;
5023	}
5024
5025	} // end switch r_vci_cmd_fsm
5026
5027	//////////////////////////////////////////////////////////////////////////
5028	// The VCI_RSP FSM controls the following ressources:
5029	// - r_vci_rsp_fsm:
5030	// - r_vci_rsp_fifo_icache (push)
5031	// - r_vci_rsp_fifo_dcache (push)
5032	// - r_vci_rsp_data_error (set)
5033	// - r_vci_rsp_ins_error (set)
5034	// - r_vci_rsp_cpt
5035	// - r_dcache_vci_sc_req (reset when SC response recieved)
5036	//
5037	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5038	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5039	// to identify the transactions.
5040	//
5041	// VCI vormat:
5042	// This component checks the response packet length and accepts only
5043	// single word packets for write response packets.
5044	//
5045	// Error handling:
5046	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5047	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5048	// flip_flop and the error is signaled by the DCACHE FSM.
5049	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5050	// flip_flop and the error is signaled by the ICACHE FSM.
5051	// In case of Cleanup Error, the simulation stops with an error message...
5052	//////////////////////////////////////////////////////////////////////////
5053
5054	switch ( r_vci_rsp_fsm.read() )
5055	{
5056	//////////////
5057	case RSP_IDLE:
5058	{
5059	if ( p_vci_ini_d.rspval.read() )
5060	{
5061	r_vci_rsp_cpt = 0;
5062
5063	if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
5064	{
5065	r_vci_rsp_fsm = RSP_DATA_UNC;
5066	}
5067	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5068	{
5069	r_vci_rsp_fsm = RSP_DATA_MISS;
5070	}
5071	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5072	{
5073	r_vci_rsp_fsm = RSP_INS_UNC;
5074	}
5075	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5076	{
5077	r_vci_rsp_fsm = RSP_INS_MISS;
5078	}
5079	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_WRITE )
5080	{
5081	r_vci_rsp_fsm = RSP_DATA_WRITE;
5082	}
5083	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_CAS )
5084	{
5085	r_vci_rsp_fsm = RSP_DATA_UNC;
5086	}
5087	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_LL )
5088	{
5089	r_vci_rsp_fsm = RSP_DATA_LL;
5090	}
5091	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_SC )
5092	{
5093	r_vci_rsp_fsm = RSP_DATA_UNC;
5094	}
5095	else
5096	{
5097	assert(false and "Unexpected VCI response");
5098	}
5099	}
5100	break;
5101	}
5102	//////////////////
5103	case RSP_INS_MISS:
5104	{
5105	if ( p_vci_ini_d.rspval.read() )
5106	{
5107	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5108	{
5109	r_vci_rsp_ins_error = true;
5110	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5111	}
5112	else // no error reported
5113	{
5114	if ( r_vci_rsp_fifo_icache.wok() )
5115	{
5116	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
5117	"The VCI response packet for instruction miss is too long" );
5118
5119	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5120	vci_rsp_fifo_icache_put = true,
5121	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
5122	if ( p_vci_ini_d.reop.read() )
5123	{
5124	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
5125	"The VCI response packet for instruction miss is too short");
5126
5127	r_vci_rsp_fsm = RSP_IDLE;
5128	}
5129	}
5130	}
5131	}
5132	break;
5133	}
5134	/////////////////
5135	case RSP_INS_UNC:
5136	{
5137	if (p_vci_ini_d.rspval.read() )
5138	{
5139	assert( p_vci_ini_d.reop.read() and
5140	"illegal VCI response packet for uncachable instruction");
5141
5142	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5143	{
5144	r_vci_rsp_ins_error = true;
5145	r_vci_rsp_fsm = RSP_IDLE;
5146	}
5147	else // no error reported
5148	{
5149	if ( r_vci_rsp_fifo_icache.wok())
5150	{
5151	vci_rsp_fifo_icache_put = true;
5152	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
5153	r_vci_rsp_fsm = RSP_IDLE;
5154	}
5155	}
5156	}
5157	break;
5158	}
5159	///////////////////
5160	case RSP_DATA_MISS:
5161	{
5162	if ( p_vci_ini_d.rspval.read() )
5163	{
5164	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5165	{
5166	r_vci_rsp_data_error = true;
5167	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5168	}
5169	else // no error reported
5170	{
5171	if ( r_vci_rsp_fifo_dcache.wok() )
5172	{
5173	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5174	"The VCI response packet for data miss is too long");
5175
5176	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5177	vci_rsp_fifo_dcache_put = true,
5178	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5179	if ( p_vci_ini_d.reop.read() )
5180	{
5181	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5182	"The VCI response packet for data miss is too short");
5183
5184	r_vci_rsp_fsm = RSP_IDLE;
5185	}
5186	}
5187	}
5188	}
5189	break;
5190	}
5191	//////////////////
5192	case RSP_DATA_UNC:
5193	{
5194	if (p_vci_ini_d.rspval.read() )
5195	{
5196	assert( p_vci_ini_d.reop.read() and
5197	"illegal VCI response packet for uncachable read data");
5198
5199	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5200	{
5201	r_vci_rsp_data_error = true;
5202	r_vci_rsp_fsm = RSP_IDLE;
5203	}
5204	else // no error reported
5205	{
5206	if ( r_vci_rsp_fifo_dcache.wok())
5207	{
5208	vci_rsp_fifo_dcache_put = true;
5209	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5210	r_vci_rsp_fsm = RSP_IDLE;
5211	}
5212	}
5213	}
5214	break;
5215	}
5216	////////////////////
5217	case RSP_DATA_LL:
5218	{
5219	if ( p_vci_ini_d.rspval.read() )
5220	{
5221	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
5222	{
5223	r_vci_rsp_data_error = true;
5224	r_vci_rsp_fsm = RSP_IDLE;
5225	}
5226	if (r_vci_rsp_cpt.read() == 0) //first flit
5227	{
5228	if(r_vci_rsp_fifo_dcache.wok())
5229	{
5230	assert(!p_vci_ini_d.reop.read() &&
5231	"illegal VCI response packet for LL");
5232	vci_rsp_fifo_dcache_put = true;
5233	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5234	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5235	}
5236	break;
5237	}
5238	else // last flit
5239	{
5240	if(r_vci_rsp_fifo_dcache.wok())
5241	{
5242	assert(p_vci_ini_d.reop.read() &&
5243	"illegal VCI response packet for LL");
5244	vci_rsp_fifo_dcache_put = true;
5245	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
5246	r_vci_rsp_fsm = RSP_IDLE;
5247	}
5248	break;
5249	}
5250	}
5251	break;
5252	}
5253	////////////////////
5254	case RSP_DATA_WRITE:
5255	{
5256	if (p_vci_ini_d.rspval.read())
5257	{
5258	assert( p_vci_ini_d.reop.read() and
5259	"a VCI response packet must contain one flit for a write transaction");
5260
5261	r_vci_rsp_fsm = RSP_IDLE;
5262	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read();
5263	bool cacheable = r_wbuf.completed(wbuf_index);
5264	if ( not cacheable ) r_dcache_pending_unc_write = false;
5265	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5266	}
5267	break;
5268	}
5269	} // end switch r_vci_rsp_fsm
5270
5271	/////////////////////////////////////////////////////////////////////////////////////
5272	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5273	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5274	// and ICACHE FSM) that are served with a round-robin priority.
5275	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5276	// soon as the request has been sent.
5277	/////////////////////////////////////////////////////////////////////////////////////
5278	switch ( r_cc_send_fsm.read() )
5279	{
5280	///////////////////////////
5281	case CC_SEND_IDLE:
5282	{
5283	///////////////////////////////////////////////////////
5284	// handling round robin between icache and dcache : //
5285	// we first check for the last client and listen for //
5286	// a request of the other, then update the client //
5287	///////////////////////////////////////////////////////
5288	// r_cc_send_last_client : 0 dcache / 1 icache
5289	bool update_last_client = r_cc_send_last_client.read();
5290	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5291	{
5292	if (r_icache_cc_send_req.read()) // request from icache
5293	update_last_client = 1; // update last client to icache
5294	}
5295	else // last client was icache
5296	{
5297	if (r_dcache_cc_send_req.read()) // request from dcache
5298	update_last_client = 0; // update last client to dcache
5299	}
5300	r_cc_send_last_client = update_last_client;
5301
5302	// if there is an actual request
5303	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5304	{
5305	// test if the new client is dcache and has a cleanup request
5306	if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5307	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5308	// test if the new client is dcache and has a multi acknowledgement request
5309	else if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5310	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5311	// test if the new client is icache and has a cleanup request
5312	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5313	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5314	// test if the new client is icache and has a multi acknowledgement request
5315	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5316	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5317	}
5318	break;
5319	}
5320	///////////////////////////
5321	case CC_SEND_CLEANUP_1:
5322	{
5323	/**/
5324	#if DEBUG_DCACHE
5325	if ( m_debug_dcache_fsm )
5326	{
5327	std::cout << " <PROC " << name()
5328	<< " r_dcache_cc_send_nline = " << r_dcache_cc_send_nline.read() << std::endl;
5329	}
5330	#endif
5331	// wait for the first flit to be consumed
5332	if (p_dspin_out.read.read())
5333	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5334
5335	break;
5336	}
5337	///////////////////////////
5338	case CC_SEND_CLEANUP_2:
5339	/**/
5340	#if DEBUG_DCACHE
5341	if ( m_debug_dcache_fsm )
5342	{
5343	std::cout << " <PROC " << name()
5344	<< " r_dcache_cc_send_nline = " << r_dcache_cc_send_nline.read() << std::endl;
5345	}
5346	#endif
5347	{
5348	assert( p_dspin_out.read.read() and
5349	"The interconnect should accept the second cleanup flit instantly" );
5350
5351	// wait for the second flit to be consumed
5352	if (p_dspin_out.read.read())
5353	{
5354	if (r_cc_send_last_client.read() == 0) // dcache active request
5355	r_dcache_cc_send_req = false; // reset dcache request
5356	else // icache active request
5357	r_icache_cc_send_req = false; // reset icache request
5358
5359	// go back to idle state
5360	r_cc_send_fsm = CC_SEND_IDLE;
5361	}
5362	break;
5363	}
5364	///////////////////////////
5365	case CC_SEND_MULTI_ACK:
5366	{
5367	// wait for the flit to be consumed
5368	if(p_dspin_out.read.read())
5369	{
5370	if(r_cc_send_last_client.read() == 0) // dcache active request
5371	r_dcache_cc_send_req = false; // reset dcache request
5372	else // icache active request
5373	r_icache_cc_send_req = false; // reset icache request
5374	// go back to idle state
5375	r_cc_send_fsm = CC_SEND_IDLE;
5376	}
5377	break;
5378	}
5379	} // end switch CC_SEND FSM
5380
5381	///////////////////////////////////////////////////////////////////////////////
5382	// C_RECEIVE FSM
5383	// This FSM receive all coherence packets on a DSPIN40 port.
5384	// There is 4 packet types:
5385	// - CC_DATA_INVAL : DCACHE invalidate request
5386	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5387	// - CC_INST_INVAL : ICACHE invalidate request
5388	// - CC_INST_UPDT : ICACHE update request (multi-words)
5389	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5390	// - CC_DATA_CLACK : DCACHE cleanup acknowledge
5391	// - CC_INST_CLACK : ICACHE cleanup acknowledge
5392	//////////////////////////////////////////////////////////////////////////////
5393	switch( r_cc_receive_fsm.read() )
5394	{
5395	/////////////////////
5396	case CC_RECEIVE_IDLE:
5397	{
5398	/**/
5399	#if DEBUG_DCACHE
5400	if ( m_debug_dcache_fsm )
5401	{
5402	std::cout << " <PROC " << name()
5403	<< " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
5404	std::cout << " <PROC " << name()
5405	<< " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
5406	}
5407	#endif
5408	// a coherence request has arrived
5409	if (p_dspin_in.write.read())
5410	{
5411	// initialize dspin received data
5412	uint64_t receive_data = p_dspin_in.data.read();
5413	// initialize coherence packet type
5414	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_TYPE);
5415	// initialize data/ins flip_flop (0 data / 1 ins)
5416	r_cc_receive_data_ins = (bool)(receive_type & 0x1);
5417	// test for a broadcast
5418	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_BC))
5419	{
5420	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5421	}
5422	// test for a CLACK
5423	else if ((receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_DATA) or
5424	(receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_INST))
5425	{
5426	r_cc_receive_fsm = CC_RECEIVE_CLACK;
5427	}
5428	// test for a multi updt
5429	else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or
5430	(receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST))
5431	{
5432	r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER;
5433	}
5434	// test for a multi inval
5435	else
5436	{
5437	r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER;
5438	}
5439	}
5440	break;
5441	}
5442	//////////////////////
5443	case CC_RECEIVE_CLACK:
5444	{
5445	// initialize dspin received data
5446	uint64_t receive_data = p_dspin_in.data.read();
5447
5448	// for data CLACK, wait for dcache to take the request
5449	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5450	{
5451	// request dcache to handle the CLACK
5452	r_cc_receive_dcache_req = true;
5453	r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
5454	r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5455	r_cc_receive_dcache_type = CC_TYPE_CLACK;
5456	// get back to idle state
5457	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5458	break;
5459	}
5460	// for ins CLACK, wait for icache to take the request
5461	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5462	{
5463	// request icache to handle the CLACK
5464	r_cc_receive_icache_req = true;
5465	r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5466	r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_icache_ways)))-1);
5467	r_cc_receive_icache_type = CC_TYPE_CLACK;
5468	// get back to idle state
5469	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5470	break;
5471	}
5472	// keep waiting for the correct cache to accept the request
5473	break;
5474	}
5475	///////////////////////////////
5476	case CC_RECEIVE_BRDCAST_HEADER:
5477	{
5478	/**/
5479	#if DEBUG_DCACHE
5480	if ( m_debug_dcache_fsm )
5481	{
5482	std::cout << " <PROC " << name()
5483	<< " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
5484	std::cout << " <PROC " << name()
5485	<< " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
5486	}
5487	#endif
5488	// no actual data in the HEADER, just skip to second flit
5489	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5490	break;
5491	}
5492	//////////////////////////////
5493	case CC_RECEIVE_BRDCAST_NLINE:
5494	{
5495	/**/
5496	#if DEBUG_DCACHE
5497	if ( m_debug_dcache_fsm )
5498	{
5499	std::cout << " <PROC " << name()
5500	<< " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
5501	std::cout << " <PROC " << name()
5502	<< " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
5503	}
5504	#endif
5505	// initialize dspin received data
5506	uint64_t receive_data = p_dspin_in.data.read();
5507	// wait for both dcache and icache to take the request
5508	// TODO maybe we need to wait for both only to leave the state, but
5509	// not to actually post a request to an available cache => need a
5510	// flip_flop to check that ?
5511	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
5512	{
5513	// request dcache to handle the BROADCAST
5514	r_cc_receive_dcache_req = true;
5515	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5516	r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
5517	// request icache to handle the BROADCAST
5518	r_cc_receive_icache_req = true;
5519	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5520	r_cc_receive_icache_type = CC_TYPE_BRDCAST;
5521	// get back to idle state
5522	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5523	break;
5524	}
5525	// keep waiting for the caches to accept the request
5526	break;
5527	}
5528	/////////////////////////////
5529	case CC_RECEIVE_INVAL_HEADER:
5530	{
5531	// sample updt tab index in the HEADER, than skip to second flit
5532	uint64_t receive_data = p_dspin_in.data.read();
5533	// for data INVAL, wait for dcache to take the request
5534	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5535	{
5536	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5537	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5538	break;
5539	}
5540	// for ins INVAL, wait for icache to take the request
5541	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5542	{
5543	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5544	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5545	break;
5546	}
5547	// keep waiting for the correct cache to accept the request
5548	break;
5549	}
5550	////////////////////////////
5551	case CC_RECEIVE_INVAL_NLINE:
5552	{
5553	// sample nline in the second flit
5554	uint64_t receive_data = p_dspin_in.data.read();
5555	// for data INVAL, wait for dcache to take the request
5556	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5557	{
5558	// request dcache to handle the INVAL
5559	r_cc_receive_dcache_req = true;
5560	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5561	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5562	// get back to idle state
5563	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5564	break;
5565	}
5566	// for ins INVAL, wait for icache to take the request
5567	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5568	{
5569	// request icache to handle the INVAL
5570	r_cc_receive_icache_req = true;
5571	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5572	r_cc_receive_icache_type = CC_TYPE_INVAL;
5573	// get back to idle state
5574	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5575	break;
5576	}
5577	// we should never get there
5578	assert ( false && "CC_RECEIVE_INVAL_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req\n");
5579	}
5580	////////////////////////////
5581	case CC_RECEIVE_UPDT_HEADER:
5582	{
5583	// sample updt tab index in the HEADER, than skip to second flit
5584	uint64_t receive_data = p_dspin_in.data.read();
5585	// for data INVAL, wait for dcache to take the request and fifo to
5586	// be empty
5587	if ((r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())
5588	{
5589	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5590	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5591	break;
5592	}
5593	// for ins INVAL, wait for icache to take the request and fifo to be
5594	// empty
5595	if ((r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())
5596	{
5597	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5598	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5599	break;
5600	}
5601	// keep waiting for the correct cache to accept the request
5602	break;
5603	}
5604	///////////////////////////
5605	case CC_RECEIVE_UPDT_NLINE:
5606	{
5607	// sample nline and word index in the second flit
5608	uint64_t receive_data = p_dspin_in.data.read();
5609	// for data INVAL, wait for dcache to take the request and fifo to
5610	// be empty
5611	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty())
5612	{
5613	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5614	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5615	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5616	// get back to idle state
5617	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5618	break;
5619	}
5620	// for ins INVAL, wait for icache to take the request and fifo to be
5621	// empty
5622	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty())
5623	{
5624	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5625	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5626	r_cc_receive_icache_type = CC_TYPE_UPDT;
5627	// get back to idle state
5628	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5629	break;
5630	}
5631	// we should never get there
5632	assert ( false && "CC_RECEIVE_UPDT_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req or r_cc_receive_fifo\n");
5633	break;
5634	}
5635	//////////////////////////
5636	case CC_RECEIVE_UPDT_DATA:
5637	{
5638	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5639	r_cc_receive_dcache_req = true;
5640	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5641	r_cc_receive_icache_req = true;
5642
5643	// sample data, be and eop
5644	uint64_t receive_data = p_dspin_in.data.read();
5645	// wait for the fifo
5646	if (r_cc_receive_updt_fifo_be.wok())
5647	{
5648	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5649	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5650	// sample eop to test for state exit
5651	bool flit_eop = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_EOP);
5652	cc_receive_updt_fifo_eop = flit_eop;
5653	cc_receive_updt_fifo_put = true;
5654	if(flit_eop)
5655	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5656	}
5657	break;
5658	}
5659	} // end switch CC_RECEIVE FSM
5660
5661	///////////////// Response FIFOs update //////////////////////
5662	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5663	vci_rsp_fifo_icache_put,
5664	vci_rsp_fifo_icache_data);
5665
5666	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5667	vci_rsp_fifo_dcache_put,
5668	vci_rsp_fifo_dcache_data);
5669	///////////////// updt FIFO update //////////////////////
5670	//TODO check this
5671	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5672	cc_receive_updt_fifo_put,
5673	cc_receive_updt_fifo_be);
5674	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5675	cc_receive_updt_fifo_put,
5676	cc_receive_updt_fifo_data);
5677	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5678	cc_receive_updt_fifo_put,
5679	cc_receive_updt_fifo_eop);
5680
5681	} // end transition()
5682
5683	///////////////////////
5684	tmpl(void)::genMoore()
5685	///////////////////////
5686	{
5687
5688	// VCI initiator command on the direct network
5689	// it depends on the CMD FSM state
5690
5691	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5692	(r_vci_cmd_fsm.read() == CMD_DATA_SC );
5693
5694	p_vci_ini_d.pktid = 0;
5695	p_vci_ini_d.srcid = m_srcid_d;
5696	p_vci_ini_d.cons = is_sc_or_cas;
5697	p_vci_ini_d.contig = not is_sc_or_cas;
5698	p_vci_ini_d.wrap = false;
5699	p_vci_ini_d.clen = 0;
5700	p_vci_ini_d.cfixed = false;
5701
5702	switch ( r_vci_cmd_fsm.read() ) {
5703
5704	case CMD_IDLE:
5705	p_vci_ini_d.cmdval = false;
5706	p_vci_ini_d.address = 0;
5707	p_vci_ini_d.wdata = 0;
5708	p_vci_ini_d.be = 0;
5709	p_vci_ini_d.trdid = 0;
5710	p_vci_ini_d.pktid = 0;
5711	p_vci_ini_d.plen = 0;
5712	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5713	p_vci_ini_d.eop = false;
5714	break;
5715
5716	case CMD_INS_MISS:
5717	p_vci_ini_d.cmdval = true;
5718	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5719	p_vci_ini_d.wdata = 0;
5720	p_vci_ini_d.be = 0xF;
5721	p_vci_ini_d.trdid = 0;
5722	p_vci_ini_d.pktid = TYPE_READ_INS_MISS;
5723	p_vci_ini_d.plen = m_icache_words<<2;
5724	p_vci_ini_d.cmd = vci_param::CMD_READ;
5725	p_vci_ini_d.eop = true;
5726	break;
5727
5728	case CMD_INS_UNC:
5729	p_vci_ini_d.cmdval = true;
5730	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
5731	p_vci_ini_d.wdata = 0;
5732	p_vci_ini_d.be = 0xF;
5733	p_vci_ini_d.trdid = 0;
5734	p_vci_ini_d.pktid = TYPE_READ_INS_UNC;
5735	p_vci_ini_d.plen = 4;
5736	p_vci_ini_d.cmd = vci_param::CMD_READ;
5737	p_vci_ini_d.eop = true;
5738	break;
5739
5740	case CMD_DATA_MISS:
5741	p_vci_ini_d.cmdval = true;
5742	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5743	p_vci_ini_d.wdata = 0;
5744	p_vci_ini_d.be = 0xF;
5745	p_vci_ini_d.trdid = 0;
5746	p_vci_ini_d.pktid = TYPE_READ_DATA_MISS;
5747	p_vci_ini_d.plen = m_dcache_words << 2;
5748	p_vci_ini_d.cmd = vci_param::CMD_READ;
5749	p_vci_ini_d.eop = true;
5750	break;
5751
5752	case CMD_DATA_UNC:
5753	p_vci_ini_d.cmdval = true;
5754	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5755	p_vci_ini_d.wdata = 0;
5756	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
5757	p_vci_ini_d.trdid = 0;
5758	p_vci_ini_d.pktid = TYPE_READ_DATA_UNC;
5759	p_vci_ini_d.plen = 4;
5760	p_vci_ini_d.cmd = vci_param::CMD_READ;
5761	p_vci_ini_d.eop = true;
5762	break;
5763
5764	case CMD_DATA_WRITE:
5765	p_vci_ini_d.cmdval = true;
5766	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5767	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5768	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5769	p_vci_ini_d.trdid = r_wbuf.getIndex();
5770	p_vci_ini_d.pktid = TYPE_WRITE;
5771	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5772	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
5773	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5774	break;
5775
5776	case CMD_DATA_LL:
5777	p_vci_ini_d.cmdval = true;
5778	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5779	p_vci_ini_d.wdata = 0;
5780	p_vci_ini_d.be = 0xF;
5781	p_vci_ini_d.trdid = 0;
5782	p_vci_ini_d.pktid = TYPE_LL;
5783	p_vci_ini_d.plen = 8;
5784	p_vci_ini_d.cmd = vci_param::CMD_LOCKED_READ;
5785	p_vci_ini_d.eop = true;
5786	break;
5787
5788	case CMD_DATA_SC:
5789	p_vci_ini_d.cmdval = true;
5790	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5791	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_llsc_key.read();
5792	else p_vci_ini_d.wdata = r_dcache_vci_sc_data.read();
5793	p_vci_ini_d.be = 0xF;
5794	p_vci_ini_d.trdid = 0;
5795	p_vci_ini_d.pktid = TYPE_SC;
5796	p_vci_ini_d.plen = 8;
5797	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5798	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
5799	break;
5800
5801	case CMD_DATA_CAS:
5802	p_vci_ini_d.cmdval = true;
5803	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5804	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_cas_old.read();
5805	else p_vci_ini_d.wdata = r_dcache_vci_cas_new.read();
5806	p_vci_ini_d.be = 0xF;
5807	p_vci_ini_d.trdid = 0;
5808	p_vci_ini_d.pktid = TYPE_CAS;
5809	p_vci_ini_d.plen = 8;
5810	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5811	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
5812	break;
5813	} // end switch r_vci_cmd_fsm
5814
5815	// VCI initiator response on the direct network
5816	// it depends on the VCI RSP state
5817
5818	switch (r_vci_rsp_fsm.read() )
5819	{
5820	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
5821	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
5822	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
5823	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5824	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5825	case RSP_DATA_LL : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5826	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
5827	} // end switch r_vci_rsp_fsm
5828
5829	/////////////////
5830	// CC_SEND FSM //
5831	/////////////////
5832	uint64_t dspin_send_data = 0;
5833	switch ( r_cc_send_fsm.read() )
5834	{
5835	///////////////////////////
5836	case CC_SEND_IDLE:
5837	{
5838	p_dspin_out.write = false;
5839	break;
5840	}
5841	///////////////////////////
5842	case CC_SEND_CLEANUP_1:
5843	{
5844	// initialize dspin send data
5845	DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_EOP);
5846	DspinDhccpParam::dspin_set(dspin_send_data,m_srcid_c,DspinDhccpParam::CLEANUP_SRCID);
5847	DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_BC);
5848	// dcache active request
5849	if(r_cc_send_last_client.read() == 0)
5850	{
5851	// compute global id
5852	uint32_t nline_size = vci_param::N - (uint32_log2(m_dcache_words)) - (uint32_log2(vci_param::B));
5853	uint64_t global_id = (uint64_t) r_dcache_cc_send_nline.read();
5854	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5855
5856	DspinDhccpParam::dspin_set(dspin_send_data,
5857	global_id,
5858	DspinDhccpParam::CLEANUP_DEST);
5859
5860	DspinDhccpParam::dspin_set(dspin_send_data,
5861	r_dcache_cc_send_nline.read() & 0x300000000ULL,
5862	DspinDhccpParam::CLEANUP_NLINE_MSB);
5863
5864	DspinDhccpParam::dspin_set(dspin_send_data,
5865	r_dcache_cc_send_way.read(),
5866	DspinDhccpParam::CLEANUP_WAY_INDEX);
5867
5868	DspinDhccpParam::dspin_set(dspin_send_data,
5869	DspinDhccpParam::TYPE_CLEANUP_DATA,
5870	DspinDhccpParam::FROM_L1_TYPE);
5871	}
5872	// icache active request
5873	else
5874	{
5875	// compute global id
5876	uint32_t nline_size = vci_param::N - (uint32_log2(m_icache_words)) - (uint32_log2(vci_param::B));
5877	uint64_t global_id = (uint64_t) r_icache_cc_send_nline.read();
5878	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5879
5880	DspinDhccpParam::dspin_set(dspin_send_data,
5881	global_id,
5882	DspinDhccpParam::CLEANUP_DEST);
5883
5884	DspinDhccpParam::dspin_set(dspin_send_data,
5885	r_icache_cc_send_nline.read() & 0x300000000ULL,
5886	DspinDhccpParam::CLEANUP_NLINE_MSB);
5887
5888	DspinDhccpParam::dspin_set(dspin_send_data,
5889	r_icache_cc_send_way.read(),
5890	DspinDhccpParam::CLEANUP_WAY_INDEX);
5891
5892	DspinDhccpParam::dspin_set(dspin_send_data,
5893	DspinDhccpParam::TYPE_CLEANUP_INST,
5894	DspinDhccpParam::FROM_L1_TYPE);
5895	}
5896	// send flit
5897	p_dspin_out.data = dspin_send_data;
5898	p_dspin_out.write = true;
5899	break;
5900	}
5901	///////////////////////////
5902	case CC_SEND_CLEANUP_2:
5903	{
5904	// initialize dspin send data
5905	DspinDhccpParam::dspin_set(dspin_send_data,1,DspinDhccpParam::FROM_L1_EOP);
5906	// dcache active request
5907	if(r_cc_send_last_client.read() == 0)
5908	{
5909	DspinDhccpParam::dspin_set(dspin_send_data,
5910	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
5911	DspinDhccpParam::CLEANUP_NLINE_LSB);
5912	}
5913	// icache active request
5914	else
5915	{
5916	DspinDhccpParam::dspin_set(dspin_send_data,
5917	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
5918	DspinDhccpParam::CLEANUP_NLINE_LSB);
5919	}
5920	// send flit
5921	p_dspin_out.data = dspin_send_data;
5922	p_dspin_out.write = true;
5923	break;
5924	}
5925	///////////////////////////
5926	case CC_SEND_MULTI_ACK:
5927	{
5928	// initialize dspin send data
5929	DspinDhccpParam::dspin_set(dspin_send_data,1,DspinDhccpParam::FROM_L1_EOP);
5930	DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_BC);
5931	DspinDhccpParam::dspin_set(dspin_send_data,
5932	DspinDhccpParam::TYPE_MULTI_ACK,
5933	DspinDhccpParam::FROM_L1_TYPE);
5934	// dcache active request
5935	if(r_cc_send_last_client.read() == 0)
5936	{
5937	// compute global id
5938	uint32_t nline_size = vci_param::N - (uint32_log2(m_dcache_words)) - (uint32_log2(vci_param::B));
5939	uint64_t global_id = (uint64_t) r_dcache_cc_send_nline.read();
5940	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5941
5942	DspinDhccpParam::dspin_set(dspin_send_data,
5943	global_id,
5944	DspinDhccpParam::MULTI_ACK_DEST);
5945
5946	DspinDhccpParam::dspin_set(dspin_send_data,
5947	r_dcache_cc_send_updt_tab_idx.read(),
5948	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5949	}
5950	// icache active request
5951	else
5952	{
5953	// compute global id
5954	uint32_t nline_size = vci_param::N - (uint32_log2(m_icache_words)) - (uint32_log2(vci_param::B));
5955	uint64_t global_id = (uint64_t) r_icache_cc_send_nline.read();
5956	global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5957
5958	DspinDhccpParam::dspin_set(dspin_send_data,
5959	global_id,
5960	DspinDhccpParam::MULTI_ACK_DEST);
5961
5962	DspinDhccpParam::dspin_set(dspin_send_data,
5963	r_icache_cc_send_updt_tab_idx.read(),
5964	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5965	}
5966	// send flit
5967	p_dspin_out.data = dspin_send_data;
5968	p_dspin_out.write = true;
5969	break;
5970	}
5971	} // end switch CC_SEND FSM
5972
5973	////////////////////
5974	// CC_RECEIVE FSM //
5975	////////////////////
5976	switch( r_cc_receive_fsm.read() )
5977	{
5978	/////////////////////
5979	case CC_RECEIVE_IDLE:
5980	{
5981	p_dspin_in.read = false;
5982	break;
5983	}
5984	//////////////////////
5985	case CC_RECEIVE_CLACK:
5986	{
5987	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5988	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5989	p_dspin_in.read = true;
5990	else
5991	p_dspin_in.read = false;
5992	break;
5993	}
5994	///////////////////////////////
5995	case CC_RECEIVE_BRDCAST_HEADER:
5996	{
5997	p_dspin_in.read = true;
5998	break;
5999	}
6000	//////////////////////////////
6001	case CC_RECEIVE_BRDCAST_NLINE:
6002	{
6003	// TODO maybe we need to wait for both only to leave the state, but
6004	// not to actually post a request to an available cache => need a
6005	// flip_flop to check that ?
6006	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
6007	p_dspin_in.read = true;
6008	else
6009	p_dspin_in.read = false;
6010	break;
6011	}
6012	/////////////////////////////
6013	case CC_RECEIVE_INVAL_HEADER:
6014	{
6015	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
6016	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
6017	p_dspin_in.read = true;
6018	else
6019	p_dspin_in.read = false;
6020	break;
6021	}
6022	////////////////////////////
6023	case CC_RECEIVE_INVAL_NLINE:
6024	{
6025	p_dspin_in.read = true;
6026	break;
6027	}
6028	////////////////////////////
6029	case CC_RECEIVE_UPDT_HEADER:
6030	{
6031	if (((r_cc_receive_data_ins.read() == 0) and
6032	not r_cc_receive_dcache_req.read() and
6033	r_cc_receive_updt_fifo_be.empty())
6034	or
6035	((r_cc_receive_data_ins.read() == 1) and
6036	not r_cc_receive_icache_req.read()) and
6037	r_cc_receive_updt_fifo_be.empty())
6038	p_dspin_in.read = true;
6039	else
6040	p_dspin_in.read = false;
6041	break;
6042	}
6043	///////////////////////////
6044	case CC_RECEIVE_UPDT_NLINE:
6045	{
6046	if (((r_cc_receive_data_ins.read() == 0) and
6047	not (r_cc_receive_dcache_req.read()) and
6048	r_cc_receive_updt_fifo_be.empty())
6049	or
6050	((r_cc_receive_data_ins.read() == 1) and
6051	not (r_cc_receive_icache_req.read()) and
6052	r_cc_receive_updt_fifo_be.empty()))
6053	p_dspin_in.read = true;
6054	else
6055	p_dspin_in.read = false;
6056	break;
6057	}
6058	//////////////////////////
6059	case CC_RECEIVE_UPDT_DATA:
6060	{
6061	if (r_cc_receive_updt_fifo_be.wok())
6062	p_dspin_in.read = true;
6063	else
6064	p_dspin_in.read = false;
6065	break;
6066	}
6067	} // end switch CC_RECEIVE FSM
6068
6069	} // end genMoore
6070
6071	}}
6072
6073	// Local Variables:
6074	// tab-width: 4
6075	// c-basic-offset: 4
6076	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6077	// indent-tabs-mode: nil
6078	// End:
6079
6080	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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