source: branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache.h @ 307

Last change on this file since 307 was 307, checked in by cfuguet, 11 years ago

Including vci_mem_cache v5 using dspin interface for
the coherence network and including dspin_dhccp_param class to
handle dspin packets on the same network
File size: 35.7 KB
Line 
1/* -*- c++ -*-
2 * File         : vci_mem_cache.h
3 * Date         : 26/10/2008
4 * Copyright    : UPMC / LIP6
5 * Authors      : Alain Greiner / Eric Guthmuller
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: alain eric.guthmuller@polytechnique.edu
28 *              cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_MEM_CACHE_H
33#define SOCLIB_CABA_MEM_CACHE_H
34
35#include <inttypes.h>
36#include <systemc>
37#include <list>
38#include <cassert>
39#include "arithmetics.h"
40#include "alloc_elems.h"
41#include "caba_base_module.h"
42#include "vci_target.h"
43#include "vci_initiator.h"
44#include "generic_fifo.h"
45#include "mapping_table.h"
46#include "int_tab.h"
47#include "generic_llsc_global_table.h"
48#include "mem_cache_directory.h"
49#include "xram_transaction.h"
50#include "update_tab.h"
51#include "dspin_interface.h"
52#include "dspin_dhccp_param.h"
53
54#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
55#define UPDATE_TAB_LINES      4 // Number of lines in the update tab
56
57namespace soclib {  namespace caba {
58  using namespace sc_core;
59
60  template<typename vci_param, int from_mc_flit_width, int from_l1_flit_width>
61    class VciMemCache
62    : public soclib::caba::BaseModule
63    {
64      typedef sc_dt::sc_uint<40> addr_t;
65      typedef typename vci_param::fast_addr_t vci_addr_t;
66      typedef uint32_t data_t;
67      typedef uint32_t tag_t;
68      typedef uint32_t size_t;
69      typedef uint32_t be_t;
70      typedef uint32_t copy_t;
71
72      typedef soclib::caba::DspinDhccpParam
73        <from_mc_flit_width
74        ,from_l1_flit_width> dspin_param;
75
76      /* States of the TGT_CMD fsm */
77      enum tgt_cmd_fsm_state_e{
78        TGT_CMD_IDLE,
79        TGT_CMD_READ,
80        TGT_CMD_WRITE,
81        TGT_CMD_CAS
82      };
83
84      /* States of the TGT_RSP fsm */
85      enum tgt_rsp_fsm_state_e{
86        TGT_RSP_READ_IDLE,
87        TGT_RSP_WRITE_IDLE,
88        TGT_RSP_CAS_IDLE,
89        TGT_RSP_XRAM_IDLE,
90        TGT_RSP_INIT_IDLE,
91        TGT_RSP_CLEANUP_IDLE,
92        TGT_RSP_READ,
93        TGT_RSP_WRITE,
94        TGT_RSP_CAS,
95        TGT_RSP_XRAM,
96        TGT_RSP_INIT,
97        TGT_RSP_CLEANUP
98      };
99
100      /* States of the DSPIN_TGT fsm */
101      enum cc_receive_fsm_state_e{
102        CC_RECEIVE_IDLE,
103        CC_RECEIVE_CLEANUP,
104        CC_RECEIVE_MULTI_ACK
105      };
106
107      /* States of the CC_SEND fsm */
108      enum cc_send_fsm_state_e{
109        CC_SEND_XRAM_RSP_IDLE,
110        CC_SEND_WRITE_IDLE,
111        CC_SEND_CAS_IDLE,
112        CC_SEND_CLEANUP_IDLE,
113        CC_SEND_CLEANUP_ACK,
114        CC_SEND_XRAM_RSP_BRDCAST_HEADER,
115        CC_SEND_XRAM_RSP_BRDCAST_NLINE,
116        CC_SEND_XRAM_RSP_INVAL_HEADER,
117        CC_SEND_XRAM_RSP_INVAL_NLINE,
118        CC_SEND_WRITE_BRDCAST_HEADER,
119        CC_SEND_WRITE_BRDCAST_NLINE,
120        CC_SEND_WRITE_UPDT_HEADER,
121        CC_SEND_WRITE_UPDT_NLINE,
122        CC_SEND_WRITE_UPDT_DATA,
123        CC_SEND_CAS_BRDCAST_HEADER,
124        CC_SEND_CAS_BRDCAST_NLINE,
125        CC_SEND_CAS_UPDT_HEADER,
126        CC_SEND_CAS_UPDT_NLINE,
127        CC_SEND_CAS_UPDT_DATA,
128        CC_SEND_CAS_UPDT_DATA_HIGH
129      };
130
131      /* States of the MULTI_ACK fsm */
132      enum multi_ack_fsm_state_e{
133        MULTI_ACK_IDLE,
134        MULTI_ACK_UPT_LOCK,
135        MULTI_ACK_UPT_CLEAR,
136        MULTI_ACK_WRITE_RSP
137      };
138
139      /* States of the READ fsm */
140      enum read_fsm_state_e{
141        READ_IDLE,
142        READ_DIR_REQ,
143        READ_DIR_LOCK,
144        READ_DIR_HIT,
145        READ_HEAP_REQ,
146        READ_HEAP_LOCK,
147        READ_HEAP_WRITE,
148        READ_HEAP_ERASE,
149        READ_HEAP_LAST,
150        READ_RSP,
151        READ_TRT_LOCK,
152        READ_TRT_SET,
153        READ_TRT_REQ
154      };
155
156      /* States of the WRITE fsm */
157      enum write_fsm_state_e{
158        WRITE_IDLE,
159        WRITE_NEXT,
160        WRITE_DIR_REQ,
161        WRITE_DIR_LOCK,
162        WRITE_DIR_READ,
163        WRITE_DIR_HIT,
164        WRITE_UPT_LOCK,
165        WRITE_UPT_HEAP_LOCK,
166        WRITE_UPT_REQ,
167        WRITE_UPT_NEXT,
168        WRITE_UPT_DEC,
169        WRITE_RSP,
170        WRITE_MISS_TRT_LOCK,
171        WRITE_MISS_TRT_DATA,
172        WRITE_MISS_TRT_SET,
173        WRITE_MISS_XRAM_REQ,
174        WRITE_BC_TRT_LOCK,
175        WRITE_BC_UPT_LOCK,
176        WRITE_BC_DIR_INVAL,
177        WRITE_BC_CC_SEND,
178        WRITE_BC_XRAM_REQ,
179        WRITE_WAIT
180      };
181
182      /* States of the IXR_RSP fsm */
183      enum ixr_rsp_fsm_state_e{
184        IXR_RSP_IDLE,
185        IXR_RSP_ACK,
186        IXR_RSP_TRT_ERASE,
187        IXR_RSP_TRT_READ
188      };
189
190      /* States of the XRAM_RSP fsm */
191      enum xram_rsp_fsm_state_e{
192        XRAM_RSP_IDLE,
193        XRAM_RSP_TRT_COPY,
194        XRAM_RSP_TRT_DIRTY,
195        XRAM_RSP_DIR_LOCK,
196        XRAM_RSP_DIR_UPDT,
197        XRAM_RSP_DIR_RSP,
198        XRAM_RSP_INVAL_LOCK,
199        XRAM_RSP_INVAL_WAIT,
200        XRAM_RSP_INVAL,
201        XRAM_RSP_WRITE_DIRTY,
202        XRAM_RSP_HEAP_REQ,
203        XRAM_RSP_HEAP_ERASE,
204        XRAM_RSP_HEAP_LAST,
205        XRAM_RSP_ERROR_ERASE,
206        XRAM_RSP_ERROR_RSP
207      };
208
209      /* States of the IXR_CMD fsm */
210      enum ixr_cmd_fsm_state_e{
211        IXR_CMD_READ_IDLE,
212        IXR_CMD_WRITE_IDLE,
213        IXR_CMD_CAS_IDLE,
214        IXR_CMD_XRAM_IDLE,
215        IXR_CMD_READ_NLINE,
216        IXR_CMD_WRITE_NLINE,
217        IXR_CMD_CAS_NLINE,
218        IXR_CMD_XRAM_DATA
219      };
220
221      /* States of the CAS fsm */
222      enum cas_fsm_state_e{
223        CAS_IDLE,
224        CAS_DIR_REQ,
225        CAS_DIR_LOCK,
226        CAS_DIR_HIT_READ,
227        CAS_DIR_HIT_WRITE,
228        CAS_UPT_LOCK,
229        CAS_UPT_HEAP_LOCK,
230        CAS_UPT_REQ,
231        CAS_UPT_NEXT,
232        CAS_BC_TRT_LOCK,
233        CAS_BC_UPT_LOCK,
234        CAS_BC_DIR_INVAL,
235        CAS_BC_CC_SEND,
236        CAS_BC_XRAM_REQ,
237        CAS_RSP_FAIL,
238        CAS_RSP_SUCCESS,
239        CAS_MISS_TRT_LOCK,
240        CAS_MISS_TRT_SET,
241        CAS_MISS_XRAM_REQ,
242        CAS_WAIT
243      };
244
245      /* States of the CLEANUP fsm */
246      enum cleanup_fsm_state_e{
247        CLEANUP_IDLE,
248        CLEANUP_GET_NLINE,
249        CLEANUP_DIR_REQ,
250        CLEANUP_DIR_LOCK,
251        CLEANUP_DIR_WRITE,
252        CLEANUP_HEAP_REQ,
253        CLEANUP_HEAP_LOCK,
254        CLEANUP_HEAP_SEARCH,
255        CLEANUP_HEAP_CLEAN,
256        CLEANUP_HEAP_FREE,
257        CLEANUP_UPT_LOCK,
258        CLEANUP_UPT_DECREMENT,
259        CLEANUP_UPT_CLEAR,
260        CLEANUP_WRITE_RSP,
261        CLEANUP_SEND_ACK
262      };
263
264      /* States of the ALLOC_DIR fsm */
265      enum alloc_dir_fsm_state_e{
266        ALLOC_DIR_RESET,
267        ALLOC_DIR_READ,
268        ALLOC_DIR_WRITE,
269        ALLOC_DIR_CAS,
270        ALLOC_DIR_CLEANUP,
271        ALLOC_DIR_XRAM_RSP
272      };
273
274      /* States of the ALLOC_TRT fsm */
275      enum alloc_trt_fsm_state_e{
276        ALLOC_TRT_READ,
277        ALLOC_TRT_WRITE,
278        ALLOC_TRT_CAS,
279        ALLOC_TRT_XRAM_RSP,
280        ALLOC_TRT_IXR_RSP
281      };
282
283      /* States of the ALLOC_UPT fsm */
284      enum alloc_upt_fsm_state_e{
285        ALLOC_UPT_WRITE,
286        ALLOC_UPT_XRAM_RSP,
287        ALLOC_UPT_MULTI_ACK,
288        ALLOC_UPT_CLEANUP,
289        ALLOC_UPT_CAS
290      };
291
292      /* States of the ALLOC_HEAP fsm */
293      enum alloc_heap_fsm_state_e{
294        ALLOC_HEAP_RESET,
295        ALLOC_HEAP_READ,
296        ALLOC_HEAP_WRITE,
297        ALLOC_HEAP_CAS,
298        ALLOC_HEAP_CLEANUP,
299        ALLOC_HEAP_XRAM_RSP
300      };
301
302      /* transaction type, pktid field */
303      enum transaction_type_e
304      {
305          // b3 unused
306          // b2 READ / NOT READ
307          // Si READ
308          //  b1 DATA / INS
309          //  b0 UNC / MISS
310          // Si NOT READ
311          //  b1 accÚs table llsc type SW / other
312          //  b2 WRITE/CAS/LL/SC
313          TYPE_READ_DATA_UNC          = 0x0,
314          TYPE_READ_DATA_MISS         = 0x1,
315          TYPE_READ_INS_UNC           = 0x2,
316          TYPE_READ_INS_MISS          = 0x3,
317          TYPE_WRITE                  = 0x4,
318          TYPE_CAS                    = 0x5,
319          TYPE_LL                     = 0x6,
320          TYPE_SC                     = 0x7
321      };
322
323      /* SC return values */
324      enum sc_status_type_e
325      {
326          SC_SUCCESS  =   0x00000000,
327          SC_FAIL     =   0x00000001
328      };
329
330      // debug variables (for each FSM)
331      size_t       m_debug_start_cycle;
332      bool         m_debug_ok;
333      bool         m_debug_global;
334      bool         m_debug_tgt_cmd_fsm;
335      bool         m_debug_tgt_rsp_fsm;
336      bool         m_debug_cc_send_fsm;
337      bool         m_debug_cc_receive_fsm;
338      bool         m_debug_multi_ack_fsm;
339      bool         m_debug_read_fsm;
340      bool         m_debug_write_fsm;
341      bool         m_debug_cas_fsm;
342      bool         m_debug_cleanup_fsm;
343      bool         m_debug_ixr_cmd_fsm;
344      bool         m_debug_ixr_rsp_fsm;
345      bool         m_debug_xram_rsp_fsm;
346      bool         m_debug_previous_hit;
347      size_t       m_debug_previous_count;
348
349      bool         m_monitor_ok;
350      vci_addr_t   m_monitor_base;
351      vci_addr_t   m_monitor_length;
352
353      // instrumentation counters
354      uint32_t     m_cpt_cycles;        // Counter of cycles
355      uint32_t     m_cpt_read;          // Number of READ transactions
356      uint32_t     m_cpt_read_miss;     // Number of MISS READ
357      uint32_t     m_cpt_write;         // Number of WRITE transactions
358      uint32_t     m_cpt_write_miss;    // Number of MISS WRITE
359      uint32_t     m_cpt_write_cells;   // Cumulated length for WRITE transactions
360      uint32_t     m_cpt_write_dirty;   // Cumulated length for WRITE transactions
361      uint32_t     m_cpt_update;        // Number of UPDATE transactions
362      uint32_t     m_cpt_trt_rb;        // Read blocked by a hit in trt
363      uint32_t     m_cpt_trt_full;      // Transaction blocked due to a full trt
364      uint32_t     m_cpt_update_mult;   // Number of targets for UPDATE
365      uint32_t     m_cpt_inval;         // Number of INVAL  transactions
366      uint32_t     m_cpt_inval_mult;    // Number of targets for INVAL
367      uint32_t     m_cpt_inval_brdcast; // Number of BROADCAST INVAL
368      uint32_t     m_cpt_cleanup;       // Number of CLEANUP transactions
369      uint32_t     m_cpt_ll;            // Number of LL transactions
370      uint32_t     m_cpt_sc;            // Number of SC transactions
371      uint32_t     m_cpt_cas;           // Number of CAS transactions
372
373      size_t       m_prev_count;
374
375      protected:
376
377      SC_HAS_PROCESS(VciMemCache);
378
379      public:
380      sc_in<bool>                           p_clk;
381      sc_in<bool>                           p_resetn;
382      soclib::caba::VciTarget<vci_param>    p_vci_tgt;
383      soclib::caba::VciInitiator<vci_param> p_vci_ixr;
384
385      soclib::caba::DspinInput <from_l1_flit_width> p_dspin_in;
386      soclib::caba::DspinOutput<from_mc_flit_width> p_dspin_out;
387
388      VciMemCache(
389          sc_module_name name,                                // Instance Name
390          const soclib::common::MappingTable &mtp,            // Mapping table for primary requets
391          const soclib::common::MappingTable &mtc,            // Mapping table for coherence requets
392          const soclib::common::MappingTable &mtx,            // Mapping table for XRAM
393          const soclib::common::IntTab &vci_ixr_index,        // VCI port to XRAM (initiator)
394          const soclib::common::IntTab &vci_ini_index,        // VCI port to PROC (initiator)
395          const soclib::common::IntTab &vci_tgt_index,        // VCI port to PROC (target)
396          const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup
397          size_t nways,                                       // Number of ways per set
398          size_t nsets,                                       // Number of sets
399          size_t nwords,                                      // Number of words per line
400          size_t heap_size=1024,                              // Size of the heap
401          size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT
402          size_t update_tab_lines=UPDATE_TAB_LINES,           // Size of the UPT
403          size_t debug_start_cycle=0,
404          bool   debug_ok=false);
405
406      ~VciMemCache();
407
408      void print_stats();
409      void print_trace();
410      void copies_monitor(vci_addr_t addr);
411      void start_monitor(vci_addr_t addr, vci_addr_t length);
412      void stop_monitor();
413
414      private:
415
416      void transition();
417      void genMoore();
418      void check_monitor( const char *buf, vci_addr_t addr, data_t data);
419
420      // Component attributes
421      std::list<soclib::common::Segment> m_seglist;  // memory cached into the cache
422      std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
423
424      const size_t    m_initiators; // Number of initiators
425      const size_t    m_heap_size;  // Size of the heap
426      const size_t    m_ways;       // Number of ways in a set
427      const size_t    m_sets;       // Number of cache sets
428      const size_t    m_words;      // Number of words in a line
429      const size_t    m_srcid_ixr;  // Srcid for requests to XRAM
430      const size_t    m_srcid_ini;  // Srcid for requests to processors
431
432      uint32_t        m_transaction_tab_lines;
433      TransactionTab  m_transaction_tab;  // xram transaction table
434      uint32_t        m_update_tab_lines;
435      UpdateTab       m_update_tab;       // pending update & invalidate
436      CacheDirectory  m_cache_directory;  // data cache directory
437      CacheData       m_cache_data;       // data array[set][way][word]
438      HeapDirectory   m_heap;             // heap for copies
439      GenericLLSCGlobalTable
440      <
441        32  ,   // desired number of slots
442        4096,   // number of processors in the system
443        8000,   // registratioçn life span (in # of LL operations)
444        typename vci_param::fast_addr_t // address type
445      >
446      m_llsc_table;       // ll/sc global registration table
447
448      // adress masks
449      const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
450      const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
451      const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
452      const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
453
454      // broadcast address
455      uint32_t m_broadcast_address;
456
457      //////////////////////////////////////////////////
458      // Others registers
459      //////////////////////////////////////////////////
460      sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
461      sc_signal<size_t> xxx_count;
462
463      //////////////////////////////////////////////////
464      // Registers controlled by the TGT_CMD fsm
465      //////////////////////////////////////////////////
466
467      // Fifo between TGT_CMD fsm and READ fsm
468      GenericFifo<uint64_t>  m_cmd_read_addr_fifo;
469      GenericFifo<size_t>    m_cmd_read_length_fifo;
470      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
471      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
472      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
473
474      // Fifo between TGT_CMD fsm and WRITE fsm
475      GenericFifo<uint64_t>  m_cmd_write_addr_fifo;
476      GenericFifo<bool>      m_cmd_write_eop_fifo;
477      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
478      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
479      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
480      GenericFifo<data_t>    m_cmd_write_data_fifo;
481      GenericFifo<be_t>      m_cmd_write_be_fifo;
482
483      // Fifo between TGT_CMD fsm and CAS fsm
484      GenericFifo<uint64_t>  m_cmd_cas_addr_fifo;
485      GenericFifo<bool>      m_cmd_cas_eop_fifo;
486      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
487      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
488      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
489      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
490
491      // Fifo between INIT_RSP fsm and CLEANUP fsm
492      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
493     
494      // Fifo between INIT_RSP fsm and MULTI_ACK fsm
495      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
496
497      sc_signal<int>         r_tgt_cmd_fsm;
498
499      size_t                   m_nseg;
500      size_t                   m_ncseg;
501      soclib::common::Segment  **m_seg;
502      soclib::common::Segment  **m_cseg;
503      ///////////////////////////////////////////////////////
504      // Registers controlled by the READ fsm
505      ///////////////////////////////////////////////////////
506
507      sc_signal<int>      r_read_fsm;        // FSM state
508      sc_signal<size_t>   r_read_copy;       // Srcid of the first copy
509      sc_signal<size_t>   r_read_copy_cache; // Srcid of the first copy
510      sc_signal<bool>     r_read_copy_inst;  // Type of the first copy
511      sc_signal<tag_t>    r_read_tag;        // cache line tag (in directory)
512      sc_signal<bool>     r_read_is_cnt;     // is_cnt bit (in directory)
513      sc_signal<bool>     r_read_lock;       // lock bit (in directory)
514      sc_signal<bool>     r_read_dirty;      // dirty bit (in directory)
515      sc_signal<size_t>   r_read_count;      // number of copies
516      sc_signal<size_t>   r_read_ptr;        // pointer to the heap
517      sc_signal<data_t> * r_read_data;       // data (one cache line)
518      sc_signal<size_t>   r_read_way;        // associative way (in cache)
519      sc_signal<size_t>   r_read_trt_index;  // Transaction Table index
520      sc_signal<size_t>   r_read_next_ptr;   // Next entry to point to
521      sc_signal<bool>     r_read_last_free;  // Last free entry
522      sc_signal<typename vci_param::fast_addr_t>
523                          r_read_ll_key;     // LL key returned by the llsc_global_table
524
525      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
526      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
527      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
528      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
529
530      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
531      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
532      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
533      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
534      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
535      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
536      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
537      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
538      sc_signal<typename vci_param::fast_addr_t>
539                          r_read_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
540
541      ///////////////////////////////////////////////////////////////
542      // Registers controlled by the WRITE fsm
543      ///////////////////////////////////////////////////////////////
544
545      sc_signal<int>      r_write_fsm;        // FSM state
546      sc_signal<addr_t>   r_write_address;    // first word address
547      sc_signal<size_t>   r_write_word_index; // first word index in line
548      sc_signal<size_t>   r_write_word_count; // number of words in line
549      sc_signal<size_t>   r_write_srcid;      // transaction srcid
550      sc_signal<size_t>   r_write_trdid;      // transaction trdid
551      sc_signal<size_t>   r_write_pktid;      // transaction pktid
552      sc_signal<data_t> * r_write_data;       // data (one cache line)
553      sc_signal<be_t>   * r_write_be;         // one byte enable per word
554      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
555      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
556      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
557      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
558      sc_signal<size_t>   r_write_copy;       // first owner of the line
559      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
560      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
561      sc_signal<size_t>   r_write_count;      // number of copies
562      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
563      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
564      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
565      sc_signal<size_t>   r_write_way;        // way of the line
566      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
567      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
568      sc_signal<bool>     r_write_sc_fail;    // sc command failed
569      sc_signal<bool>     r_write_pending_sc; // sc command pending in WRITE fsm
570
571      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
572      sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
573      sc_signal<size_t>   r_write_to_tgt_rsp_srcid;   // transaction srcid
574      sc_signal<size_t>   r_write_to_tgt_rsp_trdid;   // transaction trdid
575      sc_signal<size_t>   r_write_to_tgt_rsp_pktid;   // transaction pktid
576      sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
577
578      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
579      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
580      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
581      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
582      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
583      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
584
585      // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
586      sc_signal<bool>     r_write_to_cc_send_multi_req;     // valid multicast request
587      sc_signal<bool>     r_write_to_cc_send_brdcast_req;   // valid brdcast request
588      sc_signal<addr_t>   r_write_to_cc_send_nline;         // cache line index
589      sc_signal<size_t>   r_write_to_cc_send_trdid;         // index in Update Table
590      sc_signal<data_t> * r_write_to_cc_send_data;          // data (one cache line)
591      sc_signal<be_t>   * r_write_to_cc_send_be;            // word enable
592      sc_signal<size_t>   r_write_to_cc_send_count;         // number of words in line
593      sc_signal<size_t>   r_write_to_cc_send_index;         // index of first word in line
594      GenericFifo<bool>   m_write_to_cc_send_inst_fifo;     // fifo for the L1 type
595      GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
596#if L1_MULTI_CACHE
597      GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
598#endif
599
600      // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
601      sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
602      sc_signal<size_t>   r_write_to_multi_ack_upt_index; // index in update table
603
604      /////////////////////////////////////////////////////////
605      // Registers controlled by MULTI_ACK fsm
606      //////////////////////////////////////////////////////////
607
608      sc_signal<int>      r_multi_ack_fsm;       // FSM state
609      sc_signal<size_t>   r_multi_ack_upt_index; // index in the Update Table
610      sc_signal<size_t>   r_multi_ack_srcid;     // pending write srcid
611      sc_signal<size_t>   r_multi_ack_trdid;     // pending write trdid
612      sc_signal<size_t>   r_multi_ack_pktid;     // pending write pktid
613      sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
614
615      // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
616      sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
617      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
618      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
619      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
620
621      ///////////////////////////////////////////////////////
622      // Registers controlled by CLEANUP fsm
623      ///////////////////////////////////////////////////////
624
625      sc_signal<int>      r_cleanup_fsm;           // FSM state
626      sc_signal<size_t>   r_cleanup_srcid;         // transaction srcid
627      sc_signal<bool>     r_cleanup_inst;          // Instruction or Data ?
628      sc_signal<size_t>   r_cleanup_way_index;     // L1 Cache Way index
629      sc_signal<addr_t>   r_cleanup_nline;         // cache line index
630
631#if L1_MULTI_CACHE
632      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
633#endif
634
635      sc_signal<copy_t>   r_cleanup_copy;          // first copy
636      sc_signal<copy_t>   r_cleanup_copy_cache;    // first copy
637      sc_signal<size_t>   r_cleanup_copy_inst;     // type of the first copy
638      sc_signal<copy_t>   r_cleanup_count;         // number of copies
639      sc_signal<size_t>   r_cleanup_ptr;           // pointer to the heap
640      sc_signal<size_t>   r_cleanup_prev_ptr;      // previous pointer to the heap
641      sc_signal<size_t>   r_cleanup_prev_srcid;    // srcid of previous heap entry
642      sc_signal<size_t>   r_cleanup_prev_cache_id; // srcid of previous heap entry
643      sc_signal<bool>     r_cleanup_prev_inst;     // inst bit of previous heap entry
644      sc_signal<size_t>   r_cleanup_next_ptr;      // next pointer to the heap
645      sc_signal<tag_t>    r_cleanup_tag;           // cache line tag (in directory)
646      sc_signal<bool>     r_cleanup_is_cnt;        // inst bit (in directory)
647      sc_signal<bool>     r_cleanup_lock;          // lock bit (in directory)
648      sc_signal<bool>     r_cleanup_dirty;         // dirty bit (in directory)
649      sc_signal<size_t>   r_cleanup_way;           // associative way (in cache)
650
651      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write response
652      sc_signal<size_t>   r_cleanup_write_trdid;   // trdid of write rsp
653      sc_signal<size_t>   r_cleanup_write_pktid;   // pktid of write rsp
654      sc_signal<bool>     r_cleanup_write_need_rsp;// needs a write rsp
655
656      sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
657
658      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
659      sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
660      sc_signal<size_t>   r_cleanup_to_tgt_rsp_srcid; // transaction srcid
661      sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
662      sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
663
664      // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)
665      sc_signal<bool>     r_cleanup_to_cc_send_req;       // valid request
666      sc_signal<size_t>   r_cleanup_to_cc_send_srcid;     // L1 srcid
667      sc_signal<size_t>   r_cleanup_to_cc_send_set_index; // L1 set index
668      sc_signal<size_t>   r_cleanup_to_cc_send_way_index; // L1 way index
669
670      ///////////////////////////////////////////////////////
671      // Registers controlled by CAS fsm
672      ///////////////////////////////////////////////////////
673
674      sc_signal<int>      r_cas_fsm;        // FSM state
675      sc_signal<data_t>   r_cas_wdata;      // write data word
676      sc_signal<data_t> * r_cas_rdata;      // read data word
677      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
678      sc_signal<size_t>   r_cas_cpt;        // size of command
679      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
680      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
681      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
682      sc_signal<size_t>   r_cas_count;      // number of copies
683      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
684      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
685      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
686      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
687      sc_signal<size_t>   r_cas_way;        // way in directory
688      sc_signal<size_t>   r_cas_set;        // set in directory
689      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
690      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
691      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
692
693      // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
694      sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
695      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
696      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
697      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
698      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
699
700
701      // Buffer between CAS fsm and TGT_RSP fsm
702      sc_signal<bool>     r_cas_to_tgt_rsp_req;   // valid request
703      sc_signal<data_t>   r_cas_to_tgt_rsp_data;  // read data word
704      sc_signal<size_t>   r_cas_to_tgt_rsp_srcid; // Transaction srcid
705      sc_signal<size_t>   r_cas_to_tgt_rsp_trdid; // Transaction trdid
706      sc_signal<size_t>   r_cas_to_tgt_rsp_pktid; // Transaction pktid
707
708      // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
709      sc_signal<bool>     r_cas_to_cc_send_multi_req;     // valid request
710      sc_signal<bool>     r_cas_to_cc_send_brdcast_req;   // brdcast request
711      sc_signal<addr_t>   r_cas_to_cc_send_nline;         // cache line index
712      sc_signal<size_t>   r_cas_to_cc_send_trdid;         // index in Update Table
713      sc_signal<data_t>   r_cas_to_cc_send_wdata;         // data (one word)
714      sc_signal<bool>     r_cas_to_cc_send_is_long;       // it is a 64 bits CAS
715      sc_signal<data_t>   r_cas_to_cc_send_wdata_high;    // data high (one word)
716      sc_signal<size_t>   r_cas_to_cc_send_index;         // index of the word in line
717      GenericFifo<bool>   m_cas_to_cc_send_inst_fifo;     // fifo for the L1 type
718      GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
719#if L1_MULTI_CACHE
720      GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
721#endif
722
723      ////////////////////////////////////////////////////
724      // Registers controlled by the IXR_RSP fsm
725      ////////////////////////////////////////////////////
726
727      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
728      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
729      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
730
731      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
732      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
733
734      ////////////////////////////////////////////////////
735      // Registers controlled by the XRAM_RSP fsm
736      ////////////////////////////////////////////////////
737
738      sc_signal<int>      r_xram_rsp_fsm;               // FSM state
739      sc_signal<size_t>   r_xram_rsp_trt_index;         // TRT entry index
740      TransactionTabEntry r_xram_rsp_trt_buf;           // TRT entry local buffer
741      sc_signal<bool>     r_xram_rsp_victim_inval;      // victim line invalidate
742      sc_signal<bool>     r_xram_rsp_victim_is_cnt;     // victim line inst bit
743      sc_signal<bool>     r_xram_rsp_victim_dirty;      // victim line dirty bit
744      sc_signal<size_t>   r_xram_rsp_victim_way;        // victim line way
745      sc_signal<size_t>   r_xram_rsp_victim_set;        // victim line set
746      sc_signal<addr_t>   r_xram_rsp_victim_nline;      // victim line index
747      sc_signal<copy_t>   r_xram_rsp_victim_copy;       // victim line first copy
748      sc_signal<copy_t>   r_xram_rsp_victim_copy_cache; // victim line first copy
749      sc_signal<bool>     r_xram_rsp_victim_copy_inst;  // victim line type of first copy
750      sc_signal<size_t>   r_xram_rsp_victim_count;      // victim line number of copies
751      sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
752      sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
753      sc_signal<size_t>   r_xram_rsp_upt_index;         // UPT entry index
754      sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
755
756      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
757      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_req;    // Valid request
758      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_srcid;  // Transaction srcid
759      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_trdid;  // Transaction trdid
760      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_pktid;  // Transaction pktid
761      sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data;   // data (one cache line)
762      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_word;   // first word index
763      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
764      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
765      sc_signal<typename vci_param::fast_addr_t>
766                          r_xram_rsp_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
767
768      // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
769      sc_signal<bool>     r_xram_rsp_to_cc_send_multi_req;     // Valid request
770      sc_signal<bool>     r_xram_rsp_to_cc_send_brdcast_req;   // Broadcast request
771      sc_signal<addr_t>   r_xram_rsp_to_cc_send_nline;         // cache line index;
772      sc_signal<size_t>   r_xram_rsp_to_cc_send_trdid;         // index of UPT entry
773      GenericFifo<bool>   m_xram_rsp_to_cc_send_inst_fifo;     // fifo for the L1 type
774      GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
775#if L1_MULTI_CACHE
776      GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
777#endif
778
779      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
780      sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
781      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
782      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
783      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
784
785      ////////////////////////////////////////////////////
786      // Registers controlled by the IXR_CMD fsm
787      ////////////////////////////////////////////////////
788
789      sc_signal<int>      r_ixr_cmd_fsm;
790      sc_signal<size_t>   r_ixr_cmd_cpt;
791
792      ////////////////////////////////////////////////////
793      // Registers controlled by TGT_RSP fsm
794      ////////////////////////////////////////////////////
795
796      sc_signal<int>      r_tgt_rsp_fsm;
797      sc_signal<size_t>   r_tgt_rsp_cpt;
798
799      ////////////////////////////////////////////////////
800      // Registers controlled by CC_SEND fsm
801      ////////////////////////////////////////////////////
802
803      sc_signal<int>      r_cc_send_fsm;
804      sc_signal<size_t>   r_cc_send_cpt;
805      sc_signal<bool>     r_cc_send_inst;
806
807      ////////////////////////////////////////////////////
808      // Registers controlled by CC_RECEIVE fsm
809      ////////////////////////////////////////////////////
810
811      sc_signal<int>      r_cc_receive_fsm;
812
813      ////////////////////////////////////////////////////
814      // Registers controlled by ALLOC_DIR fsm
815      ////////////////////////////////////////////////////
816
817      sc_signal<int>      r_alloc_dir_fsm;
818      sc_signal<unsigned> r_alloc_dir_reset_cpt;
819
820      ////////////////////////////////////////////////////
821      // Registers controlled by ALLOC_TRT fsm
822      ////////////////////////////////////////////////////
823
824      sc_signal<int>      r_alloc_trt_fsm;
825
826      ////////////////////////////////////////////////////
827      // Registers controlled by ALLOC_UPT fsm
828      ////////////////////////////////////////////////////
829
830      sc_signal<int>      r_alloc_upt_fsm;
831
832      ////////////////////////////////////////////////////
833      // Registers controlled by ALLOC_HEAP fsm
834      ////////////////////////////////////////////////////
835
836      sc_signal<int>      r_alloc_heap_fsm;
837      sc_signal<unsigned> r_alloc_heap_reset_cpt;
838    }; // end class VciMemCache
839
840}}
841
842#endif
843
844// Local Variables:
845// tab-width: 2
846// c-basic-offset: 2
847// c-file-offsets:((innamespace . 0)(inline-open . 0))
848// indent-tabs-mode: nil
849// End:
850
851// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
852
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