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vci_cc_vcache_wrapper2_v1.h @ 68

Last change on this file since 68 was 68, checked in by bouyer, 14 years ago
A SC cause the dcache entry to be updated by the memcache, and the tlb entry to be invalidated. So just go back to DCACHE_IDLE to redo a lookup. Assert that the data is not in dcache in CC_CHECK when we're not going to update/invalidate the cache or tlb. Drop DCACHE_WRITE_DIRTY state, it's not used any more.
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1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper2_v1.h
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H
28	#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H
29
30	#include <inttypes.h>
31	#include <systemc>
32	#include "caba_base_module.h"
33	#include "write_buffer.h"
34	#include "generic_cache.h"
35	#include "vci_initiator.h"
36	#include "vci_target.h"
37	#include "mapping_table.h"
38	#include "generic_tlb.h"
39	#include "static_assert.h"
40
41	namespace soclib {
42	namespace caba {
43
44	using namespace sc_core;
45
46	////////////////////////////////////////////
47	template<typename vci_param, typename iss_t>
48	class VciCcVCacheWrapper2V1
49	////////////////////////////////////////////
50	: public soclib::caba::BaseModule
51	{
52	typedef uint32_t vaddr_t;
53	typedef uint32_t data_t;
54	typedef uint32_t tag_t;
55	typedef uint32_t type_t;
56	typedef typename iss_t::DataOperationType data_op_t;
57
58	typedef typename vci_param::addr_t paddr_t;
59	typedef typename vci_param::be_t vci_be_t;
60	typedef typename vci_param::srcid_t vci_srcid_t;
61	typedef typename vci_param::trdid_t vci_trdid_t;
62	typedef typename vci_param::pktid_t vci_pktid_t;
63	typedef typename vci_param::plen_t vci_plen_t;
64
65	enum icache_fsm_state_e {
66	ICACHE_IDLE, // 00
67	ICACHE_BIS, // 01
68	ICACHE_TLB1_READ, // 02
69	ICACHE_TLB1_WRITE, // 03
70	ICACHE_TLB1_UPDT, // 04
71	ICACHE_TLB2_READ, // 05
72	ICACHE_TLB2_WRITE, // 06
73	ICACHE_TLB2_UPDT, // 07
74	ICACHE_SW_FLUSH, // 08
75	ICACHE_TLB_FLUSH, // 09
76	ICACHE_CACHE_FLUSH, // 0a
77	ICACHE_TLB_INVAL, // 0b
78	ICACHE_CACHE_INVAL, // 0c
79	ICACHE_CACHE_INVAL_PA, // 0d
80	ICACHE_MISS_WAIT, // 0e
81	ICACHE_UNC_WAIT, // 0f
82	ICACHE_MISS_UPDT, // 10
83	ICACHE_ERROR, // 11
84	ICACHE_CC_INVAL, // 12
85	ICACHE_TLB_CC_INVAL, // 13
86	};
87
88	enum dcache_fsm_state_e {
89	DCACHE_IDLE, // 00
90	DCACHE_BIS, // 01
91	DCACHE_DTLB1_READ_CACHE, // 02
92	DCACHE_TLB1_LL_WAIT, // 03
93	DCACHE_TLB1_SC_WAIT, // 04
94	DCACHE_TLB1_READ, // 05
95	DCACHE_TLB1_READ_UPDT, // 06
96	DCACHE_TLB1_UPDT, // 07
97	DCACHE_DTLB2_READ_CACHE, // 08
98	DCACHE_TLB2_LL_WAIT, // 09
99	DCACHE_TLB2_SC_WAIT, // 0a
100	DCACHE_TLB2_READ, // 0b
101	DCACHE_TLB2_READ_UPDT, // 0c
102	DCACHE_TLB2_UPDT, // 0d
103	DCACHE_CTXT_SWITCH, // 0e
104	DCACHE_ICACHE_FLUSH, // 0f
105	DCACHE_DCACHE_FLUSH, // 10
106	DCACHE_ITLB_INVAL, // 11
107	DCACHE_DTLB_INVAL, // 12
108	DCACHE_ICACHE_INVAL, // 13
109	DCACHE_DCACHE_INVAL, // 14
110	DCACHE_ICACHE_INVAL_PA, // 15
111	DCACHE_DCACHE_INVAL_PA, // 16
112	DCACHE_DCACHE_SYNC, // 17
113	DCACHE_LL_DIRTY_WAIT, // 18
114	DCACHE_SC_DIRTY_WAIT, // 19
115	DCACHE_WRITE_UPDT, // 1a
116	DCACHE_WRITE_REQ, // 1b
117	DCACHE_MISS_WAIT, // 1c
118	DCACHE_MISS_UPDT, // 1d
119	DCACHE_UNC_WAIT, // 1e
120	DCACHE_ERROR, // 1f
121	DCACHE_ITLB_READ, // 20
122	DCACHE_ITLB_UPDT, // 21
123	DCACHE_ITLB_LL_WAIT, // 22
124	DCACHE_ITLB_SC_WAIT, // 23
125	DCACHE_CC_CHECK, // 24
126	DCACHE_CC_INVAL, // 25
127	DCACHE_CC_UPDT, // 26
128	DCACHE_CC_NOP, // 27
129	DCACHE_TLB_CC_INVAL, // 28
130	DCACHE_ITLB_CLEANUP, // 29
131	};
132
133	enum cmd_fsm_state_e {
134	CMD_IDLE, // 00
135	CMD_ITLB_READ, // 01
136	CMD_ITLB_ACC_LL, // 02
137	CMD_ITLB_ACC_SC, // 03
138	CMD_INS_MISS, // 04
139	CMD_INS_UNC, // 05
140	CMD_DTLB_READ, // 06
141	CMD_DTLB_ACC_LL, // 07
142	CMD_DTLB_ACC_SC, // 08
143	CMD_DTLB_DIRTY_LL, // 09
144	CMD_DTLB_DIRTY_SC, // 0a
145	CMD_DATA_UNC, // 0b
146	CMD_DATA_MISS, // 0c
147	CMD_DATA_WRITE, // 0d
148	CMD_INS_CLEANUP, // 0e
149	CMD_DATA_CLEANUP, // 0f
150	};
151
152	enum rsp_fsm_state_e {
153	RSP_IDLE, // 00
154	RSP_ITLB_READ, // 01
155	RSP_ITLB_ACC_LL, // 02
156	RSP_ITLB_ACC_SC, // 03
157	RSP_INS_MISS, // 04
158	RSP_INS_UNC, // 05
159	RSP_DTLB_READ, // 06
160	RSP_DTLB_ACC_LL, // 07
161	RSP_DTLB_ACC_SC, // 08
162	RSP_DTLB_DIRTY_LL, // 09
163	RSP_DTLB_DIRTY_SC, // 0a
164	RSP_DATA_MISS, // 0b
165	RSP_DATA_UNC, // 0c
166	RSP_DATA_WRITE, // 0d
167	RSP_INS_CLEANUP, // 0e
168	RSP_DATA_CLEANUP, // 0f
169	};
170
171	enum tgt_fsm_state_e {
172	TGT_IDLE, // 00
173	TGT_UPDT_WORD, // 01
174	TGT_UPDT_DATA, // 02
175	TGT_REQ_BROADCAST, // 03
176	TGT_REQ_ICACHE, // 04
177	TGT_REQ_DCACHE, // 05
178	TGT_RSP_BROADCAST, // 06
179	TGT_RSP_ICACHE, // 07
180	TGT_RSP_DCACHE, // 08
181	};
182
183	enum inval_itlb_fsm_state_e {
184	INVAL_ITLB_IDLE, // 00
185	INVAL_ITLB_CHECK, // 01
186	INVAL_ITLB_INVAL, // 02
187	INVAL_ITLB_CLEAR, // 03
188	};
189
190	enum inval_dtlb_fsm_state_e {
191	INVAL_DTLB_IDLE, // 00
192	INVAL_DTLB_CHECK, // 01
193	INVAL_DTLB_INVAL, // 02
194	INVAL_DTLB_CLEAR, // 03
195	};
196
197	// TLB Mode ITLB / DTLB / ICACHE / DCACHE
198	enum {
199	ALL_DEACTIVE = 0x0000, // TLBs disactive caches disactive
200	INS_TLB_MASK = 0x8,
201	DATA_TLB_MASK = 0x4,
202	INS_CACHE_MASK = 0x2,
203	DATA_CACHE_MASK = 0x1,
204	};
205
206	// Error Type
207	enum mmu_error_type_e {
208	MMU_NONE = 0x0000, // None
209	MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write access of Page fault on Page Table 1 (non fatal error)
210	MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write access of Page fault on Page Table 2 (non fatal error)
211	MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode (user error)
212	MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access of write access to a non writable page (user error)
213	MMU_WRITE_UNDEFINED_XTN = 0x0020, // Write access of undefined external access address (user error)
214	MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write access of Bus Error accessing Table 1 (kernel error)
215	MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write access of Bus Error accessing Table 2 (kernel error)
216	MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access (kernel error)
217	MMU_READ_PT1_UNMAPPED = 0x1001, // Read access of Page fault on Page Table 1 (non fatal error)
218	MMU_READ_PT2_UNMAPPED = 0x1002, // Read access of Page fault on Page Table 2 (non fatal error)
219	MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read access of Protected access in user mode (user error)
220	MMU_READ_EXEC_VIOLATION = 0x1010, // Exec access to a non exec page (user error)
221	MMU_READ_UNDEFINED_XTN = 0x1020, // Read access of Undefined external access address (user error)
222	MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read access of Bus Error in Table1 access (kernel error)
223	MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read access of Bus Error in Table2 access (kernel error)
224	MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read access of Bus Error in cache access (kernel error)
225	};
226
227	public:
228	sc_in<bool> p_clk;
229	sc_in<bool> p_resetn;
230	sc_in<bool> p_irq[iss_t::n_irq];
231	soclib::caba::VciInitiator<vci_param> p_vci_ini_rw;
232	soclib::caba::VciInitiator<vci_param> p_vci_ini_c;
233	soclib::caba::VciTarget<vci_param> p_vci_tgt;
234
235	private:
236	// STRUCTURAL PARAMETERS
237	soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table;
238	const soclib::common::Segment m_segment;
239	iss_t m_iss;
240	const vci_srcid_t m_srcid_rw;
241	const vci_srcid_t m_srcid_c;
242
243	const size_t m_itlb_ways;
244	const size_t m_itlb_sets;
245
246	const size_t m_dtlb_ways;
247	const size_t m_dtlb_sets;
248
249	const size_t m_icache_ways;
250	const size_t m_icache_sets;
251	const size_t m_icache_yzmask;
252	const size_t m_icache_words;
253
254	const size_t m_dcache_ways;
255	const size_t m_dcache_sets;
256	const size_t m_dcache_yzmask;
257	const size_t m_dcache_words;
258
259	const size_t m_write_buf_size;
260	const size_t m_paddr_nbits;
261
262	// instruction and data vcache tlb instances
263	soclib::caba::GenericCcTlb<paddr_t> icache_tlb;
264	soclib::caba::GenericCcTlb<paddr_t> dcache_tlb;
265
266	sc_signal<vaddr_t> r_mmu_ptpr; // page table pointer register
267	sc_signal<int> r_mmu_mode; // tlb mode register
268	sc_signal<int> r_mmu_params; // mmu parameters register
269	sc_signal<int> r_mmu_release; // mmu release register
270	sc_signal<int> r_mmu_word_lo; // mmu misc data low
271	sc_signal<int> r_mmu_word_hi; // mmu mmu misc data hight
272
273	// DCACHE FSM REGISTERS
274	sc_signal<int> r_dcache_fsm; // state register
275	sc_signal<paddr_t> r_dcache_paddr_save; // physical address
276	sc_signal<data_t> r_dcache_wdata_save; // write data
277	sc_signal<data_t> r_dcache_rdata_save; // read data
278	sc_signal<type_t> r_dcache_type_save; // access type
279	sc_signal<vci_be_t> r_dcache_be_save; // byte enable
280	sc_signal<bool> r_dcache_cached_save; // used by the write buffer
281	sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of tlb miss
282	sc_signal<bool> r_dcache_dirty_save; // used for TLB dirty bit update
283	sc_signal<size_t> r_dcache_tlb_set_save; // used for TLB dirty bit update
284	sc_signal<size_t> r_dcache_tlb_way_save; // used for TLB dirty bit update
285	sc_signal<vaddr_t> r_dcache_id1_save; // used by the PT1 bypass
286	sc_signal<paddr_t> r_dcache_ptba_save; // used by the PT1 bypass
287	sc_signal<bool> r_dcache_ptba_ok; // used by the PT1 bypass
288	sc_signal<data_t> r_dcache_pte_update; // used for page table update
289	sc_signal<data_t> r_dcache_ppn_update; // used for physical page number update
290	sc_signal<tag_t> r_dcache_ppn_save; // used for speculative cache access
291	sc_signal<tag_t> r_dcache_vpn_save; // used for speculative cache access
292	sc_signal<bool> r_dtlb_translation_valid; // used for speculative address
293	sc_signal<bool> r_dcache_buf_unc_valid; // used for uncached read
294	sc_signal<bool> r_dcache_hit_p_save; // used to save hit_p in case BIS
295
296	sc_signal<data_t> r_dcache_error_type; // software visible register
297	sc_signal<vaddr_t> r_dcache_bad_vaddr; // software visible register
298
299	sc_signal<bool> r_dcache_miss_req; // used for cached read miss
300	sc_signal<bool> r_dcache_unc_req; // used for uncached read miss
301	sc_signal<bool> r_dcache_write_req; // used for write
302	sc_signal<bool> r_dcache_tlb_read_req; // used for tlb ptba or pte read
303
304	sc_signal<bool> r_dcache_llsc_reserved; // used for check address reserved
305	sc_signal<paddr_t> r_dcache_llsc_addr_save; // used for save llsc address
306
307	sc_signal<bool> r_dcache_tlb_ll_acc_req; // used for tlb access bit update
308	sc_signal<bool> r_dcache_tlb_sc_acc_req; // used for tlb access bit update
309	sc_signal<bool> r_dcache_tlb_ll_dirty_req; // used for tlb dirty bit update
310	sc_signal<bool> r_dcache_tlb_sc_dirty_req; // used for tlb dirty bit update
311	sc_signal<bool> r_dcache_tlb_ptba_read; // used for tlb ptba read when write dirty bit
312	sc_signal<bool> r_dcache_xtn_req; // used for xtn write for ICACHE
313
314	bool *r_dcache_in_itlb; // indicates some words of dcache line in ins TLB
315	bool *r_dcache_in_dtlb; // indicates some words of dcache line in data TLB
316
317	// coherence registers
318	sc_signal<int> r_dcache_fsm_save; // state save register
319	sc_signal<size_t> r_dcache_way;
320	sc_signal<size_t> r_dcache_set;
321	sc_signal<bool> r_dcache_cleanup_req; // data cleanup request
322	sc_signal<paddr_t> r_dcache_cleanup_line; // data cleanup NLINE
323	sc_signal<bool> r_dcache_inval_rsp; // data cache invalidate
324
325	// ICACHE FSM REGISTERS
326	sc_signal<int> r_icache_fsm; // state register
327	sc_signal<paddr_t> r_icache_paddr_save; // physical address
328	sc_signal<vaddr_t> r_icache_id1_save; // used by the PT1 bypass
329	sc_signal<paddr_t> r_icache_ptba_save; // used by the PT1 bypass
330	sc_signal<bool> r_icache_ptba_ok; // used by the PT1 bypass
331	sc_signal<data_t> r_icache_pte_update; // used for page table update
332	sc_signal<tag_t> r_icache_ppn_save; // used for speculative cache access
333	sc_signal<tag_t> r_icache_vpn_save; // used for speculative cache access
334	sc_signal<bool> r_itlb_translation_valid; // used for speculative physical address
335	sc_signal<bool> r_icache_buf_unc_valid; // used for uncached read
336
337	sc_signal<data_t> r_icache_error_type; // software visible registers
338	sc_signal<vaddr_t> r_icache_bad_vaddr; // software visible registers
339
340	sc_signal<bool> r_icache_miss_req; // used for cached read miss
341	sc_signal<bool> r_icache_unc_req; // used for uncached read miss
342	sc_signal<bool> r_dcache_itlb_read_req; // used for tlb ptba or pte read
343
344	sc_signal<bool> r_dcache_itlb_ll_acc_req; // used for tlb access bit update
345	sc_signal<bool> r_dcache_itlb_sc_acc_req; // used for tlb access bit update
346
347	sc_signal<bool> r_itlb_read_dcache_req; // used for instruction tlb miss, request in data cache
348	sc_signal<bool> r_itlb_k_read_dcache; // used for instruction tlb miss, request in data cache
349	sc_signal<bool> r_itlb_acc_dcache_req; // used for itlb update access bit via dcache
350	sc_signal<bool> r_dcache_rsp_itlb_error; // used for data cache rsp error when itlb miss
351	sc_signal<data_t> r_dcache_rsp_itlb_miss; // used for dcache rsp data when itlb miss
352	sc_signal<data_t> r_dcache_rsp_itlb_ppn; // used for dcache rsp ppn when itlb miss
353	sc_signal<vaddr_t> r_icache_vaddr_req; // virtual address requested by the CPU
354
355	// coherence registers
356	sc_signal<int> r_icache_fsm_save; // state save register
357	sc_signal<size_t> r_icache_way;
358	sc_signal<size_t> r_icache_set;
359	sc_signal<bool> r_icache_cleanup_req; // ins cleanup request
360	sc_signal<paddr_t> r_icache_cleanup_line; // ins cleanup NLINE
361	sc_signal<bool> r_icache_inval_rsp; // ins cache invalidate
362
363	// VCI_CMD FSM REGISTERS
364	sc_signal<int> r_vci_cmd_fsm;
365	sc_signal<size_t> r_vci_cmd_min;
366	sc_signal<size_t> r_vci_cmd_max;
367	sc_signal<size_t> r_vci_cmd_cpt;
368
369	// VCI_RSP FSM REGISTERS
370	sc_signal<int> r_vci_rsp_fsm;
371	sc_signal<size_t> r_vci_rsp_cpt;
372	sc_signal<bool> r_vci_rsp_ins_error;
373	sc_signal<bool> r_vci_rsp_data_error;
374	sc_signal<bool> r_dcache_tlb_sc_fail;
375
376	data_t *r_icache_miss_buf;
377	data_t *r_dcache_miss_buf;
378
379	// VCI_TGT FSM REGISTERS
380	data_t *r_tgt_buf;
381	bool *r_tgt_val;
382
383	sc_signal<int> r_vci_tgt_fsm;
384	sc_signal<paddr_t> r_tgt_addr;
385	sc_signal<size_t> r_tgt_word;
386	sc_signal<bool> r_tgt_update;
387	sc_signal<vci_srcid_t> r_tgt_srcid;
388	sc_signal<vci_pktid_t> r_tgt_pktid;
389	sc_signal<vci_trdid_t> r_tgt_trdid;
390	sc_signal<vci_plen_t> r_tgt_plen;
391	sc_signal<bool> r_tgt_req;
392	sc_signal<bool> r_tgt_icache_req;
393	sc_signal<bool> r_tgt_dcache_req;
394	sc_signal<bool> r_tgt_icache_rsp;
395	sc_signal<bool> r_tgt_dcache_rsp;
396
397	// INVAL CHECK FSM
398	sc_signal<int> r_inval_itlb_fsm;
399	sc_signal<bool> r_dcache_itlb_inval_req;
400	sc_signal<paddr_t> r_dcache_itlb_inval_line;
401	sc_signal<bool> r_itlb_cc_check_end;
402	sc_signal<size_t> r_ccinval_itlb_way;
403	sc_signal<size_t> r_ccinval_itlb_set;
404	sc_signal<bool> r_icache_inval_tlb_rsp;
405	sc_signal<paddr_t> r_icache_tlb_nline;
406
407	sc_signal<int> r_inval_dtlb_fsm;
408	sc_signal<bool> r_dcache_dtlb_inval_req;
409	sc_signal<paddr_t> r_dcache_dtlb_inval_line;
410	sc_signal<bool> r_dtlb_cc_check_end;
411	sc_signal<size_t> r_ccinval_dtlb_way;
412	sc_signal<size_t> r_ccinval_dtlb_set;
413	sc_signal<bool> r_dcache_inval_tlb_rsp;
414	sc_signal<paddr_t> r_dcache_tlb_nline;
415
416	sc_signal<bool> r_dcache_itlb_cleanup_req;
417	sc_signal<paddr_t> r_dcache_itlb_cleanup_line;
418
419	sc_signal<bool> r_dcache_dtlb_cleanup_req;
420	sc_signal<paddr_t> r_dcache_dtlb_cleanup_line;
421
422	sc_signal<bool> r_itlb_inval_req;
423	sc_signal<bool> r_dcache_cc_check;
424
425	WriteBuffer<paddr_t> r_wbuf;
426	GenericCache<paddr_t> r_icache;
427	GenericCache<paddr_t> r_dcache;
428
429	// Activity counters
430	uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ
431	uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE
432	uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ
433	uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE
434
435	uint32_t m_cpt_icache_data_read; // ICACHE DATA READ
436	uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE
437	uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ
438	uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE
439
440	uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen
441	uint32_t m_cpt_total_cycles; // total number of cycles
442	uint32_t m_cpt_dcache_frz_cycles; // number of cycles where the data cache is frozen
443
444	// Cache activity counters
445	uint32_t m_cpt_read; // total number of read data
446	uint32_t m_cpt_write; // total number of write data
447	uint32_t m_cpt_data_miss; // number of read miss
448	uint32_t m_cpt_ins_miss; // number of instruction miss
449	uint32_t m_cpt_unc_read; // number of read uncached
450	uint32_t m_cpt_write_cached; // number of cached write
451	uint32_t m_cpt_ins_read; // number of instruction read
452
453	uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer
454	uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss
455	uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read
456	uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss
457
458	uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions
459	uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions
460	uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions
461	uint32_t m_cpt_write_transaction; // number of VCI write transactions
462	uint32_t m_cpt_icache_unc_transaction;
463
464	uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions
465	uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions
466	uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions
467	uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions
468	uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions
469	uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions
470
471	// TLB activity counters
472	uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read
473	uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss
474	uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update acc
475	uint32_t m_cpt_data_tlb_read; // number of data tlb read
476	uint32_t m_cpt_data_tlb_miss; // number of data tlb miss
477	uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update acc
478	uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty
479	uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache
480	uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache
481	uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line
482	uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line
483	uint32_t m_cpt_tlb_occup_dcache;
484
485	uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss
486	uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss
487	uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc
488	uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc
489	uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
490	uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache
491	uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache
492
493	uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions
494	uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions
495	uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions
496	uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions
497	uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions
498	uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions
499	uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions
500	uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions
501
502	uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions
503	uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions
504	uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions
505	uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions
506	uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions
507	uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions
508	uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions
509	uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions
510
511	uint32_t m_cpt_cc_update_data; // number of coherence update data packets
512	uint32_t m_cpt_cc_inval_ins; // number of coherence inval instruction packets
513	uint32_t m_cpt_cc_inval_data; // number of coherence inval data packets
514	uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets
515	uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets
516	uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets
517
518	uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions
519	uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions
520	uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions
521	uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions
522
523	uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate
524	uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate
525
526	uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate
527	uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate
528
529	protected:
530	SC_HAS_PROCESS(VciCcVCacheWrapper2V1);
531
532	public:
533	VciCcVCacheWrapper2V1(
534	sc_module_name insname,
535	int proc_id,
536	const soclib::common::MappingTable &mtp,
537	const soclib::common::MappingTable &mtc,
538	const soclib::common::IntTab &initiator_index_rw,
539	const soclib::common::IntTab &initiator_index_c,
540	const soclib::common::IntTab &target_index,
541	size_t itlb_ways,
542	size_t itlb_sets,
543	size_t dtlb_ways,
544	size_t dtlb_sets,
545	size_t icache_ways,
546	size_t icache_sets,
547	size_t icache_words,
548	size_t dcache_ways,
549	size_t dcache_sets,
550	size_t dcache_words,
551	size_t write_buf_size );
552
553	~VciCcVCacheWrapper2V1();
554
555	void print_cpi();
556	void print_stats();
557
558	private:
559	void transition();
560	void genMoore();
561
562	soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
563	soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
564	};
565
566	}}
567
568	#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H */
569
570	// Local Variables:
571	// tab-width: 4
572	// c-basic-offset: 4
573	// c-file-offsets:((innamespace . 0)(inline-open . 0))
574	// indent-tabs-mode: nil
575	// End:
576
577	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
578
579
580
581

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