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vci_cc_vcache_wrapper2_v1.cpp @ 71

Last change on this file since 71 was 71, checked in by bouyer, 14 years ago
When updating PTE bits, don't write back to the dcache locally, the ll/sc will update the cache for us. Avoids potential coherence issues between the L1 cache and ram.
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1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper2_v1.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#include <cassert>
28	#include "arithmetics.h"
29	#include "../include/vci_cc_vcache_wrapper2_v1.h"
30
31	namespace soclib {
32	namespace caba {
33
34	//#define SOCLIB_MODULE_DEBUG
35	#ifdef SOCLIB_MODULE_DEBUG
36	namespace {
37	const char *icache_fsm_state_str[] = {
38	"ICACHE_IDLE",
39	"ICACHE_BIS",
40	"ICACHE_TLB1_READ",
41	"ICACHE_TLB1_WRITE",
42	"ICACHE_TLB1_UPDT",
43	"ICACHE_TLB2_READ",
44	"ICACHE_TLB2_WRITE",
45	"ICACHE_TLB2_UPDT",
46	"ICACHE_SW_FLUSH",
47	"ICACHE_TLB_FLUSH",
48	"ICACHE_CACHE_FLUSH",
49	"ICACHE_TLB_INVAL",
50	"ICACHE_CACHE_INVAL",
51	"ICACHE_CACHE_INVAL_PA",
52	"ICACHE_MISS_WAIT",
53	"ICACHE_UNC_WAIT",
54	"ICACHE_MISS_UPDT",
55	"ICACHE_ERROR",
56	"ICACHE_CC_INVAL",
57	"ICACHE_TLB_CC_INVAL",
58	};
59	const char *dcache_fsm_state_str[] = {
60	"DCACHE_IDLE",
61	"DCACHE_BIS",
62	"DCACHE_DTLB1_READ_CACHE",
63	"DCACHE_TLB1_LL_WAIT",
64	"DCACHE_TLB1_SC_WAIT",
65	"DCACHE_TLB1_READ",
66	"DCACHE_TLB1_READ_UPDT",
67	"DCACHE_TLB1_UPDT",
68	"DCACHE_DTLB2_READ_CACHE",
69	"DCACHE_TLB2_LL_WAIT",
70	"DCACHE_TLB2_SC_WAIT",
71	"DCACHE_TLB2_READ",
72	"DCACHE_TLB2_READ_UPDT",
73	"DCACHE_TLB2_UPDT",
74	"DCACHE_CTXT_SWITCH",
75	"DCACHE_ICACHE_FLUSH",
76	"DCACHE_DCACHE_FLUSH",
77	"DCACHE_ITLB_INVAL",
78	"DCACHE_DTLB_INVAL",
79	"DCACHE_ICACHE_INVAL",
80	"DCACHE_DCACHE_INVAL",
81	"DCACHE_ICACHE_INVAL_PA",
82	"DCACHE_DCACHE_INVAL_PA",
83	"DCACHE_DCACHE_SYNC",
84	"DCACHE_LL_DIRTY_WAIT",
85	"DCACHE_SC_DIRTY_WAIT",
86	"DCACHE_WRITE_UPDT",
87	"DCACHE_WRITE_REQ",
88	"DCACHE_MISS_WAIT",
89	"DCACHE_MISS_UPDT",
90	"DCACHE_UNC_WAIT",
91	"DCACHE_ERROR",
92	"DCACHE_ITLB_READ",
93	"DCACHE_ITLB_UPDT",
94	"DCACHE_ITLB_LL_WAIT",
95	"DCACHE_ITLB_SC_WAIT",
96	"DCACHE_CC_CHECK",
97	"DCACHE_CC_INVAL",
98	"DCACHE_CC_UPDT",
99	"DCACHE_CC_NOP",
100	"DCACHE_TLB_CC_INVAL",
101	"DCACHE_ITLB_CLEANUP",
102	};
103	const char *cmd_fsm_state_str[] = {
104	"CMD_IDLE",
105	"CMD_ITLB_READ",
106	"CMD_ITLB_ACC_LL",
107	"CMD_ITLB_ACC_SC",
108	"CMD_INS_MISS",
109	"CMD_INS_UNC",
110	"CMD_DTLB_READ",
111	"CMD_DTLB_ACC_LL",
112	"CMD_DTLB_ACC_SC",
113	"CMD_DTLB_DIRTY_LL",
114	"CMD_DTLB_DIRTY_SC",
115	"CMD_DATA_UNC",
116	"CMD_DATA_MISS",
117	"CMD_DATA_WRITE",
118	"CMD_INS_CLEANUP",
119	"CMD_DATA_CLEANUP",
120	};
121	const char *rsp_fsm_state_str[] = {
122	"RSP_IDLE",
123	"RSP_ITLB_READ",
124	"RSP_ITLB_ACC_LL",
125	"RSP_ITLB_ACC_SC",
126	"RSP_INS_MISS",
127	"RSP_INS_UNC",
128	"RSP_DTLB_READ",
129	"RSP_DTLB_ACC_LL",
130	"RSP_DTLB_ACC_SC",
131	"RSP_DTLB_DIRTY_LL",
132	"RSP_DTLB_DIRTY_SC",
133	"RSP_DATA_MISS",
134	"RSP_DATA_UNC",
135	"RSP_DATA_WRITE",
136	"RSP_INS_CLEANUP",
137	"RSP_DATA_CLEANUP",
138	};
139	const char *tgt_fsm_state_str[] = {
140	"TGT_IDLE",
141	"TGT_UPDT_WORD",
142	"TGT_UPDT_DATA",
143	"TGT_REQ_BROADCAST",
144	"TGT_REQ_ICACHE",
145	"TGT_REQ_DCACHE",
146	"TGT_RSP_BROADCAST",
147	"TGT_RSP_ICACHE",
148	"TGT_RSP_DCACHE",
149	};
150	const char *inval_itlb_fsm_state_str[] = {
151	"INVAL_ITLB_IDLE",
152	"INVAL_ITLB_CHECK" ,
153	"INVAL_ITLB_INVAL",
154	"INVAL_ITLB_CLEAR",
155	};
156	const char *inval_dtlb_fsm_state_str[] = {
157	"INVAL_DTLB_IDLE",
158	"INVAL_DTLB_CHECK",
159	"INVAL_DTLB_INVAL",
160	"INVAL_DTLB_CLEAR",
161	};
162	}
163	#endif
164
165	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper2V1<vci_param, iss_t>
166
167	using soclib::common::uint32_log2;
168
169	/***********************************************/
170	tmpl(/**/)::VciCcVCacheWrapper2V1(
171	sc_module_name name,
172	int proc_id,
173	const soclib::common::MappingTable &mtp,
174	const soclib::common::MappingTable &mtc,
175	const soclib::common::IntTab &initiator_index_rw,
176	const soclib::common::IntTab &initiator_index_c,
177	const soclib::common::IntTab &target_index,
178	size_t itlb_ways,
179	size_t itlb_sets,
180	size_t dtlb_ways,
181	size_t dtlb_sets,
182	size_t icache_ways,
183	size_t icache_sets,
184	size_t icache_words,
185	size_t dcache_ways,
186	size_t dcache_sets,
187	size_t dcache_words,
188	size_t write_buf_size )
189	/***********************************************/
190	: soclib::caba::BaseModule(name),
191
192	p_clk("clk"),
193	p_resetn("resetn"),
194	p_vci_ini_rw("vci_ini_rw"),
195	p_vci_ini_c("vci_ini_c"),
196	p_vci_tgt("vci_tgt"),
197
198	m_cacheability_table(mtp.getCacheabilityTable()),
199	m_segment(mtc.getSegment(target_index)),
200	m_iss(this->name(), proc_id),
201	m_srcid_rw(mtp.indexForId(initiator_index_rw)),
202	m_srcid_c(mtp.indexForId(initiator_index_c)),
203
204	m_itlb_ways(itlb_ways),
205	m_itlb_sets(itlb_sets),
206
207	m_dtlb_ways(dtlb_ways),
208	m_dtlb_sets(dtlb_sets),
209
210	m_icache_ways(icache_ways),
211	m_icache_sets(icache_sets),
212	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
213	m_icache_words(icache_words),
214
215	m_dcache_ways(dcache_ways),
216	m_dcache_sets(dcache_sets),
217	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
218	m_dcache_words(dcache_words),
219
220	m_write_buf_size(write_buf_size),
221	m_paddr_nbits(vci_param::N),
222
223	icache_tlb(itlb_ways,itlb_sets,vci_param::N),
224	dcache_tlb(dtlb_ways,dtlb_sets,vci_param::N),
225
226	r_dcache_fsm("r_dcache_fsm"),
227	r_dcache_paddr_save("r_dcache_paddr_save"),
228	r_dcache_wdata_save("r_dcache_wdata_save"),
229	r_dcache_rdata_save("r_dcache_rdata_save"),
230	r_dcache_type_save("r_dcache_type_save"),
231	r_dcache_be_save("r_dcache_be_save"),
232	r_dcache_cached_save("r_dcache_cached_save"),
233	r_dcache_tlb_paddr("r_dcache_tlb_paddr"),
234	r_dcache_miss_req("r_dcache_miss_req"),
235	r_dcache_unc_req("r_dcache_unc_req"),
236	r_dcache_write_req("r_dcache_write_req"),
237	r_dcache_tlb_read_req("r_dcache_tlb_read_req"),
238
239	r_dcache_tlb_ll_acc_req("r_dcache_tlb_ll_acc_req"),
240	r_dcache_tlb_sc_acc_req("r_dcache_tlb_sc_acc_req"),
241	r_dcache_tlb_ll_dirty_req("r_dcache_tlb_ll_dirty_req"),
242	r_dcache_tlb_sc_dirty_req("r_dcache_tlb_sc_dirty_req"),
243	r_dcache_tlb_ptba_read("r_dcache_tlb_ptba_read"),
244	r_dcache_xtn_req("r_dcache_xtn_req"),
245
246	r_dcache_fsm_save("r_dcache_fsm_save"),
247	r_dcache_cleanup_req("r_dcache_cleanup_req"),
248	r_dcache_inval_rsp("r_dcache_inval_rsp"),
249
250	r_icache_fsm("r_icache_fsm"),
251	r_icache_paddr_save("r_icache_paddr_save"),
252	r_icache_miss_req("r_icache_miss_req"),
253	r_icache_unc_req("r_icache_unc_req"),
254	r_dcache_itlb_read_req("r_dcache_itlb_read_req"),
255	r_dcache_itlb_ll_acc_req("r_dcache_itlb_ll_acc_req"),
256	r_dcache_itlb_sc_acc_req("r_dcache_itlb_sc_acc_req"),
257
258	r_itlb_read_dcache_req("r_itlb_read_dcache_req"),
259	r_itlb_k_read_dcache("r_itlb_k_read_dcache"),
260	r_itlb_acc_dcache_req("r_itlb_acc_dcache_req"),
261	r_dcache_rsp_itlb_error("r_dcache_rsp_itlb_error"),
262
263	r_icache_fsm_save("r_icache_fsm_save"),
264	r_icache_cleanup_req("r_icache_cleanup_req"),
265	r_icache_inval_rsp("r_icache_inval_rsp"),
266
267	r_vci_cmd_fsm("r_vci_cmd_fsm"),
268	r_vci_cmd_min("r_vci_cmd_min"),
269	r_vci_cmd_max("r_vci_cmd_max"),
270	r_vci_cmd_cpt("r_vci_cmd_cpt"),
271
272	r_vci_rsp_fsm("r_vci_rsp_fsm"),
273	r_vci_rsp_cpt("r_vci_rsp_cpt"),
274	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
275	r_vci_rsp_data_error("r_vci_rsp_data_error"),
276	r_dcache_tlb_sc_fail("r_dcache_tlb_sc_fail"),
277
278	r_vci_tgt_fsm("r_vci_tgt_fsm"),
279	r_tgt_addr("r_tgt_addr"),
280	r_tgt_word("r_tgt_word"),
281	r_tgt_update("r_tgt_update"),
282	r_tgt_srcid("r_tgt_srcid"),
283	r_tgt_pktid("r_tgt_pktid"),
284	r_tgt_trdid("r_tgt_trdid"),
285	r_tgt_icache_req("r_tgt_icache_req"),
286	r_tgt_dcache_req("r_tgt_dcache_req"),
287
288	r_inval_itlb_fsm("r_inval_itlb_fsm"),
289	r_dcache_itlb_inval_req("r_dcache_itlb_inval_req"),
290	r_dcache_itlb_inval_line("r_dcache_itlb_inval_line"),
291	r_itlb_cc_check_end("r_itlb_cc_check_end"),
292	r_ccinval_itlb_way("r_ccinval_itlb_way"),
293	r_ccinval_itlb_set("r_ccinval_itlb_set"),
294	r_icache_inval_tlb_rsp("r_icache_inval_tlb_rsp"),
295	r_icache_tlb_nline("r_icache_tlb_nline"),
296
297	r_inval_dtlb_fsm("r_inval_dtlb_fsm"),
298	r_dcache_dtlb_inval_req("r_dcache_dtlb_inval_req"),
299	r_dcache_dtlb_inval_line("r_dcache_dtlb_inval_line"),
300	r_dtlb_cc_check_end("r_dtlb_cc_check_end"),
301	r_ccinval_dtlb_way("r_ccinval_dtlb_way"),
302	r_ccinval_dtlb_set("r_ccinval_dtlb_set"),
303	r_dcache_inval_tlb_rsp("r_dcache_inval_tlb_rsp"),
304	r_dcache_tlb_nline("r_dcache_tlb_nline"),
305
306	r_dcache_itlb_cleanup_req("r_dcache_itlb_cleanup_req"),
307	r_dcache_itlb_cleanup_line("r_dcache_itlb_cleanup_line"),
308
309	r_dcache_dtlb_cleanup_req("r_dcache_dtlb_cleanup_req"),
310	r_dcache_dtlb_cleanup_line("r_dcache_dtlb_cleanup_line"),
311
312	r_wbuf("wbuf", write_buf_size ),
313	r_icache("icache", icache_ways, icache_sets, icache_words),
314	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
315	{
316	r_icache_miss_buf = new data_t[icache_words];
317	r_dcache_miss_buf = new data_t[dcache_words];
318	r_tgt_buf = new data_t[dcache_words];
319	r_tgt_val = new bool[dcache_words];
320	r_dcache_in_itlb = new bool[dcache_ways*dcache_sets];
321	r_dcache_in_dtlb = new bool[dcache_ways*dcache_sets];
322
323	SC_METHOD(transition);
324	dont_initialize();
325	sensitive << p_clk.pos();
326
327	SC_METHOD(genMoore);
328	dont_initialize();
329	sensitive << p_clk.neg();
330
331	typename iss_t::CacheInfo cache_info;
332	cache_info.has_mmu = true;
333	cache_info.icache_line_size = icache_words*sizeof(data_t);
334	cache_info.icache_assoc = icache_ways;
335	cache_info.icache_n_lines = icache_sets;
336	cache_info.dcache_line_size = dcache_words*sizeof(data_t);
337	cache_info.dcache_assoc = dcache_ways;
338	cache_info.dcache_n_lines = dcache_sets;
339	m_iss.setCacheInfo(cache_info);
340	}
341
342	/////////////////////////////////////
343	tmpl(/**/)::~VciCcVCacheWrapper2V1()
344	/////////////////////////////////////
345	{
346	delete [] r_icache_miss_buf;
347	delete [] r_dcache_miss_buf;
348	delete [] r_tgt_val;
349	delete [] r_tgt_buf;
350	delete [] r_dcache_in_itlb;
351	delete [] r_dcache_in_dtlb;
352	}
353
354	////////////////////////
355	tmpl(void)::print_cpi()
356	////////////////////////
357	{
358	std::cout << name() << " CPI = "
359	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
360	}
361
362	////////////////////////
363	tmpl(void)::print_stats()
364	////////////////////////
365	{
366	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
367	std::cout << name() << std::endl
368	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
369	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
370	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
371	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
372	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
373	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
374	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
375	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
376	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
377	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
378	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
379	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
380	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
381	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
382	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
383	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
384	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
385	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
386	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
387	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
388	<< "- DCACHE FROZEN BY TLB OP= " << (float)(m_cost_ins_tlb_occup_cache_frz+m_cost_data_tlb_occup_cache_frz)/m_cpt_dcache_frz_cycles << std::endl
389	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
390	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
391	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
392	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
393	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
394	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
395	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
396	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
397	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
398	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
399	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
400	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
401	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
402	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
403	}
404
405	/*************************************************/
406	tmpl(void)::transition()
407	/*************************************************/
408	{
409	if ( ! p_resetn.read() )
410	{
411	m_iss.reset();
412
413	r_dcache_fsm = DCACHE_IDLE;
414	r_icache_fsm = ICACHE_IDLE;
415	r_vci_cmd_fsm = CMD_IDLE;
416	r_vci_rsp_fsm = RSP_IDLE;
417	r_vci_tgt_fsm = TGT_IDLE;
418	r_inval_itlb_fsm = INVAL_ITLB_IDLE;
419	r_inval_dtlb_fsm = INVAL_DTLB_IDLE;
420
421	// write buffer & caches
422	r_wbuf.reset();
423	r_icache.reset();
424	r_dcache.reset();
425
426	icache_tlb.reset();
427	dcache_tlb.reset();
428
429	std::memset(r_dcache_in_itlb, 0, sizeof(r_dcache_in_itlb)m_icache_ways*m_icache_sets);
430	std::memset(r_dcache_in_dtlb, 0, sizeof(r_dcache_in_dtlb)m_dcache_ways*m_dcache_sets);
431
432	//r_mmu_mode = ALL_DEACTIVE;
433	r_mmu_mode = 0x3;
434	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
435	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
436	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
437	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
438	(uint32_log2(m_icache_words * 4));
439	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
440
441	r_icache_miss_req = false;
442	r_icache_unc_req = false;
443	r_dcache_itlb_read_req = false;
444
445	r_itlb_read_dcache_req = false;
446	r_itlb_k_read_dcache = false;
447	r_itlb_acc_dcache_req = false;
448	r_dcache_rsp_itlb_error = false;
449
450	r_dcache_miss_req = false;
451	r_dcache_unc_req = false;
452	r_dcache_write_req = false;
453	r_dcache_tlb_read_req = false;
454	r_dcache_tlb_ptba_read = false;
455	r_dcache_xtn_req = false;
456	r_dcache_llsc_reserved = false;
457
458	r_dcache_tlb_ll_acc_req = false;
459	r_dcache_tlb_sc_acc_req = false;
460	r_dcache_tlb_ll_dirty_req = false;
461	r_dcache_tlb_sc_dirty_req = false;
462	r_dcache_itlb_ll_acc_req = false;
463	r_dcache_itlb_sc_acc_req = false;
464
465	r_icache_cleanup_req = false;
466	r_dcache_cleanup_req = false;
467
468	r_tgt_icache_req = false;
469	r_tgt_dcache_req = false;
470
471	r_icache_inval_rsp = false;
472	r_dcache_inval_rsp = false;
473
474	r_dcache_dirty_save = false;
475	r_dcache_hit_p_save = false;
476	r_dcache_cached_save = false;
477
478	r_icache_buf_unc_valid = false;
479	r_dcache_buf_unc_valid = false;
480
481	r_vci_rsp_ins_error = false;
482	r_vci_rsp_data_error = false;
483
484	r_icache_id1_save = 0;
485	r_icache_ppn_save = 0;
486	r_icache_vpn_save = 0;
487	r_itlb_translation_valid = false;
488
489	r_dcache_id1_save = 0;
490	r_dcache_ppn_save = 0;
491	r_dcache_vpn_save = 0;
492	r_dtlb_translation_valid = false;
493
494	r_icache_ptba_ok = false;
495	r_dcache_ptba_ok = false;
496
497	r_icache_error_type = MMU_NONE;
498	r_dcache_error_type = MMU_NONE;
499
500	// coherence registers
501	r_icache_way = 0;
502	r_icache_set = 0;
503	r_icache_cleanup_req = false;
504	r_icache_inval_rsp = false;
505
506	r_dcache_way = 0;
507	r_dcache_set = 0;
508	r_dcache_cleanup_req = false;
509	r_dcache_inval_rsp = false;
510
511	r_itlb_inval_req = false;
512	r_dcache_itlb_inval_req = false;
513	r_itlb_cc_check_end = false;
514	r_ccinval_itlb_way = 0;
515	r_ccinval_itlb_set = 0;
516	r_icache_inval_tlb_rsp = false;
517
518	r_dcache_dtlb_inval_req = false;
519	r_dtlb_cc_check_end = false;
520	r_ccinval_dtlb_way = 0;
521	r_ccinval_dtlb_set = 0;
522	r_dcache_inval_tlb_rsp = false;
523
524	r_dcache_itlb_cleanup_req = false;
525	r_dcache_dtlb_cleanup_req = false;
526
527	r_dcache_cc_check = false;
528	r_dcache_tlb_sc_fail = false;
529
530	// activity counters
531	m_cpt_dcache_data_read = 0;
532	m_cpt_dcache_data_write = 0;
533	m_cpt_dcache_dir_read = 0;
534	m_cpt_dcache_dir_write = 0;
535	m_cpt_icache_data_read = 0;
536	m_cpt_icache_data_write = 0;
537	m_cpt_icache_dir_read = 0;
538	m_cpt_icache_dir_write = 0;
539
540	m_cpt_frz_cycles = 0;
541	m_cpt_dcache_frz_cycles = 0;
542	m_cpt_total_cycles = 0;
543
544	m_cpt_read = 0;
545	m_cpt_write = 0;
546	m_cpt_data_miss = 0;
547	m_cpt_ins_miss = 0;
548	m_cpt_unc_read = 0;
549	m_cpt_write_cached = 0;
550	m_cpt_ins_read = 0;
551
552	m_cost_write_frz = 0;
553	m_cost_data_miss_frz = 0;
554	m_cost_unc_read_frz = 0;
555	m_cost_ins_miss_frz = 0;
556
557	m_cpt_imiss_transaction = 0;
558	m_cpt_dmiss_transaction = 0;
559	m_cpt_unc_transaction = 0;
560	m_cpt_write_transaction = 0;
561	m_cpt_icache_unc_transaction = 0;
562
563	m_cost_imiss_transaction = 0;
564	m_cost_dmiss_transaction = 0;
565	m_cost_unc_transaction = 0;
566	m_cost_write_transaction = 0;
567	m_cost_icache_unc_transaction = 0;
568	m_length_write_transaction = 0;
569
570	m_cpt_ins_tlb_read = 0;
571	m_cpt_ins_tlb_miss = 0;
572	m_cpt_ins_tlb_update_acc = 0;
573
574	m_cpt_data_tlb_read = 0;
575	m_cpt_data_tlb_miss = 0;
576	m_cpt_data_tlb_update_acc = 0;
577	m_cpt_data_tlb_update_dirty = 0;
578	m_cpt_ins_tlb_hit_dcache = 0;
579	m_cpt_data_tlb_hit_dcache = 0;
580	m_cpt_ins_tlb_occup_cache = 0;
581	m_cpt_data_tlb_occup_cache = 0;
582
583	m_cost_ins_tlb_miss_frz = 0;
584	m_cost_data_tlb_miss_frz = 0;
585	m_cost_ins_tlb_update_acc_frz = 0;
586	m_cost_data_tlb_update_acc_frz = 0;
587	m_cost_data_tlb_update_dirty_frz = 0;
588	m_cost_ins_tlb_occup_cache_frz = 0;
589	m_cost_data_tlb_occup_cache_frz = 0;
590
591	m_cpt_itlbmiss_transaction = 0;
592	m_cpt_itlb_ll_transaction = 0;
593	m_cpt_itlb_sc_transaction = 0;
594	m_cpt_dtlbmiss_transaction = 0;
595	m_cpt_dtlb_ll_transaction = 0;
596	m_cpt_dtlb_sc_transaction = 0;
597	m_cpt_dtlb_ll_dirty_transaction = 0;
598	m_cpt_dtlb_sc_dirty_transaction = 0;
599
600	m_cost_itlbmiss_transaction = 0;
601	m_cost_itlb_ll_transaction = 0;
602	m_cost_itlb_sc_transaction = 0;
603	m_cost_dtlbmiss_transaction = 0;
604	m_cost_dtlb_ll_transaction = 0;
605	m_cost_dtlb_sc_transaction = 0;
606	m_cost_dtlb_ll_dirty_transaction = 0;
607	m_cost_dtlb_sc_dirty_transaction = 0;
608	return;
609	}
610
611	#ifdef SOCLIB_MODULE_DEBUG
612	std::cout << name() << " cycle = " << std::dec << m_cpt_total_cycles
613	<< " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
614	<< " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm]
615	<< " icache fsm: " << icache_fsm_state_str[r_icache_fsm]
616	<< " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm]
617	<< " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm]
618	<< " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm]
619	<< " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl;
620	#endif
621
622	m_cpt_total_cycles++;
623
624	typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
625	typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
626
627	typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
628	typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
629
630	m_iss.getRequests( ireq, dreq );
631
632	#ifdef SOCLIB_MODULE_DEBUG
633	std::cout << name() << " Instruction Request: " << ireq << std::endl;
634	std::cout << name() << " Data Request: " << dreq << std::endl;
635	#endif
636
637	/////////////////////////////////////////////////////////////////////
638	// The TGT_FSM controls the following ressources:
639	// - r_vci_tgt_fsm
640	// - r_tgt_buf[nwords]
641	// - r_tgt_val[nwords]
642	// - r_tgt_update
643	// - r_tgt_word
644	// - r_tgt_addr
645	// - r_tgt_srcid
646	// - r_tgt_trdid
647	// - r_tgt_pktid
648	// All VCI commands must be CMD_WRITE.
649	// If the VCI address offset is null, the command is an invalidate
650	// request. It is an update request otherwise.
651	// The VCI_TGT FSM stores the external request arguments in the
652	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
653	// & r_tgt_dcache_req flip-flops to signal the external request to
654	// the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
655	// of the update or invalidate request in the RSP state.
656	// - for an invalidate request the VCI packet length is 1 word.
657	// The WDATA field contains the line index (i.e. the Z & Y fields).
658	// - for an update request the VCI packet length is (n+2) words.
659	// The WDATA field of the first VCI word contains the line number.
660	// The WDATA field of the second VCI word contains the word index.
661	// The WDATA field of the n following words contains the values.
662	// - for both invalidate & update requests, the VCI response
663	// is one single word.
664	// In case of errors in the VCI command packet, the simulation
665	// is stopped with an error message.
666	/////////////////////////////////////////////////////////////////////
667
668	switch(r_vci_tgt_fsm) {
669	//////////////
670	case TGT_IDLE:
671	{
672	if ( p_vci_tgt.cmdval.read() )
673	{
674	paddr_t address = p_vci_tgt.address.read();
675
676	if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE)
677	{
678	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
679	std::cout << "the received VCI command is not a write" << std::endl;
680	exit(0);
681	}
682
683	// multi-update or multi-invalidate for data type
684	if ( ( address != 0x3 ) && ( ! m_segment.contains(address)) )
685	{
686	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
687	std::cout << "out of segment VCI command received for a multi-updt or multi-inval request" << std::endl;
688	exit(0);
689	}
690
691	r_tgt_srcid = p_vci_tgt.srcid.read();
692	r_tgt_trdid = p_vci_tgt.trdid.read();
693	r_tgt_pktid = p_vci_tgt.pktid.read();
694	r_tgt_plen = p_vci_tgt.plen.read(); // todo: wait L2 modification
695	r_tgt_addr = (paddr_t)(p_vci_tgt.be.read() & 0x3) << 32 \|
696	(paddr_t)p_vci_tgt.wdata.read() * m_dcache_words * 4;
697
698	if ( address == 0x3 ) // broadcast invalidate for data or instruction type
699	{
700	if ( ! p_vci_tgt.eop.read() )
701	{
702	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
703	std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
704	exit(0);
705	}
706	r_tgt_update = false;
707	r_vci_tgt_fsm = TGT_REQ_BROADCAST;
708	m_cpt_cc_broadcast++;
709	}
710	else // multi-update or multi-invalidate for data type
711	{
712	paddr_t cell = address - m_segment.baseAddress();
713
714	if (cell == 0) // invalidate
715	{
716	if ( ! p_vci_tgt.eop.read() )
717	{
718	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
719	std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
720	exit(0);
721	}
722	r_tgt_update = false;
723	r_vci_tgt_fsm = TGT_REQ_DCACHE;
724	m_cpt_cc_inval_data++ ;
725	}
726	else if (cell == 4) // update
727	{
728	if ( p_vci_tgt.eop.read() )
729	{
730	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
731	std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
732	exit(0);
733	}
734	r_tgt_update = true;
735	r_vci_tgt_fsm = TGT_UPDT_WORD;
736	m_cpt_cc_update_data++ ;
737	}
738	else if (cell == 8)
739	{
740	if ( ! p_vci_tgt.eop.read() )
741	{
742	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
743	std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
744	exit(0);
745	}
746	r_tgt_update = false;
747	r_vci_tgt_fsm = TGT_REQ_ICACHE;
748	m_cpt_cc_inval_ins++ ;
749
750	}
751	} // end if address
752	} // end if cmdval
753	break;
754	}
755	///////////////////
756	case TGT_UPDT_WORD:
757	{
758	if (p_vci_tgt.cmdval.read())
759	{
760	if ( p_vci_tgt.eop.read() )
761	{
762	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
763	std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
764	exit(0);
765	}
766	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_val[i] = false;
767	r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
768	r_vci_tgt_fsm = TGT_UPDT_DATA;
769	}
770	break;
771	}
772	///////////////////
773	case TGT_UPDT_DATA:
774	{
775	if (p_vci_tgt.cmdval.read())
776	{
777	size_t word = r_tgt_word.read();
778	if (word >= m_dcache_words)
779	{
780	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
781	std::cout << "the reveived MULTI-UPDATE command length is wrong" << std::endl;
782	exit(0);
783	}
784	r_tgt_buf[word] = p_vci_tgt.wdata.read();
785	if(p_vci_tgt.be.read()) r_tgt_val[word] = true;
786	r_tgt_word = word + 1;
787	if (p_vci_tgt.eop.read()) r_vci_tgt_fsm = TGT_REQ_DCACHE;
788	}
789	break;
790	}
791	////////////////////////
792	case TGT_REQ_BROADCAST:
793	{
794	if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
795	{
796	r_vci_tgt_fsm = TGT_RSP_BROADCAST;
797	r_tgt_icache_req = true;
798	r_tgt_dcache_req = true;
799	}
800	break;
801	}
802	/////////////////////
803	case TGT_REQ_ICACHE:
804	{
805	if ( !r_tgt_icache_req.read() )
806	{
807	r_vci_tgt_fsm = TGT_RSP_ICACHE;
808	r_tgt_icache_req = true;
809	}
810	break;
811	}
812	/////////////////////
813	case TGT_REQ_DCACHE:
814	{
815	if ( !r_tgt_dcache_req.read() )
816	{
817	r_vci_tgt_fsm = TGT_RSP_DCACHE;
818	r_tgt_dcache_req = true;
819	}
820	break;
821	}
822	///////////////////////
823	case TGT_RSP_BROADCAST:
824	{
825	// no response
826	if ( !r_tgt_icache_rsp.read() && !r_tgt_dcache_rsp.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
827	{
828	r_vci_tgt_fsm = TGT_IDLE;
829	break;
830	}
831
832	if ( p_vci_tgt.rspack.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
833	{
834	// one response
835	if ( !r_tgt_icache_rsp \|\| !r_tgt_dcache_rsp )
836	{
837	r_vci_tgt_fsm = TGT_IDLE;
838	r_tgt_icache_rsp = false;
839	r_tgt_dcache_rsp = false;
840	}
841
842	// if data and instruction have the inval line, need two responses
843	if ( r_tgt_icache_rsp && r_tgt_dcache_rsp )
844	{
845	r_tgt_icache_rsp = false; // only reset one for respond the second time
846	}
847	}
848	break;
849	}
850	/////////////////////
851	case TGT_RSP_ICACHE:
852	{
853	if ( (p_vci_tgt.rspack.read() \|\| !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() )
854	{
855	r_vci_tgt_fsm = TGT_IDLE;
856	r_tgt_icache_rsp = false;
857	}
858	break;
859	}
860	/////////////////////
861	case TGT_RSP_DCACHE:
862	{
863	if ( (p_vci_tgt.rspack.read() \|\| !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() )
864	{
865	r_vci_tgt_fsm = TGT_IDLE;
866	r_tgt_dcache_rsp = false;
867	}
868	break;
869	}
870	} // end switch TGT_FSM
871
872	////////////////////////////////////////////////////////////////////////////////////////
873	// ICACHE_FSM
874	//
875	// There is 9 mutually exclusive conditions to exit the IDLE state.
876	// Four configurations corresponding to an XTN request from processor,
877	// - Flush TLB (in case of Context switch) => TLB_FLUSH state
878	// - Flush cache => CACHE_FLUSH state
879	// - Invalidate a TLB entry => TLB_INVAL state
880	// - Invalidate a cache line => CACHE_INVAL state
881	// Five configurations corresponding to various TLB or cache MISS :
882	// - TLB miss(in case hit_p miss) => TLB1_READ state
883	// - TLB miss(in case hit_p hit) => TLB2_READ state
884	// - Hit in TLB but VPN changed => BIS state
885	// - Cached read miss => MISS_REQ state
886	// - Uncache read miss => UNC_REQ state
887	//
888	// In case of MISS, the controller writes a request in the r_icache_paddr_save register
889	// and sets the corresponding request flip-flop : r_dcache_itlb_read_req, r_icache_miss_req
890	// or r_icache_unc_req. These request flip-flops are reset by the VCI_RSP controller
891	// when the response is ready in the ICACHE buffer.
892	//
893	// The DCACHE FSM signals XTN processor requests using the r_dcache_xtn_req flip-flop.
894	// The request opcod and the address to be invalidated are transmitted
895	// in the r_dcache_paddr_save & r_dcache_wdata_save registers respectively.
896	// The request flip-flop is reset by the ICACHE_FSM when the operation is completed.
897	//
898	// The r_vci_rsp_ins_error flip-flop is set by the VCI_RSP FSM and reset
899	// by the ICACHE-FSM in the ICACHE_ERROR state.
900	//
901	//-----------------------------------------------------------------------------------
902	// Instruction TLB:
903	//
904	// - int ET (00: unmapped; 01: unused or PTD)
905	// (10: PTE new; 11: PTE old )
906	// - bool cachable (cached bit)
907	// - bool writable (** not used alwayse false)
908	// - bool executable (executable bit)
909	// - bool user (access in user mode allowed)
910	// - bool global (PTE not invalidated by a TLB flush)
911	// - bool dirty (** not used alwayse false)
912	// - uint32_t vpn (virtual page number)
913	// - uint32_t ppn (physical page number)
914	////////////////////////////////////////////////////////////////////////////////////////
915
916	switch(r_icache_fsm) {
917
918	////////////////
919	case ICACHE_IDLE:
920	{
921	pte_info_t icache_pte_info;
922	paddr_t tlb_ipaddr = 0; // physical address obtained from TLB
923	paddr_t spc_ipaddr = 0; // physical adress obtained from PPN_save (speculative)
924	data_t icache_ins = 0; // read instruction
925	bool icache_hit_c = false; // Cache hit
926	bool icache_cached = false; // cacheable access (read)
927	bool icache_hit_t = false; // hit on TLB
928	bool icache_hit_x = false; // VPN unmodified (can use spc_dpaddr)
929	bool icache_hit_p = false; // PTP unmodified (can skip first level page table walk)
930	size_t icache_tlb_way = 0; // selected way (in case of cache hit)
931	size_t icache_tlb_set = 0; // selected set (Y field in address)
932	paddr_t icache_tlb_nline = 0; // TLB NLINE
933
934	// Decoding processor XTN requests
935	// They are sent by DCACHE FSM
936
937	if (r_dcache_xtn_req)
938	{
939	if ((int)r_dcache_type_save == (int)iss_t::XTN_PTPR )
940	{
941	r_icache_way = 0;
942	r_icache_set = 0;
943	r_icache_fsm = ICACHE_SW_FLUSH;
944	break;
945	}
946	if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_FLUSH)
947	{
948	r_icache_way = 0;
949	r_icache_set = 0;
950	r_icache_fsm = ICACHE_CACHE_FLUSH;
951	break;
952	}
953	if ((int)r_dcache_type_save == (int)iss_t::XTN_ITLB_INVAL)
954	{
955	r_icache_fsm = ICACHE_TLB_INVAL;
956	break;
957	}
958	if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_INVAL)
959	{
960	r_icache_fsm = ICACHE_CACHE_INVAL;
961	break;
962	}
963	if ((int)r_dcache_type_save == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
964	{
965	r_icache_fsm = ICACHE_CACHE_INVAL_PA;
966	break;
967	}
968	if ((int)r_dcache_type_save == (int)iss_t::XTN_DCACHE_FLUSH )
969	{
970	// special for ins tlb miss via data cache
971	r_icache_fsm = ICACHE_TLB_FLUSH;
972	break;
973	}
974	} // end if xtn_req
975
976	// external cache invalidate request
977	if ( r_tgt_icache_req )
978	{
979	r_icache_fsm = ICACHE_CC_INVAL;
980	r_icache_fsm_save = r_icache_fsm;
981	break;
982	}
983
984	// external tlb invalidate request
985	if ( r_dcache_itlb_inval_req )
986	{
987	r_itlb_inval_req = true;
988	r_icache_fsm = ICACHE_TLB_CC_INVAL;
989	r_icache_fsm_save = r_icache_fsm;
990	break;
991	}
992
993	// icache_hit_t_m, icache_hit_t_k, icache_hit_x, icache_hit_p
994	// icache_pte_info, icache_tlb_way, icache_tlb_set & ipaddr & cacheability
995	// - If MMU activated : cacheability is defined by the cachable bit in the TLB
996	// - If MMU not activated : cacheability is defined by the segment table.
997
998	if ( !(r_mmu_mode.read() & INS_TLB_MASK) ) // MMU not activated
999	{
1000	icache_hit_t = true;
1001	icache_hit_x = true;
1002	icache_hit_p = true;
1003	tlb_ipaddr = ireq.addr;
1004	spc_ipaddr = ireq.addr;
1005	icache_cached = m_cacheability_table[ireq.addr];
1006	}
1007	else // MMU activated
1008	{
1009	m_cpt_ins_tlb_read++;
1010	icache_hit_t = icache_tlb.cctranslate(ireq.addr, &tlb_ipaddr, &icache_pte_info,
1011	&icache_tlb_nline, &icache_tlb_way, &icache_tlb_set);
1012	icache_hit_x = (((vaddr_t)r_icache_vpn_save << PAGE_K_NBITS) == (ireq.addr & ~PAGE_K_MASK)) && r_itlb_translation_valid;
1013	icache_hit_p = (((ireq.addr >> PAGE_M_NBITS) == r_icache_id1_save) && r_icache_ptba_ok);
1014	spc_ipaddr = ((paddr_t)r_icache_ppn_save << PAGE_K_NBITS) \| (paddr_t)(ireq.addr & PAGE_K_MASK);
1015	icache_cached = icache_pte_info.c;
1016	}
1017
1018	if ( !(r_mmu_mode.read() & INS_CACHE_MASK) ) // cache not actived
1019	{
1020	icache_cached = false;
1021	}
1022
1023	if ( ireq.valid )
1024	{
1025	m_cpt_icache_dir_read += m_icache_ways;
1026	m_cpt_icache_data_read += m_icache_ways;
1027
1028	// icache_hit_c & icache_ins
1029	if ( icache_cached ) // using speculative physical address for cached access
1030	{
1031	icache_hit_c = r_icache.read(spc_ipaddr, &icache_ins);
1032	}
1033	else // using actual physical address for uncached access
1034	{
1035	icache_hit_c = ( r_icache_buf_unc_valid && (tlb_ipaddr == (paddr_t)r_icache_paddr_save) );
1036	icache_ins = r_icache_miss_buf[0];
1037	}
1038
1039	if ( r_mmu_mode.read() & INS_TLB_MASK )
1040	{
1041	if ( icache_hit_t )
1042	{
1043	// check access rights
1044	if ( !icache_pte_info.u && (ireq.mode == iss_t::MODE_USER))
1045	{
1046	r_icache_error_type = MMU_READ_PRIVILEGE_VIOLATION;
1047	r_icache_bad_vaddr = ireq.addr;
1048	irsp.valid = true;
1049	irsp.error = true;
1050	irsp.instruction = 0;
1051	break;
1052	}
1053	if ( !icache_pte_info.x )
1054	{
1055	r_icache_error_type = MMU_READ_EXEC_VIOLATION;
1056	r_icache_bad_vaddr = ireq.addr;
1057	irsp.valid = true;
1058	irsp.error = true;
1059	irsp.instruction = 0;
1060	break;
1061	}
1062	}
1063
1064	// update LRU, save ppn, vpn and page type
1065	if ( icache_hit_t )
1066	{
1067	icache_tlb.setlru(icache_tlb_way,icache_tlb_set);
1068	r_icache_ppn_save = tlb_ipaddr >> PAGE_K_NBITS;
1069	r_icache_vpn_save = ireq.addr >> PAGE_K_NBITS;
1070	r_icache_tlb_nline = icache_tlb_nline;
1071	r_itlb_translation_valid = true;
1072	}
1073	else
1074	{
1075	r_itlb_translation_valid = false;
1076	}
1077
1078	} // end if MMU activated
1079
1080	// compute next state
1081	if ( !icache_hit_t && !icache_hit_p ) // TLB miss
1082	{
1083	// walk page table level 1
1084	r_icache_paddr_save = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((ireq.addr>>PAGE_M_NBITS)<<2);
1085	r_itlb_read_dcache_req = true;
1086	r_icache_vaddr_req = ireq.addr;
1087	r_icache_fsm = ICACHE_TLB1_READ;
1088	m_cpt_ins_tlb_miss++;
1089	m_cost_ins_tlb_miss_frz++;
1090	}
1091	else if ( !icache_hit_t && icache_hit_p ) // TLB Miss with possibility of bypass first level page
1092	{
1093	// walk page table level 2
1094	r_icache_paddr_save = (paddr_t)r_icache_ptba_save \|
1095	(paddr_t)(((ireq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
1096	r_itlb_read_dcache_req = true;
1097	r_icache_vaddr_req = ireq.addr;
1098	r_itlb_k_read_dcache = true;
1099	r_icache_fsm = ICACHE_TLB2_READ;
1100	m_cpt_ins_tlb_miss++;
1101	m_cost_ins_tlb_miss_frz++;
1102	}
1103	else if ( icache_hit_t && !icache_hit_x && icache_cached ) // cached access with an ucorrect speculative physical address
1104	{
1105	r_icache_paddr_save = tlb_ipaddr; // save actual physical address for BIS
1106	r_icache_vaddr_req = ireq.addr;
1107	r_icache_fsm = ICACHE_BIS;
1108	m_cost_ins_miss_frz++;
1109	}
1110	else // cached or uncached access with a correct speculative physical address
1111	{
1112	m_cpt_ins_read++;
1113	if ( !icache_hit_c )
1114	{
1115	m_cpt_ins_miss++;
1116	m_cost_ins_miss_frz++;
1117	if ( icache_cached )
1118	{
1119	r_icache_miss_req = true;
1120	r_icache_paddr_save = spc_ipaddr;
1121	r_icache_vaddr_req = ireq.addr;
1122	r_icache_fsm = ICACHE_MISS_WAIT;
1123	}
1124	else
1125	{
1126	r_icache_unc_req = true;
1127	r_icache_buf_unc_valid = false;
1128	r_icache_paddr_save = tlb_ipaddr;
1129	r_icache_vaddr_req = ireq.addr;
1130	r_icache_fsm = ICACHE_UNC_WAIT;
1131	}
1132	}
1133	else
1134	{
1135	r_icache_buf_unc_valid = false;
1136	r_icache_fsm = ICACHE_IDLE;
1137	}
1138	irsp.valid = icache_hit_c;
1139	irsp.instruction = icache_ins;
1140	} // end if next states
1141
1142	} // end if ireq.valid
1143	break;
1144	}
1145	////////////////
1146	case ICACHE_BIS:
1147	{
1148	// external cache invalidate request
1149	if ( r_tgt_icache_req )
1150	{
1151	if ( ireq.valid ) m_cost_ins_miss_frz++;
1152	r_icache_fsm = ICACHE_CC_INVAL;
1153	r_icache_fsm_save = r_icache_fsm;
1154	break;
1155	}
1156
1157	// external tlb invalidate request
1158	if ( r_dcache_itlb_inval_req )
1159	{
1160	if ( ireq.valid ) m_cost_ins_miss_frz++;
1161	r_itlb_inval_req = true;
1162	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1163	r_icache_fsm_save = r_icache_fsm;
1164	break;
1165	}
1166
1167	// using page is invalidated
1168	if ( r_icache_inval_tlb_rsp )
1169	{
1170	if ( ireq.valid ) m_cost_ins_miss_frz++;
1171	r_icache_inval_tlb_rsp = false;
1172	r_icache_fsm = ICACHE_IDLE;
1173	break;
1174	}
1175
1176	data_t icache_ins = 0;
1177	bool icache_hit_c = false;
1178	bool icache_hit_t = false;
1179	paddr_t tlb_ipaddr = 0;
1180
1181	icache_hit_t = icache_tlb.translate(ireq.addr, &tlb_ipaddr);
1182
1183	if ( (tlb_ipaddr == r_icache_paddr_save.read()) && ireq.valid && icache_hit_t ) // unmodified & valid
1184	{
1185	m_cpt_ins_read++;
1186
1187	// acces is always cached in this state
1188	icache_hit_c = r_icache.read(r_icache_paddr_save, &icache_ins);
1189
1190	if ( !icache_hit_c )
1191	{
1192	r_icache_miss_req = true;
1193	r_icache_fsm = ICACHE_MISS_WAIT;
1194	m_cpt_ins_miss++;
1195	m_cost_ins_miss_frz++;
1196	}
1197	else
1198	{
1199	r_icache_fsm = ICACHE_IDLE;
1200	}
1201	irsp.valid = icache_hit_c;
1202	if (irsp.valid)
1203	assert((r_icache_vaddr_req.read() == ireq.addr) &&
1204	"vaddress should not be modified while ICACHE_BIS");
1205	irsp.error = false;
1206	irsp.instruction = icache_ins;
1207	}
1208	else // modified or invalid
1209	{
1210	irsp.valid = false;
1211	irsp.error = false;
1212	irsp.instruction = 0;
1213	r_icache_fsm = ICACHE_IDLE;
1214	}
1215	break;
1216	}
1217	//////////////////////
1218	case ICACHE_TLB1_READ:
1219	{
1220	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1221
1222	// external cache invalidate request
1223	if ( r_tgt_icache_req )
1224	{
1225	r_icache_fsm = ICACHE_CC_INVAL;
1226	r_icache_fsm_save = r_icache_fsm;
1227	break;
1228	}
1229
1230	// external tlb invalidate request
1231	if ( r_dcache_itlb_inval_req )
1232	{
1233	r_itlb_inval_req = true;
1234	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1235	r_icache_fsm_save = r_icache_fsm;
1236	break;
1237	}
1238
1239	if ( !r_itlb_read_dcache_req )
1240	{
1241	if (r_icache_vaddr_req.read() != ireq.addr \|\| !ireq.valid)
1242	{
1243	/* request modified, drop response and restart */
1244	r_icache_ptba_ok = false;
1245	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
1246	if ( r_dcache_rsp_itlb_error ) r_dcache_rsp_itlb_error = false;
1247	r_icache_fsm = ICACHE_IDLE;
1248	break;
1249	}
1250
1251	if ( !r_icache_inval_tlb_rsp ) // TLB miss read response and no invalidation
1252	{
1253	if ( !r_dcache_rsp_itlb_error ) // vci response ok
1254	{
1255	if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
1256	{
1257	r_icache_ptba_ok = false;
1258	r_icache_error_type = MMU_READ_PT1_UNMAPPED;
1259	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1260	r_icache_fsm = ICACHE_ERROR;
1261	}
1262	else if ( (r_dcache_rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT ) // PTD
1263	{
1264	r_icache_ptba_ok = true;
1265	r_icache_ptba_save = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;
1266	r_icache_id1_save = r_icache_vaddr_req.read() >> PAGE_M_NBITS;
1267	r_icache_paddr_save = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
1268	(paddr_t)(((r_icache_vaddr_req.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
1269	r_itlb_read_dcache_req = true;
1270	r_itlb_k_read_dcache = true;
1271	r_icache_fsm = ICACHE_TLB2_READ;
1272	}
1273	else
1274	{
1275	r_icache_ptba_ok = false;
1276
1277	if ( (m_srcid_rw >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
1278	{
1279	if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
1280	{
1281	r_icache_pte_update = r_dcache_rsp_itlb_miss;
1282	r_icache_fsm = ICACHE_TLB1_UPDT;
1283	}
1284	else
1285	{
1286	r_icache_pte_update = r_dcache_rsp_itlb_miss \| PTE_L_MASK;
1287	r_itlb_acc_dcache_req = true;
1288	r_icache_fsm = ICACHE_TLB1_WRITE;
1289	m_cpt_ins_tlb_update_acc++;
1290	m_cost_ins_tlb_update_acc_frz++;
1291	}
1292	}
1293	else // remotely
1294	{
1295	if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
1296	{
1297	r_icache_pte_update = r_dcache_rsp_itlb_miss;
1298	r_icache_fsm = ICACHE_TLB1_UPDT;
1299	}
1300	else
1301	{
1302	r_icache_pte_update = r_dcache_rsp_itlb_miss \| PTE_R_MASK;
1303	r_itlb_acc_dcache_req = true;
1304	r_icache_fsm = ICACHE_TLB1_WRITE;
1305	m_cpt_ins_tlb_update_acc++;
1306	m_cost_ins_tlb_update_acc_frz++;
1307	}
1308	}
1309	}
1310	}
1311	else // vci response error
1312	{
1313	r_icache_fsm = ICACHE_ERROR;
1314	r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
1315	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1316	}
1317	}
1318
1319	if ( r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation
1320	{
1321	if ( r_dcache_rsp_itlb_error )
1322	{
1323	r_icache_inval_tlb_rsp = false;
1324	r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
1325	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1326	r_icache_fsm = ICACHE_ERROR;
1327	}
1328	else
1329	{
1330	r_icache_inval_tlb_rsp = false;
1331	r_icache_fsm = ICACHE_IDLE;
1332	}
1333	}
1334	}
1335	break;
1336	}
1337	///////////////////////
1338	case ICACHE_TLB1_WRITE:
1339	{
1340	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1341	m_cost_ins_tlb_update_acc_frz++;
1342
1343	// external cache invalidate request
1344	if ( r_tgt_icache_req )
1345	{
1346	r_icache_fsm = ICACHE_CC_INVAL;
1347	r_icache_fsm_save = r_icache_fsm;
1348	break;
1349	}
1350	// external tlb invalidate request
1351	if ( r_dcache_itlb_inval_req )
1352	{
1353	r_itlb_inval_req = true;
1354	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1355	r_icache_fsm_save = r_icache_fsm;
1356	break;
1357	}
1358
1359	if ( !r_itlb_acc_dcache_req ) // TLB access bits write response
1360	{
1361	if ( !r_icache_inval_tlb_rsp ) // TLB access bits write response and no invalidation
1362	{
1363	if ( r_dcache_rsp_itlb_error )
1364	{
1365	r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
1366	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1367	r_icache_fsm = ICACHE_ERROR;
1368	}
1369	else
1370	{
1371	r_icache_fsm = ICACHE_TLB1_UPDT;
1372	}
1373	}
1374
1375	if ( r_icache_inval_tlb_rsp) // TLB ET write response and invalidation
1376	{
1377	if ( r_dcache_rsp_itlb_error )
1378	{
1379	r_icache_inval_tlb_rsp = false;
1380	r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
1381	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1382	r_icache_fsm = ICACHE_ERROR;
1383	}
1384	else
1385	{
1386	r_icache_inval_tlb_rsp = false;
1387	r_icache_fsm = ICACHE_IDLE;
1388	}
1389	}
1390	}
1391	break;
1392	}
1393	//////////////////////
1394	case ICACHE_TLB1_UPDT:
1395	{
1396	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1397
1398	// external cache invalidate request
1399	if ( r_tgt_icache_req )
1400	{
1401	r_icache_fsm = ICACHE_CC_INVAL;
1402	r_icache_fsm_save = r_icache_fsm;
1403	break;
1404	}
1405
1406	// external tlb invalidate request
1407	if ( r_dcache_itlb_inval_req )
1408	{
1409	r_itlb_inval_req = true;
1410	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1411	r_icache_fsm_save = r_icache_fsm;
1412	break;
1413	}
1414
1415	// TLB update and invalidate different PTE
1416	if ( !r_dcache_itlb_cleanup_req && !r_icache_inval_tlb_rsp )
1417	{
1418	paddr_t victim_index = 0;
1419	r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
1420	r_dcache_itlb_cleanup_line = victim_index;
1421	m_cpt_cc_cleanup_ins++;
1422	r_icache_fsm = ICACHE_IDLE;
1423	}
1424
1425	// TLB update and invalidate same PTE
1426	if ( r_icache_inval_tlb_rsp )
1427	{
1428	r_icache_inval_tlb_rsp = false;
1429	r_icache_fsm = ICACHE_IDLE;
1430	}
1431	break;
1432	}
1433	/////////////////////
1434	case ICACHE_TLB2_READ:
1435	{
1436	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1437
1438	// external cache invalidate request
1439	if ( r_tgt_icache_req )
1440	{
1441	r_icache_fsm = ICACHE_CC_INVAL;
1442	r_icache_fsm_save = r_icache_fsm;
1443	break;
1444	}
1445
1446	// external tlb invalidate request
1447	if ( r_dcache_itlb_inval_req )
1448	{
1449	r_itlb_inval_req = true;
1450	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1451	r_icache_fsm_save = r_icache_fsm;
1452	break;
1453	}
1454
1455	if ( !r_itlb_read_dcache_req ) // TLB miss read response
1456	{
1457	if (r_icache_vaddr_req.read() != ireq.addr \|\| !ireq.valid)
1458	{
1459	/* request modified, drop response and restart */
1460	r_icache_ptba_ok = false;
1461	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
1462	if ( r_dcache_rsp_itlb_error ) r_dcache_rsp_itlb_error = false;
1463	r_icache_fsm = ICACHE_IDLE;
1464	break;
1465	}
1466
1467	if ( !r_icache_inval_tlb_rsp ) // TLB miss read response
1468	{
1469	if ( !r_dcache_rsp_itlb_error ) // VCI response ok
1470	{
1471	if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
1472	{
1473	r_icache_error_type = MMU_READ_PT2_UNMAPPED;
1474	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1475	r_icache_fsm = ICACHE_ERROR;
1476	}
1477	else
1478	{
1479	if ( (m_srcid_rw >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
1480	{
1481	if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
1482	{
1483	r_icache_fsm = ICACHE_TLB2_UPDT;
1484	r_icache_pte_update = r_dcache_rsp_itlb_miss;
1485	}
1486	else
1487	{
1488	r_icache_pte_update = r_dcache_rsp_itlb_miss \| PTE_L_MASK;
1489	r_itlb_acc_dcache_req = true;
1490	r_icache_fsm = ICACHE_TLB2_WRITE;
1491	m_cpt_ins_tlb_update_acc++;
1492	m_cost_ins_tlb_update_acc_frz++;
1493	}
1494	}
1495	else // remotely
1496	{
1497	if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
1498	{
1499	r_icache_fsm = ICACHE_TLB2_UPDT;
1500	r_icache_pte_update = r_dcache_rsp_itlb_miss;
1501	}
1502	else
1503	{
1504	r_icache_pte_update = r_dcache_rsp_itlb_miss \| PTE_R_MASK;
1505	r_itlb_acc_dcache_req = true;
1506	r_icache_fsm = ICACHE_TLB2_WRITE;
1507	m_cpt_ins_tlb_update_acc++;
1508	m_cost_ins_tlb_update_acc_frz++;
1509	}
1510	}
1511	}
1512	}
1513	else // VCI response error
1514	{
1515	r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
1516	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1517	r_icache_fsm = ICACHE_ERROR;
1518	}
1519	}
1520
1521	if ( r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation
1522	{
1523	if ( r_dcache_rsp_itlb_error )
1524	{
1525	r_icache_inval_tlb_rsp = false;
1526	r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
1527	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1528	r_icache_fsm = ICACHE_ERROR;
1529	}
1530	else
1531	{
1532	r_icache_inval_tlb_rsp = false;
1533	r_icache_fsm = ICACHE_IDLE;
1534	}
1535	}
1536	}
1537	break;
1538	}
1539	/////////////////////////
1540	case ICACHE_TLB2_WRITE:
1541	{
1542	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1543	m_cost_ins_tlb_update_acc_frz++;
1544
1545	// external cache invalidate request
1546	if ( r_tgt_icache_req )
1547	{
1548	r_icache_fsm = ICACHE_CC_INVAL;
1549	r_icache_fsm_save = r_icache_fsm;
1550	break;
1551	}
1552	// external tlb invalidate request
1553	if ( r_dcache_itlb_inval_req )
1554	{
1555	r_itlb_inval_req = true;
1556	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1557	r_icache_fsm_save = r_icache_fsm;
1558	break;
1559	}
1560
1561	if ( !r_itlb_acc_dcache_req ) // TLB access bits write response
1562	{
1563	if ( !r_icache_inval_tlb_rsp ) // TLB access bits write response
1564	{
1565	if ( r_dcache_rsp_itlb_error )
1566	{
1567	r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
1568	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1569	r_icache_fsm = ICACHE_ERROR;
1570	}
1571	else
1572	{
1573	r_icache_fsm = ICACHE_TLB2_UPDT;
1574	}
1575	}
1576
1577	if ( r_icache_inval_tlb_rsp ) // TLB ET write response and invalidation
1578	{
1579	if ( r_dcache_rsp_itlb_error )
1580	{
1581	r_icache_inval_tlb_rsp = false;
1582	r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
1583	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1584	r_icache_fsm = ICACHE_ERROR;
1585	}
1586	else
1587	{
1588	r_icache_inval_tlb_rsp = false;
1589	r_icache_fsm = ICACHE_IDLE;
1590	}
1591	}
1592	}
1593	break;
1594	}
1595	/////////////////////
1596	case ICACHE_TLB2_UPDT:
1597	{
1598	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1599
1600	// external cache invalidate request
1601	if ( r_tgt_icache_req )
1602	{
1603	r_icache_fsm = ICACHE_CC_INVAL;
1604	r_icache_fsm_save = r_icache_fsm;
1605	break;
1606	}
1607
1608	// external tlb invalidate request
1609	if ( r_dcache_itlb_inval_req )
1610	{
1611	r_itlb_inval_req = true;
1612	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1613	r_icache_fsm_save = r_icache_fsm;
1614	break;
1615	}
1616
1617	// TLB update and invalidate different PTE
1618	if ( !r_dcache_itlb_cleanup_req && !r_icache_inval_tlb_rsp )
1619	{
1620	paddr_t victim_index = 0;
1621	r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_dcache_rsp_itlb_ppn,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
1622	r_dcache_itlb_cleanup_line = victim_index;
1623	m_cpt_cc_cleanup_ins++;
1624	r_icache_fsm = ICACHE_IDLE;
1625	}
1626	// TLB update and invalidate same PTE
1627	if ( r_icache_inval_tlb_rsp )
1628	{
1629	r_icache_inval_tlb_rsp = false;
1630	r_icache_fsm = ICACHE_IDLE;
1631	}
1632	break;
1633	}
1634	/////////////////////////////
1635	case ICACHE_SW_FLUSH:
1636	{
1637	size_t way = r_icache_way;
1638	size_t set = r_icache_set;
1639	bool clean = false;
1640
1641	// 4K page size TLB flush leads to cleanup req to data cache
1642	if ( !r_dcache_itlb_cleanup_req ) // last cleanup finish
1643	{
1644	paddr_t victim_index = 0;
1645	for ( ; way < m_itlb_ways; way++)
1646	{
1647	for ( ; set < m_itlb_sets; set++)
1648	{
1649	if(icache_tlb.checkcleanup(way, set, &victim_index))
1650	{
1651	clean = true;
1652	r_dcache_itlb_cleanup_req = true;
1653	r_dcache_itlb_cleanup_line = victim_index;
1654	r_icache_way = way + ((set+1)/m_itlb_sets);
1655	r_icache_set = (set+1) % m_itlb_sets;
1656	break;
1657	}
1658	}
1659	if (clean) break;
1660	}
1661
1662	if (way == m_itlb_ways)
1663	{
1664	r_dcache_xtn_req = false;
1665	r_itlb_translation_valid = false;
1666	r_icache_ptba_ok = false;
1667	r_icache_fsm = ICACHE_IDLE;
1668	break;
1669	}
1670	}
1671	break;
1672	}
1673	/////////////////////
1674	case ICACHE_TLB_FLUSH:
1675	{
1676	// data cache flush leads to ins tlb flush, flush all tlb entry
1677	icache_tlb.flush(true); // global entries are invalidated
1678	r_dcache_xtn_req = false;
1679	r_itlb_translation_valid = false;
1680	r_icache_ptba_ok = false;
1681	r_icache_fsm = ICACHE_IDLE;
1682	break;
1683	}
1684	////////////////////////
1685	case ICACHE_CACHE_FLUSH:
1686	{
1687	// external cache invalidate request
1688	if ( r_tgt_icache_req )
1689	{
1690	r_icache_fsm = ICACHE_CC_INVAL;
1691	r_icache_fsm_save = r_icache_fsm;
1692	break;
1693	}
1694
1695	size_t way = r_icache_way;
1696	size_t set = r_icache_set;
1697	bool clean = false;
1698
1699	// cache flush and send cleanup to external
1700	if ( !r_icache_cleanup_req )
1701	{
1702	paddr_t victim_index = 0;
1703	for ( ; way < m_icache_ways; way++ )
1704	{
1705	for ( ; set < m_icache_sets; set++ )
1706	{
1707	if ( r_icache.flush(way, set, &victim_index) )
1708	{
1709	clean = true;
1710	r_icache_cleanup_req = true;
1711	r_icache_cleanup_line = victim_index;
1712	m_cpt_cc_cleanup_ins++;
1713	r_icache_way = way + ((set+1)/m_icache_sets);
1714	r_icache_set = (set+1) % m_icache_sets;
1715	break;
1716	}
1717	}
1718	if (clean) break;
1719	}
1720	if (way == m_icache_ways)
1721	{
1722	r_dcache_xtn_req = false;
1723	r_icache_fsm = ICACHE_IDLE;
1724	break;
1725	}
1726	}
1727	break;
1728	}
1729	/////////////////////
1730	case ICACHE_TLB_INVAL:
1731	{
1732	paddr_t victim_index = 0;
1733
1734	if ( !r_dcache_itlb_cleanup_req )
1735	{
1736	r_dcache_itlb_cleanup_req = icache_tlb.inval(r_dcache_wdata_save, &victim_index);
1737	r_dcache_itlb_cleanup_line = victim_index;
1738	m_cpt_cc_cleanup_ins++;
1739	r_dcache_xtn_req = false;
1740	r_itlb_translation_valid = false;
1741	r_icache_ptba_ok = false;
1742	r_icache_fsm = ICACHE_IDLE;
1743	}
1744	break;
1745	}
1746	////////////////////////
1747	case ICACHE_CACHE_INVAL:
1748	{
1749	// external cache invalidate request
1750	if ( r_tgt_icache_req )
1751	{
1752	r_icache_fsm = ICACHE_CC_INVAL;
1753	r_icache_fsm_save = r_icache_fsm;
1754	break;
1755	}
1756
1757	paddr_t ipaddr = 0;
1758	bool icache_hit_t = false;
1759
1760	if ( !r_icache_cleanup_req )
1761	{
1762	if ( r_mmu_mode.read() & INS_TLB_MASK )
1763	{
1764	icache_hit_t = icache_tlb.translate(r_dcache_wdata_save, &ipaddr);
1765	}
1766	else
1767	{
1768	ipaddr = (paddr_t)r_dcache_wdata_save;
1769	icache_hit_t = true;
1770	}
1771	if ( icache_hit_t )
1772	{
1773	// invalidate and cleanup if necessary
1774	r_icache_cleanup_req = r_icache.inval(ipaddr);
1775	r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);
1776	m_cpt_cc_cleanup_ins++;
1777	}
1778	r_dcache_xtn_req = false;
1779	r_icache_fsm = ICACHE_IDLE;
1780	}
1781	break;
1782	}
1783	////////////////////////
1784	case ICACHE_CACHE_INVAL_PA:
1785	{
1786	// external cache invalidate request
1787	if ( r_tgt_icache_req )
1788	{
1789	r_icache_fsm = ICACHE_CC_INVAL;
1790	r_icache_fsm_save = r_icache_fsm;
1791	break;
1792	}
1793
1794	paddr_t ipaddr = (paddr_t)r_mmu_word_hi.read() << 32 \| r_mmu_word_lo.read();
1795
1796	if ( !r_icache_cleanup_req )
1797	{
1798	// invalidate and cleanup if necessary
1799	r_icache_cleanup_req = r_icache.inval(ipaddr);
1800	r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);
1801	m_cpt_cc_cleanup_ins++;
1802	r_dcache_xtn_req = false;
1803	r_icache_fsm = ICACHE_IDLE;
1804	}
1805	break;
1806	}
1807	///////////////////////
1808	case ICACHE_MISS_WAIT:
1809	{
1810	m_cost_ins_miss_frz++;
1811
1812	// external cache invalidate request
1813	if ( r_tgt_icache_req )
1814	{
1815	r_icache_fsm = ICACHE_CC_INVAL;
1816	r_icache_fsm_save = r_icache_fsm;
1817	break;
1818	}
1819
1820	// external tlb invalidate request
1821	if ( r_dcache_itlb_inval_req )
1822	{
1823	r_itlb_inval_req = true;
1824	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1825	r_icache_fsm_save = r_icache_fsm;
1826	break;
1827	}
1828
1829	if ( !r_icache_miss_req )
1830	{
1831	if ( r_vci_rsp_ins_error )
1832	{
1833	r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;
1834	r_icache_bad_vaddr = ireq.addr;
1835	r_icache_fsm = ICACHE_ERROR;
1836
1837	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
1838	if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
1839	break;
1840	}
1841
1842	if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
1843	{
1844	if ( r_icache_cleanup_req ) break;
1845	r_icache_cleanup_req = true;
1846	r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);
1847	m_cpt_cc_cleanup_ins++;
1848	r_icache_fsm = ICACHE_IDLE;
1849	r_icache_inval_tlb_rsp = false;
1850	if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
1851	break;
1852	}
1853
1854	if ( r_icache_inval_rsp ) // Miss read response and tlb invalidation
1855	{
1856	if ( r_icache_cleanup_req ) break;
1857	r_icache_cleanup_req = true;
1858	r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);
1859	m_cpt_cc_cleanup_ins++;
1860	r_icache_fsm = ICACHE_IDLE;
1861	r_icache_inval_rsp = false;
1862	break;
1863	}
1864	r_icache_fsm = ICACHE_MISS_UPDT;
1865	}
1866	break;
1867	}
1868	////////////////////
1869	case ICACHE_UNC_WAIT:
1870	{
1871	// external cache invalidate request
1872	if ( r_tgt_icache_req )
1873	{
1874	r_icache_fsm = ICACHE_CC_INVAL;
1875	r_icache_fsm_save = r_icache_fsm;
1876	break;
1877	}
1878
1879	// external tlb invalidate request
1880	if ( r_dcache_itlb_inval_req )
1881	{
1882	r_itlb_inval_req = true;
1883	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1884	r_icache_fsm_save = r_icache_fsm;
1885	break;
1886	}
1887
1888	if ( !r_icache_unc_req )
1889	{
1890	if ( r_vci_rsp_ins_error )
1891	{
1892	r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;
1893	r_icache_bad_vaddr = ireq.addr;
1894	r_icache_fsm = ICACHE_ERROR;
1895
1896	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
1897	//if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
1898	break;
1899	}
1900
1901	if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
1902	{
1903	r_icache_inval_tlb_rsp = false;
1904	r_icache_fsm = ICACHE_IDLE;
1905	break;
1906	}
1907
1908	// Miss read response and no invalidation
1909	r_icache_buf_unc_valid = true;
1910	r_icache_fsm = ICACHE_IDLE;
1911	}
1912	break;
1913	}
1914	//////////////////////
1915	case ICACHE_MISS_UPDT:
1916	{
1917	m_cost_ins_miss_frz++;
1918
1919	// external cache invalidate request
1920	if ( r_tgt_icache_req )
1921	{
1922	r_icache_fsm = ICACHE_CC_INVAL;
1923	r_icache_fsm_save = r_icache_fsm;
1924	break;
1925	}
1926
1927	// external tlb invalidate request
1928	if ( r_dcache_itlb_inval_req )
1929	{
1930	r_itlb_inval_req = true;
1931	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1932	r_icache_fsm_save = r_icache_fsm;
1933	break;
1934	}
1935
1936	if ( r_icache_inval_tlb_rsp ) // tlb invalidation
1937	{
1938	if ( r_icache_cleanup_req ) break;
1939	r_icache_cleanup_req = true;
1940	r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);
1941	m_cpt_cc_cleanup_ins++;
1942	r_icache_inval_tlb_rsp = false;
1943	if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
1944	r_icache_fsm = ICACHE_IDLE;
1945	break;
1946	}
1947
1948	if ( !r_icache_cleanup_req ) // Miss update and no invalidation
1949	{
1950	if ( r_icache_inval_rsp ) // invalidation
1951	{
1952	r_icache_cleanup_req = true;
1953	r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);
1954	m_cpt_cc_cleanup_ins++;
1955	r_icache_fsm = ICACHE_IDLE;
1956	r_icache_inval_rsp = false;
1957	}
1958	else
1959	{
1960	data_t* buf = r_icache_miss_buf;
1961	paddr_t victim_index = 0;
1962	m_cpt_icache_dir_write++;
1963	m_cpt_icache_data_write++;
1964
1965	r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index);
1966	r_icache_cleanup_line = victim_index; m_cpt_cc_cleanup_ins++;
1967	r_icache_fsm = ICACHE_IDLE;
1968	}
1969	}
1970	break;
1971	}
1972	///////////////////
1973	case ICACHE_ERROR:
1974	{
1975	r_vci_rsp_ins_error = false;
1976	r_dcache_rsp_itlb_error = false;
1977	irsp.valid = true;
1978	irsp.error = true;
1979	irsp.instruction = 0;
1980	r_icache_fsm = ICACHE_IDLE;
1981	break;
1982	}
1983	/////////////////////
1984	case ICACHE_CC_INVAL:
1985	{
1986	m_cpt_icache_dir_read += m_icache_ways;
1987	/* activity counter */
1988	if ( (( r_icache_fsm_save == ICACHE_BIS ) \|\|( r_icache_fsm_save == ICACHE_MISS_WAIT ) \|\| ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) )
1989	{
1990	m_cost_ins_miss_frz++;
1991	}
1992	if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_READ ) \|\|
1993	( r_icache_fsm_save == ICACHE_TLB1_WRITE ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) \|\|
1994	( r_icache_fsm_save == ICACHE_TLB1_UPDT ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && (ireq.valid) )
1995	{
1996	m_cost_ins_tlb_miss_frz++;
1997	}
1998
1999	// invalidate cache
2000	if( (( r_icache_fsm_save == ICACHE_MISS_WAIT ) \|\| ( r_icache_fsm_save == ICACHE_MISS_UPDT ) /*\|\|
2001	( r_icache_fsm_save == ICACHE_UNC_WAIT )*/ ) &&
2002	((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_icache_words<<2)-1))) )
2003	{
2004	r_icache_inval_rsp = true;
2005	r_tgt_icache_rsp = false;
2006	}
2007	else
2008	{
2009	r_tgt_icache_rsp = r_icache.inval(r_tgt_addr.read());
2010	}
2011	r_tgt_icache_req = false;
2012	r_icache_fsm = r_icache_fsm_save;
2013	break;
2014	}
2015	/////////////////////////
2016	case ICACHE_TLB_CC_INVAL:
2017	{
2018	/* activity counter */
2019	if ( (( r_icache_fsm_save == ICACHE_BIS ) \|\|( r_icache_fsm_save == ICACHE_MISS_WAIT ) \|\| ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) )
2020	{
2021	m_cost_ins_miss_frz++;
2022	}
2023	if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_READ ) \|\|
2024	( r_icache_fsm_save == ICACHE_TLB1_WRITE ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) \|\|
2025	( r_icache_fsm_save == ICACHE_TLB1_UPDT ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && (ireq.valid) )
2026	{
2027	m_cost_ins_tlb_miss_frz++;
2028	}
2029
2030	if ( r_itlb_inval_req ) break;
2031	// invalidate cache
2032	if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_READ ) \|\|
2033	/* ( r_icache_fsm_save == ICACHE_TLB1_WRITE )\|\| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) \|\|*/
2034	( r_icache_fsm_save == ICACHE_TLB1_UPDT ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) &&
2035	(((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2) ) == r_dcache_itlb_inval_line.read()) )
2036	{
2037	r_icache_inval_tlb_rsp = true;
2038	}
2039	else if (((r_icache_fsm_save == ICACHE_BIS)\|\|(r_icache_fsm_save == ICACHE_MISS_WAIT) \|\|
2040	/* (r_icache_fsm_save == ICACHE_UNC_WAIT)\|\|*/(r_icache_fsm_save == ICACHE_MISS_UPDT)) &&
2041	(r_icache_tlb_nline.read() == r_dcache_itlb_inval_line.read()))
2042	{
2043	r_icache_inval_tlb_rsp = true;
2044	}
2045	r_dcache_itlb_inval_req = false;
2046	r_itlb_translation_valid = false;
2047	r_icache_ptba_ok = false;
2048	r_icache_fsm = r_icache_fsm_save;
2049	break;
2050	}
2051	} // end switch r_icache_fsm
2052
2053	#ifdef SOCLIB_MODULE_DEBUG
2054	std::cout << name() << " Instruction Response: " << irsp << std::endl;
2055	#endif
2056
2057	////////////////////////////////////////////////////////////////////////////////////
2058	// INVAL ITLB CHECK FSM
2059	////////////////////////////////////////////////////////////////////////////////////////
2060	switch(r_inval_itlb_fsm) {
2061	/////////////////////
2062	case INVAL_ITLB_IDLE:
2063	{
2064	if ( r_itlb_inval_req )
2065	{
2066	r_ccinval_itlb_way = 0;
2067	r_ccinval_itlb_set = 0;
2068	r_inval_itlb_fsm = INVAL_ITLB_CHECK;
2069	m_cost_ins_tlb_inval_frz++;
2070	}
2071	break;
2072	}
2073	////////////////////////////
2074	case INVAL_ITLB_CHECK:
2075	{
2076	m_cost_ins_tlb_inval_frz++;
2077
2078	size_t way = r_ccinval_itlb_way;
2079	size_t set = r_ccinval_itlb_set;
2080	bool end = false;
2081	bool tlb_hit = icache_tlb.cccheck(r_dcache_itlb_inval_line.read(), way, set, &way, &set, &end);
2082
2083	if ( tlb_hit )
2084	{
2085	r_ccinval_itlb_way = way;
2086	r_ccinval_itlb_set = set;
2087	r_itlb_cc_check_end = end;
2088	r_inval_itlb_fsm = INVAL_ITLB_INVAL;
2089	m_cpt_ins_tlb_inval++;
2090	}
2091	else
2092	{
2093	r_inval_itlb_fsm = INVAL_ITLB_CLEAR;
2094	}
2095	break;
2096	}
2097	/////////////////////////
2098	case INVAL_ITLB_INVAL:
2099	{
2100	m_cost_ins_tlb_inval_frz++;
2101
2102	icache_tlb.ccinval(r_ccinval_itlb_way, r_ccinval_itlb_set);
2103
2104	if ( !r_itlb_cc_check_end )
2105	{
2106	r_inval_itlb_fsm = INVAL_ITLB_CHECK;
2107	}
2108	else
2109	{
2110	r_inval_itlb_fsm = INVAL_ITLB_CLEAR;
2111	}
2112	break;
2113	}
2114	////////////////////
2115	case INVAL_ITLB_CLEAR:
2116	{
2117	r_itlb_inval_req = false;
2118	r_itlb_cc_check_end = false;
2119	r_ccinval_itlb_way = 0;
2120	r_ccinval_itlb_set = 0;
2121	r_inval_itlb_fsm = INVAL_ITLB_IDLE;
2122	m_cost_ins_tlb_inval_frz++;
2123	break;
2124	}
2125	} // end switch r_inval_itlb_fsm
2126
2127	////////////////////////////////////////////////////////////////////////////////////
2128	// DCACHE FSM
2129	//
2130	// Both the Cacheability Table, and the MMU cached bit are used to define
2131	// the cacheability.
2132	//
2133	// There is 14 mutually exclusive conditions to exit the IDLE state.
2134	// Seven configurations corresponding to an XTN request from processor:
2135	// - Context switch => CTXT_SWITCH state
2136	// - Flush dcache => DCACHE_FLUSH state
2137	// - Flush icache => ICACHE_FLUSH state
2138	// - Invalidate a dtlb entry => DTLB_INVAL state
2139	// - Invalidate a itlb entry => ITLB_INVAL state
2140	// - Invalidate a dcache line => DCACHE_INVAL state
2141	// - Invalidate a icache line => ICACHE_INVAL state
2142	// Seven configurations corresponding to various read miss or write requests:
2143	// - TLB miss(in case hit_p miss) => TLB1_READ state
2144	// - TLB miss(in case hit_p hit) => TLB2_READ state
2145	// - Hit in TLB but VPN changed => BIS state
2146	// - Cached read miss => MISS_REQ state
2147	// - Uncache read miss => UNC_REQ state
2148	// - Write hit => WRITE_UPDT state
2149	// - Write miss => WRITE_REQ
2150	//
2151	// The r_vci_rsp_data_error flip-flop is set by the VCI_RSP controller and reset
2152	// by DCACHE-FSM when its state is in DCACHE_ERROR.
2153	//---------------------------------------------------------------------
2154	// Data TLB:
2155	//
2156	// - int ET (00: unmapped; 01: unused or PTD)
2157	// (10: PTE new; 11: PTE old )
2158	// - bool cachable (cached bit)
2159	// - bool writable (writable bit)
2160	// - bool executable (** not used alwayse false)
2161	// - bool user (access in user mode allowed)
2162	// - bool global (PTE not invalidated by a TLB flush)
2163	// - bool dirty (page has been modified)
2164	// - uint32_t vpn (virtual page number)
2165	// - uint32_t ppn (physical page number)
2166	////////////////////////////////////////////////////////////////////////////////////////
2167
2168	switch (r_dcache_fsm) {
2169	//////////////////////
2170	case DCACHE_WRITE_REQ:
2171	{
2172	// external cache invalidate request
2173	if ( r_tgt_dcache_req )
2174	{
2175	r_dcache_fsm = DCACHE_CC_CHECK;
2176	r_dcache_fsm_save = r_dcache_fsm;
2177	break;
2178	}
2179
2180	// try to post the write request in the write buffer
2181	if ( !r_dcache_write_req ) // no previous write transaction
2182	{
2183	if ( r_wbuf.wok(r_dcache_paddr_save) ) // write request in the same cache line
2184	{
2185	r_wbuf.write(r_dcache_paddr_save.read(), r_dcache_be_save.read(), r_dcache_wdata_save);
2186	// closing the write packet if uncached
2187	if ( !r_dcache_cached_save )
2188	{
2189	r_dcache_write_req = true;
2190	}
2191	}
2192	else
2193	{ // close the write packet if write request not in the same cache line
2194	r_dcache_write_req = true;
2195	m_cost_write_frz++;
2196	break; // posting not possible : stay in DCACHE_WRITEREQ state
2197	}
2198	}
2199	else // previous write transaction not completed
2200	{
2201	m_cost_write_frz++;
2202	break; // posting not possible : stay in DCACHE_WRITEREQ state
2203	}
2204
2205	// close the write packet if the next processor request is not a write
2206	if ( !dreq.valid \|\| (dreq.type != iss_t::DATA_WRITE))
2207	{
2208	r_dcache_write_req = true;
2209	}
2210
2211	// The next state and the processor request parameters are computed
2212	// as in the DCACHE_IDLE state (see below ...)
2213	}
2214	/////////////////
2215	case DCACHE_IDLE:
2216	{
2217	// external cache invalidate request
2218	if ( r_tgt_dcache_req )
2219	{
2220	r_dcache_fsm = DCACHE_CC_CHECK;
2221	r_dcache_fsm_save = DCACHE_IDLE;
2222	break;
2223	}
2224
2225	// ins tlb cleanup
2226	if ( r_dcache_itlb_cleanup_req )
2227	{
2228	r_dcache_fsm = DCACHE_ITLB_CLEANUP;
2229	break;
2230	}
2231	// ins tlb miss
2232	if ( r_itlb_read_dcache_req )
2233	{
2234	if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
2235	data_t rsp_itlb_miss;
2236	data_t rsp_itlb_ppn;
2237
2238	bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
2239	if ( r_itlb_k_read_dcache && itlb_hit_dcache )
2240	{
2241	r_itlb_k_read_dcache = false;
2242	bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
2243	assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
2244	}
2245
2246	m_cpt_dcache_data_read += m_dcache_ways;
2247	m_cpt_dcache_dir_read += m_dcache_ways;
2248
2249	if ( itlb_hit_dcache ) // ins TLB request hits in data cache
2250	{
2251	if (!((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT)) m_cpt_ins_tlb_hit_dcache++;
2252	r_dcache_rsp_itlb_miss = rsp_itlb_miss;
2253	r_dcache_rsp_itlb_ppn = rsp_itlb_ppn;
2254	r_itlb_read_dcache_req = false;
2255	r_dcache_fsm = DCACHE_IDLE;
2256
2257	// set TLB bit if it's a PTE
2258	if ( !((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT) )
2259	{
2260	r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
2261	}
2262	}
2263	else // ins TLB request miss in data cache
2264	{
2265	r_dcache_itlb_read_req = true;
2266	r_dcache_fsm = DCACHE_ITLB_READ;
2267	}
2268	}
2269	else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit
2270	{
2271	r_dcache_itlb_ll_acc_req = true;
2272	r_dcache_fsm = DCACHE_ITLB_LL_WAIT;
2273	m_cpt_dcache_data_write++;
2274	}
2275	else if (dreq.valid)
2276	{
2277	pte_info_t dcache_pte_info;
2278	int xtn_opcod = (int)dreq.addr/4;
2279	paddr_t tlb_dpaddr = 0; // physical address obtained from TLB
2280	paddr_t spc_dpaddr = 0; // physical adress obtained from PPN_save (speculative)
2281	bool dcache_hit_t = false; // hit on 4Kilo TLB
2282	bool dcache_hit_x = false; // VPN unmodified (can use spc_dpaddr)
2283	bool dcache_hit_p = false; // PTP unmodified (can skip first level page table walk)
2284	bool dcache_hit_c = false; // Cache hit
2285	bool dcache_cached = false; // cacheable access (read or write)
2286	size_t dcache_tlb_way = 0; // selected way (in case of cache hit)
2287	size_t dcache_tlb_set = 0; // selected set (Y field in address)
2288	data_t dcache_rdata = 0; // read data
2289	paddr_t dcache_tlb_nline = 0; // TLB NLINE
2290
2291	m_cpt_dcache_data_read += m_dcache_ways;
2292	m_cpt_dcache_dir_read += m_dcache_ways;
2293
2294	// Decoding READ XTN requests from processor
2295	// They are executed in this DCACHE_IDLE state
2296
2297	if (dreq.type == iss_t::XTN_READ)
2298	{
2299	switch(xtn_opcod) {
2300	case iss_t::XTN_INS_ERROR_TYPE:
2301	drsp.rdata = (uint32_t)r_icache_error_type;
2302	r_icache_error_type = MMU_NONE;
2303	drsp.valid = true;
2304	drsp.error = false;
2305	break;
2306	case iss_t::XTN_DATA_ERROR_TYPE:
2307	drsp.rdata = (uint32_t)r_dcache_error_type;
2308	r_dcache_error_type = MMU_NONE;
2309	drsp.valid = true;
2310	drsp.error = false;
2311	break;
2312	case iss_t::XTN_INS_BAD_VADDR:
2313	drsp.rdata = (uint32_t)r_icache_bad_vaddr;
2314	drsp.valid = true;
2315	drsp.error = false;
2316	break;
2317	case iss_t::XTN_DATA_BAD_VADDR:
2318	drsp.rdata = (uint32_t)r_dcache_bad_vaddr;
2319	drsp.valid = true;
2320	drsp.error = false;
2321	break;
2322	case iss_t::XTN_PTPR:
2323	drsp.rdata = (uint32_t)r_mmu_ptpr;
2324	drsp.valid = true;
2325	drsp.error = false;
2326	break;
2327	case iss_t::XTN_TLB_MODE:
2328	drsp.rdata = (uint32_t)r_mmu_mode;
2329	drsp.valid = true;
2330	drsp.error = false;
2331	break;
2332	case iss_t::XTN_MMU_PARAMS:
2333	drsp.rdata = (uint32_t)r_mmu_params;
2334	drsp.valid = true;
2335	drsp.error = false;
2336	break;
2337	case iss_t::XTN_MMU_RELEASE:
2338	drsp.rdata = (uint32_t)r_mmu_release;
2339	drsp.valid = true;
2340	drsp.error = false;
2341	break;
2342	case iss_t::XTN_MMU_WORD_LO:
2343	drsp.rdata = (uint32_t)r_mmu_word_lo;
2344	drsp.valid = true;
2345	drsp.error = false;
2346	break;
2347	case iss_t::XTN_MMU_WORD_HI:
2348	drsp.rdata = (uint32_t)r_mmu_word_hi;
2349	drsp.valid = true;
2350	drsp.error = false;
2351	break;
2352	default:
2353	r_dcache_error_type = MMU_READ_UNDEFINED_XTN;
2354	r_dcache_bad_vaddr = dreq.addr;
2355	drsp.valid = true;
2356	drsp.error = true;
2357	break;
2358	}
2359	r_dcache_fsm = DCACHE_IDLE;
2360	break;
2361	}
2362
2363	// Decoding WRITE XTN requests from processor
2364	// If there is no privilege violation, they are not executed in this DCACHE_IDLE state,
2365	// but in the next state, because they generally require access to the caches or the TLBs
2366
2367	if (dreq.type == iss_t::XTN_WRITE)
2368	{
2369	drsp.valid = false;
2370	drsp.error = false;
2371	drsp.rdata = 0;
2372	r_dcache_wdata_save = dreq.wdata;
2373	switch(xtn_opcod) {
2374
2375	case iss_t::XTN_PTPR: // context switch : checking the kernel mode
2376	// both instruction & data TLBs must be flushed
2377	if ((dreq.mode == iss_t::MODE_HYPER) \|\| (dreq.mode == iss_t::MODE_KERNEL))
2378	{
2379	r_mmu_ptpr = dreq.wdata;
2380	r_icache_error_type = MMU_NONE;
2381	r_dcache_error_type = MMU_NONE;
2382	r_dcache_type_save = dreq.addr/4;
2383	r_dcache_xtn_req = true;
2384	r_dcache_fsm = DCACHE_CTXT_SWITCH;
2385	}
2386	else
2387	{
2388	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2389	r_dcache_bad_vaddr = dreq.addr;
2390	drsp.valid = true;
2391	drsp.error = true;
2392	r_dcache_fsm = DCACHE_IDLE;
2393	}
2394	break;
2395
2396	case iss_t::XTN_TLB_MODE: // modifying TLBs mode : checking the kernel mode
2397	if ((dreq.mode == iss_t::MODE_HYPER) \|\| (dreq.mode == iss_t::MODE_KERNEL))
2398	{
2399	r_mmu_mode = (int)dreq.wdata;
2400	drsp.valid = true;
2401	}
2402	else
2403	{
2404	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2405	r_dcache_bad_vaddr = dreq.addr;
2406	drsp.valid = true;
2407	drsp.error = true;
2408	}
2409	r_dcache_fsm = DCACHE_IDLE;
2410	break;
2411
2412	case iss_t::XTN_DTLB_INVAL: // checking the kernel mode
2413	if ((dreq.mode == iss_t::MODE_HYPER) \|\| (dreq.mode == iss_t::MODE_KERNEL))
2414	{
2415	r_dcache_fsm = DCACHE_DTLB_INVAL;
2416	}
2417	else
2418	{
2419	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2420	r_dcache_bad_vaddr = dreq.addr;
2421	drsp.valid = true;
2422	drsp.error = true;
2423	r_dcache_fsm = DCACHE_IDLE;
2424	}
2425	break;
2426
2427	case iss_t::XTN_ITLB_INVAL: // checking the kernel mode
2428	if ((dreq.mode == iss_t::MODE_HYPER) \|\| (dreq.mode == iss_t::MODE_KERNEL))
2429	{
2430	r_dcache_xtn_req = true;
2431	r_dcache_type_save = dreq.addr/4;
2432	r_dcache_fsm = DCACHE_ITLB_INVAL;
2433	}
2434	else
2435	{
2436	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2437	r_dcache_bad_vaddr = dreq.addr;
2438	drsp.valid = true;
2439	drsp.error = true;
2440	r_dcache_fsm = DCACHE_IDLE;
2441	}
2442	break;
2443
2444	case iss_t::XTN_DCACHE_INVAL: // cache inval can be executed in user mode.
2445	r_dcache_fsm = DCACHE_DCACHE_INVAL;
2446	break;
2447
2448	case iss_t::XTN_MMU_DCACHE_PA_INV: // cache inval can be executed in user mode.
2449	r_dcache_fsm = DCACHE_DCACHE_INVAL_PA;
2450	break;
2451
2452	case iss_t::XTN_DCACHE_FLUSH: // cache flush can be executed in user mode.
2453	r_dcache_type_save = dreq.addr/4;
2454	r_dcache_xtn_req = true;
2455	r_dcache_way = 0;
2456	r_dcache_set = 0;
2457	r_dcache_fsm = DCACHE_DCACHE_FLUSH;
2458	break;
2459
2460	case iss_t::XTN_ICACHE_INVAL: // cache inval can be executed in user mode.
2461	r_dcache_type_save = dreq.addr/4;
2462	r_dcache_xtn_req = true;
2463	r_dcache_fsm = DCACHE_ICACHE_INVAL;
2464	break;
2465
2466	case iss_t::XTN_MMU_ICACHE_PA_INV: // cache inval can be executed in user mode.
2467	r_dcache_type_save = dreq.addr/4;
2468	r_dcache_xtn_req = true;
2469	r_dcache_fsm = DCACHE_ICACHE_INVAL_PA;
2470	break;
2471
2472	case iss_t::XTN_ICACHE_FLUSH: // cache flush can be executed in user mode.
2473	r_dcache_type_save = dreq.addr/4;
2474	r_dcache_xtn_req = true;
2475	r_dcache_fsm = DCACHE_ICACHE_FLUSH;
2476	break;
2477
2478	case iss_t::XTN_SYNC: // cache synchronization can be executed in user mode.
2479	if (r_wbuf.rok())
2480	{
2481	r_dcache_fsm = DCACHE_DCACHE_SYNC;
2482	}
2483	else
2484	{
2485	drsp.valid = true;
2486	r_dcache_fsm = DCACHE_IDLE;
2487	}
2488	break;
2489
2490	case iss_t::XTN_MMU_WORD_LO: // modifying MMU misc registers
2491	if ((dreq.mode == iss_t::MODE_HYPER) \|\| (dreq.mode == iss_t::MODE_KERNEL))
2492	{
2493	r_mmu_word_lo = (int)dreq.wdata;
2494	drsp.valid = true;
2495	}
2496	else
2497	{
2498	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2499	r_dcache_bad_vaddr = dreq.addr;
2500	drsp.valid = true;
2501	drsp.error = true;
2502	}
2503	r_dcache_fsm = DCACHE_IDLE;
2504	break;
2505
2506	case iss_t::XTN_MMU_WORD_HI: // modifying MMU misc registers
2507	if ((dreq.mode == iss_t::MODE_HYPER) \|\| (dreq.mode == iss_t::MODE_KERNEL))
2508	{
2509	r_mmu_word_hi = (int)dreq.wdata;
2510	drsp.valid = true;
2511	}
2512	else
2513	{
2514	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2515	r_dcache_bad_vaddr = dreq.addr;
2516	drsp.valid = true;
2517	drsp.error = true;
2518	}
2519	r_dcache_fsm = DCACHE_IDLE;
2520	break;
2521
2522	case iss_t::XTN_ICACHE_PREFETCH:
2523	case iss_t::XTN_DCACHE_PREFETCH:
2524	drsp.valid = true;
2525	drsp.error = false;
2526	break;
2527
2528	default:
2529	r_dcache_error_type = MMU_WRITE_UNDEFINED_XTN;
2530	r_dcache_bad_vaddr = dreq.addr;
2531	drsp.valid = true;
2532	drsp.error = true;
2533	r_dcache_fsm = DCACHE_IDLE;
2534	break;
2535	} // end switch xtn_opcod
2536
2537	break;
2538	} // end if XTN_WRITE
2539
2540	// Evaluating dcache_hit_t, dcache_hit_x, dcache_hit_p, dcache_hit_c,
2541	// dcache_pte_info, dcache_tlb_way, dcache_tlb_set & dpaddr & cacheability
2542	// - If MMU activated : cacheability is defined by the cachable bit in the TLB
2543	// - If MMU not activated : cacheability is defined by the segment table.
2544
2545	if ( !(r_mmu_mode.read() & DATA_TLB_MASK) ) // MMU not activated
2546	{
2547	dcache_hit_t = true;
2548	dcache_hit_x = true;
2549	dcache_hit_p = true;
2550	tlb_dpaddr = dreq.addr;
2551	spc_dpaddr = dreq.addr;
2552	dcache_cached = m_cacheability_table[dreq.addr] &&
2553	((dreq.type != iss_t::DATA_LL) && (dreq.type != iss_t::DATA_SC) &&
2554	(dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));
2555	}
2556	else // MMU activated
2557	{
2558	m_cpt_data_tlb_read++;
2559	dcache_hit_t = dcache_tlb.cctranslate(dreq.addr, &tlb_dpaddr, &dcache_pte_info,
2560	&dcache_tlb_nline, &dcache_tlb_way, &dcache_tlb_set);
2561	dcache_hit_x = (((vaddr_t)r_dcache_vpn_save << PAGE_K_NBITS) == (dreq.addr & ~PAGE_K_MASK)) && r_dtlb_translation_valid;
2562	dcache_hit_p = (((dreq.addr >> PAGE_M_NBITS) == r_dcache_id1_save) && r_dcache_ptba_ok );
2563	spc_dpaddr = ((paddr_t)r_dcache_ppn_save << PAGE_K_NBITS) \| (paddr_t)((dreq.addr & PAGE_K_MASK));
2564	dcache_cached = dcache_pte_info.c &&
2565	((dreq.type != iss_t::DATA_LL) && (dreq.type != iss_t::DATA_SC) &&
2566	(dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));
2567	}
2568
2569	if ( !(r_mmu_mode.read() & DATA_CACHE_MASK) ) // cache not actived
2570	{
2571	dcache_cached = false;
2572	}
2573
2574	// dcache_hit_c & dcache_rdata
2575	if ( dcache_cached ) // using speculative physical address for cached access
2576	{
2577	dcache_hit_c = r_dcache.read(spc_dpaddr, &dcache_rdata);
2578	}
2579	else // using actual physical address for uncached access
2580	{
2581	dcache_hit_c = false;
2582	}
2583
2584	if ( r_mmu_mode.read() & DATA_TLB_MASK )
2585	{
2586	// Checking access rights
2587	if ( dcache_hit_t )
2588	{
2589	if (!dcache_pte_info.u && (dreq.mode == iss_t::MODE_USER))
2590	{
2591	if ((dreq.type == iss_t::DATA_READ)\|\|(dreq.type == iss_t::DATA_LL))
2592	{
2593	r_dcache_error_type = MMU_READ_PRIVILEGE_VIOLATION;
2594	}
2595	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
2596	{
2597	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2598	}
2599	r_dcache_bad_vaddr = dreq.addr;
2600	drsp.valid = true;
2601	drsp.error = true;
2602	drsp.rdata = 0;
2603	r_dcache_fsm = DCACHE_IDLE;
2604	break;
2605	}
2606	if (!dcache_pte_info.w && ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC)))
2607	{
2608	r_dcache_error_type = MMU_WRITE_ACCES_VIOLATION;
2609	r_dcache_bad_vaddr = dreq.addr;
2610	drsp.valid = true;
2611	drsp.error = true;
2612	drsp.rdata = 0;
2613	r_dcache_fsm = DCACHE_IDLE;
2614	break;
2615	}
2616	}
2617
2618	// update LRU, save ppn, vpn and page type
2619	if ( dcache_hit_t ) {
2620	dcache_tlb.setlru(dcache_tlb_way,dcache_tlb_set);
2621	r_dcache_ppn_save = tlb_dpaddr >> PAGE_K_NBITS;
2622	r_dcache_vpn_save = dreq.addr >> PAGE_K_NBITS;
2623	r_dcache_tlb_nline = dcache_tlb_nline;
2624	r_dtlb_translation_valid = true;
2625	}
2626	else
2627	{
2628	r_dtlb_translation_valid = false;
2629	}
2630
2631	} // end if MMU activated
2632
2633	// compute next state
2634	if ( !dcache_hit_p && !dcache_hit_t ) // TLB miss
2635	{
2636	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
2637	r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
2638	m_cpt_data_tlb_miss++;
2639	m_cost_data_tlb_miss_frz++;
2640	}
2641	else if ( dcache_hit_p && !dcache_hit_t ) // TLB Miss with possibility of bypass first level page
2642	{
2643	// walk page table level 2
2644	r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save \|
2645	(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
2646	r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
2647	m_cpt_data_tlb_miss++;
2648	m_cost_data_tlb_miss_frz++;
2649	}
2650	else if ( dcache_hit_t && !dcache_hit_x && dcache_cached )// cached access with an ucorrect speculative physical address
2651	{
2652	r_dcache_hit_p_save = dcache_hit_p;
2653	r_dcache_fsm = DCACHE_BIS;
2654	m_cost_data_tlb_miss_frz++;
2655	}
2656	else // cached or uncached access with a correct speculative physical address
2657	{
2658	switch( dreq.type ) {
2659	case iss_t::DATA_READ:
2660	case iss_t::DATA_LL:
2661	case iss_t::DATA_SC:
2662	m_cpt_read++;
2663	if ( dcache_hit_c )
2664	{
2665	r_dcache_fsm = DCACHE_IDLE;
2666	drsp.valid = true;
2667	drsp.rdata = dcache_rdata;
2668	}
2669	else
2670	{
2671	if ( dcache_cached )
2672	{
2673	r_dcache_miss_req = true;
2674	r_dcache_fsm = DCACHE_MISS_WAIT;
2675	m_cpt_data_miss++;
2676	m_cost_data_miss_frz++;
2677	}
2678	else
2679	{
2680	if (dreq.type == iss_t::DATA_SC &&
2681	(r_mmu_mode.read() & DATA_TLB_MASK) &&
2682	!dcache_pte_info.d)
2683	{
2684	/* dirty bit update */
2685	m_cpt_data_tlb_update_dirty++;
2686	m_cost_data_tlb_update_dirty_frz++;
2687	if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) ) // 2M page size, one level page table
2688	{
2689	r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) \| PTE_D_MASK;
2690	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
2691	r_dcache_tlb_ll_dirty_req = true;
2692	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2693	}
2694	else // 4k page size, two levels page table
2695	{
2696	if (dcache_hit_p)
2697	{
2698	r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) \| PTE_D_MASK;
2699	r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save \| (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
2700	r_dcache_tlb_ll_dirty_req = true;
2701	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2702	}
2703	else // get PTBA to calculate the physical address of PTE
2704	{
2705	r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) \| PTE_D_MASK;
2706	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
2707	r_dcache_tlb_ptba_read = true;
2708	r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
2709	}
2710	}
2711	}
2712	else
2713	{
2714	r_dcache_unc_req = true;
2715	r_dcache_fsm = DCACHE_UNC_WAIT;
2716	m_cpt_unc_read++;
2717	m_cost_unc_read_frz++;
2718	}
2719	}
2720	}
2721	break;
2722	/*
2723	case iss_t::DATA_READ:
2724	m_cpt_read++;
2725	if ( dcache_hit_c )
2726	{
2727	r_dcache_buf_unc_valid = false;
2728	r_dcache_fsm = DCACHE_IDLE;
2729	drsp.valid = true;
2730	drsp.rdata = dcache_rdata;
2731	}
2732	else
2733	{
2734	if ( dcache_cached )
2735	{
2736	r_dcache_miss_req = true;
2737	r_dcache_fsm = DCACHE_MISS_WAIT;
2738	m_cpt_data_miss++;
2739	m_cost_data_miss_frz++;
2740	}
2741	else
2742	{
2743	r_dcache_unc_req = true;
2744	r_dcache_fsm = DCACHE_UNC_WAIT;
2745	m_cpt_unc_read++;
2746	m_cost_unc_read_frz++;
2747	}
2748	}
2749	break;
2750	case iss_t::DATA_LL:
2751	if (r_dcache_llsc_reserved && (r_dcache_llsc_addr_save == tlb_dpaddr) && r_dcache_buf_unc_valid)
2752	{
2753	r_dcache_buf_unc_valid = false;
2754	r_dcache_fsm = DCACHE_IDLE;
2755	drsp.valid = true;
2756	drsp.rdata = dcache_rdata;
2757	}
2758	else
2759	{
2760	r_dcache_llsc_reserved = true;
2761	r_dcache_llsc_addr_save = tlb_dpaddr;
2762	r_dcache_unc_req = true;
2763	r_dcache_fsm = DCACHE_UNC_WAIT;
2764	}
2765	break;
2766	case iss_t::DATA_SC:
2767	if (r_dcache_llsc_reserved && (r_dcache_llsc_addr_save == tlb_dpaddr))
2768	{
2769	r_dcache_llsc_reserved = false;
2770	r_dcache_unc_req = true;
2771	r_dcache_fsm = DCACHE_UNC_WAIT;
2772	}
2773	else
2774	{
2775	if ( r_dcache_buf_unc_valid )
2776	{
2777	r_dcache_llsc_reserved = false;
2778	r_dcache_buf_unc_valid = false;
2779	drsp.valid = true;
2780	drsp.rdata = dcache_rdata;
2781	}
2782	r_dcache_fsm = DCACHE_IDLE;
2783	}
2784	break;
2785	*/
2786	case iss_t::DATA_WRITE:
2787	m_cpt_write++;
2788	if ( dcache_cached ) m_cpt_write_cached++;
2789	m_cost_write_frz++;
2790	if ( dcache_hit_c && dcache_cached ) // cache update required
2791	{
2792	r_dcache_fsm = DCACHE_WRITE_UPDT;
2793	}
2794	else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) ) // dirty bit update required
2795	{
2796	m_cpt_data_tlb_update_dirty++;
2797	m_cost_data_tlb_update_dirty_frz++;
2798	if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) ) // 2M page size, one level page table
2799	{
2800	r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) \| PTE_D_MASK;
2801	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
2802	r_dcache_tlb_ll_dirty_req = true;
2803	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2804	}
2805	else // 4k page size, two levels page table
2806	{
2807	if (dcache_hit_p)
2808	{
2809	r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) \| PTE_D_MASK;
2810	r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save \| (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
2811	r_dcache_tlb_ll_dirty_req = true;
2812	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2813	}
2814	else // get PTBA to calculate the physical address of PTE
2815	{
2816	r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) \| PTE_D_MASK;
2817	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
2818	r_dcache_tlb_ptba_read = true;
2819	r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
2820	}
2821	}
2822	}
2823	else // no cache update, not dirty bit update
2824	{
2825	r_dcache_fsm = DCACHE_WRITE_REQ;
2826	drsp.valid = true;
2827	drsp.rdata = 0;
2828	}
2829	break;
2830	default:
2831	break;
2832	} // end switch dreq.type
2833	} // end if next states
2834
2835	// save values for the next states
2836	r_dcache_paddr_save = tlb_dpaddr;
2837	r_dcache_type_save = dreq.type;
2838	r_dcache_wdata_save = dreq.wdata;
2839	r_dcache_be_save = dreq.be;
2840	r_dcache_rdata_save = dcache_rdata;
2841	r_dcache_cached_save = dcache_cached;
2842	r_dcache_dirty_save = dcache_pte_info.d;
2843	r_dcache_tlb_set_save = dcache_tlb_set;
2844	r_dcache_tlb_way_save = dcache_tlb_way;
2845
2846	} // end if dreq.valid
2847	else
2848	{
2849	r_dcache_fsm = DCACHE_IDLE;
2850	}
2851
2852	// processor request are not accepted in the WRITE_REQ state
2853	// when the write buffer is not writeable
2854
2855	if ((r_dcache_fsm == DCACHE_WRITE_REQ) &&
2856	(r_dcache_write_req \|\| !r_wbuf.wok(r_dcache_paddr_save)))
2857	{
2858	drsp.valid = false;
2859	}
2860	break;
2861	}
2862	/////////////////
2863	case DCACHE_BIS:
2864	{
2865	// external cache invalidate request
2866	if ( r_tgt_dcache_req )
2867	{
2868	r_dcache_fsm = DCACHE_CC_CHECK;
2869	r_dcache_fsm_save = r_dcache_fsm;
2870	if ( dreq.valid ) m_cost_data_miss_frz++;
2871	break;
2872	}
2873
2874	// Using tlb entry is invalidated
2875	if ( r_dcache_inval_tlb_rsp )
2876	{
2877	r_dcache_inval_tlb_rsp = false;
2878	r_dcache_fsm = DCACHE_IDLE;
2879	if ( dreq.valid ) m_cost_data_miss_frz++;
2880	break;
2881	}
2882
2883	data_t dcache_rdata = 0;
2884	bool dcache_hit_c = false;
2885	bool dcache_hit_t = false;
2886	paddr_t tlb_dpaddr = 0;
2887
2888	dcache_hit_t = dcache_tlb.translate(dreq.addr, &tlb_dpaddr);
2889
2890	if ( (tlb_dpaddr == r_dcache_paddr_save.read()) && dreq.valid && dcache_hit_t )
2891	{
2892	// acces always cached in this state
2893	dcache_hit_c = r_dcache.read(r_dcache_paddr_save, &dcache_rdata);
2894
2895	if ( dreq.type == iss_t::DATA_READ ) // cached read
2896	{
2897	m_cpt_read++;
2898	if ( !dcache_hit_c )
2899	{
2900	r_dcache_miss_req = true;
2901	r_dcache_fsm = DCACHE_MISS_WAIT;
2902	m_cpt_data_miss++;
2903	m_cost_data_miss_frz++;
2904	}
2905	else
2906	{
2907	r_dcache_fsm = DCACHE_IDLE;
2908	}
2909	drsp.valid = dcache_hit_c;
2910	drsp.error = false;
2911	drsp.rdata = dcache_rdata;
2912	}
2913	else // cached write
2914	{
2915	m_cpt_write++;
2916	m_cpt_write_cached++;
2917	if ( dcache_hit_c ) // cache update required
2918	{
2919	r_dcache_rdata_save = dcache_rdata;
2920	r_dcache_fsm = DCACHE_WRITE_UPDT;
2921	}
2922	else if (!r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK)) // dirty bit update required
2923	{
2924	m_cpt_data_tlb_update_dirty++;
2925	m_cost_data_tlb_update_dirty_frz++;
2926	if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
2927	{
2928	r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) \| PTE_D_MASK;
2929	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
2930	r_dcache_tlb_ll_dirty_req = true;
2931	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2932	}
2933	else
2934	{
2935	if (r_dcache_hit_p_save)
2936	{
2937	r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) \| PTE_D_MASK;
2938	r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save\|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
2939	r_dcache_tlb_ll_dirty_req = true;
2940	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2941	}
2942	else
2943	{
2944	r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) \| PTE_D_MASK;
2945	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
2946	r_dcache_tlb_ptba_read = true;
2947	r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
2948	}
2949	}
2950	}
2951	else // no cache update, not dirty bit update
2952	{
2953	r_dcache_fsm = DCACHE_WRITE_REQ;
2954	drsp.valid = true;
2955	drsp.rdata = 0;
2956	}
2957	}
2958	}
2959	else
2960	{
2961	drsp.valid = false;
2962	drsp.error = false;
2963	drsp.rdata = 0;
2964	r_dcache_fsm = DCACHE_IDLE;
2965	}
2966	break;
2967	}
2968	//////////////////////////
2969	case DCACHE_LL_DIRTY_WAIT:
2970	{
2971	m_cost_data_tlb_update_dirty_frz++;
2972
2973	// external cache invalidate request
2974	if ( r_tgt_dcache_req )
2975	{
2976	r_dcache_fsm = DCACHE_CC_CHECK;
2977	r_dcache_fsm_save = r_dcache_fsm;
2978	break;
2979	}
2980
2981	if (!r_dcache_tlb_ll_dirty_req)
2982	{
2983	if ( r_vci_rsp_data_error ) // VCI response ko
2984	{
2985	if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
2986	{
2987	r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
2988	}
2989	else
2990	{
2991	r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
2992	}
2993	r_dcache_bad_vaddr = dreq.addr;
2994	r_dcache_fsm = DCACHE_ERROR;
2995
2996	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
2997	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
2998	}
2999	else
3000	{
3001	if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) ) // unmapped
3002	{
3003	if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
3004	{
3005	r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
3006	}
3007	else
3008	{
3009	r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
3010	}
3011	r_dcache_bad_vaddr = dreq.addr;
3012	r_dcache_fsm = DCACHE_ERROR;
3013
3014	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3015	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3016	}
3017	else if ( r_dcache_inval_tlb_rsp )
3018	{
3019	r_dcache_inval_tlb_rsp = false;
3020	r_dcache_fsm = DCACHE_IDLE;
3021	}
3022	else if ( r_dcache_inval_rsp )
3023	{
3024	r_dcache_inval_rsp = false;
3025	r_dcache_fsm = DCACHE_IDLE;
3026	}
3027	else
3028	{
3029	r_dcache_tlb_sc_dirty_req = true;
3030	r_dcache_pte_update = r_dcache_miss_buf[0] \| r_dcache_pte_update.read();
3031	r_dcache_fsm = DCACHE_SC_DIRTY_WAIT;
3032	}
3033	}
3034	}
3035	break;
3036	}
3037	//////////////////////////
3038	case DCACHE_SC_DIRTY_WAIT:
3039	{
3040	m_cost_data_tlb_update_dirty_frz++;
3041	// external cache invalidate request
3042	if ( r_tgt_dcache_req )
3043	{
3044	r_dcache_fsm = DCACHE_CC_CHECK;
3045	r_dcache_fsm_save = r_dcache_fsm;
3046	break;
3047	}
3048
3049	if ( !r_dcache_tlb_sc_dirty_req )
3050	{
3051	if ( r_vci_rsp_data_error ) // VCI response ko
3052	{
3053	if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
3054	{
3055	r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
3056	}
3057	else
3058	{
3059	r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
3060	}
3061	r_dcache_bad_vaddr = dreq.addr;
3062	r_dcache_fsm = DCACHE_ERROR;
3063
3064	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3065	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3066	}
3067	else
3068	{
3069	// Using tlb entry is invalidated
3070	if ( r_dcache_inval_tlb_rsp )
3071	{
3072	r_dcache_inval_tlb_rsp = false;
3073	r_dcache_fsm = DCACHE_IDLE;
3074	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
3075	}
3076	else if ( r_dcache_inval_rsp )
3077	{
3078	r_dcache_inval_rsp = false;
3079	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
3080	r_dcache_fsm = DCACHE_IDLE;
3081	}
3082	else if ( r_dcache_tlb_sc_fail )
3083	{
3084	r_dcache_tlb_ll_dirty_req = true;
3085	r_dcache_tlb_sc_fail = false;
3086	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
3087	m_cpt_data_tlb_update_dirty++;
3088	}
3089	else
3090	{
3091	/*
3092	* SC succeeded, but has updated the cache and
3093	* invalidated the TLB entry. Redo the translation
3094	*/
3095	r_dcache_fsm = DCACHE_IDLE;
3096	}
3097	}
3098	}
3099	break;
3100	}
3101	////////////////////////////
3102	case DCACHE_DTLB1_READ_CACHE:
3103	{
3104	m_cost_data_tlb_miss_frz++;
3105
3106	// external cache invalidate request
3107	if ( r_tgt_dcache_req )
3108	{
3109	r_dcache_fsm = DCACHE_CC_CHECK;
3110	r_dcache_fsm_save = r_dcache_fsm;
3111	break;
3112	}
3113
3114	// Using tlb entry is invalidated
3115	if ( r_dcache_inval_tlb_rsp )
3116	{
3117	r_dcache_inval_tlb_rsp = false;
3118	r_dcache_fsm = DCACHE_IDLE;
3119	break;
3120	}
3121
3122	data_t tlb_data = 0;
3123	bool write_hit = false;
3124	bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
3125
3126	// DTLB request hit in cache
3127	if ( tlb_hit_cache )
3128	{
3129	if ( !(tlb_data >> PTE_V_SHIFT) ) // unmapped
3130	{
3131	r_dcache_ptba_ok = false;
3132	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3133	{
3134	r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
3135	}
3136	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3137	{
3138	r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
3139	}
3140	r_dcache_bad_vaddr = dreq.addr;
3141	r_dcache_fsm = DCACHE_ERROR;
3142	}
3143	else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
3144	{
3145	r_dcache_ptba_ok = true;
3146	r_dcache_ptba_save = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;
3147	r_dcache_id1_save = dreq.addr >> PAGE_M_NBITS;
3148	r_dcache_tlb_paddr = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
3149	(paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3150	if ( r_dcache_tlb_ptba_read )
3151	{
3152	r_dcache_tlb_ptba_read = false;
3153	r_dcache_tlb_ll_dirty_req = true;
3154	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
3155	m_cpt_dcache_data_write++;
3156	m_cost_data_tlb_update_dirty_frz++;
3157	}
3158	else
3159	{
3160	r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
3161	}
3162	}
3163	else // PTE
3164	{
3165	m_cpt_data_tlb_hit_dcache++;
3166	r_dcache_ptba_ok = false;
3167	if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
3168	{
3169	if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
3170	{
3171	r_dcache_pte_update = tlb_data;
3172	r_dcache_fsm = DCACHE_TLB1_UPDT;
3173	}
3174	else
3175	{
3176	r_dcache_pte_update = tlb_data \| PTE_L_MASK;
3177	r_dcache_tlb_ll_acc_req = true;
3178	r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
3179	m_cpt_dcache_data_write++;
3180	m_cpt_data_tlb_update_acc++;
3181	m_cost_data_tlb_update_acc_frz++;
3182	}
3183	}
3184	else // remotely
3185	{
3186	if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
3187	{
3188	r_dcache_pte_update = tlb_data;
3189	r_dcache_fsm = DCACHE_TLB1_UPDT;
3190	}
3191	else
3192	{
3193	r_dcache_pte_update = tlb_data \| PTE_R_MASK;
3194	r_dcache_tlb_ll_acc_req = true;
3195	r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
3196	m_cpt_dcache_data_write++;
3197	m_cpt_data_tlb_update_acc++;
3198	m_cost_data_tlb_update_acc_frz++;
3199	}
3200	}
3201	}
3202	}
3203	else
3204	{
3205	// DTLB request miss in cache and walk page table level 1
3206	r_dcache_tlb_read_req = true;
3207	r_dcache_fsm = DCACHE_TLB1_READ;
3208	}
3209	break;
3210	}
3211	///////////////////////
3212	case DCACHE_TLB1_LL_WAIT:
3213	{
3214	if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
3215	m_cost_data_tlb_update_acc_frz++;
3216	// external cache invalidate request
3217	if ( r_tgt_dcache_req )
3218	{
3219	r_dcache_fsm = DCACHE_CC_CHECK;
3220	r_dcache_fsm_save = r_dcache_fsm;
3221	break;
3222	}
3223
3224	if (!r_dcache_tlb_ll_acc_req)
3225	{
3226	if ( r_vci_rsp_data_error ) // VCI response ko
3227	{
3228	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3229	{
3230	r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
3231	}
3232	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3233	{
3234	r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
3235	}
3236	r_dcache_bad_vaddr = dreq.addr;
3237	r_dcache_fsm = DCACHE_ERROR;
3238
3239	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3240	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3241	}
3242	else
3243	{
3244	if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) ) // unmapped
3245	{
3246	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3247	{
3248	r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
3249	}
3250	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3251	{
3252	r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
3253	}
3254	r_dcache_bad_vaddr = dreq.addr;
3255	r_dcache_fsm = DCACHE_ERROR;
3256
3257	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3258	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3259	}
3260	else if ( r_dcache_inval_tlb_rsp )
3261	{
3262	r_dcache_inval_tlb_rsp = false;
3263	r_dcache_fsm = DCACHE_IDLE;
3264	}
3265	else if ( r_dcache_inval_rsp )
3266	{
3267	r_dcache_inval_rsp = false;
3268	r_dcache_fsm = DCACHE_IDLE;
3269	}
3270	else
3271	{
3272	r_dcache_tlb_sc_acc_req = true;
3273	r_dcache_pte_update = r_dcache_miss_buf[0] \| r_dcache_pte_update.read();
3274	r_dcache_fsm = DCACHE_TLB1_SC_WAIT;
3275	}
3276	}
3277	}
3278	break;
3279	}
3280	///////////////////////
3281	case DCACHE_TLB1_SC_WAIT:
3282	{
3283	if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
3284	m_cost_data_tlb_update_acc_frz++;
3285	// external cache invalidate request
3286	if ( r_tgt_dcache_req )
3287	{
3288	r_dcache_fsm = DCACHE_CC_CHECK;
3289	r_dcache_fsm_save = r_dcache_fsm;
3290	break;
3291	}
3292
3293	if ( !r_dcache_tlb_sc_acc_req )
3294	{
3295	if ( r_vci_rsp_data_error ) // VCI response ko
3296	{
3297	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3298	{
3299	r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
3300	}
3301	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3302	{
3303	r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
3304	}
3305	r_dcache_bad_vaddr = dreq.addr;
3306	r_dcache_fsm = DCACHE_ERROR;
3307
3308	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3309	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3310	}
3311	else
3312	{
3313	// Using tlb entry is invalidated
3314	if ( r_dcache_inval_tlb_rsp )
3315	{
3316	r_dcache_inval_tlb_rsp = false;
3317	r_dcache_fsm = DCACHE_IDLE;
3318	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
3319	}
3320	else if ( r_dcache_inval_rsp )
3321	{
3322	r_dcache_inval_rsp = false;
3323	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
3324	r_dcache_fsm = DCACHE_IDLE;
3325	}
3326	else if ( r_dcache_tlb_sc_fail )
3327	{
3328	r_dcache_tlb_sc_fail = false;
3329	r_dcache_tlb_ll_acc_req = true;
3330	r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
3331	m_cpt_data_tlb_update_acc++;
3332	}
3333	else
3334	{
3335	r_dcache_fsm = DCACHE_TLB1_UPDT;
3336	}
3337	}
3338	}
3339	break;
3340	}
3341	//////////////////////
3342	case DCACHE_TLB1_READ:
3343	{
3344	if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
3345
3346	// external cache invalidate request
3347	if ( r_tgt_dcache_req )
3348	{
3349	r_dcache_fsm = DCACHE_CC_CHECK;
3350	r_dcache_fsm_save = r_dcache_fsm;
3351	break;
3352	}
3353
3354	if ( !r_dcache_tlb_read_req )
3355	{
3356	if ( r_vci_rsp_data_error ) // VCI response ko
3357	{
3358	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3359	{
3360	r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
3361	}
3362	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3363	{
3364	r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
3365	}
3366	r_dcache_bad_vaddr = dreq.addr;
3367	r_dcache_fsm = DCACHE_ERROR;
3368
3369	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3370	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3371	break;
3372	}
3373
3374	if ( r_dcache_inval_tlb_rsp ) // TLB miss response and invalidation
3375	{
3376	r_dcache_fsm = DCACHE_IDLE;
3377	r_dcache_inval_tlb_rsp = false;
3378	break;
3379	}
3380
3381	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
3382	{
3383	if ( r_dcache_cleanup_req ) break;
3384	r_dcache_cleanup_req = true;
3385	r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3386	m_cpt_cc_cleanup_data++;
3387	r_dcache_fsm = DCACHE_IDLE;
3388	r_dcache_inval_rsp = false;
3389	break;
3390	}
3391
3392	// TLB miss response and no invalidation
3393	r_dcache_fsm = DCACHE_TLB1_READ_UPDT;
3394	}
3395	break;
3396	}
3397	//////////////////////////
3398	case DCACHE_TLB1_READ_UPDT:
3399	{
3400	m_cost_data_tlb_miss_frz++;
3401
3402	// external cache invalidate request
3403	if ( r_tgt_dcache_req )
3404	{
3405	r_dcache_fsm = DCACHE_CC_CHECK;
3406	r_dcache_fsm_save = r_dcache_fsm;
3407	break;
3408	}
3409
3410	// Using tlb entry is invalidated
3411	if ( r_dcache_inval_tlb_rsp )
3412	{
3413	r_dcache_inval_tlb_rsp = false;
3414	r_dcache_fsm = DCACHE_IDLE;
3415	break;
3416	}
3417
3418	if ( !r_dcache_cleanup_req ) // Miss update and no invalidation
3419	{
3420	// update dcache
3421	data_t rsp_dtlb_miss = 0;
3422	paddr_t victim_index = 0;
3423	bool write_hit = false;
3424	size_t way = 0;
3425	size_t set = 0;
3426
3427	// Using tlb entry is in the invalidated cache line
3428	if ( r_dcache_inval_rsp )
3429	{
3430	r_dcache_cleanup_req = true;
3431	r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3432	m_cpt_cc_cleanup_data++;
3433	r_dcache_fsm = DCACHE_IDLE;
3434	r_dcache_inval_rsp = false;
3435	break;
3436	}
3437
3438	bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
3439
3440	if ( cleanup_req )
3441	{
3442	// ins tlb invalidate verification
3443	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
3444	r_dcache_itlb_inval_line = victim_index;
3445	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
3446
3447	// data tlb invalidate verification
3448	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
3449	r_dcache_dtlb_inval_line = victim_index;
3450	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
3451
3452	r_dcache_cleanup_req = true;
3453	r_dcache_cleanup_line = victim_index;
3454	m_cpt_cc_cleanup_data++;
3455	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
3456	r_dcache_fsm_save = r_dcache_fsm;
3457	break;
3458	}
3459
3460	r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
3461	r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);
3462	m_cpt_data_tlb_occup_cache++;
3463
3464	if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) ) // unmapped
3465	{
3466	r_dcache_ptba_ok = false;
3467	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3468	{
3469	r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
3470	}
3471	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3472	{
3473	r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
3474	}
3475	r_dcache_bad_vaddr = dreq.addr;
3476	r_dcache_fsm = DCACHE_ERROR;
3477	}
3478	else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
3479	{
3480	r_dcache_ptba_ok = true;
3481	r_dcache_ptba_save = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;
3482	r_dcache_id1_save = dreq.addr >> PAGE_M_NBITS;
3483	r_dcache_tlb_paddr = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
3484	(paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3485	if ( r_dcache_tlb_ptba_read )
3486	{
3487	r_dcache_tlb_ptba_read = false;
3488	r_dcache_tlb_ll_dirty_req = true;
3489	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
3490	m_cpt_dcache_data_write++;
3491	m_cpt_data_tlb_update_dirty++;
3492	m_cost_data_tlb_update_dirty_frz++;
3493	}
3494	else
3495	{
3496	r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
3497	}
3498	}
3499	else // PTE
3500	{
3501	r_dcache_ptba_ok = false;
3502	if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
3503	{
3504	if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
3505	{
3506	r_dcache_pte_update = rsp_dtlb_miss;
3507	r_dcache_fsm = DCACHE_TLB1_UPDT;
3508	}
3509	else
3510	{
3511	r_dcache_pte_update = rsp_dtlb_miss \| PTE_L_MASK;
3512	r_dcache_tlb_ll_acc_req = true;
3513	r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
3514	m_cpt_dcache_data_write++;
3515	m_cpt_data_tlb_update_acc++;
3516	m_cost_data_tlb_update_acc_frz++;
3517	}
3518	}
3519	else // remotely
3520	{
3521	if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
3522	{
3523	r_dcache_pte_update = rsp_dtlb_miss;
3524	r_dcache_fsm = DCACHE_TLB1_UPDT;
3525	}
3526	else
3527	{
3528	r_dcache_pte_update = rsp_dtlb_miss \| PTE_R_MASK;
3529	r_dcache_tlb_ll_acc_req = true;
3530	r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
3531	m_cpt_dcache_data_write++;
3532	m_cpt_data_tlb_update_acc++;
3533	m_cost_data_tlb_update_acc_frz++;
3534	}
3535	}
3536	}
3537	}
3538	break;
3539	}
3540	//////////////////////
3541	case DCACHE_TLB1_UPDT:
3542	{
3543	m_cost_data_tlb_miss_frz++;
3544
3545	// external cache invalidate request
3546	if ( r_tgt_dcache_req )
3547	{
3548	r_dcache_fsm = DCACHE_CC_CHECK;
3549	r_dcache_fsm_save = r_dcache_fsm;
3550	break;
3551	}
3552
3553	if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
3554	{
3555	paddr_t victim_index = 0;
3556	if (dcache_tlb.update(r_dcache_pte_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
3557	{
3558	r_dcache.setinbit((paddr_t)victim_indexm_dcache_words2, r_dcache_in_dtlb, false);
3559	}
3560	r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
3561	r_dcache_fsm = DCACHE_IDLE;
3562	}
3563	else
3564	{
3565	if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
3566	if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
3567	r_dcache_fsm = DCACHE_IDLE;
3568	}
3569	break;
3570	}
3571	/////////////////////////////
3572	case DCACHE_DTLB2_READ_CACHE:
3573	{
3574	m_cost_data_tlb_miss_frz++;
3575
3576	// external cache invalidate request
3577	if ( r_tgt_dcache_req )
3578	{
3579	r_dcache_fsm = DCACHE_CC_CHECK;
3580	r_dcache_fsm_save = r_dcache_fsm;
3581	break;
3582	}
3583
3584	// Using tlb entry is invalidated
3585	if ( r_dcache_inval_tlb_rsp )
3586	{
3587	r_dcache_inval_tlb_rsp = false;
3588	r_dcache_fsm = DCACHE_IDLE;
3589	break;
3590	}
3591
3592	data_t tlb_data = 0;
3593	data_t tlb_data_ppn = 0;
3594	bool write_hit = false;
3595	bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
3596
3597	if ( tlb_hit_cache )
3598	{
3599	bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
3600	assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
3601	}
3602
3603	// DTLB request hit in cache
3604	if ( tlb_hit_cache )
3605	{
3606	if ( !(tlb_data >> PTE_V_SHIFT) ) // unmapped
3607	{
3608	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3609	{
3610	r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
3611	}
3612	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3613	{
3614	r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
3615	}
3616	r_dcache_bad_vaddr = dreq.addr;
3617	r_dcache_fsm = DCACHE_ERROR;
3618	}
3619	else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT ) //PTD
3620	{
3621	r_dcache_pte_update = tlb_data;
3622	r_dcache_ppn_update = tlb_data_ppn;
3623	r_dcache_fsm = DCACHE_TLB2_UPDT;
3624	}
3625	else
3626	{
3627	m_cpt_data_tlb_hit_dcache++;
3628	if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
3629	{
3630	if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
3631	{
3632	r_dcache_pte_update = tlb_data;
3633	r_dcache_ppn_update = tlb_data_ppn;
3634	r_dcache_fsm = DCACHE_TLB2_UPDT;
3635	}
3636	else
3637	{
3638	r_dcache_pte_update = tlb_data \| PTE_L_MASK;
3639	r_dcache_ppn_update = tlb_data_ppn;
3640	r_dcache_tlb_ll_acc_req = true;
3641	r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
3642	m_cpt_dcache_data_write++;
3643	m_cpt_data_tlb_update_acc++;
3644	m_cost_data_tlb_update_acc_frz++;
3645	}
3646	}
3647	else // remotely
3648	{
3649	if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
3650	{
3651	r_dcache_pte_update = tlb_data;
3652	r_dcache_ppn_update = tlb_data_ppn;
3653	r_dcache_fsm = DCACHE_TLB2_UPDT;
3654	}
3655	else
3656	{
3657	r_dcache_pte_update = tlb_data \| PTE_R_MASK;
3658	r_dcache_ppn_update = tlb_data_ppn;
3659	r_dcache_tlb_ll_acc_req = true;
3660	r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
3661	m_cpt_dcache_data_write++;
3662	m_cpt_data_tlb_update_acc++;
3663	m_cost_data_tlb_update_acc_frz++;
3664	}
3665	}
3666	}
3667	}
3668	else
3669	{
3670	// DTLB request miss in cache and walk page table level 2
3671	r_dcache_tlb_read_req = true;
3672	r_dcache_fsm = DCACHE_TLB2_READ;
3673	}
3674	break;
3675	}
3676	///////////////////////
3677	case DCACHE_TLB2_LL_WAIT:
3678	{
3679	if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
3680	m_cost_data_tlb_update_acc_frz++;
3681
3682	// external cache invalidate request
3683	if ( r_tgt_dcache_req )
3684	{
3685	r_dcache_fsm = DCACHE_CC_CHECK;
3686	r_dcache_fsm_save = r_dcache_fsm;
3687	break;
3688	}
3689
3690	if (!r_dcache_tlb_ll_acc_req)
3691	{
3692	if ( r_vci_rsp_data_error ) // VCI response ko
3693	{
3694	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3695	{
3696	r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
3697	}
3698	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3699	{
3700	r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
3701	}
3702	r_dcache_bad_vaddr = dreq.addr;
3703	r_dcache_fsm = DCACHE_ERROR;
3704
3705	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3706	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3707	}
3708	else
3709	{
3710	if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) ) // unmapped
3711	{
3712	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3713	{
3714	r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
3715	}
3716	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3717	{
3718	r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
3719	}
3720	r_dcache_bad_vaddr = dreq.addr;
3721	r_dcache_fsm = DCACHE_ERROR;
3722
3723	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3724	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3725	}
3726	else if ( r_dcache_inval_tlb_rsp )
3727	{
3728	r_dcache_inval_tlb_rsp = false;
3729	r_dcache_fsm = DCACHE_IDLE;
3730	}
3731	else if ( r_dcache_inval_rsp )
3732	{
3733	r_dcache_inval_rsp = false;
3734	r_dcache_fsm = DCACHE_IDLE;
3735	}
3736	else
3737	{
3738	r_dcache_tlb_sc_acc_req = true;
3739	r_dcache_pte_update = r_dcache_miss_buf[0] \| r_dcache_pte_update.read();
3740	r_dcache_fsm = DCACHE_TLB2_SC_WAIT;
3741	}
3742	}
3743	}
3744	break;
3745	}
3746	///////////////////////
3747	case DCACHE_TLB2_SC_WAIT:
3748	{
3749	if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
3750	m_cost_data_tlb_update_acc_frz++;
3751	// external cache invalidate request
3752	if ( r_tgt_dcache_req )
3753	{
3754	r_dcache_fsm = DCACHE_CC_CHECK;
3755	r_dcache_fsm_save = r_dcache_fsm;
3756	break;
3757	}
3758
3759	if ( !r_dcache_tlb_sc_acc_req )
3760	{
3761	if ( r_vci_rsp_data_error ) // VCI response ko
3762	{
3763	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3764	{
3765	r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
3766	}
3767	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3768	{
3769	r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
3770	}
3771	r_dcache_bad_vaddr = dreq.addr;
3772	r_dcache_fsm = DCACHE_ERROR;
3773
3774	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3775	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3776	}
3777	else
3778	{
3779	// Using tlb entry is invalidated
3780	if ( r_dcache_inval_tlb_rsp )
3781	{
3782	r_dcache_inval_tlb_rsp = false;
3783	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
3784	r_dcache_fsm = DCACHE_IDLE;
3785	}
3786	else if ( r_dcache_inval_rsp )
3787	{
3788	r_dcache_inval_rsp = false;
3789	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
3790	r_dcache_fsm = DCACHE_IDLE;
3791	}
3792	else if ( r_dcache_tlb_sc_fail )
3793	{
3794	r_dcache_tlb_ll_acc_req = true;
3795	r_dcache_tlb_sc_fail = false;
3796	r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
3797	m_cpt_data_tlb_update_acc++;
3798	}
3799	else
3800	{
3801	r_dcache_fsm = DCACHE_TLB2_UPDT;
3802	}
3803	}
3804	}
3805	break;
3806	}
3807	/////////////////////
3808	case DCACHE_TLB2_READ:
3809	{
3810	m_cost_data_tlb_miss_frz++;
3811
3812	// external cache invalidate request
3813	if ( r_tgt_dcache_req )
3814	{
3815	r_dcache_fsm = DCACHE_CC_CHECK;
3816	r_dcache_fsm_save = r_dcache_fsm;
3817	break;
3818	}
3819
3820	if ( !r_dcache_tlb_read_req )
3821	{
3822	if ( r_vci_rsp_data_error ) // VCI response ko
3823	{
3824	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3825	{
3826	r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
3827	}
3828	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3829	{
3830	r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
3831	}
3832	r_dcache_bad_vaddr = dreq.addr;
3833	r_dcache_fsm = DCACHE_ERROR;
3834
3835	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3836	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3837	break;
3838	}
3839
3840	if ( r_dcache_inval_tlb_rsp ) // TLB miss response and invalidation
3841	{
3842	r_dcache_fsm = DCACHE_IDLE;
3843	r_dcache_inval_tlb_rsp = false;
3844	break;
3845	}
3846
3847	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
3848	{
3849	if ( r_dcache_cleanup_req ) break;
3850	r_dcache_cleanup_req = true;
3851	r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3852	m_cpt_cc_cleanup_data++;
3853	r_dcache_fsm = DCACHE_IDLE;
3854	r_dcache_inval_rsp = false;
3855	break;
3856	}
3857
3858	// TLB miss response and no invalidation
3859	r_dcache_fsm = DCACHE_TLB2_READ_UPDT;
3860	}
3861	break;
3862	}
3863	//////////////////////////
3864	case DCACHE_TLB2_READ_UPDT:
3865	{
3866	m_cost_data_tlb_miss_frz++;
3867
3868	// external cache invalidate request
3869	if ( r_tgt_dcache_req )
3870	{
3871	r_dcache_fsm = DCACHE_CC_CHECK;
3872	r_dcache_fsm_save = r_dcache_fsm;
3873	break;
3874	}
3875
3876	// Using tlb entry is invalidated
3877	if ( r_dcache_inval_tlb_rsp )
3878	{
3879	r_dcache_inval_tlb_rsp = false;
3880	r_dcache_fsm = DCACHE_IDLE;
3881	break;
3882	}
3883
3884	if ( !r_dcache_cleanup_req )
3885	{
3886	// update cache
3887	data_t rsp_dtlb_miss;
3888	data_t tlb_data_ppn;
3889	bool write_hit = false;
3890	paddr_t victim_index = 0;
3891	size_t way = 0;
3892	size_t set = 0;
3893
3894	// Using tlb entry is in the invalidated cache line
3895	if ( r_dcache_inval_rsp )
3896	{
3897	r_dcache_cleanup_req = true;
3898	r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3899	m_cpt_cc_cleanup_data++;
3900	r_dcache_fsm = DCACHE_IDLE;
3901	r_dcache_inval_rsp = false;
3902	break;
3903	}
3904
3905	bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
3906
3907	if ( cleanup_req )
3908	{
3909	// ins tlb invalidate verification
3910	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
3911	r_dcache_itlb_inval_line = victim_index;
3912	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
3913
3914	// data tlb invalidate verification
3915	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
3916	r_dcache_dtlb_inval_line = victim_index;
3917	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
3918
3919	r_dcache_cleanup_req = true;
3920	r_dcache_cleanup_line = victim_index;
3921	m_cpt_cc_cleanup_data++;
3922	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
3923	r_dcache_fsm_save = r_dcache_fsm;
3924	break;
3925	}
3926
3927	r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
3928	r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);
3929	m_cpt_data_tlb_occup_cache++;
3930
3931	bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
3932	assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
3933
3934	if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) ) // unmapped
3935	{
3936	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3937	{
3938	r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
3939	}
3940	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3941	{
3942	r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
3943	}
3944	r_dcache_bad_vaddr = dreq.addr;
3945	r_dcache_fsm = DCACHE_ERROR;
3946	}
3947	else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
3948	{
3949	r_dcache_pte_update = rsp_dtlb_miss;
3950	r_dcache_ppn_update = tlb_data_ppn;
3951	r_dcache_fsm = DCACHE_TLB2_UPDT;
3952	}
3953	else
3954	{
3955	if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
3956	{
3957	if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
3958	{
3959	r_dcache_pte_update = rsp_dtlb_miss;
3960	r_dcache_ppn_update = tlb_data_ppn;
3961	r_dcache_fsm = DCACHE_TLB2_UPDT;
3962	}
3963	else
3964	{
3965	r_dcache_pte_update = rsp_dtlb_miss \| PTE_L_MASK;
3966	r_dcache_ppn_update = tlb_data_ppn;
3967	r_dcache_tlb_ll_acc_req = true;
3968	r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
3969	m_cpt_dcache_data_write++;
3970	m_cpt_data_tlb_update_acc++;
3971	m_cost_data_tlb_update_acc_frz++;
3972	}
3973	}
3974	else // remotely
3975	{
3976	if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
3977	{
3978	r_dcache_pte_update = rsp_dtlb_miss;
3979	r_dcache_ppn_update = tlb_data_ppn;
3980	r_dcache_fsm = DCACHE_TLB2_UPDT;
3981	}
3982	else
3983	{
3984	r_dcache_pte_update = rsp_dtlb_miss \| PTE_R_MASK;
3985	r_dcache_ppn_update = tlb_data_ppn;
3986	r_dcache_tlb_ll_acc_req = true;
3987	r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
3988	m_cpt_dcache_data_write++;
3989	m_cpt_data_tlb_update_acc++;
3990	m_cost_data_tlb_update_acc_frz++;
3991	}
3992	}
3993	}
3994	}
3995	break;
3996	}
3997	//////////////////////
3998	case DCACHE_TLB2_UPDT:
3999	{
4000	m_cost_data_tlb_miss_frz++;
4001
4002	// external cache invalidate request
4003	if ( r_tgt_dcache_req )
4004	{
4005	r_dcache_fsm = DCACHE_CC_CHECK;
4006	r_dcache_fsm_save = r_dcache_fsm;
4007	break;
4008	}
4009
4010	if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
4011	{
4012	paddr_t victim_index = 0;
4013	if (dcache_tlb.update(r_dcache_pte_update,r_dcache_ppn_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
4014	{
4015	r_dcache.setinbit((paddr_t)victim_indexm_dcache_words2, r_dcache_in_dtlb, false);
4016	}
4017	r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
4018	r_dcache_fsm = DCACHE_IDLE;
4019	}
4020	else
4021	{
4022	if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
4023	if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
4024	r_dcache_fsm = DCACHE_IDLE;
4025	}
4026	break;
4027	}
4028	///////////////////////
4029	case DCACHE_CTXT_SWITCH:
4030	{
4031	// TLB flush leads to cleanup corresponding data cache line
4032	paddr_t victim_index = 0;
4033	size_t way = 0;
4034	size_t set = 0;
4035
4036	if ( r_dcache_itlb_cleanup_req )
4037	{
4038	r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()m_dcache_words2), r_dcache_in_itlb, false);
4039	r_dcache_itlb_cleanup_req = false;
4040	}
4041
4042	for ( way = 0; way < m_dtlb_ways; way++)
4043	{
4044	for ( set = 0; set < m_dtlb_sets; set++)
4045	{
4046	if(dcache_tlb.checkcleanup(way, set, &victim_index))
4047	{
4048	r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false);
4049	}
4050	}
4051	}
4052
4053	if ( !r_dcache_xtn_req )
4054	{
4055	r_dcache_fsm = DCACHE_IDLE;
4056	r_dtlb_translation_valid = false;
4057	r_dcache_ptba_ok = false;
4058	drsp.valid = true;
4059	}
4060	break;
4061	}
4062	////////////////////////
4063	case DCACHE_ICACHE_FLUSH:
4064	case DCACHE_ICACHE_INVAL:
4065	case DCACHE_ICACHE_INVAL_PA:
4066	case DCACHE_ITLB_INVAL:
4067	{
4068	// external cache invalidate request
4069	if ( r_tgt_dcache_req )
4070	{
4071	r_dcache_fsm = DCACHE_CC_CHECK;
4072	r_dcache_fsm_save = r_dcache_fsm;
4073	break;
4074	}
4075	if ( !r_dcache_xtn_req )
4076	{
4077	r_dcache_fsm = DCACHE_IDLE;
4078	drsp.valid = true;
4079	}
4080	break;
4081	}
4082	////////////////////////
4083	case DCACHE_DCACHE_FLUSH:
4084	{
4085	// external cache invalidate request
4086	if ( r_tgt_dcache_req )
4087	{
4088	r_dcache_fsm = DCACHE_CC_CHECK;
4089	r_dcache_fsm_save = r_dcache_fsm;
4090	break;
4091	}
4092	size_t way = r_dcache_way;
4093	size_t set = r_dcache_set;
4094	bool clean = false;
4095
4096	// cache flush and send cleanup to external
4097	if ( !r_dcache_cleanup_req )
4098	{
4099	paddr_t victim_index = 0;
4100	for ( ; way < m_dcache_ways; way++ )
4101	{
4102	for ( ; set < m_dcache_sets; set++ )
4103	{
4104	if ( r_dcache.flush(way, set, &victim_index) )
4105	{
4106	clean = true;
4107	r_dcache_cleanup_req = true;
4108	r_dcache_cleanup_line = victim_index;
4109	m_cpt_cc_cleanup_data++;
4110	r_dcache_way = way + ((set+1)/m_dcache_sets);
4111	r_dcache_set = (set+1) % m_dcache_sets;
4112	break;
4113	}
4114	}
4115	if (clean) break;
4116	}
4117
4118	if ((way == m_dcache_ways) && !r_dcache_xtn_req )
4119	{
4120	// data TLB flush
4121	dcache_tlb.flush(true); // global entries are not invalidated
4122	r_dtlb_translation_valid = false;
4123	r_dcache_ptba_ok = false;
4124
4125	for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++)
4126	{
4127	r_dcache_in_itlb[line] = false;
4128	r_dcache_in_dtlb[line] = false;
4129	}
4130
4131	r_dcache_fsm = DCACHE_IDLE;
4132	drsp.valid = true;
4133	break;
4134	}
4135	}
4136	break;
4137	}
4138	//////////////////////
4139	case DCACHE_DTLB_INVAL:
4140	{
4141	paddr_t victim_index = 0;
4142	// clean indicate data tlb bit
4143	if ( dcache_tlb.inval(r_dcache_wdata_save, &victim_index) )
4144	{
4145	r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false);
4146	}
4147	r_dtlb_translation_valid = false;
4148	r_dcache_ptba_ok = false;
4149	r_dcache_fsm = DCACHE_IDLE;
4150	drsp.valid = true;
4151	break;
4152	}
4153	////////////////////////
4154	case DCACHE_DCACHE_INVAL:
4155	{
4156	// external cache invalidate request
4157	if ( r_tgt_dcache_req )
4158	{
4159	r_dcache_fsm = DCACHE_CC_CHECK;
4160	r_dcache_fsm_save = r_dcache_fsm;
4161	break;
4162	}
4163
4164	m_cpt_dcache_dir_read += m_dcache_ways;
4165	vaddr_t invadr = dreq.wdata;
4166	paddr_t dpaddr = 0;
4167	bool dcache_hit_t = false;
4168	size_t way = 0;
4169	size_t set = 0;
4170
4171	if ( !r_dcache_cleanup_req )
4172	{
4173	if ( r_mmu_mode.read() & DATA_TLB_MASK )
4174	{
4175	dcache_hit_t = dcache_tlb.translate(invadr, &dpaddr);
4176	}
4177	else
4178	{
4179	dpaddr = invadr;
4180	dcache_hit_t = true;
4181	}
4182
4183	if ( dcache_hit_t )
4184	{
4185	r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
4186	r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
4187	m_cpt_cc_cleanup_data++;
4188
4189	if ( r_dcache_in_itlb[waym_dcache_sets+set] \|\| r_dcache_in_dtlb[waym_dcache_sets+set] )
4190	{
4191	// ins tlb invalidate verification
4192	r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
4193	r_dcache_itlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
4194	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4195
4196	// data tlb invalidate verification
4197	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
4198	r_dcache_dtlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
4199	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4200	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
4201	r_dcache_fsm_save = r_dcache_fsm;
4202	break;
4203	}
4204	}
4205	r_dcache_fsm = DCACHE_IDLE;
4206	drsp.valid = true;
4207	}
4208	break;
4209	}
4210	////////////////////////
4211	case DCACHE_DCACHE_INVAL_PA:
4212	{
4213	// external cache invalidate request
4214	if ( r_tgt_dcache_req )
4215	{
4216	r_dcache_fsm = DCACHE_CC_CHECK;
4217	r_dcache_fsm_save = r_dcache_fsm;
4218	break;
4219	}
4220	m_cpt_dcache_dir_read += m_dcache_ways;
4221	paddr_t dpaddr = (paddr_t)r_mmu_word_hi.read() << 32 \| r_mmu_word_lo.read();
4222	size_t way = 0;
4223	size_t set = 0;
4224
4225	if ( !r_dcache_cleanup_req )
4226	{
4227	r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
4228	r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
4229	m_cpt_cc_cleanup_data++;
4230
4231	if ( r_dcache_in_itlb[waym_dcache_sets+set] \|\| r_dcache_in_dtlb[waym_dcache_sets+set] )
4232	{
4233	// ins tlb invalidate verification
4234	r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
4235	r_dcache_itlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
4236	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4237
4238	// data tlb invalidate verification
4239	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
4240	r_dcache_dtlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
4241	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4242	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
4243	r_dcache_fsm_save = r_dcache_fsm;
4244	break;
4245	}
4246	r_dcache_fsm = DCACHE_IDLE;
4247	drsp.valid = true;
4248	}
4249	break;
4250	}
4251	/////////////////////////
4252	case DCACHE_DCACHE_SYNC:
4253	{
4254	// external cache invalidate request
4255	if ( r_tgt_dcache_req )
4256	{
4257	r_dcache_fsm = DCACHE_CC_CHECK;
4258	r_dcache_fsm_save = r_dcache_fsm;
4259	break;
4260	}
4261	if ( !r_dcache_write_req )
4262	{
4263	r_dcache_write_req = r_wbuf.rok();
4264	drsp.valid = true;
4265	r_dcache_fsm = DCACHE_IDLE;
4266	}
4267	break;
4268	}
4269	/////////////////////
4270	case DCACHE_MISS_WAIT:
4271	{
4272	m_cost_data_miss_frz++;
4273
4274	// external cache invalidate request
4275	if ( r_tgt_dcache_req )
4276	{
4277	r_dcache_fsm = DCACHE_CC_CHECK;
4278	r_dcache_fsm_save = r_dcache_fsm;
4279	break;
4280	}
4281
4282	if ( !r_dcache_miss_req )
4283	{
4284	if ( r_vci_rsp_data_error )
4285	{
4286	r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;
4287	r_dcache_bad_vaddr = dreq.addr;
4288	r_dcache_fsm = DCACHE_ERROR;
4289
4290	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
4291	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
4292	break;
4293	}
4294
4295	if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
4296	{
4297	if ( r_dcache_cleanup_req ) break;
4298	r_dcache_cleanup_req = true;
4299	r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);
4300	m_cpt_cc_cleanup_data++;
4301	r_dcache_fsm = DCACHE_IDLE;
4302	r_dcache_inval_tlb_rsp = false;
4303	if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
4304	break;
4305	}
4306
4307	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
4308	{
4309	if ( r_dcache_cleanup_req ) break;
4310	r_dcache_cleanup_req = true;
4311	r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);
4312	m_cpt_cc_cleanup_data++;
4313	r_dcache_fsm = DCACHE_IDLE;
4314	r_dcache_inval_rsp = false;
4315	break;
4316	}
4317	// Miss read response and no tlb invalidation
4318	r_dcache_fsm = DCACHE_MISS_UPDT;
4319	}
4320	break;
4321	}
4322	/////////////////////
4323	case DCACHE_MISS_UPDT:
4324	{
4325	m_cost_data_miss_frz++;
4326
4327	// external cache invalidate request
4328	if ( r_tgt_dcache_req )
4329	{
4330	r_dcache_fsm = DCACHE_CC_CHECK;
4331	r_dcache_fsm_save = r_dcache_fsm;
4332	break;
4333	}
4334
4335	if ( r_dcache_inval_tlb_rsp ) // tlb invalidation
4336	{
4337	if ( r_dcache_cleanup_req ) break;
4338	r_dcache_cleanup_req = true;
4339	r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);
4340	m_cpt_cc_cleanup_data++;
4341	r_dcache_inval_tlb_rsp = false;
4342	r_dcache_inval_rsp = false;
4343	r_dcache_fsm = DCACHE_IDLE;
4344	break;
4345	}
4346
4347	if (!r_dcache_cleanup_req ) // Miss update and no invalidation
4348	{
4349	paddr_t victim_index = 0;
4350	size_t way = 0;
4351	size_t set = 0;
4352
4353	// Using tlb entry is in the invalidated cache line
4354	if ( r_dcache_inval_rsp )
4355	{
4356	r_dcache_cleanup_req = true;
4357	r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);
4358	m_cpt_cc_cleanup_data++;
4359	r_dcache_fsm = DCACHE_IDLE;
4360	r_dcache_inval_rsp = false;
4361	break;
4362	}
4363
4364	bool cleanup_req = r_dcache.find(r_dcache_paddr_save.read(), r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
4365
4366	if ( cleanup_req )
4367	{
4368	// ins tlb invalidate verification
4369	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
4370	r_dcache_itlb_inval_line = victim_index;
4371	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4372
4373	// data tlb invalidate verification
4374	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
4375	r_dcache_dtlb_inval_line = victim_index;
4376	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4377
4378	r_dcache_cleanup_req = true;
4379	r_dcache_cleanup_line = victim_index;
4380	m_cpt_cc_cleanup_data++;
4381	if ( r_dcache_in_itlb[m_dcache_setsway+set] \|\| r_dcache_in_dtlb[m_dcache_setsway+set] )
4382	{
4383	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
4384	r_dcache_fsm_save = r_dcache_fsm;
4385	break;
4386	}
4387	}
4388	m_cpt_dcache_dir_write++;
4389	m_cpt_dcache_data_write++;
4390	r_dcache.update(r_dcache_paddr_save.read(), way, set, r_dcache_miss_buf);
4391	r_dcache_fsm = DCACHE_IDLE;
4392	}
4393	break;
4394	}
4395	//////////////////////
4396	case DCACHE_UNC_WAIT:
4397	{
4398	m_cost_unc_read_frz++;
4399
4400	// external cache invalidate request
4401	if ( r_tgt_dcache_req )
4402	{
4403	r_dcache_fsm = DCACHE_CC_CHECK;
4404	r_dcache_fsm_save = r_dcache_fsm;
4405	break;
4406	}
4407
4408	if ( !r_dcache_unc_req )
4409	{
4410	if ( r_vci_rsp_data_error )
4411	{
4412	r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;
4413	r_dcache_bad_vaddr = dreq.addr;
4414	r_dcache_fsm = DCACHE_ERROR;
4415
4416	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
4417	break;
4418	}
4419
4420	if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
4421	{
4422	r_dcache_inval_tlb_rsp = false;
4423	}
4424
4425	drsp.valid = true;
4426	drsp.rdata = r_dcache_miss_buf[0];
4427	r_dcache_fsm = DCACHE_IDLE;
4428	}
4429	break;
4430	}
4431	///////////////////////
4432	case DCACHE_WRITE_UPDT:
4433	{
4434	m_cost_write_frz++;
4435	m_cpt_dcache_data_write++;
4436	size_t way = 0;
4437	size_t set = 0;
4438	bool write_hit = false;
4439	data_t mask = vci_param::be2mask(r_dcache_be_save.read());
4440	data_t wdata = (mask & r_dcache_wdata_save) \| (~mask & r_dcache_rdata_save);
4441	write_hit = r_dcache.write(r_dcache_paddr_save, wdata, &way, &set);
4442	assert(write_hit && "Write on miss ignores data");
4443
4444	if (r_dcache_in_itlb[waym_dcache_sets+set] \|\| r_dcache_in_dtlb[m_dcache_setsway+set])
4445	{
4446	// ins tlb invalidate verification
4447	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
4448	r_dcache_itlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
4449	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4450
4451	// data tlb invalidate verification
4452	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
4453	r_dcache_dtlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
4454	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4455
4456	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
4457	r_dcache_fsm_save = r_dcache_fsm;
4458	break;
4459	}
4460
4461	if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) )
4462	{
4463	m_cpt_data_tlb_update_dirty++;
4464	m_cost_data_tlb_update_dirty_frz++;
4465	if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) ) // 2M page size, one level page table
4466	{
4467	r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) \| PTE_D_MASK;
4468	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
4469	r_dcache_tlb_ll_dirty_req = true;
4470	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
4471	}
4472	else
4473	{
4474	if (r_dcache_hit_p_save)
4475	{
4476	r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) \| PTE_D_MASK;
4477	r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save\|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
4478	r_dcache_tlb_ll_dirty_req = true;
4479	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
4480	}
4481	else
4482	{
4483	r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) \| PTE_D_MASK;
4484	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
4485	r_dcache_tlb_ptba_read = true;
4486	r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
4487	}
4488	}
4489	}
4490	else
4491	{
4492	r_dcache_fsm = DCACHE_WRITE_REQ;
4493	drsp.valid = true;
4494	drsp.rdata = 0;
4495	}
4496	break;
4497	}
4498	/////////////////
4499	case DCACHE_ERROR:
4500	{
4501	r_vci_rsp_data_error = false;
4502	drsp.valid = true;
4503	drsp.error = true;
4504	drsp.rdata = 0;
4505	r_dcache_fsm = DCACHE_IDLE;
4506	break;
4507	}
4508	//////////////////////
4509	case DCACHE_ITLB_READ:
4510	{
4511	if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
4512
4513	// external cache invalidate request
4514	if ( r_tgt_dcache_req )
4515	{
4516	r_dcache_fsm = DCACHE_CC_CHECK;
4517	r_dcache_fsm_save = r_dcache_fsm;
4518	break;
4519	}
4520
4521	if ( !r_dcache_itlb_read_req ) // vci response ok
4522	{
4523	if ( r_vci_rsp_data_error )
4524	{
4525	r_dcache_rsp_itlb_error = true;
4526	r_itlb_read_dcache_req = false;
4527	r_vci_rsp_data_error = false;
4528	r_dcache_fsm = DCACHE_IDLE;
4529
4530	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
4531	break;
4532	}
4533
4534	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
4535	{
4536	if ( r_dcache_cleanup_req ) break;
4537	r_dcache_cleanup_req = true;
4538	r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);
4539	m_cpt_cc_cleanup_data++;
4540	r_dcache_fsm = DCACHE_IDLE;
4541	r_dcache_inval_rsp = false;
4542	break;
4543	}
4544
4545	r_dcache_fsm = DCACHE_ITLB_UPDT;
4546	}
4547	break;
4548	}
4549	//////////////////////
4550	case DCACHE_ITLB_UPDT:
4551	{
4552	if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
4553
4554	// external cache invalidate request
4555	if ( r_tgt_dcache_req )
4556	{
4557	r_dcache_fsm = DCACHE_CC_CHECK;
4558	r_dcache_fsm_save = r_dcache_fsm;
4559	break;
4560	}
4561
4562	if ( !r_dcache_cleanup_req )
4563	{
4564	data_t rsp_itlb_miss = 0;
4565	data_t rsp_itlb_ppn = 0;
4566
4567	paddr_t victim_index = 0;
4568	size_t way = 0;
4569	size_t set = 0;
4570
4571	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
4572	{
4573	r_dcache_cleanup_req = true;
4574	r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);
4575	m_cpt_cc_cleanup_data++;
4576	r_dcache_fsm = DCACHE_IDLE;
4577	r_dcache_inval_rsp = false;
4578	break;
4579	}
4580
4581	bool cleanup = r_dcache.find(r_icache_paddr_save, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
4582
4583	if ( cleanup )
4584	{
4585	// ins tlb invalidate verification
4586	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
4587	r_dcache_itlb_inval_line = victim_index;
4588	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4589
4590	// data tlb invalidate verification
4591	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
4592	r_dcache_dtlb_inval_line = victim_index;
4593	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4594
4595	r_dcache_cleanup_req = true;
4596	r_dcache_cleanup_line = victim_index;
4597	m_cpt_cc_cleanup_data++;
4598	if ( r_dcache_in_itlb[m_dcache_setsway+set] \|\| r_dcache_in_dtlb[m_dcache_setsway+set] )
4599	{
4600	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
4601	r_dcache_fsm_save = r_dcache_fsm;
4602	break;
4603	}
4604	}
4605
4606	r_dcache.update(r_icache_paddr_save, way, set, r_dcache_miss_buf);
4607
4608	r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
4609	bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
4610	m_cpt_ins_tlb_occup_cache++;
4611
4612	if ( r_itlb_k_read_dcache && itlb_hit_dcache )
4613	{
4614	r_itlb_k_read_dcache = false;
4615	bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
4616	assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
4617	}
4618
4619	r_dcache_rsp_itlb_miss = rsp_itlb_miss;
4620	r_dcache_rsp_itlb_ppn = rsp_itlb_ppn;
4621	r_dcache_rsp_itlb_error = false;
4622	r_itlb_read_dcache_req = false;
4623	r_dcache_fsm = DCACHE_IDLE;
4624	}
4625	break;
4626	}
4627	//////////////////////////
4628	case DCACHE_ITLB_LL_WAIT:
4629	{
4630	if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
4631	// external cache invalidate request
4632	if ( r_tgt_dcache_req )
4633	{
4634	r_dcache_fsm = DCACHE_CC_CHECK;
4635	r_dcache_fsm_save = r_dcache_fsm;
4636	break;
4637	}
4638
4639	if (!r_dcache_itlb_ll_acc_req)
4640	{
4641	if ( r_vci_rsp_data_error ) // VCI response ko
4642	{
4643	r_dcache_rsp_itlb_error = true;
4644	r_vci_rsp_data_error = false;
4645	r_itlb_acc_dcache_req = false;
4646	r_dcache_fsm = DCACHE_IDLE;
4647	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
4648	}
4649	else
4650	{
4651	if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) ) // unmapped
4652	{
4653	r_dcache_rsp_itlb_error = true;
4654	r_itlb_acc_dcache_req = false;
4655	r_dcache_fsm = DCACHE_IDLE;
4656	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
4657	}
4658	else if ( r_dcache_inval_rsp )
4659	{
4660	r_dcache_inval_rsp = false;
4661	r_dcache_fsm = DCACHE_IDLE;
4662	}
4663	else
4664	{
4665	r_dcache_itlb_sc_acc_req = true;
4666	r_icache_pte_update = r_dcache_miss_buf[0] \| r_icache_pte_update.read();
4667	r_dcache_fsm = DCACHE_ITLB_SC_WAIT;
4668	}
4669	}
4670	}
4671	break;
4672	}
4673	//////////////////////////
4674	case DCACHE_ITLB_SC_WAIT:
4675	{
4676	if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
4677	// external cache invalidate request
4678	if ( r_tgt_dcache_req )
4679	{
4680	r_dcache_fsm = DCACHE_CC_CHECK;
4681	r_dcache_fsm_save = r_dcache_fsm;
4682	break;
4683	}
4684
4685	if ( !r_dcache_itlb_sc_acc_req )
4686	{
4687	if ( r_vci_rsp_data_error ) // VCI response ko
4688	{
4689	r_dcache_rsp_itlb_error = true;
4690	r_vci_rsp_data_error = false;
4691	r_itlb_acc_dcache_req = false;
4692	r_dcache_fsm = DCACHE_IDLE;
4693	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
4694	}
4695	else
4696	{
4697	if ( r_dcache_inval_rsp )
4698	{
4699	r_dcache_inval_rsp = false;
4700	r_dcache_fsm = DCACHE_IDLE;
4701	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
4702	}
4703	else if ( r_dcache_tlb_sc_fail )
4704	{
4705	r_dcache_tlb_sc_fail = false;
4706	r_dcache_itlb_ll_acc_req = true;
4707	r_dcache_fsm = DCACHE_ITLB_LL_WAIT;
4708	}
4709	else
4710	{
4711	r_itlb_acc_dcache_req = false;
4712	r_dcache_fsm = DCACHE_IDLE;
4713	}
4714	}
4715	}
4716	break;
4717	}
4718	/////////////////////
4719	case DCACHE_CC_CHECK: // read directory in case of invalidate or update request
4720	{
4721	m_cpt_dcache_dir_read += m_dcache_ways;
4722	m_cpt_dcache_data_read += m_dcache_ways;
4723
4724	/* activity counter */
4725	if ( (( r_dcache_fsm_save == DCACHE_BIS ) \|\|( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )
4726	{
4727	m_cost_data_miss_frz++;
4728	}
4729	if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) \|\| ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) \|\|
4730	( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
4731	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
4732	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
4733	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) \|\|
4734	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
4735	{
4736	m_cost_data_tlb_miss_frz++;
4737	}
4738
4739	// DCACHE_TLB1_LL_WAIT DCACHE_TLB1_SC_WAIT DCACHE_LL_DIRTY_WAIT DCACHE_ITLB_LL_WAIT DCACHE_ITLB_SC_WAIT
4740	// DCACHE_TLB2_LL_WAIT DCACHE_TLB2_SC_WAIT DCACHE_SC_DIRTY_WAIT
4741	if((( /( r_dcache_fsm_save == DCACHE_UNC_WAIT ) \|\|/
4742	( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) &&
4743	( (r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))))
4744	\|\| (( ( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
4745	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) \|\|
4746	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT ) /* \|\|
4747	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
4748	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
4749	( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) */ ) &&
4750	( (r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) )
4751	\|\| (( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) \|\| ( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) /*\|\|
4752	( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT )*/ ) &&
4753	( (r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) )
4754	{
4755	data_t dcache_rdata = 0;
4756	size_t way = 0;
4757	size_t set = 0;
4758	bool dcache_hit = r_dcache.read(r_tgt_addr.read(), &dcache_rdata, &way, &set);
4759	assert(!dcache_hit && "ignored update req should not be in dcache");
4760
4761	r_dcache_inval_rsp = true;
4762	r_tgt_dcache_req = false;
4763	if ( r_tgt_update )
4764	{ // Also send a cleanup and answer
4765	r_tgt_dcache_rsp = true;
4766	}
4767	else
4768	{ // Also send a cleanup but don't answer
4769	r_tgt_dcache_rsp = false;
4770	}
4771	r_dcache_fsm = r_dcache_fsm_save;
4772	}
4773	else
4774	{
4775	data_t dcache_rdata = 0;
4776	size_t way = 0;
4777	size_t set = 0;
4778
4779	bool dcache_hit = r_dcache.read(r_tgt_addr.read(), &dcache_rdata, &way, &set);
4780
4781	if ( dcache_hit )
4782	{
4783	if ( r_dcache_in_dtlb[m_dcache_setsway+set] \|\| r_dcache_in_itlb[m_dcache_setsway+set] )
4784	{
4785	// ins tlb invalidate verification
4786	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
4787	r_dcache_itlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
4788	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4789
4790	// data tlb invalidate verification
4791	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
4792	r_dcache_dtlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
4793	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4794
4795	r_dcache_cc_check = true;
4796	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
4797	break;
4798	}
4799
4800	if ( r_tgt_update ) // update
4801	{
4802	r_dcache_fsm = DCACHE_CC_UPDT;
4803	}
4804	else // invalidate
4805	{
4806	r_dcache_fsm = DCACHE_CC_INVAL;
4807	}
4808	}
4809	else // nothing
4810	{
4811	r_dcache_fsm = DCACHE_CC_NOP;
4812	}
4813	}
4814	break;
4815	}
4816	///////////////////
4817	case DCACHE_CC_UPDT: // update directory and data cache
4818	{
4819	/* activity counter */
4820	if ( (( r_dcache_fsm_save == DCACHE_BIS ) \|\|( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )
4821	{
4822	m_cost_data_miss_frz++;
4823	}
4824	if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) \|\| ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) \|\|
4825	( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
4826	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
4827	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
4828	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) \|\|
4829	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
4830	{
4831	m_cost_data_tlb_miss_frz++;
4832	}
4833
4834	m_cpt_dcache_dir_write++;
4835	m_cpt_dcache_data_write++;
4836	data_t* buf = r_tgt_buf;
4837	for( size_t i = 0; i < m_dcache_words; i++ )
4838	{
4839	if( r_tgt_val[i] ) r_dcache.write( r_tgt_addr.read() + i*4, buf[i] );
4840	}
4841
4842	r_tgt_dcache_req = false;
4843	r_tgt_dcache_rsp = true;
4844	r_dcache_fsm = r_dcache_fsm_save;
4845	break;
4846	}
4847	/////////////////////
4848	case DCACHE_CC_INVAL: // invalidate a cache line
4849	{
4850	/* activity counter */
4851	if ( (( r_dcache_fsm_save == DCACHE_BIS ) \|\|( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )
4852	{
4853	m_cost_data_miss_frz++;
4854	}
4855	if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) \|\| ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) \|\|
4856	( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
4857	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
4858	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
4859	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) \|\|
4860	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
4861	{
4862	m_cost_data_tlb_miss_frz++;
4863	}
4864
4865	r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read());
4866	r_tgt_dcache_req = false;
4867	r_dcache_fsm = r_dcache_fsm_save;
4868	break;
4869	}
4870	///////////////////
4871	case DCACHE_CC_NOP: // no external hit
4872	{
4873	/* activity counter */
4874	if ( (( r_dcache_fsm_save == DCACHE_BIS ) \|\|( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )
4875	{
4876	m_cost_data_miss_frz++;
4877	}
4878	if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) \|\| ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) \|\|
4879	( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
4880	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
4881	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
4882	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) \|\|
4883	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
4884	{
4885	m_cost_data_tlb_miss_frz++;
4886	}
4887
4888	r_tgt_dcache_req = false;
4889	if ( r_tgt_update )
4890	{
4891	r_tgt_dcache_rsp = true;
4892	}
4893	else
4894	{
4895	r_tgt_dcache_rsp = false;
4896	}
4897
4898	r_dcache_fsm = r_dcache_fsm_save;
4899	break;
4900	}
4901	/////////////////////////
4902	case DCACHE_TLB_CC_INVAL:
4903	{
4904	/* activity counter */
4905	if ( (( r_dcache_fsm_save == DCACHE_BIS ) \|\|( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )
4906	{
4907	m_cost_data_miss_frz++;
4908	}
4909	if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) \|\| ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) \|\|
4910	( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
4911	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
4912	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
4913	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) \|\|
4914	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
4915	{
4916	m_cost_data_tlb_miss_frz++;
4917	}
4918
4919	if ( r_dcache_itlb_inval_req \|\| r_dcache_dtlb_inval_req ) break;
4920
4921	if( (( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
4922	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) \|\|
4923	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
4924	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
4925	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT ) \|\|
4926	( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) \|\| ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) \|\|
4927	( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) ) &&
4928	(((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_dtlb_inval_line.read()) )
4929	{
4930	r_dcache_inval_tlb_rsp = true;
4931	}
4932
4933	if (((r_dcache_fsm_save == DCACHE_BIS)\|\|(r_dcache_fsm_save == DCACHE_MISS_WAIT) \|\|
4934	(r_dcache_fsm_save == DCACHE_MISS_UPDT)) &&
4935	(r_dcache_tlb_nline.read() == r_dcache_dtlb_inval_line.read()))
4936	{
4937	r_dcache_inval_tlb_rsp = true;
4938	}
4939
4940	if ( !r_dcache_cc_check )
4941	{
4942	r_dcache_fsm = r_dcache_fsm_save;
4943	}
4944	else
4945	{
4946	r_dcache_fsm = DCACHE_CC_CHECK;
4947	r_dcache_cc_check = false;
4948	}
4949	r_dtlb_translation_valid = false;
4950	r_dcache_ptba_ok = false;
4951	break;
4952	}
4953	/////////////////////////
4954	case DCACHE_ITLB_CLEANUP:
4955	{
4956	if ( dreq.valid ) m_cost_data_miss_frz++;
4957
4958	r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()m_dcache_words2), r_dcache_in_itlb, false);
4959	r_dcache_itlb_cleanup_req = false;
4960	r_dcache_fsm = DCACHE_IDLE;
4961	break;
4962	}
4963	} // end switch r_dcache_fsm
4964
4965	#ifdef SOCLIB_MODULE_DEBUG
4966	std::cout << name() << " Data Response: " << drsp << std::endl;
4967	#endif
4968
4969	////////////////////////////////////////////////////////////////////////////////////
4970	// INVAL DTLB CHECK FSM
4971	////////////////////////////////////////////////////////////////////////////////////////
4972	switch(r_inval_dtlb_fsm) {
4973	/////////////////////
4974	case INVAL_DTLB_IDLE:
4975	{
4976	if ( r_dcache_dtlb_inval_req )
4977	{
4978	r_ccinval_dtlb_way = 0;
4979	r_ccinval_dtlb_set = 0;
4980	r_inval_dtlb_fsm = INVAL_DTLB_CHECK;
4981	m_cost_data_tlb_inval_frz++;
4982	}
4983	break;
4984	}
4985	////////////////////////////
4986	case INVAL_DTLB_CHECK:
4987	{
4988	m_cost_data_tlb_inval_frz++;
4989
4990	size_t way = r_ccinval_dtlb_way;
4991	size_t set = r_ccinval_dtlb_set;
4992	bool end = false;
4993	bool tlb_hit = dcache_tlb.cccheck(r_dcache_dtlb_inval_line.read(), way, set, &way, &set, &end);
4994
4995	if ( tlb_hit )
4996	{
4997	r_ccinval_dtlb_way = way;
4998	r_ccinval_dtlb_set = set;
4999	r_dtlb_cc_check_end = end;
5000	r_inval_dtlb_fsm = INVAL_DTLB_INVAL;
5001	m_cpt_data_tlb_inval++;
5002	}
5003	else
5004	{
5005	r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;
5006	}
5007	break;
5008	}
5009	/////////////////////////
5010	case INVAL_DTLB_INVAL:
5011	{
5012	m_cost_data_tlb_inval_frz++;
5013
5014	dcache_tlb.ccinval(r_ccinval_dtlb_way, r_ccinval_dtlb_set);
5015
5016	if ( !r_dtlb_cc_check_end )
5017	{
5018	r_inval_dtlb_fsm = INVAL_DTLB_CHECK;
5019	}
5020	else
5021	{
5022	r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;
5023	}
5024	break;
5025	}
5026	////////////////////
5027	case INVAL_DTLB_CLEAR:
5028	{
5029	r_dcache_dtlb_inval_req = false;
5030	r_dtlb_cc_check_end = false;
5031	r_ccinval_dtlb_way = 0;
5032	r_ccinval_dtlb_set = 0;
5033	r_inval_dtlb_fsm = INVAL_DTLB_IDLE;
5034	m_cpt_data_tlb_inval++;
5035	break;
5036	}
5037	} // end switch r_inval_itlb_fsm
5038
5039	/////////// execute one iss cycle /////////////////////////////////
5040	{
5041	uint32_t it = 0;
5042	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
5043	m_iss.executeNCycles(1, irsp, drsp, it);
5044	}
5045
5046	////////////// number of frozen cycles //////////////////////////
5047	if ( (ireq.valid && !irsp.valid) \|\| (dreq.valid && !drsp.valid) )
5048	{
5049	m_cpt_frz_cycles++;
5050	}
5051	if ( dreq.valid && !drsp.valid )
5052	{
5053	m_cpt_dcache_frz_cycles++;
5054	}
5055	for (size_t way = 0; way < m_dcache_ways; way++ )
5056	{
5057	for (size_t set = 0; set < m_dcache_sets; set++ )
5058	{
5059	if (r_dcache_in_itlb[waym_dcache_sets+set] \|\| r_dcache_in_dtlb[waym_dcache_sets+set])
5060	m_cpt_tlb_occup_dcache++;
5061	}
5062	}
5063	////////////////////////////////////////////////////////////////////////////
5064	// VCI_CMD FSM
5065	//
5066	// This FSM handles requests from both the DCACHE controler
5067	// (request registers) and the ICACHE controler (request registers).
5068	// There is 10 VCI transaction types :
5069	// - INS_TLB_READ
5070	// - INS_TLB_WRITE
5071	// - INS_MISS
5072	// - INS_UNC_MISS
5073	// - DATA_TLB_READ
5074	// - DATA_TLB_WRITE
5075	// - DATA_TLB_DIRTY
5076	// - DATA_MISS
5077	// - DATA_UNC
5078	// - DATA_WRITE
5079	// The ICACHE requests have the highest priority.
5080	// There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM and RSP_FSM
5081	// exit simultaneously the IDLE state.
5082	//////////////////////////////////////////////////////////////////////////////
5083
5084	switch (r_vci_cmd_fsm) {
5085
5086	case CMD_IDLE:
5087	if (r_vci_rsp_fsm != RSP_IDLE)
5088	break;
5089
5090	r_vci_cmd_cpt = 0;
5091
5092	if (r_icache_cleanup_req)
5093	{
5094	r_vci_cmd_fsm = CMD_INS_CLEANUP;
5095	m_cpt_icleanup_transaction++;
5096	}
5097	else if (r_dcache_cleanup_req)
5098	{
5099	r_vci_cmd_fsm = CMD_DATA_CLEANUP;
5100	m_cpt_dcleanup_transaction++;
5101	}
5102	else if (r_dcache_itlb_read_req)
5103	{
5104	r_vci_cmd_fsm = CMD_ITLB_READ;
5105	m_cpt_itlbmiss_transaction++;
5106	}
5107	else if (r_dcache_itlb_ll_acc_req)
5108	{
5109	r_vci_cmd_fsm = CMD_ITLB_ACC_LL;
5110	m_cpt_itlb_ll_transaction++;
5111	}
5112	else if (r_dcache_itlb_sc_acc_req)
5113	{
5114	r_vci_cmd_fsm = CMD_ITLB_ACC_SC;
5115	m_cpt_itlb_sc_transaction++;
5116	}
5117	else if (r_icache_miss_req)
5118	{
5119	r_vci_cmd_fsm = CMD_INS_MISS;
5120	m_cpt_imiss_transaction++;
5121	}
5122	else if (r_icache_unc_req)
5123	{
5124	r_vci_cmd_fsm = CMD_INS_UNC;
5125	m_cpt_icache_unc_transaction++;
5126	}
5127	else if (r_dcache_tlb_read_req)
5128	{
5129	r_vci_cmd_fsm = CMD_DTLB_READ;
5130	m_cpt_dtlbmiss_transaction++;
5131	}
5132	else if (r_dcache_tlb_ll_acc_req)
5133	{
5134	r_vci_cmd_fsm = CMD_DTLB_ACC_LL;
5135	m_cpt_dtlb_ll_transaction++;
5136	}
5137	else if (r_dcache_tlb_sc_acc_req)
5138	{
5139	r_vci_cmd_fsm = CMD_DTLB_ACC_SC;
5140	m_cpt_dtlb_sc_transaction++;
5141	}
5142	else if (r_dcache_tlb_ll_dirty_req)
5143	{
5144	r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL;
5145	m_cpt_dtlb_ll_dirty_transaction++;
5146	}
5147	else if (r_dcache_tlb_sc_dirty_req)
5148	{
5149	r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC;
5150	m_cpt_dtlb_sc_dirty_transaction++;
5151	}
5152	else if (r_dcache_write_req)
5153	{
5154	r_vci_cmd_fsm = CMD_DATA_WRITE;
5155	r_vci_cmd_cpt = r_wbuf.getMin();
5156	r_vci_cmd_min = r_wbuf.getMin();
5157	r_vci_cmd_max = r_wbuf.getMax();
5158	m_cpt_write_transaction++;
5159	m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1);
5160	}
5161	else if (r_dcache_miss_req)
5162	{
5163	r_vci_cmd_fsm = CMD_DATA_MISS;
5164	m_cpt_dmiss_transaction++;
5165	}
5166	else if (r_dcache_unc_req)
5167	{
5168	r_vci_cmd_fsm = CMD_DATA_UNC;
5169	m_cpt_unc_transaction++;
5170	}
5171	break;
5172
5173	case CMD_DATA_WRITE:
5174	if ( p_vci_ini_rw.cmdack.read() )
5175	{
5176	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5177	if (r_vci_cmd_cpt == r_vci_cmd_max)
5178	{
5179	r_vci_cmd_fsm = CMD_IDLE;
5180	r_wbuf.reset();
5181	}
5182	}
5183	break;
5184
5185	case CMD_INS_CLEANUP:
5186	case CMD_DATA_CLEANUP:
5187	if ( p_vci_ini_c.cmdack.read() )
5188	{
5189	r_vci_cmd_fsm = CMD_IDLE;
5190	}
5191	break;
5192
5193	default:
5194	if ( p_vci_ini_rw.cmdack.read() )
5195	{
5196	r_vci_cmd_fsm = CMD_IDLE;
5197	}
5198	break;
5199
5200	} // end switch r_vci_cmd_fsm
5201
5202	//////////////////////////////////////////////////////////////////////////
5203	// VCI_RSP FSM
5204	//
5205	// This FSM is synchronized with the VCI_CMD FSM, as both FSMs exit the
5206	// IDLE state simultaneously.
5207	//////////////////////////////////////////////////////////////////////////
5208
5209	switch (r_vci_rsp_fsm) {
5210
5211	case RSP_IDLE:
5212	assert( !p_vci_ini_rw.rspval.read() && !p_vci_ini_c.rspval.read() && "Unexpected response" );
5213
5214	if (r_vci_cmd_fsm != CMD_IDLE)
5215	break;
5216
5217	r_vci_rsp_cpt = 0;
5218	if (r_icache_cleanup_req) // ICACHE cleanup response
5219	{
5220	r_vci_rsp_fsm = RSP_INS_CLEANUP;
5221	}
5222	else if (r_dcache_cleanup_req) // DCACHE cleanup response
5223	{
5224	r_vci_rsp_fsm = RSP_DATA_CLEANUP;
5225	}
5226	else if (r_dcache_itlb_read_req) // ITLB miss response
5227	{
5228	r_vci_rsp_fsm = RSP_ITLB_READ;
5229	}
5230	else if (r_dcache_itlb_ll_acc_req) // ITLB linked load response
5231	{
5232	r_vci_rsp_fsm = RSP_ITLB_ACC_LL;
5233	}
5234	else if (r_dcache_itlb_sc_acc_req) // ITLB store conditional response
5235	{
5236	r_vci_rsp_fsm = RSP_ITLB_ACC_SC;
5237	}
5238	else if (r_icache_miss_req) // ICACHE cached miss response
5239	{
5240	r_vci_rsp_fsm = RSP_INS_MISS;
5241	}
5242	else if (r_icache_unc_req) // ICACHE uncached miss response
5243	{
5244	r_vci_rsp_fsm = RSP_INS_UNC;
5245	}
5246	else if (r_dcache_tlb_read_req) // ITLB miss response
5247	{
5248	r_vci_rsp_fsm = RSP_DTLB_READ;
5249	}
5250	else if (r_dcache_tlb_ll_acc_req) // DTLB access bits linked load response
5251	{
5252	r_vci_rsp_fsm = RSP_DTLB_ACC_LL;
5253	}
5254	else if (r_dcache_tlb_sc_acc_req) // DTLB access bits store conditional response
5255	{
5256	r_vci_rsp_fsm = RSP_DTLB_ACC_SC;
5257	}
5258	else if (r_dcache_tlb_ll_dirty_req) // DTLB dirty bit linked load response
5259	{
5260	r_vci_rsp_fsm = RSP_DTLB_DIRTY_LL;
5261	}
5262	else if (r_dcache_tlb_sc_dirty_req) // DTLB dirty bit store conditional response
5263	{
5264	r_vci_rsp_fsm = RSP_DTLB_DIRTY_SC;
5265	}
5266	else if (r_dcache_write_req) // DCACHE write response
5267	{
5268	r_vci_rsp_fsm = RSP_DATA_WRITE;
5269	}
5270	else if (r_dcache_miss_req) // DCACHE read response
5271	{
5272	r_vci_rsp_fsm = RSP_DATA_MISS;
5273	}
5274	else if (r_dcache_unc_req) // DCACHE uncached read response
5275	{
5276	r_vci_rsp_fsm = RSP_DATA_UNC;
5277	}
5278	break;
5279
5280	case RSP_ITLB_READ:
5281	m_cost_itlbmiss_transaction++;
5282	if ( ! p_vci_ini_rw.rspval.read() )
5283	break;
5284
5285	assert(r_vci_rsp_cpt != m_dcache_words &&
5286	"illegal VCI response packet for data read miss");
5287
5288	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
5289	r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
5290	if ( p_vci_ini_rw.reop.read() )
5291	{
5292	assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
5293	"illegal VCI response packet for data read miss");
5294	r_dcache_itlb_read_req = false;
5295	r_vci_rsp_fsm = RSP_IDLE;
5296	}
5297	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5298	{
5299	r_vci_rsp_data_error = true;
5300	}
5301	break;
5302
5303	case RSP_ITLB_ACC_LL:
5304	m_cost_itlb_ll_transaction++;
5305	if ( ! p_vci_ini_rw.rspval.read() )
5306	break;
5307
5308	assert(p_vci_ini_rw.reop.read() &&
5309	"illegal VCI response packet for ll tlb");
5310
5311	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5312	{
5313	r_vci_rsp_data_error = true;
5314	}
5315	else
5316	{
5317	r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
5318	}
5319	r_dcache_itlb_ll_acc_req = false;
5320	r_vci_rsp_fsm = RSP_IDLE;
5321	break;
5322
5323	case RSP_ITLB_ACC_SC:
5324	m_cost_itlb_sc_transaction++;
5325	if ( ! p_vci_ini_rw.rspval.read() )
5326	break;
5327
5328	assert(p_vci_ini_rw.reop.read() &&
5329	"illegal VCI response packet for sc tlb");
5330
5331	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5332	{
5333	r_vci_rsp_data_error = true;
5334	}
5335	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
5336	{
5337	r_dcache_tlb_sc_fail = true;
5338	//r_dcache_itlb_ll_acc_req = true;
5339	}
5340	r_dcache_itlb_sc_acc_req = false;
5341	r_vci_rsp_fsm = RSP_IDLE;
5342	break;
5343
5344	case RSP_INS_MISS:
5345	m_cost_imiss_transaction++;
5346	if ( ! p_vci_ini_rw.rspval.read() )
5347	break;
5348
5349	assert( (r_vci_rsp_cpt < m_icache_words) &&
5350	"The VCI response packet for instruction miss is too long");
5351	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
5352	r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
5353
5354	if ( p_vci_ini_rw.reop.read() )
5355	{
5356	assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
5357	"The VCI response packet for instruction miss is too short");
5358	r_icache_miss_req = false;
5359	r_vci_rsp_fsm = RSP_IDLE;
5360
5361	}
5362	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5363	{
5364	r_vci_rsp_ins_error = true;
5365	}
5366	break;
5367
5368	case RSP_INS_UNC:
5369	m_cost_icache_unc_transaction++;
5370	if ( ! p_vci_ini_rw.rspval.read() )
5371	break;
5372
5373	assert(p_vci_ini_rw.reop.read() &&
5374	"illegal VCI response packet for uncached instruction");
5375
5376	r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
5377	r_icache_buf_unc_valid = true;
5378	r_icache_unc_req = false;
5379	r_vci_rsp_fsm = RSP_IDLE;
5380
5381	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5382	{
5383	r_vci_rsp_ins_error = true;
5384	}
5385	break;
5386
5387	case RSP_DTLB_READ:
5388	m_cost_dtlbmiss_transaction++;
5389	if ( ! p_vci_ini_rw.rspval.read() )
5390	break;
5391
5392	assert(r_vci_rsp_cpt != m_dcache_words &&
5393	"illegal VCI response packet for data read miss");
5394
5395	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
5396	r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
5397	if ( p_vci_ini_rw.reop.read() )
5398	{
5399	assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
5400	"illegal VCI response packet for data read miss");
5401	r_dcache_tlb_read_req = false;
5402	r_vci_rsp_fsm = RSP_IDLE;
5403	}
5404	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5405	{
5406	r_vci_rsp_data_error = true;
5407	}
5408	break;
5409
5410	case RSP_DTLB_ACC_LL:
5411	m_cost_dtlb_ll_transaction++;
5412	if ( ! p_vci_ini_rw.rspval.read() )
5413	break;
5414
5415	assert(p_vci_ini_rw.reop.read() &&
5416	"illegal VCI response packet for ll tlb");
5417
5418	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5419	{
5420	r_vci_rsp_data_error = true;
5421	}
5422	else
5423	{
5424	r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
5425	}
5426	r_dcache_tlb_ll_acc_req = false;
5427	r_vci_rsp_fsm = RSP_IDLE;
5428	break;
5429
5430	case RSP_DTLB_ACC_SC:
5431	m_cost_dtlb_sc_transaction++;
5432	if ( ! p_vci_ini_rw.rspval.read() )
5433	break;
5434
5435	assert(p_vci_ini_rw.reop.read() &&
5436	"illegal VCI response packet for sc tlb");
5437
5438	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5439	{
5440	r_vci_rsp_data_error = true;
5441	}
5442	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
5443	{
5444	r_dcache_tlb_sc_fail = true;
5445	//r_dcache_tlb_ll_acc_req = true;
5446	}
5447	r_dcache_tlb_sc_acc_req = false;
5448	r_vci_rsp_fsm = RSP_IDLE;
5449	break;
5450
5451	case RSP_DTLB_DIRTY_LL:
5452	m_cost_dtlb_ll_dirty_transaction++;
5453	if ( ! p_vci_ini_rw.rspval.read() )
5454	break;
5455
5456	assert(p_vci_ini_rw.reop.read() &&
5457	"illegal VCI response packet for ll tlb");
5458
5459	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5460	{
5461	r_vci_rsp_data_error = true;
5462	}
5463	else
5464	{
5465	r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
5466	}
5467	r_dcache_tlb_ll_dirty_req = false;
5468	r_vci_rsp_fsm = RSP_IDLE;
5469	break;
5470
5471	case RSP_DTLB_DIRTY_SC:
5472	m_cost_dtlb_sc_dirty_transaction++;
5473	if ( ! p_vci_ini_rw.rspval.read() )
5474	break;
5475
5476	assert(p_vci_ini_rw.reop.read() &&
5477	"illegal VCI response packet for sc tlb");
5478
5479	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5480	{
5481	r_vci_rsp_data_error = true;
5482	}
5483	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
5484	{
5485	r_dcache_tlb_sc_fail = true;
5486	//r_dcache_tlb_ll_dirty_req = true;
5487	}
5488	r_dcache_tlb_sc_dirty_req = false;
5489	r_vci_rsp_fsm = RSP_IDLE;
5490	break;
5491
5492	case RSP_DATA_UNC:
5493	m_cost_unc_transaction++;
5494	if ( ! p_vci_ini_rw.rspval.read() )
5495	break;
5496
5497	assert(p_vci_ini_rw.reop.read() &&
5498	"illegal VCI response packet for data read uncached");
5499
5500	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5501	{
5502	r_vci_rsp_data_error = true;
5503	}
5504	else
5505	{
5506	r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
5507	r_dcache_buf_unc_valid = true;
5508	}
5509	r_dcache_unc_req = false;
5510	r_vci_rsp_fsm = RSP_IDLE;
5511	break;
5512
5513	case RSP_DATA_MISS:
5514	m_cost_dmiss_transaction++;
5515	if ( ! p_vci_ini_rw.rspval.read() )
5516	break;
5517
5518	assert(r_vci_rsp_cpt != m_dcache_words &&
5519	"illegal VCI response packet for data read miss");
5520
5521	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
5522	r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
5523	if ( p_vci_ini_rw.reop.read() )
5524	{
5525	assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
5526	"illegal VCI response packet for data read miss");
5527	r_dcache_miss_req = false;
5528	r_vci_rsp_fsm = RSP_IDLE;
5529	}
5530	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5531	{
5532	r_vci_rsp_data_error = true;
5533	}
5534	break;
5535
5536	case RSP_DATA_WRITE:
5537	m_cost_write_transaction++;
5538	if ( ! p_vci_ini_rw.rspval.read() )
5539	break;
5540
5541	if ( p_vci_ini_rw.reop.read() )
5542	{
5543	r_vci_rsp_fsm = RSP_IDLE;
5544	r_dcache_write_req = false;
5545	}
5546	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5547	{
5548	m_iss.setWriteBerr();
5549	}
5550	break;
5551
5552	case RSP_INS_CLEANUP:
5553	case RSP_DATA_CLEANUP:
5554	if ( r_vci_rsp_fsm == RSP_INS_CLEANUP )
5555	{
5556	m_cost_icleanup_transaction++;
5557	}
5558	else
5559	{
5560	m_cost_dcleanup_transaction++;
5561	}
5562
5563	if ( ! p_vci_ini_c.rspval.read() )
5564	break;
5565	assert( p_vci_ini_c.reop.read() &&
5566	"illegal VCI response packet for icache cleanup");
5567	assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&
5568	"error in response packet for icache cleanup");
5569
5570	if ( r_vci_rsp_fsm == RSP_INS_CLEANUP )
5571	{
5572	r_icache_cleanup_req = false;
5573	}
5574	else
5575	{
5576	r_dcache_cleanup_req = false;
5577	}
5578	r_vci_rsp_fsm = RSP_IDLE;
5579	break;
5580
5581	} // end switch r_vci_rsp_fsm
5582	} // end transition()
5583
5584	///////////////////////
5585	tmpl(void)::genMoore()
5586	///////////////////////
5587	{
5588	// VCI initiator response
5589
5590	p_vci_ini_rw.rspack = true;
5591	p_vci_ini_c.rspack = true;
5592
5593	// VCI initiator command
5594
5595	p_vci_ini_rw.pktid = 0;
5596	p_vci_ini_rw.srcid = m_srcid_rw;
5597	p_vci_ini_rw.cons = false;
5598	p_vci_ini_rw.wrap = false;
5599	p_vci_ini_rw.contig = true;
5600	p_vci_ini_rw.clen = 0;
5601	p_vci_ini_rw.cfixed = false;
5602
5603	p_vci_ini_c.cmdval = false;
5604	p_vci_ini_c.address = 0;
5605	p_vci_ini_c.wdata = 0;
5606	p_vci_ini_c.be = 0;
5607	p_vci_ini_c.plen = 0;
5608	p_vci_ini_c.cmd = vci_param::CMD_NOP;
5609	p_vci_ini_c.trdid = 0;
5610	p_vci_ini_c.pktid = 0;
5611	p_vci_ini_c.srcid = 0;
5612	p_vci_ini_c.cons = false;
5613	p_vci_ini_c.wrap = false;
5614	p_vci_ini_c.contig = false;
5615	p_vci_ini_c.clen = 0;
5616	p_vci_ini_c.cfixed = false;
5617	p_vci_ini_c.eop = false;
5618
5619	switch (r_vci_cmd_fsm) {
5620
5621	case CMD_IDLE:
5622	p_vci_ini_rw.cmdval = false;
5623	p_vci_ini_rw.address = 0;
5624	p_vci_ini_rw.wdata = 0;
5625	p_vci_ini_rw.be = 0;
5626	p_vci_ini_rw.trdid = 0;
5627	p_vci_ini_rw.plen = 0;
5628	p_vci_ini_rw.cmd = vci_param::CMD_NOP;
5629	p_vci_ini_rw.eop = false;
5630	break;
5631
5632	case CMD_ITLB_READ:
5633	p_vci_ini_rw.cmdval = true;
5634	p_vci_ini_rw.address = r_icache_paddr_save.read() & m_dcache_yzmask;
5635	p_vci_ini_rw.wdata = 0;
5636	p_vci_ini_rw.be = 0xF;
5637	p_vci_ini_rw.trdid = 1; // via data cache cached read
5638	p_vci_ini_rw.plen = m_dcache_words << 2;
5639	p_vci_ini_rw.cmd = vci_param::CMD_READ;
5640	p_vci_ini_rw.eop = true;
5641	break;
5642
5643	case CMD_ITLB_ACC_LL:
5644	p_vci_ini_rw.cmdval = true;
5645	p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
5646	p_vci_ini_rw.wdata = 0;
5647	p_vci_ini_rw.be = 0xF;
5648	p_vci_ini_rw.trdid = 0; // data cache uncached read
5649	p_vci_ini_rw.plen = 4;
5650	p_vci_ini_rw.cmd = vci_param::CMD_LOCKED_READ;
5651	p_vci_ini_rw.eop = true;
5652	break;
5653
5654	case CMD_ITLB_ACC_SC:
5655	p_vci_ini_rw.cmdval = true;
5656	p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
5657	p_vci_ini_rw.wdata = r_icache_pte_update.read();
5658	p_vci_ini_rw.be = 0xF;
5659	p_vci_ini_rw.trdid = 0; // data cache uncached read
5660	p_vci_ini_rw.plen = 4;
5661	p_vci_ini_rw.cmd = vci_param::CMD_STORE_COND;
5662	p_vci_ini_rw.eop = true;
5663	break;
5664
5665	case CMD_INS_MISS:
5666	p_vci_ini_rw.cmdval = true;
5667	p_vci_ini_rw.address = r_icache_paddr_save.read() & m_icache_yzmask;
5668	p_vci_ini_rw.wdata = 0;
5669	p_vci_ini_rw.be = 0xF;
5670	p_vci_ini_rw.trdid = 3; // ins cache cached read
5671	p_vci_ini_rw.plen = m_icache_words << 2;
5672	p_vci_ini_rw.cmd = vci_param::CMD_READ;
5673	p_vci_ini_rw.eop = true;
5674	break;
5675
5676	case CMD_INS_UNC:
5677	p_vci_ini_rw.cmdval = true;
5678	p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
5679	p_vci_ini_rw.wdata = 0;
5680	p_vci_ini_rw.be = 0xF;
5681	p_vci_ini_rw.trdid = 2; // ins cache uncached read
5682	p_vci_ini_rw.plen = 4;
5683	p_vci_ini_rw.cmd = vci_param::CMD_READ;
5684	p_vci_ini_rw.eop = true;
5685	break;
5686
5687	case CMD_DTLB_READ:
5688	p_vci_ini_rw.cmdval = true;
5689	p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & m_dcache_yzmask;
5690	p_vci_ini_rw.wdata = 0;
5691	p_vci_ini_rw.be = 0xF;
5692	p_vci_ini_rw.trdid = 1; // via dcache cached read
5693	p_vci_ini_rw.plen = m_dcache_words << 2;
5694	p_vci_ini_rw.cmd = vci_param::CMD_READ;
5695	p_vci_ini_rw.eop = true;
5696	break;
5697
5698	case CMD_DTLB_ACC_LL:
5699	p_vci_ini_rw.cmdval = true;
5700	p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
5701	p_vci_ini_rw.wdata = 0;
5702	p_vci_ini_rw.be = 0xF;
5703	p_vci_ini_rw.trdid = 0; // data cache uncached read
5704	p_vci_ini_rw.plen = 4;
5705	p_vci_ini_rw.cmd = vci_param::CMD_LOCKED_READ;
5706	p_vci_ini_rw.eop = true;
5707	break;
5708
5709	case CMD_DTLB_ACC_SC:
5710	p_vci_ini_rw.cmdval = true;
5711	p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
5712	p_vci_ini_rw.wdata = r_dcache_pte_update.read();
5713	p_vci_ini_rw.be = 0xF;
5714	p_vci_ini_rw.trdid = 0; // data cache uncached read
5715	p_vci_ini_rw.plen = 4;
5716	p_vci_ini_rw.cmd = vci_param::CMD_STORE_COND;
5717	p_vci_ini_rw.eop = true;
5718	break;
5719
5720	case CMD_DTLB_DIRTY_LL:
5721	p_vci_ini_rw.cmdval = true;
5722	p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
5723	p_vci_ini_rw.wdata = 0;
5724	p_vci_ini_rw.be = 0xF;
5725	p_vci_ini_rw.trdid = 0; // data cache uncached read
5726	p_vci_ini_rw.plen = 4;
5727	p_vci_ini_rw.cmd = vci_param::CMD_LOCKED_READ;
5728	p_vci_ini_rw.eop = true;
5729	break;
5730
5731	case CMD_DTLB_DIRTY_SC:
5732	p_vci_ini_rw.cmdval = true;
5733	p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
5734	p_vci_ini_rw.wdata = r_dcache_pte_update.read();
5735	p_vci_ini_rw.be = 0xF;
5736	p_vci_ini_rw.trdid = 0; // data cache uncached read
5737	p_vci_ini_rw.plen = 4;
5738	p_vci_ini_rw.cmd = vci_param::CMD_STORE_COND;
5739	p_vci_ini_rw.eop = true;
5740	break;
5741
5742	case CMD_DATA_UNC:
5743	p_vci_ini_rw.cmdval = true;
5744	p_vci_ini_rw.address = r_dcache_paddr_save.read() & ~0x3;
5745	p_vci_ini_rw.trdid = 0; // data cache uncached read
5746	p_vci_ini_rw.plen = 4;
5747	p_vci_ini_rw.eop = true;
5748	switch(r_dcache_type_save) {
5749	case iss_t::DATA_READ:
5750	p_vci_ini_rw.wdata = 0;
5751	p_vci_ini_rw.be = r_dcache_be_save.read();
5752	p_vci_ini_rw.cmd = vci_param::CMD_READ;
5753	break;
5754	case iss_t::DATA_LL:
5755	p_vci_ini_rw.wdata = 0;
5756	p_vci_ini_rw.be = 0xF;
5757	p_vci_ini_rw.cmd = vci_param::CMD_LOCKED_READ;
5758	break;
5759	case iss_t::DATA_SC:
5760	p_vci_ini_rw.wdata = r_dcache_wdata_save.read();
5761	p_vci_ini_rw.be = 0xF;
5762	p_vci_ini_rw.cmd = vci_param::CMD_STORE_COND;
5763	break;
5764	default:
5765	assert("this should not happen");
5766	}
5767	break;
5768
5769	case CMD_DATA_WRITE:
5770	p_vci_ini_rw.cmdval = true;
5771	p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt);
5772	p_vci_ini_rw.wdata = r_wbuf.getData(r_vci_cmd_cpt);
5773	p_vci_ini_rw.be = r_wbuf.getBe(r_vci_cmd_cpt);
5774	p_vci_ini_rw.trdid = 0; // data cache write
5775	p_vci_ini_rw.plen = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
5776	p_vci_ini_rw.cmd = vci_param::CMD_WRITE;
5777	p_vci_ini_rw.eop = (r_vci_cmd_cpt == r_vci_cmd_max);
5778	break;
5779
5780	case CMD_DATA_MISS:
5781	p_vci_ini_rw.cmdval = true;
5782	p_vci_ini_rw.address = r_dcache_paddr_save.read() & m_dcache_yzmask;
5783	p_vci_ini_rw.wdata = 0;
5784	p_vci_ini_rw.be = 0xF;
5785	p_vci_ini_rw.trdid = 1; // data cache cached read
5786	p_vci_ini_rw.plen = m_dcache_words << 2;
5787	p_vci_ini_rw.cmd = vci_param::CMD_READ;
5788	p_vci_ini_rw.eop = true;
5789	break;
5790
5791	case CMD_INS_CLEANUP:
5792	case CMD_DATA_CLEANUP:
5793	p_vci_ini_rw.cmdval = false;
5794	p_vci_ini_rw.address = 0;
5795	p_vci_ini_rw.wdata = 0;
5796	p_vci_ini_rw.be = 0;
5797	p_vci_ini_rw.trdid = 0;
5798	p_vci_ini_rw.plen = 0;
5799	p_vci_ini_rw.cmd = vci_param::CMD_NOP;
5800	p_vci_ini_rw.eop = false;
5801
5802	p_vci_ini_c.cmdval = true;
5803	if ( r_vci_cmd_fsm == CMD_INS_CLEANUP )
5804	{
5805	p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2);
5806	p_vci_ini_c.trdid = 1; // cleanup instruction
5807	}
5808	else
5809	{
5810	p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
5811	p_vci_ini_c.trdid = 0; // cleanup data
5812	}
5813	p_vci_ini_c.wdata = 0;
5814	p_vci_ini_c.be = 0;
5815	p_vci_ini_c.plen = 4;
5816	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
5817	p_vci_ini_c.pktid = 0;
5818	p_vci_ini_c.srcid = m_srcid_c;
5819	p_vci_ini_c.cons = false;
5820	p_vci_ini_c.wrap = false;
5821	p_vci_ini_c.contig = false;
5822	p_vci_ini_c.clen = 0;
5823	p_vci_ini_c.cfixed = false;
5824	p_vci_ini_c.eop = true;
5825	break;
5826
5827	} // end switch r_vci_cmd_fsm
5828
5829	// VCI_TGT
5830	switch ( r_vci_tgt_fsm.read() ) {
5831
5832	case TGT_IDLE:
5833	case TGT_UPDT_WORD:
5834	case TGT_UPDT_DATA:
5835	p_vci_tgt.cmdack = true;
5836	p_vci_tgt.rspval = false;
5837	break;
5838
5839	case TGT_RSP_BROADCAST:
5840	p_vci_tgt.cmdack = false;
5841	p_vci_tgt.rspval = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && ( r_tgt_icache_rsp \| r_tgt_dcache_rsp );
5842	p_vci_tgt.rsrcid = r_tgt_srcid.read();
5843	p_vci_tgt.rpktid = r_tgt_pktid.read();
5844	p_vci_tgt.rtrdid = r_tgt_trdid.read();
5845	p_vci_tgt.rdata = 0;
5846	p_vci_tgt.rerror = 0;
5847	p_vci_tgt.reop = true;
5848	break;
5849
5850	case TGT_RSP_ICACHE:
5851	p_vci_tgt.cmdack = false;
5852	p_vci_tgt.rspval = !r_tgt_icache_req.read() && r_tgt_icache_rsp.read();
5853	p_vci_tgt.rsrcid = r_tgt_srcid.read();
5854	p_vci_tgt.rpktid = r_tgt_pktid.read();
5855	p_vci_tgt.rtrdid = r_tgt_trdid.read();
5856	p_vci_tgt.rdata = 0;
5857	p_vci_tgt.rerror = 0;
5858	p_vci_tgt.reop = true;
5859	break;
5860
5861	case TGT_RSP_DCACHE:
5862	p_vci_tgt.cmdack = false;
5863	p_vci_tgt.rspval = !r_tgt_dcache_req.read() && r_tgt_dcache_rsp.read();
5864	p_vci_tgt.rsrcid = r_tgt_srcid.read();
5865	p_vci_tgt.rpktid = r_tgt_pktid.read();
5866	p_vci_tgt.rtrdid = r_tgt_trdid.read();
5867	p_vci_tgt.rdata = 0;
5868	p_vci_tgt.rerror = 0;
5869	p_vci_tgt.reop = true;
5870	break;
5871
5872	case TGT_REQ_BROADCAST:
5873	case TGT_REQ_ICACHE:
5874	case TGT_REQ_DCACHE:
5875	p_vci_tgt.cmdack = false;
5876	p_vci_tgt.rspval = false;
5877	break;
5878
5879	} // end switch TGT_FSM
5880
5881	#ifdef SOCLIB_MODULE_DEBUG
5882	std::cout << name()
5883	<< " Moore R/W:" << std::hex
5884	<< " p_vci_ini_rw.cmdval: " << p_vci_ini_rw.cmdval
5885	<< " p_vci_ini_rw.address: " << p_vci_ini_rw.address
5886	<< " p_vci_ini_rw.wdata: " << p_vci_ini_rw.wdata
5887	<< " p_vci_ini_rw.cmd: " << p_vci_ini_rw.cmd
5888	<< " p_vci_ini_rw.eop: " << p_vci_ini_rw.eop
5889	<< std::endl;
5890
5891	std::cout << name()
5892	<< " Moore TGT:" << std::hex
5893	<< " p_vci_tgt.rspval: " << p_vci_tgt.rspval
5894	<< std::endl;
5895
5896	std::cout << name()
5897	<< " Moore Cleanup:" << std::hex
5898	<< " p_vci_ini_c.cmdval: " << p_vci_ini_c.cmdval
5899	<< " p_vci_ini_c.address: " << p_vci_ini_c.address
5900	<< " p_vci_ini_c.trdid: " << p_vci_ini_c.trdid
5901	<< " p_vci_ini_c.cmd: " << p_vci_ini_c.cmd
5902	<< " p_vci_ini_c.eop: " << p_vci_ini_c.eop
5903	<< std::endl;
5904	#endif
5905	}
5906
5907	}}
5908
5909	// Local Variables:
5910	// tab-width: 4
5911	// c-basic-offset: 4
5912	// c-file-offsets:((innamespace . 0)(inline-open . 0))
5913	// indent-tabs-mode: nil
5914	// End:
5915
5916	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
5917
5918
5919
5920
5921
5922
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5925

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