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vci_cc_vcache_wrapper2_v1.cpp @ 96

Last change on this file since 96 was 96, checked in by gao, 14 years ago
Redo ins TLB access bit update when it miss in dcache
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1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper2_v1.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#include <cassert>
28	#include "arithmetics.h"
29	#include "../include/vci_cc_vcache_wrapper2_v1.h"
30
31	namespace soclib {
32	namespace caba {
33
34	//#define SOCLIB_MODULE_DEBUG
35	#ifdef SOCLIB_MODULE_DEBUG
36	namespace {
37	const char *icache_fsm_state_str[] = {
38	"ICACHE_IDLE",
39	"ICACHE_BIS",
40	"ICACHE_TLB1_READ",
41	"ICACHE_TLB1_WRITE",
42	"ICACHE_TLB1_UPDT",
43	"ICACHE_TLB2_READ",
44	"ICACHE_TLB2_WRITE",
45	"ICACHE_TLB2_UPDT",
46	"ICACHE_SW_FLUSH",
47	"ICACHE_TLB_FLUSH",
48	"ICACHE_CACHE_FLUSH",
49	"ICACHE_TLB_INVAL",
50	"ICACHE_CACHE_INVAL",
51	"ICACHE_CACHE_INVAL_PA",
52	"ICACHE_MISS_WAIT",
53	"ICACHE_UNC_WAIT",
54	"ICACHE_MISS_UPDT",
55	"ICACHE_ERROR",
56	"ICACHE_CC_INVAL",
57	"ICACHE_TLB_CC_INVAL",
58	};
59	const char *dcache_fsm_state_str[] = {
60	"DCACHE_IDLE",
61	"DCACHE_BIS",
62	"DCACHE_DTLB1_READ_CACHE",
63	"DCACHE_TLB1_LL_WAIT",
64	"DCACHE_TLB1_SC_WAIT",
65	"DCACHE_TLB1_READ",
66	"DCACHE_TLB1_READ_UPDT",
67	"DCACHE_TLB1_UPDT",
68	"DCACHE_DTLB2_READ_CACHE",
69	"DCACHE_TLB2_LL_WAIT",
70	"DCACHE_TLB2_SC_WAIT",
71	"DCACHE_TLB2_READ",
72	"DCACHE_TLB2_READ_UPDT",
73	"DCACHE_TLB2_UPDT",
74	"DCACHE_CTXT_SWITCH",
75	"DCACHE_ICACHE_FLUSH",
76	"DCACHE_DCACHE_FLUSH",
77	"DCACHE_ITLB_INVAL",
78	"DCACHE_DTLB_INVAL",
79	"DCACHE_ICACHE_INVAL",
80	"DCACHE_DCACHE_INVAL",
81	"DCACHE_ICACHE_INVAL_PA",
82	"DCACHE_DCACHE_INVAL_PA",
83	"DCACHE_DCACHE_SYNC",
84	"DCACHE_LL_DIRTY_WAIT",
85	"DCACHE_SC_DIRTY_WAIT",
86	"DCACHE_WRITE_UPDT",
87	"DCACHE_WRITE_DIRTY",
88	"DCACHE_WRITE_REQ",
89	"DCACHE_MISS_WAIT",
90	"DCACHE_MISS_UPDT",
91	"DCACHE_UNC_WAIT",
92	"DCACHE_ERROR",
93	"DCACHE_ITLB_READ",
94	"DCACHE_ITLB_UPDT",
95	"DCACHE_ITLB_LL_WAIT",
96	"DCACHE_ITLB_SC_WAIT",
97	"DCACHE_CC_CHECK",
98	"DCACHE_CC_INVAL",
99	"DCACHE_CC_UPDT",
100	"DCACHE_CC_NOP",
101	"DCACHE_TLB_CC_INVAL",
102	"DCACHE_ITLB_CLEANUP",
103	};
104	const char *cmd_fsm_state_str[] = {
105	"CMD_IDLE",
106	"CMD_ITLB_READ",
107	"CMD_ITLB_ACC_LL",
108	"CMD_ITLB_ACC_SC",
109	"CMD_INS_MISS",
110	"CMD_INS_UNC",
111	"CMD_DTLB_READ",
112	"CMD_DTLB_ACC_LL",
113	"CMD_DTLB_ACC_SC",
114	"CMD_DTLB_DIRTY_LL",
115	"CMD_DTLB_DIRTY_SC",
116	"CMD_DATA_UNC",
117	"CMD_DATA_MISS",
118	"CMD_DATA_WRITE",
119	"CMD_INS_CLEANUP",
120	"CMD_DATA_CLEANUP",
121	};
122	const char *rsp_fsm_state_str[] = {
123	"RSP_IDLE",
124	"RSP_ITLB_READ",
125	"RSP_ITLB_ACC_LL",
126	"RSP_ITLB_ACC_SC",
127	"RSP_INS_MISS",
128	"RSP_INS_UNC",
129	"RSP_DTLB_READ",
130	"RSP_DTLB_ACC_LL",
131	"RSP_DTLB_ACC_SC",
132	"RSP_DTLB_DIRTY_LL",
133	"RSP_DTLB_DIRTY_SC",
134	"RSP_DATA_MISS",
135	"RSP_DATA_UNC",
136	"RSP_DATA_WRITE",
137	"RSP_INS_CLEANUP",
138	"RSP_DATA_CLEANUP",
139	};
140	const char *tgt_fsm_state_str[] = {
141	"TGT_IDLE",
142	"TGT_UPDT_WORD",
143	"TGT_UPDT_DATA",
144	"TGT_REQ_BROADCAST",
145	"TGT_REQ_ICACHE",
146	"TGT_REQ_DCACHE",
147	"TGT_RSP_BROADCAST",
148	"TGT_RSP_ICACHE",
149	"TGT_RSP_DCACHE",
150	};
151	const char *inval_itlb_fsm_state_str[] = {
152	"INVAL_ITLB_IDLE",
153	"INVAL_ITLB_CHECK" ,
154	"INVAL_ITLB_INVAL",
155	"INVAL_ITLB_CLEAR",
156	};
157	const char *inval_dtlb_fsm_state_str[] = {
158	"INVAL_DTLB_IDLE",
159	"INVAL_DTLB_CHECK",
160	"INVAL_DTLB_INVAL",
161	"INVAL_DTLB_CLEAR",
162	};
163	}
164	#endif
165
166	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper2V1<vci_param, iss_t>
167
168	using soclib::common::uint32_log2;
169
170	/***********************************************/
171	tmpl(/**/)::VciCcVCacheWrapper2V1(
172	sc_module_name name,
173	int proc_id,
174	const soclib::common::MappingTable &mtp,
175	const soclib::common::MappingTable &mtc,
176	const soclib::common::IntTab &initiator_index_rw,
177	const soclib::common::IntTab &initiator_index_c,
178	const soclib::common::IntTab &target_index,
179	size_t itlb_ways,
180	size_t itlb_sets,
181	size_t dtlb_ways,
182	size_t dtlb_sets,
183	size_t icache_ways,
184	size_t icache_sets,
185	size_t icache_words,
186	size_t dcache_ways,
187	size_t dcache_sets,
188	size_t dcache_words,
189	size_t write_buf_size )
190	/***********************************************/
191	: soclib::caba::BaseModule(name),
192
193	p_clk("clk"),
194	p_resetn("resetn"),
195	p_vci_ini_rw("vci_ini_rw"),
196	p_vci_ini_c("vci_ini_c"),
197	p_vci_tgt("vci_tgt"),
198
199	m_cacheability_table(mtp.getCacheabilityTable()),
200	m_segment(mtc.getSegment(target_index)),
201	m_iss(this->name(), proc_id),
202	m_srcid_rw(mtp.indexForId(initiator_index_rw)),
203	m_srcid_c(mtp.indexForId(initiator_index_c)),
204
205	m_itlb_ways(itlb_ways),
206	m_itlb_sets(itlb_sets),
207
208	m_dtlb_ways(dtlb_ways),
209	m_dtlb_sets(dtlb_sets),
210
211	m_icache_ways(icache_ways),
212	m_icache_sets(icache_sets),
213	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
214	m_icache_words(icache_words),
215
216	m_dcache_ways(dcache_ways),
217	m_dcache_sets(dcache_sets),
218	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
219	m_dcache_words(dcache_words),
220
221	m_write_buf_size(write_buf_size),
222	m_paddr_nbits(vci_param::N),
223
224	icache_tlb(itlb_ways,itlb_sets,vci_param::N),
225	dcache_tlb(dtlb_ways,dtlb_sets,vci_param::N),
226
227	r_dcache_fsm("r_dcache_fsm"),
228	r_dcache_paddr_save("r_dcache_paddr_save"),
229	r_dcache_wdata_save("r_dcache_wdata_save"),
230	r_dcache_rdata_save("r_dcache_rdata_save"),
231	r_dcache_type_save("r_dcache_type_save"),
232	r_dcache_be_save("r_dcache_be_save"),
233	r_dcache_cached_save("r_dcache_cached_save"),
234	r_dcache_tlb_paddr("r_dcache_tlb_paddr"),
235	r_dcache_miss_req("r_dcache_miss_req"),
236	r_dcache_unc_req("r_dcache_unc_req"),
237	r_dcache_write_req("r_dcache_write_req"),
238	r_dcache_tlb_read_req("r_dcache_tlb_read_req"),
239
240	r_dcache_tlb_ll_acc_req("r_dcache_tlb_ll_acc_req"),
241	r_dcache_tlb_sc_acc_req("r_dcache_tlb_sc_acc_req"),
242	r_dcache_tlb_ll_dirty_req("r_dcache_tlb_ll_dirty_req"),
243	r_dcache_tlb_sc_dirty_req("r_dcache_tlb_sc_dirty_req"),
244	r_dcache_tlb_ptba_read("r_dcache_tlb_ptba_read"),
245	r_dcache_xtn_req("r_dcache_xtn_req"),
246
247	r_dcache_fsm_save("r_dcache_fsm_save"),
248	r_dcache_cleanup_req("r_dcache_cleanup_req"),
249	r_dcache_inval_rsp("r_dcache_inval_rsp"),
250
251	r_icache_fsm("r_icache_fsm"),
252	r_icache_paddr_save("r_icache_paddr_save"),
253	r_icache_miss_req("r_icache_miss_req"),
254	r_icache_unc_req("r_icache_unc_req"),
255	r_dcache_itlb_read_req("r_dcache_itlb_read_req"),
256	r_dcache_itlb_ll_acc_req("r_dcache_itlb_ll_acc_req"),
257	r_dcache_itlb_sc_acc_req("r_dcache_itlb_sc_acc_req"),
258
259	r_itlb_read_dcache_req("r_itlb_read_dcache_req"),
260	r_itlb_k_read_dcache("r_itlb_k_read_dcache"),
261	r_itlb_acc_dcache_req("r_itlb_acc_dcache_req"),
262	r_dcache_rsp_itlb_error("r_dcache_rsp_itlb_error"),
263
264	r_icache_fsm_save("r_icache_fsm_save"),
265	r_icache_cleanup_req("r_icache_cleanup_req"),
266	r_icache_inval_rsp("r_icache_inval_rsp"),
267
268	r_vci_cmd_fsm("r_vci_cmd_fsm"),
269	r_vci_cmd_min("r_vci_cmd_min"),
270	r_vci_cmd_max("r_vci_cmd_max"),
271	r_vci_cmd_cpt("r_vci_cmd_cpt"),
272
273	r_vci_rsp_fsm("r_vci_rsp_fsm"),
274	r_vci_rsp_cpt("r_vci_rsp_cpt"),
275	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
276	r_vci_rsp_data_error("r_vci_rsp_data_error"),
277	r_dcache_tlb_sc_fail("r_dcache_tlb_sc_fail"),
278
279	r_vci_tgt_fsm("r_vci_tgt_fsm"),
280	r_tgt_addr("r_tgt_addr"),
281	r_tgt_word("r_tgt_word"),
282	r_tgt_update("r_tgt_update"),
283	r_tgt_srcid("r_tgt_srcid"),
284	r_tgt_pktid("r_tgt_pktid"),
285	r_tgt_trdid("r_tgt_trdid"),
286	r_tgt_icache_req("r_tgt_icache_req"),
287	r_tgt_dcache_req("r_tgt_dcache_req"),
288
289	r_inval_itlb_fsm("r_inval_itlb_fsm"),
290	r_dcache_itlb_inval_req("r_dcache_itlb_inval_req"),
291	r_dcache_itlb_inval_line("r_dcache_itlb_inval_line"),
292	r_itlb_cc_check_end("r_itlb_cc_check_end"),
293	r_ccinval_itlb_way("r_ccinval_itlb_way"),
294	r_ccinval_itlb_set("r_ccinval_itlb_set"),
295	r_icache_inval_tlb_rsp("r_icache_inval_tlb_rsp"),
296	r_icache_tlb_nline("r_icache_tlb_nline"),
297
298	r_inval_dtlb_fsm("r_inval_dtlb_fsm"),
299	r_dcache_dtlb_inval_req("r_dcache_dtlb_inval_req"),
300	r_dcache_dtlb_inval_line("r_dcache_dtlb_inval_line"),
301	r_dtlb_cc_check_end("r_dtlb_cc_check_end"),
302	r_ccinval_dtlb_way("r_ccinval_dtlb_way"),
303	r_ccinval_dtlb_set("r_ccinval_dtlb_set"),
304	r_dcache_inval_tlb_rsp("r_dcache_inval_tlb_rsp"),
305	r_dcache_tlb_nline("r_dcache_tlb_nline"),
306
307	r_dcache_itlb_cleanup_req("r_dcache_itlb_cleanup_req"),
308	r_dcache_itlb_cleanup_line("r_dcache_itlb_cleanup_line"),
309
310	r_dcache_dtlb_cleanup_req("r_dcache_dtlb_cleanup_req"),
311	r_dcache_dtlb_cleanup_line("r_dcache_dtlb_cleanup_line"),
312
313	r_wbuf("wbuf", write_buf_size ),
314	r_icache("icache", icache_ways, icache_sets, icache_words),
315	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
316	{
317	r_icache_miss_buf = new data_t[icache_words];
318	r_dcache_miss_buf = new data_t[dcache_words];
319	r_tgt_buf = new data_t[dcache_words];
320	r_tgt_val = new bool[dcache_words];
321	r_dcache_in_itlb = new bool[dcache_ways*dcache_sets];
322	r_dcache_in_dtlb = new bool[dcache_ways*dcache_sets];
323
324	SC_METHOD(transition);
325	dont_initialize();
326	sensitive << p_clk.pos();
327
328	SC_METHOD(genMoore);
329	dont_initialize();
330	sensitive << p_clk.neg();
331
332	typename iss_t::CacheInfo cache_info;
333	cache_info.has_mmu = true;
334	cache_info.icache_line_size = icache_words*sizeof(data_t);
335	cache_info.icache_assoc = icache_ways;
336	cache_info.icache_n_lines = icache_sets;
337	cache_info.dcache_line_size = dcache_words*sizeof(data_t);
338	cache_info.dcache_assoc = dcache_ways;
339	cache_info.dcache_n_lines = dcache_sets;
340	m_iss.setCacheInfo(cache_info);
341	}
342
343	/////////////////////////////////////
344	tmpl(/**/)::~VciCcVCacheWrapper2V1()
345	/////////////////////////////////////
346	{
347	delete [] r_icache_miss_buf;
348	delete [] r_dcache_miss_buf;
349	delete [] r_tgt_val;
350	delete [] r_tgt_buf;
351	delete [] r_dcache_in_itlb;
352	delete [] r_dcache_in_dtlb;
353	}
354
355	////////////////////////
356	tmpl(void)::print_cpi()
357	////////////////////////
358	{
359	std::cout << name() << " CPI = "
360	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
361	}
362
363	////////////////////////
364	tmpl(void)::print_stats()
365	////////////////////////
366	{
367	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
368	std::cout << name() << std::endl
369	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
370	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
371	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
372	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
373	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
374	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
375	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
376	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
377	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
378	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
379	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
380	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
381	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
382	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
383	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
384	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
385	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
386	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
387	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
388	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
389	<< "- DCACHE FROZEN BY TLB OP= " << (float)(m_cost_ins_tlb_occup_cache_frz+m_cost_data_tlb_occup_cache_frz)/m_cpt_dcache_frz_cycles << std::endl
390	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
391	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
392	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
393	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
394	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
395	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
396	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
397	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
398	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
399	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
400	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
401	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
402	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
403	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
404	}
405
406	/*************************************************/
407	tmpl(void)::transition()
408	/*************************************************/
409	{
410	if ( ! p_resetn.read() )
411	{
412	m_iss.reset();
413
414	r_dcache_fsm = DCACHE_IDLE;
415	r_icache_fsm = ICACHE_IDLE;
416	r_vci_cmd_fsm = CMD_IDLE;
417	r_vci_rsp_fsm = RSP_IDLE;
418	r_vci_tgt_fsm = TGT_IDLE;
419	r_inval_itlb_fsm = INVAL_ITLB_IDLE;
420	r_inval_dtlb_fsm = INVAL_DTLB_IDLE;
421
422	// write buffer & caches
423	r_wbuf.reset();
424	r_icache.reset();
425	r_dcache.reset();
426
427	icache_tlb.reset();
428	dcache_tlb.reset();
429
430	std::memset(r_dcache_in_itlb, 0, sizeof(r_dcache_in_itlb)m_icache_ways*m_icache_sets);
431	std::memset(r_dcache_in_dtlb, 0, sizeof(r_dcache_in_dtlb)m_dcache_ways*m_dcache_sets);
432
433	//r_mmu_mode = ALL_DEACTIVE;
434	r_mmu_mode = 0x3;
435	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
436	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
437	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
438	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
439	(uint32_log2(m_icache_words * 4));
440	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
441
442	r_icache_miss_req = false;
443	r_icache_unc_req = false;
444	r_dcache_itlb_read_req = false;
445
446	r_itlb_read_dcache_req = false;
447	r_itlb_k_read_dcache = false;
448	r_itlb_acc_dcache_req = false;
449	r_itlb_acc_redo_req = false;
450	r_dcache_rsp_itlb_error = false;
451
452	r_dcache_miss_req = false;
453	r_dcache_unc_req = false;
454	r_dcache_write_req = false;
455	r_dcache_tlb_read_req = false;
456	r_dcache_tlb_ptba_read = false;
457	r_dcache_xtn_req = false;
458	r_dcache_llsc_reserved = false;
459
460	r_dcache_tlb_ll_acc_req = false;
461	r_dcache_tlb_sc_acc_req = false;
462	r_dcache_tlb_ll_dirty_req = false;
463	r_dcache_tlb_sc_dirty_req = false;
464	r_dcache_sc_updt_dirty = false;
465	r_dcache_itlb_ll_acc_req = false;
466	r_dcache_itlb_sc_acc_req = false;
467
468	r_icache_cleanup_req = false;
469	r_dcache_cleanup_req = false;
470
471	r_tgt_icache_req = false;
472	r_tgt_dcache_req = false;
473
474	r_icache_inval_rsp = false;
475	r_dcache_inval_rsp = false;
476
477	r_dcache_dirty_save = false;
478	r_dcache_hit_p_save = false;
479	r_dcache_cached_save = false;
480
481	r_icache_buf_unc_valid = false;
482	r_dcache_buf_unc_valid = false;
483
484	r_vci_rsp_ins_error = false;
485	r_vci_rsp_data_error = false;
486
487	r_icache_id1_save = 0;
488	r_icache_ppn_save = 0;
489	r_icache_vpn_save = 0;
490	r_itlb_translation_valid = false;
491
492	r_dcache_id1_save = 0;
493	r_dcache_ppn_save = 0;
494	r_dcache_vpn_save = 0;
495	r_dtlb_translation_valid = false;
496
497	r_icache_ptba_ok = false;
498	r_dcache_ptba_ok = false;
499
500	r_icache_error_type = MMU_NONE;
501	r_dcache_error_type = MMU_NONE;
502
503	// coherence registers
504	r_icache_way = 0;
505	r_icache_set = 0;
506	r_icache_cleanup_req = false;
507	r_icache_inval_rsp = false;
508
509	r_dcache_way = 0;
510	r_dcache_set = 0;
511	r_dcache_cleanup_req = false;
512	r_dcache_inval_rsp = false;
513
514	r_itlb_inval_req = false;
515	r_dcache_itlb_inval_req = false;
516	r_itlb_cc_check_end = false;
517	r_ccinval_itlb_way = 0;
518	r_ccinval_itlb_set = 0;
519	r_icache_inval_tlb_rsp = false;
520
521	r_dcache_dtlb_inval_req = false;
522	r_dtlb_cc_check_end = false;
523	r_ccinval_dtlb_way = 0;
524	r_ccinval_dtlb_set = 0;
525	r_dcache_inval_tlb_rsp = false;
526
527	r_dcache_itlb_cleanup_req = false;
528	r_dcache_dtlb_cleanup_req = false;
529
530	r_dcache_cc_check = false;
531	r_dcache_tlb_sc_fail = false;
532
533	// activity counters
534	m_cpt_dcache_data_read = 0;
535	m_cpt_dcache_data_write = 0;
536	m_cpt_dcache_dir_read = 0;
537	m_cpt_dcache_dir_write = 0;
538	m_cpt_icache_data_read = 0;
539	m_cpt_icache_data_write = 0;
540	m_cpt_icache_dir_read = 0;
541	m_cpt_icache_dir_write = 0;
542
543	m_cpt_frz_cycles = 0;
544	m_cpt_dcache_frz_cycles = 0;
545	m_cpt_total_cycles = 0;
546
547	m_cpt_read = 0;
548	m_cpt_write = 0;
549	m_cpt_data_miss = 0;
550	m_cpt_ins_miss = 0;
551	m_cpt_unc_read = 0;
552	m_cpt_write_cached = 0;
553	m_cpt_ins_read = 0;
554
555	m_cost_write_frz = 0;
556	m_cost_data_miss_frz = 0;
557	m_cost_unc_read_frz = 0;
558	m_cost_ins_miss_frz = 0;
559
560	m_cpt_imiss_transaction = 0;
561	m_cpt_dmiss_transaction = 0;
562	m_cpt_unc_transaction = 0;
563	m_cpt_write_transaction = 0;
564	m_cpt_icache_unc_transaction = 0;
565
566	m_cost_imiss_transaction = 0;
567	m_cost_dmiss_transaction = 0;
568	m_cost_unc_transaction = 0;
569	m_cost_write_transaction = 0;
570	m_cost_icache_unc_transaction = 0;
571	m_length_write_transaction = 0;
572
573	m_cpt_ins_tlb_read = 0;
574	m_cpt_ins_tlb_miss = 0;
575	m_cpt_ins_tlb_update_acc = 0;
576
577	m_cpt_data_tlb_read = 0;
578	m_cpt_data_tlb_miss = 0;
579	m_cpt_data_tlb_update_acc = 0;
580	m_cpt_data_tlb_update_dirty = 0;
581	m_cpt_ins_tlb_hit_dcache = 0;
582	m_cpt_data_tlb_hit_dcache = 0;
583	m_cpt_ins_tlb_occup_cache = 0;
584	m_cpt_data_tlb_occup_cache = 0;
585
586	m_cost_ins_tlb_miss_frz = 0;
587	m_cost_data_tlb_miss_frz = 0;
588	m_cost_ins_tlb_update_acc_frz = 0;
589	m_cost_data_tlb_update_acc_frz = 0;
590	m_cost_data_tlb_update_dirty_frz = 0;
591	m_cost_ins_tlb_occup_cache_frz = 0;
592	m_cost_data_tlb_occup_cache_frz = 0;
593
594	m_cpt_itlbmiss_transaction = 0;
595	m_cpt_itlb_ll_transaction = 0;
596	m_cpt_itlb_sc_transaction = 0;
597	m_cpt_dtlbmiss_transaction = 0;
598	m_cpt_dtlb_ll_transaction = 0;
599	m_cpt_dtlb_sc_transaction = 0;
600	m_cpt_dtlb_ll_dirty_transaction = 0;
601	m_cpt_dtlb_sc_dirty_transaction = 0;
602
603	m_cost_itlbmiss_transaction = 0;
604	m_cost_itlb_ll_transaction = 0;
605	m_cost_itlb_sc_transaction = 0;
606	m_cost_dtlbmiss_transaction = 0;
607	m_cost_dtlb_ll_transaction = 0;
608	m_cost_dtlb_sc_transaction = 0;
609	m_cost_dtlb_ll_dirty_transaction = 0;
610	m_cost_dtlb_sc_dirty_transaction = 0;
611	return;
612	}
613
614	#ifdef SOCLIB_MODULE_DEBUG
615	std::cout << name() << " cycle = " << std::dec << m_cpt_total_cycles
616	<< " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
617	<< " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm]
618	<< " icache fsm: " << icache_fsm_state_str[r_icache_fsm]
619	<< " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm]
620	<< " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm]
621	<< " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm]
622	<< " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl;
623	#endif
624
625	m_cpt_total_cycles++;
626
627	typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
628	typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
629
630	typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
631	typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
632
633	m_iss.getRequests( ireq, dreq );
634
635	#ifdef SOCLIB_MODULE_DEBUG
636	std::cout << name() << " Instruction Request: " << ireq << std::endl;
637	std::cout << name() << " Data Request: " << dreq << std::endl;
638	#endif
639
640	/////////////////////////////////////////////////////////////////////
641	// The TGT_FSM controls the following ressources:
642	// - r_vci_tgt_fsm
643	// - r_tgt_buf[nwords]
644	// - r_tgt_val[nwords]
645	// - r_tgt_update
646	// - r_tgt_word
647	// - r_tgt_addr
648	// - r_tgt_srcid
649	// - r_tgt_trdid
650	// - r_tgt_pktid
651	// All VCI commands must be CMD_WRITE.
652	// If the VCI address offset is null, the command is an invalidate
653	// request. It is an update request otherwise.
654	// The VCI_TGT FSM stores the external request arguments in the
655	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
656	// & r_tgt_dcache_req flip-flops to signal the external request to
657	// the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
658	// of the update or invalidate request in the RSP state.
659	// - for an invalidate request the VCI packet length is 1 word.
660	// The WDATA field contains the line index (i.e. the Z & Y fields).
661	// - for an update request the VCI packet length is (n+2) words.
662	// The WDATA field of the first VCI word contains the line number.
663	// The WDATA field of the second VCI word contains the word index.
664	// The WDATA field of the n following words contains the values.
665	// - for both invalidate & update requests, the VCI response
666	// is one single word.
667	// In case of errors in the VCI command packet, the simulation
668	// is stopped with an error message.
669	/////////////////////////////////////////////////////////////////////
670
671	switch(r_vci_tgt_fsm) {
672	//////////////
673	case TGT_IDLE:
674	{
675	if ( p_vci_tgt.cmdval.read() )
676	{
677	paddr_t address = p_vci_tgt.address.read();
678
679	if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE)
680	{
681	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
682	std::cout << "the received VCI command is not a write" << std::endl;
683	exit(0);
684	}
685
686	// multi-update or multi-invalidate for data type
687	if ( ( address != 0x3 ) && ( ! m_segment.contains(address)) )
688	{
689	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
690	std::cout << "out of segment VCI command received for a multi-updt or multi-inval request" << std::endl;
691	exit(0);
692	}
693
694	r_tgt_srcid = p_vci_tgt.srcid.read();
695	r_tgt_trdid = p_vci_tgt.trdid.read();
696	r_tgt_pktid = p_vci_tgt.pktid.read();
697	r_tgt_plen = p_vci_tgt.plen.read(); // todo: wait L2 modification
698	r_tgt_addr = (paddr_t)(p_vci_tgt.be.read() & 0x3) << 32 \|
699	(paddr_t)p_vci_tgt.wdata.read() * m_dcache_words * 4;
700
701	if ( address == 0x3 ) // broadcast invalidate for data or instruction type
702	{
703	if ( ! p_vci_tgt.eop.read() )
704	{
705	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
706	std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
707	exit(0);
708	}
709	r_tgt_update = false;
710	r_vci_tgt_fsm = TGT_REQ_BROADCAST;
711	m_cpt_cc_broadcast++;
712	}
713	else // multi-update or multi-invalidate for data type
714	{
715	paddr_t cell = address - m_segment.baseAddress();
716
717	if (cell == 0) // invalidate
718	{
719	if ( ! p_vci_tgt.eop.read() )
720	{
721	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
722	std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
723	exit(0);
724	}
725	r_tgt_update = false;
726	r_vci_tgt_fsm = TGT_REQ_DCACHE;
727	m_cpt_cc_inval_data++ ;
728	}
729	else if (cell == 4) // update
730	{
731	if ( p_vci_tgt.eop.read() )
732	{
733	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
734	std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
735	exit(0);
736	}
737	r_tgt_update = true;
738	r_vci_tgt_fsm = TGT_UPDT_WORD;
739	m_cpt_cc_update_data++ ;
740	}
741	else if (cell == 8)
742	{
743	if ( ! p_vci_tgt.eop.read() )
744	{
745	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
746	std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
747	exit(0);
748	}
749	r_tgt_update = false;
750	r_vci_tgt_fsm = TGT_REQ_ICACHE;
751	m_cpt_cc_inval_ins++ ;
752
753	}
754	} // end if address
755	} // end if cmdval
756	break;
757	}
758	///////////////////
759	case TGT_UPDT_WORD:
760	{
761	if (p_vci_tgt.cmdval.read())
762	{
763	if ( p_vci_tgt.eop.read() )
764	{
765	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
766	std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
767	exit(0);
768	}
769	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_val[i] = false;
770	r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
771	r_vci_tgt_fsm = TGT_UPDT_DATA;
772	}
773	break;
774	}
775	///////////////////
776	case TGT_UPDT_DATA:
777	{
778	if (p_vci_tgt.cmdval.read())
779	{
780	size_t word = r_tgt_word.read();
781	if (word >= m_dcache_words)
782	{
783	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
784	std::cout << "the reveived MULTI-UPDATE command length is wrong" << std::endl;
785	exit(0);
786	}
787	r_tgt_buf[word] = p_vci_tgt.wdata.read();
788	if(p_vci_tgt.be.read()) r_tgt_val[word] = true;
789	r_tgt_word = word + 1;
790	if (p_vci_tgt.eop.read()) r_vci_tgt_fsm = TGT_REQ_DCACHE;
791	}
792	break;
793	}
794	////////////////////////
795	case TGT_REQ_BROADCAST:
796	{
797	if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
798	{
799	r_vci_tgt_fsm = TGT_RSP_BROADCAST;
800	r_tgt_icache_req = true;
801	r_tgt_dcache_req = true;
802	}
803	break;
804	}
805	/////////////////////
806	case TGT_REQ_ICACHE:
807	{
808	if ( !r_tgt_icache_req.read() )
809	{
810	r_vci_tgt_fsm = TGT_RSP_ICACHE;
811	r_tgt_icache_req = true;
812	}
813	break;
814	}
815	/////////////////////
816	case TGT_REQ_DCACHE:
817	{
818	if ( !r_tgt_dcache_req.read() )
819	{
820	r_vci_tgt_fsm = TGT_RSP_DCACHE;
821	r_tgt_dcache_req = true;
822	}
823	break;
824	}
825	///////////////////////
826	case TGT_RSP_BROADCAST:
827	{
828	// no response
829	if ( !r_tgt_icache_rsp.read() && !r_tgt_dcache_rsp.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
830	{
831	r_vci_tgt_fsm = TGT_IDLE;
832	break;
833	}
834
835	if ( p_vci_tgt.rspack.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
836	{
837	// one response
838	if ( !r_tgt_icache_rsp \|\| !r_tgt_dcache_rsp )
839	{
840	r_vci_tgt_fsm = TGT_IDLE;
841	r_tgt_icache_rsp = false;
842	r_tgt_dcache_rsp = false;
843	}
844
845	// if data and instruction have the inval line, need two responses
846	if ( r_tgt_icache_rsp && r_tgt_dcache_rsp )
847	{
848	r_tgt_icache_rsp = false; // only reset one for respond the second time
849	}
850	}
851	break;
852	}
853	/////////////////////
854	case TGT_RSP_ICACHE:
855	{
856	if ( (p_vci_tgt.rspack.read() \|\| !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() )
857	{
858	r_vci_tgt_fsm = TGT_IDLE;
859	r_tgt_icache_rsp = false;
860	}
861	break;
862	}
863	/////////////////////
864	case TGT_RSP_DCACHE:
865	{
866	if ( (p_vci_tgt.rspack.read() \|\| !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() )
867	{
868	r_vci_tgt_fsm = TGT_IDLE;
869	r_tgt_dcache_rsp = false;
870	}
871	break;
872	}
873	} // end switch TGT_FSM
874
875	////////////////////////////////////////////////////////////////////////////////////////
876	// ICACHE_FSM
877	//
878	// There is 9 mutually exclusive conditions to exit the IDLE state.
879	// Four configurations corresponding to an XTN request from processor,
880	// - Flush TLB (in case of Context switch) => TLB_FLUSH state
881	// - Flush cache => CACHE_FLUSH state
882	// - Invalidate a TLB entry => TLB_INVAL state
883	// - Invalidate a cache line => CACHE_INVAL state
884	// Five configurations corresponding to various TLB or cache MISS :
885	// - TLB miss(in case hit_p miss) => TLB1_READ state
886	// - TLB miss(in case hit_p hit) => TLB2_READ state
887	// - Hit in TLB but VPN changed => BIS state
888	// - Cached read miss => MISS_REQ state
889	// - Uncache read miss => UNC_REQ state
890	//
891	// In case of MISS, the controller writes a request in the r_icache_paddr_save register
892	// and sets the corresponding request flip-flop : r_dcache_itlb_read_req, r_icache_miss_req
893	// or r_icache_unc_req. These request flip-flops are reset by the VCI_RSP controller
894	// when the response is ready in the ICACHE buffer.
895	//
896	// The DCACHE FSM signals XTN processor requests using the r_dcache_xtn_req flip-flop.
897	// The request opcod and the address to be invalidated are transmitted
898	// in the r_dcache_paddr_save & r_dcache_wdata_save registers respectively.
899	// The request flip-flop is reset by the ICACHE_FSM when the operation is completed.
900	//
901	// The r_vci_rsp_ins_error flip-flop is set by the VCI_RSP FSM and reset
902	// by the ICACHE-FSM in the ICACHE_ERROR state.
903	//
904	//-----------------------------------------------------------------------------------
905	// Instruction TLB:
906	//
907	// - int ET (00: unmapped; 01: unused or PTD)
908	// (10: PTE new; 11: PTE old )
909	// - bool cachable (cached bit)
910	// - bool writable (** not used alwayse false)
911	// - bool executable (executable bit)
912	// - bool user (access in user mode allowed)
913	// - bool global (PTE not invalidated by a TLB flush)
914	// - bool dirty (** not used alwayse false)
915	// - uint32_t vpn (virtual page number)
916	// - uint32_t ppn (physical page number)
917	////////////////////////////////////////////////////////////////////////////////////////
918
919	switch(r_icache_fsm) {
920
921	////////////////
922	case ICACHE_IDLE:
923	{
924	pte_info_t icache_pte_info;
925	paddr_t tlb_ipaddr = 0; // physical address obtained from TLB
926	paddr_t spc_ipaddr = 0; // physical adress obtained from PPN_save (speculative)
927	data_t icache_ins = 0; // read instruction
928	bool icache_hit_c = false; // Cache hit
929	bool icache_cached = false; // cacheable access (read)
930	bool icache_hit_t = false; // hit on TLB
931	bool icache_hit_x = false; // VPN unmodified (can use spc_dpaddr)
932	bool icache_hit_p = false; // PTP unmodified (can skip first level page table walk)
933	size_t icache_tlb_way = 0; // selected way (in case of cache hit)
934	size_t icache_tlb_set = 0; // selected set (Y field in address)
935	paddr_t icache_tlb_nline = 0; // TLB NLINE
936
937	// Decoding processor XTN requests
938	// They are sent by DCACHE FSM
939
940	if (r_dcache_xtn_req)
941	{
942	if ((int)r_dcache_type_save == (int)iss_t::XTN_PTPR )
943	{
944	r_icache_way = 0;
945	r_icache_set = 0;
946	r_icache_fsm = ICACHE_SW_FLUSH;
947	break;
948	}
949	if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_FLUSH)
950	{
951	r_icache_way = 0;
952	r_icache_set = 0;
953	r_icache_fsm = ICACHE_CACHE_FLUSH;
954	break;
955	}
956	if ((int)r_dcache_type_save == (int)iss_t::XTN_ITLB_INVAL)
957	{
958	r_icache_fsm = ICACHE_TLB_INVAL;
959	break;
960	}
961	if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_INVAL)
962	{
963	r_icache_fsm = ICACHE_CACHE_INVAL;
964	break;
965	}
966	if ((int)r_dcache_type_save == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
967	{
968	r_icache_fsm = ICACHE_CACHE_INVAL_PA;
969	break;
970	}
971	if ((int)r_dcache_type_save == (int)iss_t::XTN_DCACHE_FLUSH )
972	{
973	// special for ins tlb miss via data cache
974	r_icache_fsm = ICACHE_TLB_FLUSH;
975	break;
976	}
977	} // end if xtn_req
978
979	// external cache invalidate request
980	if ( r_tgt_icache_req )
981	{
982	r_icache_fsm = ICACHE_CC_INVAL;
983	r_icache_fsm_save = r_icache_fsm;
984	break;
985	}
986
987	// external tlb invalidate request
988	if ( r_dcache_itlb_inval_req )
989	{
990	r_itlb_inval_req = true;
991	r_icache_fsm = ICACHE_TLB_CC_INVAL;
992	r_icache_fsm_save = r_icache_fsm;
993	break;
994	}
995
996	// icache_hit_t_m, icache_hit_t_k, icache_hit_x, icache_hit_p
997	// icache_pte_info, icache_tlb_way, icache_tlb_set & ipaddr & cacheability
998	// - If MMU activated : cacheability is defined by the cachable bit in the TLB
999	// - If MMU not activated : cacheability is defined by the segment table.
1000
1001	if ( !(r_mmu_mode.read() & INS_TLB_MASK) ) // MMU not activated
1002	{
1003	icache_hit_t = true;
1004	icache_hit_x = true;
1005	icache_hit_p = true;
1006	tlb_ipaddr = ireq.addr;
1007	spc_ipaddr = ireq.addr;
1008	icache_cached = m_cacheability_table[ireq.addr];
1009	}
1010	else // MMU activated
1011	{
1012	m_cpt_ins_tlb_read++;
1013	icache_hit_t = icache_tlb.cctranslate(ireq.addr, &tlb_ipaddr, &icache_pte_info,
1014	&icache_tlb_nline, &icache_tlb_way, &icache_tlb_set);
1015	icache_hit_x = (((vaddr_t)r_icache_vpn_save << PAGE_K_NBITS) == (ireq.addr & ~PAGE_K_MASK)) && r_itlb_translation_valid;
1016	icache_hit_p = (((ireq.addr >> PAGE_M_NBITS) == r_icache_id1_save) && r_icache_ptba_ok);
1017	spc_ipaddr = ((paddr_t)r_icache_ppn_save << PAGE_K_NBITS) \| (paddr_t)(ireq.addr & PAGE_K_MASK);
1018	icache_cached = icache_pte_info.c;
1019	}
1020
1021	if ( !(r_mmu_mode.read() & INS_CACHE_MASK) ) // cache not actived
1022	{
1023	icache_cached = false;
1024	}
1025
1026	if ( ireq.valid )
1027	{
1028	m_cpt_icache_dir_read += m_icache_ways;
1029	m_cpt_icache_data_read += m_icache_ways;
1030
1031	// icache_hit_c & icache_ins
1032	if ( icache_cached ) // using speculative physical address for cached access
1033	{
1034	icache_hit_c = r_icache.read(spc_ipaddr, &icache_ins);
1035	}
1036	else // using actual physical address for uncached access
1037	{
1038	icache_hit_c = ( r_icache_buf_unc_valid && (tlb_ipaddr == (paddr_t)r_icache_paddr_save) );
1039	icache_ins = r_icache_miss_buf[0];
1040	}
1041
1042	if ( r_mmu_mode.read() & INS_TLB_MASK )
1043	{
1044	if ( icache_hit_t )
1045	{
1046	// check access rights
1047	if ( !icache_pte_info.u && (ireq.mode == iss_t::MODE_USER))
1048	{
1049	r_icache_error_type = MMU_READ_PRIVILEGE_VIOLATION;
1050	r_icache_bad_vaddr = ireq.addr;
1051	irsp.valid = true;
1052	irsp.error = true;
1053	irsp.instruction = 0;
1054	break;
1055	}
1056	if ( !icache_pte_info.x )
1057	{
1058	r_icache_error_type = MMU_READ_EXEC_VIOLATION;
1059	r_icache_bad_vaddr = ireq.addr;
1060	irsp.valid = true;
1061	irsp.error = true;
1062	irsp.instruction = 0;
1063	break;
1064	}
1065	}
1066
1067	// update LRU, save ppn, vpn and page type
1068	if ( icache_hit_t )
1069	{
1070	icache_tlb.setlru(icache_tlb_way,icache_tlb_set);
1071	r_icache_ppn_save = tlb_ipaddr >> PAGE_K_NBITS;
1072	r_icache_vpn_save = ireq.addr >> PAGE_K_NBITS;
1073	r_icache_tlb_nline = icache_tlb_nline;
1074	r_itlb_translation_valid = true;
1075	}
1076	else
1077	{
1078	r_itlb_translation_valid = false;
1079	}
1080
1081	} // end if MMU activated
1082
1083	// compute next state
1084	if ( !icache_hit_t && !icache_hit_p ) // TLB miss
1085	{
1086	// walk page table level 1
1087	r_icache_paddr_save = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((ireq.addr>>PAGE_M_NBITS)<<2);
1088	r_itlb_read_dcache_req = true;
1089	r_icache_vaddr_req = ireq.addr;
1090	r_icache_fsm = ICACHE_TLB1_READ;
1091	m_cpt_ins_tlb_miss++;
1092	m_cost_ins_tlb_miss_frz++;
1093	}
1094	else if ( !icache_hit_t && icache_hit_p ) // TLB Miss with possibility of bypass first level page
1095	{
1096	// walk page table level 2
1097	r_icache_paddr_save = (paddr_t)r_icache_ptba_save \|
1098	(paddr_t)(((ireq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
1099	r_itlb_read_dcache_req = true;
1100	r_icache_vaddr_req = ireq.addr;
1101	r_itlb_k_read_dcache = true;
1102	r_icache_fsm = ICACHE_TLB2_READ;
1103	m_cpt_ins_tlb_miss++;
1104	m_cost_ins_tlb_miss_frz++;
1105	}
1106	else if ( icache_hit_t && !icache_hit_x && icache_cached ) // cached access with an ucorrect speculative physical address
1107	{
1108	r_icache_paddr_save = tlb_ipaddr; // save actual physical address for BIS
1109	r_icache_vaddr_req = ireq.addr;
1110	r_icache_fsm = ICACHE_BIS;
1111	m_cost_ins_miss_frz++;
1112	}
1113	else // cached or uncached access with a correct speculative physical address
1114	{
1115	m_cpt_ins_read++;
1116	if ( !icache_hit_c )
1117	{
1118	m_cpt_ins_miss++;
1119	m_cost_ins_miss_frz++;
1120	if ( icache_cached )
1121	{
1122	r_icache_miss_req = true;
1123	r_icache_paddr_save = spc_ipaddr;
1124	r_icache_vaddr_req = ireq.addr;
1125	r_icache_fsm = ICACHE_MISS_WAIT;
1126	}
1127	else
1128	{
1129	r_icache_unc_req = true;
1130	r_icache_buf_unc_valid = false;
1131	r_icache_paddr_save = tlb_ipaddr;
1132	r_icache_vaddr_req = ireq.addr;
1133	r_icache_fsm = ICACHE_UNC_WAIT;
1134	}
1135	}
1136	else
1137	{
1138	r_icache_buf_unc_valid = false;
1139	r_icache_fsm = ICACHE_IDLE;
1140	}
1141	irsp.valid = icache_hit_c;
1142	irsp.instruction = icache_ins;
1143	} // end if next states
1144
1145	} // end if ireq.valid
1146	break;
1147	}
1148	////////////////
1149	case ICACHE_BIS:
1150	{
1151	// external cache invalidate request
1152	if ( r_tgt_icache_req )
1153	{
1154	if ( ireq.valid ) m_cost_ins_miss_frz++;
1155	r_icache_fsm = ICACHE_CC_INVAL;
1156	r_icache_fsm_save = r_icache_fsm;
1157	break;
1158	}
1159
1160	// external tlb invalidate request
1161	if ( r_dcache_itlb_inval_req )
1162	{
1163	if ( ireq.valid ) m_cost_ins_miss_frz++;
1164	r_itlb_inval_req = true;
1165	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1166	r_icache_fsm_save = r_icache_fsm;
1167	break;
1168	}
1169
1170	// using page is invalidated
1171	if ( r_icache_inval_tlb_rsp )
1172	{
1173	if ( ireq.valid ) m_cost_ins_miss_frz++;
1174	r_icache_inval_tlb_rsp = false;
1175	r_icache_fsm = ICACHE_IDLE;
1176	break;
1177	}
1178
1179	data_t icache_ins = 0;
1180	bool icache_hit_c = false;
1181	bool icache_hit_t = false;
1182	paddr_t tlb_ipaddr = 0;
1183
1184	icache_hit_t = icache_tlb.translate(ireq.addr, &tlb_ipaddr);
1185
1186	if ( (tlb_ipaddr == r_icache_paddr_save.read()) && ireq.valid && icache_hit_t ) // unmodified & valid
1187	{
1188	m_cpt_ins_read++;
1189
1190	// acces is always cached in this state
1191	icache_hit_c = r_icache.read(r_icache_paddr_save, &icache_ins);
1192
1193	if ( !icache_hit_c )
1194	{
1195	r_icache_miss_req = true;
1196	r_icache_fsm = ICACHE_MISS_WAIT;
1197	m_cpt_ins_miss++;
1198	m_cost_ins_miss_frz++;
1199	}
1200	else
1201	{
1202	r_icache_fsm = ICACHE_IDLE;
1203	}
1204	irsp.valid = icache_hit_c;
1205	if (irsp.valid)
1206	assert((r_icache_vaddr_req.read() == ireq.addr) &&
1207	"vaddress should not be modified while ICACHE_BIS");
1208	irsp.error = false;
1209	irsp.instruction = icache_ins;
1210	}
1211	else // modified or invalid
1212	{
1213	irsp.valid = false;
1214	irsp.error = false;
1215	irsp.instruction = 0;
1216	r_icache_fsm = ICACHE_IDLE;
1217	}
1218	break;
1219	}
1220	//////////////////////
1221	case ICACHE_TLB1_READ:
1222	{
1223	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1224
1225	// external cache invalidate request
1226	if ( r_tgt_icache_req )
1227	{
1228	r_icache_fsm = ICACHE_CC_INVAL;
1229	r_icache_fsm_save = r_icache_fsm;
1230	break;
1231	}
1232
1233	// external tlb invalidate request
1234	if ( r_dcache_itlb_inval_req )
1235	{
1236	r_itlb_inval_req = true;
1237	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1238	r_icache_fsm_save = r_icache_fsm;
1239	break;
1240	}
1241
1242	if ( !r_itlb_read_dcache_req )
1243	{
1244	if (r_icache_vaddr_req.read() != ireq.addr \|\| !ireq.valid)
1245	{
1246	/* request modified, drop response and restart */
1247	r_icache_ptba_ok = false;
1248	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
1249	if ( r_dcache_rsp_itlb_error ) r_dcache_rsp_itlb_error = false;
1250	r_icache_fsm = ICACHE_IDLE;
1251	break;
1252	}
1253
1254	if ( !r_icache_inval_tlb_rsp ) // TLB miss read response and no invalidation
1255	{
1256	if ( !r_dcache_rsp_itlb_error ) // vci response ok
1257	{
1258	if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
1259	{
1260	r_icache_ptba_ok = false;
1261	r_icache_error_type = MMU_READ_PT1_UNMAPPED;
1262	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1263	r_icache_fsm = ICACHE_ERROR;
1264	}
1265	else if ( (r_dcache_rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT ) // PTD
1266	{
1267	r_icache_ptba_ok = true;
1268	r_icache_ptba_save = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;
1269	r_icache_id1_save = r_icache_vaddr_req.read() >> PAGE_M_NBITS;
1270	r_icache_paddr_save = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
1271	(paddr_t)(((r_icache_vaddr_req.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
1272	r_itlb_read_dcache_req = true;
1273	r_itlb_k_read_dcache = true;
1274	r_icache_fsm = ICACHE_TLB2_READ;
1275	}
1276	else
1277	{
1278	r_icache_ptba_ok = false;
1279
1280	if ( (m_srcid_rw >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
1281	{
1282	if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
1283	{
1284	r_icache_pte_update = r_dcache_rsp_itlb_miss;
1285	r_icache_fsm = ICACHE_TLB1_UPDT;
1286	}
1287	else
1288	{
1289	r_icache_pte_update = r_dcache_rsp_itlb_miss \| PTE_L_MASK;
1290	r_itlb_acc_dcache_req = true;
1291	r_icache_fsm = ICACHE_TLB1_WRITE;
1292	m_cpt_ins_tlb_update_acc++;
1293	m_cost_ins_tlb_update_acc_frz++;
1294	}
1295	}
1296	else // remotely
1297	{
1298	if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
1299	{
1300	r_icache_pte_update = r_dcache_rsp_itlb_miss;
1301	r_icache_fsm = ICACHE_TLB1_UPDT;
1302	}
1303	else
1304	{
1305	r_icache_pte_update = r_dcache_rsp_itlb_miss \| PTE_R_MASK;
1306	r_itlb_acc_dcache_req = true;
1307	r_icache_fsm = ICACHE_TLB1_WRITE;
1308	m_cpt_ins_tlb_update_acc++;
1309	m_cost_ins_tlb_update_acc_frz++;
1310	}
1311	}
1312	}
1313	}
1314	else // vci response error
1315	{
1316	r_icache_fsm = ICACHE_ERROR;
1317	r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
1318	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1319	}
1320	}
1321	else // TLB miss read response and invalidation
1322	{
1323	if ( r_dcache_rsp_itlb_error )
1324	{
1325	r_icache_inval_tlb_rsp = false;
1326	r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
1327	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1328	r_icache_fsm = ICACHE_ERROR;
1329	}
1330	else
1331	{
1332	r_icache_inval_tlb_rsp = false;
1333	r_icache_fsm = ICACHE_IDLE;
1334	}
1335	}
1336	}
1337	break;
1338	}
1339	///////////////////////
1340	case ICACHE_TLB1_WRITE:
1341	{
1342	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1343	m_cost_ins_tlb_update_acc_frz++;
1344
1345	// external cache invalidate request
1346	if ( r_tgt_icache_req )
1347	{
1348	r_icache_fsm = ICACHE_CC_INVAL;
1349	r_icache_fsm_save = r_icache_fsm;
1350	break;
1351	}
1352	// external tlb invalidate request
1353	if ( r_dcache_itlb_inval_req )
1354	{
1355	r_itlb_inval_req = true;
1356	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1357	r_icache_fsm_save = r_icache_fsm;
1358	break;
1359	}
1360
1361	if ( !r_itlb_acc_dcache_req ) // TLB access bits write response
1362	{
1363	if ( !r_icache_inval_tlb_rsp ) // TLB access bits write response and no invalidation
1364	{
1365	if ( r_dcache_rsp_itlb_error )
1366	{
1367	r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
1368	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1369	r_icache_fsm = ICACHE_ERROR;
1370	}
1371	else if ( r_itlb_acc_redo_req )
1372	{
1373	r_itlb_acc_redo_req = false;
1374	r_icache_fsm = ICACHE_IDLE;
1375	}
1376	else
1377	{
1378	r_icache_fsm = ICACHE_TLB1_UPDT;
1379	}
1380	}
1381	else // TLB ET write response and invalidation
1382	{
1383	if ( r_dcache_rsp_itlb_error )
1384	{
1385	r_icache_inval_tlb_rsp = false;
1386	r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
1387	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1388	r_icache_fsm = ICACHE_ERROR;
1389	}
1390	else if ( r_itlb_acc_redo_req )
1391	{
1392	r_itlb_acc_redo_req = false;
1393	r_icache_inval_tlb_rsp = false;
1394	r_icache_fsm = ICACHE_IDLE;
1395	}
1396	else
1397	{
1398	r_icache_inval_tlb_rsp = false;
1399	r_icache_fsm = ICACHE_IDLE;
1400	}
1401	}
1402	}
1403	break;
1404	}
1405	//////////////////////
1406	case ICACHE_TLB1_UPDT:
1407	{
1408	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1409
1410	// external cache invalidate request
1411	if ( r_tgt_icache_req )
1412	{
1413	r_icache_fsm = ICACHE_CC_INVAL;
1414	r_icache_fsm_save = r_icache_fsm;
1415	break;
1416	}
1417
1418	// external tlb invalidate request
1419	if ( r_dcache_itlb_inval_req )
1420	{
1421	r_itlb_inval_req = true;
1422	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1423	r_icache_fsm_save = r_icache_fsm;
1424	break;
1425	}
1426
1427	// TLB update and invalidate different PTE
1428	if ( !r_dcache_itlb_cleanup_req && !r_icache_inval_tlb_rsp )
1429	{
1430	paddr_t victim_index = 0;
1431	r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
1432	r_dcache_itlb_cleanup_line = victim_index;
1433	m_cpt_cc_cleanup_ins++;
1434	r_icache_fsm = ICACHE_IDLE;
1435	}
1436
1437	// TLB update and invalidate same PTE
1438	if ( r_icache_inval_tlb_rsp )
1439	{
1440	r_icache_inval_tlb_rsp = false;
1441	r_icache_fsm = ICACHE_IDLE;
1442	}
1443	break;
1444	}
1445	/////////////////////
1446	case ICACHE_TLB2_READ:
1447	{
1448	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1449
1450	// external cache invalidate request
1451	if ( r_tgt_icache_req )
1452	{
1453	r_icache_fsm = ICACHE_CC_INVAL;
1454	r_icache_fsm_save = r_icache_fsm;
1455	break;
1456	}
1457
1458	// external tlb invalidate request
1459	if ( r_dcache_itlb_inval_req )
1460	{
1461	r_itlb_inval_req = true;
1462	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1463	r_icache_fsm_save = r_icache_fsm;
1464	break;
1465	}
1466
1467	if ( !r_itlb_read_dcache_req ) // TLB miss read response
1468	{
1469	if (r_icache_vaddr_req.read() != ireq.addr \|\| !ireq.valid)
1470	{
1471	/* request modified, drop response and restart */
1472	r_icache_ptba_ok = false;
1473	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
1474	if ( r_dcache_rsp_itlb_error ) r_dcache_rsp_itlb_error = false;
1475	r_icache_fsm = ICACHE_IDLE;
1476	break;
1477	}
1478
1479	if ( !r_icache_inval_tlb_rsp ) // TLB miss read response
1480	{
1481	if ( !r_dcache_rsp_itlb_error ) // VCI response ok
1482	{
1483	if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
1484	{
1485	r_icache_error_type = MMU_READ_PT2_UNMAPPED;
1486	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1487	r_icache_fsm = ICACHE_ERROR;
1488	}
1489	else
1490	{
1491	if ( (m_srcid_rw >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
1492	{
1493	if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
1494	{
1495	r_icache_fsm = ICACHE_TLB2_UPDT;
1496	r_icache_pte_update = r_dcache_rsp_itlb_miss;
1497	}
1498	else
1499	{
1500	r_icache_pte_update = r_dcache_rsp_itlb_miss \| PTE_L_MASK;
1501	r_itlb_acc_dcache_req = true;
1502	r_icache_fsm = ICACHE_TLB2_WRITE;
1503	m_cpt_ins_tlb_update_acc++;
1504	m_cost_ins_tlb_update_acc_frz++;
1505	}
1506	}
1507	else // remotely
1508	{
1509	if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
1510	{
1511	r_icache_fsm = ICACHE_TLB2_UPDT;
1512	r_icache_pte_update = r_dcache_rsp_itlb_miss;
1513	}
1514	else
1515	{
1516	r_icache_pte_update = r_dcache_rsp_itlb_miss \| PTE_R_MASK;
1517	r_itlb_acc_dcache_req = true;
1518	r_icache_fsm = ICACHE_TLB2_WRITE;
1519	m_cpt_ins_tlb_update_acc++;
1520	m_cost_ins_tlb_update_acc_frz++;
1521	}
1522	}
1523	}
1524	}
1525	else // VCI response error
1526	{
1527	r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
1528	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1529	r_icache_fsm = ICACHE_ERROR;
1530	}
1531	}
1532	else // TLB miss read response and invalidation
1533	{
1534	if ( r_dcache_rsp_itlb_error )
1535	{
1536	r_icache_inval_tlb_rsp = false;
1537	r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
1538	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1539	r_icache_fsm = ICACHE_ERROR;
1540	}
1541	else
1542	{
1543	r_icache_inval_tlb_rsp = false;
1544	r_icache_fsm = ICACHE_IDLE;
1545	}
1546	}
1547	}
1548	break;
1549	}
1550	/////////////////////////
1551	case ICACHE_TLB2_WRITE:
1552	{
1553	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1554	m_cost_ins_tlb_update_acc_frz++;
1555
1556	// external cache invalidate request
1557	if ( r_tgt_icache_req )
1558	{
1559	r_icache_fsm = ICACHE_CC_INVAL;
1560	r_icache_fsm_save = r_icache_fsm;
1561	break;
1562	}
1563	// external tlb invalidate request
1564	if ( r_dcache_itlb_inval_req )
1565	{
1566	r_itlb_inval_req = true;
1567	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1568	r_icache_fsm_save = r_icache_fsm;
1569	break;
1570	}
1571
1572	if ( !r_itlb_acc_dcache_req ) // TLB access bits write response
1573	{
1574	if ( !r_icache_inval_tlb_rsp ) // TLB access bits write response
1575	{
1576	if ( r_dcache_rsp_itlb_error )
1577	{
1578	r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
1579	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1580	r_icache_fsm = ICACHE_ERROR;
1581	}
1582	else if ( r_itlb_acc_redo_req )
1583	{
1584	r_itlb_acc_redo_req = false;
1585	r_icache_fsm = ICACHE_IDLE;
1586	}
1587	else
1588	{
1589	r_icache_fsm = ICACHE_TLB2_UPDT;
1590	}
1591	}
1592	else // TLB ET write response and invalidation
1593	{
1594	if ( r_dcache_rsp_itlb_error )
1595	{
1596	r_icache_inval_tlb_rsp = false;
1597	r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
1598	r_icache_bad_vaddr = r_icache_vaddr_req.read();
1599	r_icache_fsm = ICACHE_ERROR;
1600	}
1601	else if ( r_itlb_acc_redo_req )
1602	{
1603	r_itlb_acc_redo_req = false;
1604	r_icache_inval_tlb_rsp = false;
1605	r_icache_fsm = ICACHE_IDLE;
1606	}
1607	else
1608	{
1609	r_icache_inval_tlb_rsp = false;
1610	r_icache_fsm = ICACHE_IDLE;
1611	}
1612	}
1613	}
1614	break;
1615	}
1616	/////////////////////
1617	case ICACHE_TLB2_UPDT:
1618	{
1619	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1620
1621	// external cache invalidate request
1622	if ( r_tgt_icache_req )
1623	{
1624	r_icache_fsm = ICACHE_CC_INVAL;
1625	r_icache_fsm_save = r_icache_fsm;
1626	break;
1627	}
1628
1629	// external tlb invalidate request
1630	if ( r_dcache_itlb_inval_req )
1631	{
1632	r_itlb_inval_req = true;
1633	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1634	r_icache_fsm_save = r_icache_fsm;
1635	break;
1636	}
1637
1638	// TLB update and invalidate different PTE
1639	if ( !r_dcache_itlb_cleanup_req && !r_icache_inval_tlb_rsp )
1640	{
1641	paddr_t victim_index = 0;
1642	r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_dcache_rsp_itlb_ppn,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
1643	r_dcache_itlb_cleanup_line = victim_index;
1644	m_cpt_cc_cleanup_ins++;
1645	r_icache_fsm = ICACHE_IDLE;
1646	}
1647	// TLB update and invalidate same PTE
1648	if ( r_icache_inval_tlb_rsp )
1649	{
1650	r_icache_inval_tlb_rsp = false;
1651	r_icache_fsm = ICACHE_IDLE;
1652	}
1653	break;
1654	}
1655	/////////////////////////////
1656	case ICACHE_SW_FLUSH:
1657	{
1658	size_t way = r_icache_way;
1659	size_t set = r_icache_set;
1660	bool clean = false;
1661
1662	// 4K page size TLB flush leads to cleanup req to data cache
1663	if ( !r_dcache_itlb_cleanup_req ) // last cleanup finish
1664	{
1665	paddr_t victim_index = 0;
1666	for ( ; way < m_itlb_ways; way++)
1667	{
1668	for ( ; set < m_itlb_sets; set++)
1669	{
1670	if(icache_tlb.checkcleanup(way, set, &victim_index))
1671	{
1672	clean = true;
1673	r_dcache_itlb_cleanup_req = true;
1674	r_dcache_itlb_cleanup_line = victim_index;
1675	r_icache_way = way + ((set+1)/m_itlb_sets);
1676	r_icache_set = (set+1) % m_itlb_sets;
1677	break;
1678	}
1679	}
1680	if (clean) break;
1681	set = 0;
1682	}
1683
1684	if (way == m_itlb_ways)
1685	{
1686	r_dcache_xtn_req = false;
1687	r_itlb_translation_valid = false;
1688	r_icache_ptba_ok = false;
1689	r_icache_fsm = ICACHE_IDLE;
1690	break;
1691	}
1692	}
1693	break;
1694	}
1695	/////////////////////
1696	case ICACHE_TLB_FLUSH:
1697	{
1698	// data cache flush leads to ins tlb flush, flush all tlb entry
1699	icache_tlb.flush(true); // global entries are invalidated
1700	r_dcache_xtn_req = false;
1701	r_itlb_translation_valid = false;
1702	r_icache_ptba_ok = false;
1703	r_icache_fsm = ICACHE_IDLE;
1704	break;
1705	}
1706	////////////////////////
1707	case ICACHE_CACHE_FLUSH:
1708	{
1709	// external cache invalidate request
1710	if ( r_tgt_icache_req )
1711	{
1712	r_icache_fsm = ICACHE_CC_INVAL;
1713	r_icache_fsm_save = r_icache_fsm;
1714	break;
1715	}
1716
1717	size_t way = r_icache_way;
1718	size_t set = r_icache_set;
1719	bool clean = false;
1720
1721	// cache flush and send cleanup to external
1722	if ( !r_icache_cleanup_req )
1723	{
1724	paddr_t victim_index = 0;
1725	for ( ; way < m_icache_ways; way++ )
1726	{
1727	for ( ; set < m_icache_sets; set++ )
1728	{
1729	if ( r_icache.flush(way, set, &victim_index) )
1730	{
1731	clean = true;
1732	r_icache_cleanup_req = true;
1733	r_icache_cleanup_line = victim_index;
1734	m_cpt_cc_cleanup_ins++;
1735	r_icache_way = way + ((set+1)/m_icache_sets);
1736	r_icache_set = (set+1) % m_icache_sets;
1737	break;
1738	}
1739	}
1740	if (clean) break;
1741	set = 0;
1742	}
1743	if (way == m_icache_ways)
1744	{
1745	r_dcache_xtn_req = false;
1746	r_icache_fsm = ICACHE_IDLE;
1747	break;
1748	}
1749	}
1750	break;
1751	}
1752	/////////////////////
1753	case ICACHE_TLB_INVAL:
1754	{
1755	paddr_t victim_index = 0;
1756
1757	if ( !r_dcache_itlb_cleanup_req )
1758	{
1759	r_dcache_itlb_cleanup_req = icache_tlb.inval(r_dcache_wdata_save, &victim_index);
1760	r_dcache_itlb_cleanup_line = victim_index;
1761	m_cpt_cc_cleanup_ins++;
1762	r_dcache_xtn_req = false;
1763	r_itlb_translation_valid = false;
1764	r_icache_ptba_ok = false;
1765	r_icache_fsm = ICACHE_IDLE;
1766	}
1767	break;
1768	}
1769	////////////////////////
1770	case ICACHE_CACHE_INVAL:
1771	{
1772	// external cache invalidate request
1773	if ( r_tgt_icache_req )
1774	{
1775	r_icache_fsm = ICACHE_CC_INVAL;
1776	r_icache_fsm_save = r_icache_fsm;
1777	break;
1778	}
1779
1780	paddr_t ipaddr = 0;
1781	bool icache_hit_t = false;
1782
1783	if ( !r_icache_cleanup_req )
1784	{
1785	if ( r_mmu_mode.read() & INS_TLB_MASK )
1786	{
1787	icache_hit_t = icache_tlb.translate(r_dcache_wdata_save, &ipaddr);
1788	}
1789	else
1790	{
1791	ipaddr = (paddr_t)r_dcache_wdata_save;
1792	icache_hit_t = true;
1793	}
1794	if ( icache_hit_t )
1795	{
1796	// invalidate and cleanup if necessary
1797	r_icache_cleanup_req = r_icache.inval(ipaddr);
1798	r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);
1799	m_cpt_cc_cleanup_ins++;
1800	}
1801	r_dcache_xtn_req = false;
1802	r_icache_fsm = ICACHE_IDLE;
1803	}
1804	break;
1805	}
1806	////////////////////////
1807	case ICACHE_CACHE_INVAL_PA:
1808	{
1809	// external cache invalidate request
1810	if ( r_tgt_icache_req )
1811	{
1812	r_icache_fsm = ICACHE_CC_INVAL;
1813	r_icache_fsm_save = r_icache_fsm;
1814	break;
1815	}
1816
1817	paddr_t ipaddr = (paddr_t)r_mmu_word_hi.read() << 32 \| r_mmu_word_lo.read();
1818
1819	if ( !r_icache_cleanup_req )
1820	{
1821	// invalidate and cleanup if necessary
1822	r_icache_cleanup_req = r_icache.inval(ipaddr);
1823	r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);
1824	m_cpt_cc_cleanup_ins++;
1825	r_dcache_xtn_req = false;
1826	r_icache_fsm = ICACHE_IDLE;
1827	}
1828	break;
1829	}
1830	///////////////////////
1831	case ICACHE_MISS_WAIT:
1832	{
1833	m_cost_ins_miss_frz++;
1834
1835	// external cache invalidate request
1836	if ( r_tgt_icache_req )
1837	{
1838	r_icache_fsm = ICACHE_CC_INVAL;
1839	r_icache_fsm_save = r_icache_fsm;
1840	break;
1841	}
1842
1843	// external tlb invalidate request
1844	if ( r_dcache_itlb_inval_req )
1845	{
1846	r_itlb_inval_req = true;
1847	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1848	r_icache_fsm_save = r_icache_fsm;
1849	break;
1850	}
1851
1852	if ( !r_icache_miss_req )
1853	{
1854	if ( r_vci_rsp_ins_error )
1855	{
1856	r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;
1857	r_icache_bad_vaddr = ireq.addr;
1858	r_icache_fsm = ICACHE_ERROR;
1859
1860	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
1861	if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
1862	break;
1863	}
1864
1865	if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
1866	{
1867	if ( r_icache_cleanup_req ) break;
1868	r_icache_cleanup_req = true;
1869	r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);
1870	m_cpt_cc_cleanup_ins++;
1871	r_icache_fsm = ICACHE_IDLE;
1872	r_icache_inval_tlb_rsp = false;
1873	if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
1874	break;
1875	}
1876
1877	if ( r_icache_inval_rsp ) // Miss read response and tlb invalidation
1878	{
1879	if ( r_icache_cleanup_req ) break;
1880	r_icache_cleanup_req = true;
1881	r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);
1882	m_cpt_cc_cleanup_ins++;
1883	r_icache_fsm = ICACHE_IDLE;
1884	r_icache_inval_rsp = false;
1885	break;
1886	}
1887	r_icache_fsm = ICACHE_MISS_UPDT;
1888	}
1889	break;
1890	}
1891	////////////////////
1892	case ICACHE_UNC_WAIT:
1893	{
1894	// external cache invalidate request
1895	if ( r_tgt_icache_req )
1896	{
1897	r_icache_fsm = ICACHE_CC_INVAL;
1898	r_icache_fsm_save = r_icache_fsm;
1899	break;
1900	}
1901
1902	// external tlb invalidate request
1903	if ( r_dcache_itlb_inval_req )
1904	{
1905	r_itlb_inval_req = true;
1906	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1907	r_icache_fsm_save = r_icache_fsm;
1908	break;
1909	}
1910
1911	if ( !r_icache_unc_req )
1912	{
1913	if ( r_vci_rsp_ins_error )
1914	{
1915	r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;
1916	r_icache_bad_vaddr = ireq.addr;
1917	r_icache_fsm = ICACHE_ERROR;
1918
1919	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
1920	//if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
1921	break;
1922	}
1923
1924	if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
1925	{
1926	r_icache_inval_tlb_rsp = false;
1927	r_icache_fsm = ICACHE_IDLE;
1928	break;
1929	}
1930
1931	// Miss read response and no invalidation
1932	r_icache_buf_unc_valid = true;
1933	r_icache_fsm = ICACHE_IDLE;
1934	}
1935	break;
1936	}
1937	//////////////////////
1938	case ICACHE_MISS_UPDT:
1939	{
1940	m_cost_ins_miss_frz++;
1941
1942	// external cache invalidate request
1943	if ( r_tgt_icache_req )
1944	{
1945	r_icache_fsm = ICACHE_CC_INVAL;
1946	r_icache_fsm_save = r_icache_fsm;
1947	break;
1948	}
1949
1950	// external tlb invalidate request
1951	if ( r_dcache_itlb_inval_req )
1952	{
1953	r_itlb_inval_req = true;
1954	r_icache_fsm = ICACHE_TLB_CC_INVAL;
1955	r_icache_fsm_save = r_icache_fsm;
1956	break;
1957	}
1958
1959	if ( r_icache_inval_tlb_rsp ) // tlb invalidation
1960	{
1961	if ( r_icache_cleanup_req ) break;
1962	r_icache_cleanup_req = true;
1963	r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);
1964	m_cpt_cc_cleanup_ins++;
1965	r_icache_inval_tlb_rsp = false;
1966	if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
1967	r_icache_fsm = ICACHE_IDLE;
1968	break;
1969	}
1970
1971	if ( !r_icache_cleanup_req ) // Miss update and no invalidation
1972	{
1973	if ( r_icache_inval_rsp ) // invalidation
1974	{
1975	r_icache_cleanup_req = true;
1976	r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);
1977	m_cpt_cc_cleanup_ins++;
1978	r_icache_fsm = ICACHE_IDLE;
1979	r_icache_inval_rsp = false;
1980	}
1981	else
1982	{
1983	data_t* buf = r_icache_miss_buf;
1984	paddr_t victim_index = 0;
1985	m_cpt_icache_dir_write++;
1986	m_cpt_icache_data_write++;
1987
1988	r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index);
1989	r_icache_cleanup_line = victim_index; m_cpt_cc_cleanup_ins++;
1990	r_icache_fsm = ICACHE_IDLE;
1991	}
1992	}
1993	break;
1994	}
1995	///////////////////
1996	case ICACHE_ERROR:
1997	{
1998	r_vci_rsp_ins_error = false;
1999	r_dcache_rsp_itlb_error = false;
2000	irsp.valid = true;
2001	irsp.error = true;
2002	irsp.instruction = 0;
2003	r_icache_fsm = ICACHE_IDLE;
2004	break;
2005	}
2006	/////////////////////
2007	case ICACHE_CC_INVAL:
2008	{
2009	m_cpt_icache_dir_read += m_icache_ways;
2010	/* activity counter */
2011	if ( (( r_icache_fsm_save == ICACHE_BIS ) \|\|( r_icache_fsm_save == ICACHE_MISS_WAIT ) \|\| ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) )
2012	{
2013	m_cost_ins_miss_frz++;
2014	}
2015	if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_READ ) \|\|
2016	( r_icache_fsm_save == ICACHE_TLB1_WRITE ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) \|\|
2017	( r_icache_fsm_save == ICACHE_TLB1_UPDT ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && (ireq.valid) )
2018	{
2019	m_cost_ins_tlb_miss_frz++;
2020	}
2021
2022	// invalidate cache
2023	if( (( r_icache_fsm_save == ICACHE_MISS_WAIT ) \|\| ( r_icache_fsm_save == ICACHE_MISS_UPDT ) /*\|\|
2024	( r_icache_fsm_save == ICACHE_UNC_WAIT )*/ ) &&
2025	((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_icache_words<<2)-1))) )
2026	{
2027	r_icache_inval_rsp = true;
2028	r_tgt_icache_rsp = false;
2029	}
2030	else
2031	{
2032	r_tgt_icache_rsp = r_icache.inval(r_tgt_addr.read());
2033	}
2034	r_tgt_icache_req = false;
2035	r_icache_fsm = r_icache_fsm_save;
2036	break;
2037	}
2038	/////////////////////////
2039	case ICACHE_TLB_CC_INVAL:
2040	{
2041	/* activity counter */
2042	if ( (( r_icache_fsm_save == ICACHE_BIS ) \|\|( r_icache_fsm_save == ICACHE_MISS_WAIT ) \|\| ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) )
2043	{
2044	m_cost_ins_miss_frz++;
2045	}
2046	if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_READ ) \|\|
2047	( r_icache_fsm_save == ICACHE_TLB1_WRITE ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) \|\|
2048	( r_icache_fsm_save == ICACHE_TLB1_UPDT ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && (ireq.valid) )
2049	{
2050	m_cost_ins_tlb_miss_frz++;
2051	}
2052
2053	if ( r_itlb_inval_req ) break;
2054	// invalidate cache
2055	if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_READ ) \|\|
2056	( r_icache_fsm_save == ICACHE_TLB1_WRITE )\|\| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) \|\|
2057	( r_icache_fsm_save == ICACHE_TLB1_UPDT ) \|\| ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) &&
2058	(((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2) ) == r_dcache_itlb_inval_line.read()) )
2059	{
2060	r_icache_inval_tlb_rsp = true;
2061	}
2062	else if (((r_icache_fsm_save == ICACHE_BIS)\|\|(r_icache_fsm_save == ICACHE_MISS_WAIT) \|\|
2063	/* (r_icache_fsm_save == ICACHE_UNC_WAIT)\|\|*/(r_icache_fsm_save == ICACHE_MISS_UPDT)) &&
2064	(r_icache_tlb_nline.read() == r_dcache_itlb_inval_line.read()))
2065	{
2066	r_icache_inval_tlb_rsp = true;
2067	}
2068	r_dcache_itlb_inval_req = false;
2069	r_itlb_translation_valid = false;
2070	r_icache_ptba_ok = false;
2071	r_icache_fsm = r_icache_fsm_save;
2072	break;
2073	}
2074	} // end switch r_icache_fsm
2075
2076	#ifdef SOCLIB_MODULE_DEBUG
2077	std::cout << name() << " Instruction Response: " << irsp << std::endl;
2078	#endif
2079
2080	////////////////////////////////////////////////////////////////////////////////////
2081	// INVAL ITLB CHECK FSM
2082	////////////////////////////////////////////////////////////////////////////////////////
2083	switch(r_inval_itlb_fsm) {
2084	/////////////////////
2085	case INVAL_ITLB_IDLE:
2086	{
2087	if ( r_itlb_inval_req )
2088	{
2089	r_ccinval_itlb_way = 0;
2090	r_ccinval_itlb_set = 0;
2091	r_inval_itlb_fsm = INVAL_ITLB_CHECK;
2092	m_cost_ins_tlb_inval_frz++;
2093	}
2094	break;
2095	}
2096	////////////////////////////
2097	case INVAL_ITLB_CHECK:
2098	{
2099	m_cost_ins_tlb_inval_frz++;
2100
2101	size_t way = r_ccinval_itlb_way;
2102	size_t set = r_ccinval_itlb_set;
2103	bool end = false;
2104	bool tlb_hit = icache_tlb.cccheck(r_dcache_itlb_inval_line.read(), way, set, &way, &set, &end);
2105
2106	if ( tlb_hit )
2107	{
2108	r_ccinval_itlb_way = way;
2109	r_ccinval_itlb_set = set;
2110	r_itlb_cc_check_end = end;
2111	r_inval_itlb_fsm = INVAL_ITLB_INVAL;
2112	m_cpt_ins_tlb_inval++;
2113	}
2114	else
2115	{
2116	r_inval_itlb_fsm = INVAL_ITLB_CLEAR;
2117	}
2118	break;
2119	}
2120	/////////////////////////
2121	case INVAL_ITLB_INVAL:
2122	{
2123	m_cost_ins_tlb_inval_frz++;
2124
2125	icache_tlb.ccinval(r_ccinval_itlb_way, r_ccinval_itlb_set);
2126
2127	if ( !r_itlb_cc_check_end )
2128	{
2129	r_inval_itlb_fsm = INVAL_ITLB_CHECK;
2130	}
2131	else
2132	{
2133	r_inval_itlb_fsm = INVAL_ITLB_CLEAR;
2134	}
2135	break;
2136	}
2137	////////////////////
2138	case INVAL_ITLB_CLEAR:
2139	{
2140	r_itlb_inval_req = false;
2141	r_itlb_cc_check_end = false;
2142	r_ccinval_itlb_way = 0;
2143	r_ccinval_itlb_set = 0;
2144	r_inval_itlb_fsm = INVAL_ITLB_IDLE;
2145	m_cost_ins_tlb_inval_frz++;
2146	break;
2147	}
2148	} // end switch r_inval_itlb_fsm
2149
2150	////////////////////////////////////////////////////////////////////////////////////
2151	// DCACHE FSM
2152	//
2153	// Both the Cacheability Table, and the MMU cached bit are used to define
2154	// the cacheability.
2155	//
2156	// There is 14 mutually exclusive conditions to exit the IDLE state.
2157	// Seven configurations corresponding to an XTN request from processor:
2158	// - Context switch => CTXT_SWITCH state
2159	// - Flush dcache => DCACHE_FLUSH state
2160	// - Flush icache => ICACHE_FLUSH state
2161	// - Invalidate a dtlb entry => DTLB_INVAL state
2162	// - Invalidate a itlb entry => ITLB_INVAL state
2163	// - Invalidate a dcache line => DCACHE_INVAL state
2164	// - Invalidate a icache line => ICACHE_INVAL state
2165	// Seven configurations corresponding to various read miss or write requests:
2166	// - TLB miss(in case hit_p miss) => TLB1_READ state
2167	// - TLB miss(in case hit_p hit) => TLB2_READ state
2168	// - Hit in TLB but VPN changed => BIS state
2169	// - Cached read miss => MISS_REQ state
2170	// - Uncache read miss => UNC_REQ state
2171	// - Write hit => WRITE_UPDT state
2172	// - Write miss => WRITE_REQ
2173	//
2174	// The r_vci_rsp_data_error flip-flop is set by the VCI_RSP controller and reset
2175	// by DCACHE-FSM when its state is in DCACHE_ERROR.
2176	//---------------------------------------------------------------------
2177	// Data TLB:
2178	//
2179	// - int ET (00: unmapped; 01: unused or PTD)
2180	// (10: PTE new; 11: PTE old )
2181	// - bool cachable (cached bit)
2182	// - bool writable (writable bit)
2183	// - bool executable (** not used alwayse false)
2184	// - bool user (access in user mode allowed)
2185	// - bool global (PTE not invalidated by a TLB flush)
2186	// - bool dirty (page has been modified)
2187	// - uint32_t vpn (virtual page number)
2188	// - uint32_t ppn (physical page number)
2189	////////////////////////////////////////////////////////////////////////////////////////
2190
2191	switch (r_dcache_fsm) {
2192	//////////////////////
2193	case DCACHE_WRITE_REQ:
2194	{
2195	// external cache invalidate request
2196	if ( r_tgt_dcache_req )
2197	{
2198	r_dcache_fsm = DCACHE_CC_CHECK;
2199	r_dcache_fsm_save = r_dcache_fsm;
2200	break;
2201	}
2202
2203	// try to post the write request in the write buffer
2204	if ( !r_dcache_write_req ) // no previous write transaction
2205	{
2206	if ( r_wbuf.wok(r_dcache_paddr_save) ) // write request in the same cache line
2207	{
2208	r_wbuf.write(r_dcache_paddr_save.read(), r_dcache_be_save.read(), r_dcache_wdata_save);
2209	// closing the write packet if uncached
2210	if ( !r_dcache_cached_save )
2211	{
2212	r_dcache_write_req = true;
2213	}
2214	}
2215	else
2216	{ // close the write packet if write request not in the same cache line
2217	r_dcache_write_req = true;
2218	m_cost_write_frz++;
2219	break; // posting not possible : stay in DCACHE_WRITEREQ state
2220	}
2221	}
2222	else // previous write transaction not completed
2223	{
2224	m_cost_write_frz++;
2225	break; // posting not possible : stay in DCACHE_WRITEREQ state
2226	}
2227
2228	// close the write packet if the next processor request is not a write
2229	if ( !dreq.valid \|\| (dreq.type != iss_t::DATA_WRITE))
2230	{
2231	r_dcache_write_req = true;
2232	}
2233
2234	// The next state and the processor request parameters are computed
2235	// as in the DCACHE_IDLE state (see below ...)
2236	}
2237	/////////////////
2238	case DCACHE_IDLE:
2239	{
2240	// external cache invalidate request
2241	if ( r_tgt_dcache_req )
2242	{
2243	r_dcache_fsm = DCACHE_CC_CHECK;
2244	r_dcache_fsm_save = DCACHE_IDLE;
2245	break;
2246	}
2247
2248	// ins tlb cleanup
2249	if ( r_dcache_itlb_cleanup_req )
2250	{
2251	r_dcache_fsm = DCACHE_ITLB_CLEANUP;
2252	break;
2253	}
2254	// ins tlb miss
2255	if ( r_itlb_read_dcache_req )
2256	{
2257	if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
2258	data_t rsp_itlb_miss;
2259	data_t rsp_itlb_ppn;
2260
2261	bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
2262	if ( r_itlb_k_read_dcache && itlb_hit_dcache )
2263	{
2264	r_itlb_k_read_dcache = false;
2265	bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
2266	assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
2267	}
2268
2269	m_cpt_dcache_data_read += m_dcache_ways;
2270	m_cpt_dcache_dir_read += m_dcache_ways;
2271
2272	if ( itlb_hit_dcache ) // ins TLB request hits in data cache
2273	{
2274	if (!((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT)) m_cpt_ins_tlb_hit_dcache++;
2275	r_dcache_rsp_itlb_miss = rsp_itlb_miss;
2276	r_dcache_rsp_itlb_ppn = rsp_itlb_ppn;
2277	r_itlb_read_dcache_req = false;
2278	r_dcache_fsm = DCACHE_IDLE;
2279
2280	// set TLB bit if it's a PTE
2281	if ( !((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT) )
2282	{
2283	bool set_hit = r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
2284	assert(set_hit && "D$ IDLE ITLB set hit error");
2285	}
2286	}
2287	else // ins TLB request miss in data cache
2288	{
2289	r_dcache_itlb_read_req = true;
2290	r_dcache_fsm = DCACHE_ITLB_READ;
2291	}
2292	}
2293	else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit
2294	{
2295	data_t rsp_itlb_miss;
2296	bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
2297	if ( itlb_hit_dcache )
2298	{
2299	r_dcache_itlb_ll_acc_req = true;
2300	r_dcache_fsm = DCACHE_ITLB_LL_WAIT;
2301	m_cpt_dcache_data_write++;
2302	}
2303	else
2304	{
2305	r_itlb_acc_dcache_req = false;
2306	r_itlb_acc_redo_req = true;
2307	r_dcache_fsm = DCACHE_IDLE;
2308	}
2309	}
2310	else if (dreq.valid)
2311	{
2312	pte_info_t dcache_pte_info;
2313	int xtn_opcod = (int)dreq.addr/4;
2314	paddr_t tlb_dpaddr = 0; // physical address obtained from TLB
2315	paddr_t spc_dpaddr = 0; // physical adress obtained from PPN_save (speculative)
2316	bool dcache_hit_t = false; // hit on 4Kilo TLB
2317	bool dcache_hit_x = false; // VPN unmodified (can use spc_dpaddr)
2318	bool dcache_hit_p = false; // PTP unmodified (can skip first level page table walk)
2319	bool dcache_hit_c = false; // Cache hit
2320	bool dcache_cached = false; // cacheable access (read or write)
2321	size_t dcache_tlb_way = 0; // selected way (in case of cache hit)
2322	size_t dcache_tlb_set = 0; // selected set (Y field in address)
2323	data_t dcache_rdata = 0; // read data
2324	paddr_t dcache_tlb_nline = 0; // TLB NLINE
2325
2326	m_cpt_dcache_data_read += m_dcache_ways;
2327	m_cpt_dcache_dir_read += m_dcache_ways;
2328
2329	// Decoding READ XTN requests from processor
2330	// They are executed in this DCACHE_IDLE state
2331
2332	if (dreq.type == iss_t::XTN_READ)
2333	{
2334	switch(xtn_opcod) {
2335	case iss_t::XTN_INS_ERROR_TYPE:
2336	drsp.rdata = (uint32_t)r_icache_error_type;
2337	r_icache_error_type = MMU_NONE;
2338	drsp.valid = true;
2339	drsp.error = false;
2340	break;
2341	case iss_t::XTN_DATA_ERROR_TYPE:
2342	drsp.rdata = (uint32_t)r_dcache_error_type;
2343	r_dcache_error_type = MMU_NONE;
2344	drsp.valid = true;
2345	drsp.error = false;
2346	break;
2347	case iss_t::XTN_INS_BAD_VADDR:
2348	drsp.rdata = (uint32_t)r_icache_bad_vaddr;
2349	drsp.valid = true;
2350	drsp.error = false;
2351	break;
2352	case iss_t::XTN_DATA_BAD_VADDR:
2353	drsp.rdata = (uint32_t)r_dcache_bad_vaddr;
2354	drsp.valid = true;
2355	drsp.error = false;
2356	break;
2357	case iss_t::XTN_PTPR:
2358	drsp.rdata = (uint32_t)r_mmu_ptpr;
2359	drsp.valid = true;
2360	drsp.error = false;
2361	break;
2362	case iss_t::XTN_TLB_MODE:
2363	drsp.rdata = (uint32_t)r_mmu_mode;
2364	drsp.valid = true;
2365	drsp.error = false;
2366	break;
2367	case iss_t::XTN_MMU_PARAMS:
2368	drsp.rdata = (uint32_t)r_mmu_params;
2369	drsp.valid = true;
2370	drsp.error = false;
2371	break;
2372	case iss_t::XTN_MMU_RELEASE:
2373	drsp.rdata = (uint32_t)r_mmu_release;
2374	drsp.valid = true;
2375	drsp.error = false;
2376	break;
2377	case iss_t::XTN_MMU_WORD_LO:
2378	drsp.rdata = (uint32_t)r_mmu_word_lo;
2379	drsp.valid = true;
2380	drsp.error = false;
2381	break;
2382	case iss_t::XTN_MMU_WORD_HI:
2383	drsp.rdata = (uint32_t)r_mmu_word_hi;
2384	drsp.valid = true;
2385	drsp.error = false;
2386	break;
2387	default:
2388	r_dcache_error_type = MMU_READ_UNDEFINED_XTN;
2389	r_dcache_bad_vaddr = dreq.addr;
2390	drsp.valid = true;
2391	drsp.error = true;
2392	break;
2393	}
2394	r_dcache_fsm = DCACHE_IDLE;
2395	break;
2396	}
2397
2398	// Decoding WRITE XTN requests from processor
2399	// If there is no privilege violation, they are not executed in this DCACHE_IDLE state,
2400	// but in the next state, because they generally require access to the caches or the TLBs
2401
2402	if (dreq.type == iss_t::XTN_WRITE)
2403	{
2404	drsp.valid = false;
2405	drsp.error = false;
2406	drsp.rdata = 0;
2407	r_dcache_wdata_save = dreq.wdata;
2408	switch(xtn_opcod) {
2409
2410	case iss_t::XTN_PTPR: // context switch : checking the kernel mode
2411	// both instruction & data TLBs must be flushed
2412	if ((dreq.mode == iss_t::MODE_HYPER) \|\| (dreq.mode == iss_t::MODE_KERNEL))
2413	{
2414	r_mmu_ptpr = dreq.wdata;
2415	r_icache_error_type = MMU_NONE;
2416	r_dcache_error_type = MMU_NONE;
2417	r_dcache_type_save = dreq.addr/4;
2418	r_dcache_xtn_req = true;
2419	r_dcache_fsm = DCACHE_CTXT_SWITCH;
2420	}
2421	else
2422	{
2423	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2424	r_dcache_bad_vaddr = dreq.addr;
2425	drsp.valid = true;
2426	drsp.error = true;
2427	r_dcache_fsm = DCACHE_IDLE;
2428	}
2429	break;
2430
2431	case iss_t::XTN_TLB_MODE: // modifying TLBs mode : checking the kernel mode
2432	if ((dreq.mode == iss_t::MODE_HYPER) \|\| (dreq.mode == iss_t::MODE_KERNEL))
2433	{
2434	r_mmu_mode = (int)dreq.wdata;
2435	drsp.valid = true;
2436	}
2437	else
2438	{
2439	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2440	r_dcache_bad_vaddr = dreq.addr;
2441	drsp.valid = true;
2442	drsp.error = true;
2443	}
2444	r_dcache_fsm = DCACHE_IDLE;
2445	break;
2446
2447	case iss_t::XTN_DTLB_INVAL: // checking the kernel mode
2448	if ((dreq.mode == iss_t::MODE_HYPER) \|\| (dreq.mode == iss_t::MODE_KERNEL))
2449	{
2450	r_dcache_fsm = DCACHE_DTLB_INVAL;
2451	}
2452	else
2453	{
2454	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2455	r_dcache_bad_vaddr = dreq.addr;
2456	drsp.valid = true;
2457	drsp.error = true;
2458	r_dcache_fsm = DCACHE_IDLE;
2459	}
2460	break;
2461
2462	case iss_t::XTN_ITLB_INVAL: // checking the kernel mode
2463	if ((dreq.mode == iss_t::MODE_HYPER) \|\| (dreq.mode == iss_t::MODE_KERNEL))
2464	{
2465	r_dcache_xtn_req = true;
2466	r_dcache_type_save = dreq.addr/4;
2467	r_dcache_fsm = DCACHE_ITLB_INVAL;
2468	}
2469	else
2470	{
2471	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2472	r_dcache_bad_vaddr = dreq.addr;
2473	drsp.valid = true;
2474	drsp.error = true;
2475	r_dcache_fsm = DCACHE_IDLE;
2476	}
2477	break;
2478
2479	case iss_t::XTN_DCACHE_INVAL: // cache inval can be executed in user mode.
2480	r_dcache_fsm = DCACHE_DCACHE_INVAL;
2481	break;
2482
2483	case iss_t::XTN_MMU_DCACHE_PA_INV: // cache inval can be executed in user mode.
2484	r_dcache_fsm = DCACHE_DCACHE_INVAL_PA;
2485	break;
2486
2487	case iss_t::XTN_DCACHE_FLUSH: // cache flush can be executed in user mode.
2488	r_dcache_type_save = dreq.addr/4;
2489	r_dcache_xtn_req = true;
2490	r_dcache_way = 0;
2491	r_dcache_set = 0;
2492	r_dcache_fsm = DCACHE_DCACHE_FLUSH;
2493	break;
2494
2495	case iss_t::XTN_ICACHE_INVAL: // cache inval can be executed in user mode.
2496	r_dcache_type_save = dreq.addr/4;
2497	r_dcache_xtn_req = true;
2498	r_dcache_fsm = DCACHE_ICACHE_INVAL;
2499	break;
2500
2501	case iss_t::XTN_MMU_ICACHE_PA_INV: // cache inval can be executed in user mode.
2502	r_dcache_type_save = dreq.addr/4;
2503	r_dcache_xtn_req = true;
2504	r_dcache_fsm = DCACHE_ICACHE_INVAL_PA;
2505	break;
2506
2507	case iss_t::XTN_ICACHE_FLUSH: // cache flush can be executed in user mode.
2508	r_dcache_type_save = dreq.addr/4;
2509	r_dcache_xtn_req = true;
2510	r_dcache_fsm = DCACHE_ICACHE_FLUSH;
2511	break;
2512
2513	case iss_t::XTN_SYNC: // cache synchronization can be executed in user mode.
2514	if (r_wbuf.rok())
2515	{
2516	r_dcache_fsm = DCACHE_DCACHE_SYNC;
2517	}
2518	else
2519	{
2520	drsp.valid = true;
2521	r_dcache_fsm = DCACHE_IDLE;
2522	}
2523	break;
2524
2525	case iss_t::XTN_MMU_WORD_LO: // modifying MMU misc registers
2526	if ((dreq.mode == iss_t::MODE_HYPER) \|\| (dreq.mode == iss_t::MODE_KERNEL))
2527	{
2528	r_mmu_word_lo = (int)dreq.wdata;
2529	drsp.valid = true;
2530	}
2531	else
2532	{
2533	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2534	r_dcache_bad_vaddr = dreq.addr;
2535	drsp.valid = true;
2536	drsp.error = true;
2537	}
2538	r_dcache_fsm = DCACHE_IDLE;
2539	break;
2540
2541	case iss_t::XTN_MMU_WORD_HI: // modifying MMU misc registers
2542	if ((dreq.mode == iss_t::MODE_HYPER) \|\| (dreq.mode == iss_t::MODE_KERNEL))
2543	{
2544	r_mmu_word_hi = (int)dreq.wdata;
2545	drsp.valid = true;
2546	}
2547	else
2548	{
2549	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2550	r_dcache_bad_vaddr = dreq.addr;
2551	drsp.valid = true;
2552	drsp.error = true;
2553	}
2554	r_dcache_fsm = DCACHE_IDLE;
2555	break;
2556
2557	case iss_t::XTN_ICACHE_PREFETCH:
2558	case iss_t::XTN_DCACHE_PREFETCH:
2559	drsp.valid = true;
2560	drsp.error = false;
2561	break;
2562
2563	default:
2564	r_dcache_error_type = MMU_WRITE_UNDEFINED_XTN;
2565	r_dcache_bad_vaddr = dreq.addr;
2566	drsp.valid = true;
2567	drsp.error = true;
2568	r_dcache_fsm = DCACHE_IDLE;
2569	break;
2570	} // end switch xtn_opcod
2571
2572	break;
2573	} // end if XTN_WRITE
2574
2575	// Evaluating dcache_hit_t, dcache_hit_x, dcache_hit_p, dcache_hit_c,
2576	// dcache_pte_info, dcache_tlb_way, dcache_tlb_set & dpaddr & cacheability
2577	// - If MMU activated : cacheability is defined by the cachable bit in the TLB
2578	// - If MMU not activated : cacheability is defined by the segment table.
2579
2580	if ( !(r_mmu_mode.read() & DATA_TLB_MASK) ) // MMU not activated
2581	{
2582	dcache_hit_t = true;
2583	dcache_hit_x = true;
2584	dcache_hit_p = true;
2585	tlb_dpaddr = dreq.addr;
2586	spc_dpaddr = dreq.addr;
2587	dcache_cached = m_cacheability_table[dreq.addr] &&
2588	((dreq.type != iss_t::DATA_LL) && (dreq.type != iss_t::DATA_SC) &&
2589	(dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));
2590	}
2591	else // MMU activated
2592	{
2593	m_cpt_data_tlb_read++;
2594	dcache_hit_t = dcache_tlb.cctranslate(dreq.addr, &tlb_dpaddr, &dcache_pte_info,
2595	&dcache_tlb_nline, &dcache_tlb_way, &dcache_tlb_set);
2596	dcache_hit_x = (((vaddr_t)r_dcache_vpn_save << PAGE_K_NBITS) == (dreq.addr & ~PAGE_K_MASK)) && r_dtlb_translation_valid;
2597	dcache_hit_p = (((dreq.addr >> PAGE_M_NBITS) == r_dcache_id1_save) && r_dcache_ptba_ok );
2598	spc_dpaddr = ((paddr_t)r_dcache_ppn_save << PAGE_K_NBITS) \| (paddr_t)((dreq.addr & PAGE_K_MASK));
2599	dcache_cached = dcache_pte_info.c &&
2600	((dreq.type != iss_t::DATA_LL) && (dreq.type != iss_t::DATA_SC) &&
2601	(dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));
2602	}
2603
2604	if ( !(r_mmu_mode.read() & DATA_CACHE_MASK) ) // cache not actived
2605	{
2606	dcache_cached = false;
2607	}
2608
2609	// dcache_hit_c & dcache_rdata
2610	if ( dcache_cached ) // using speculative physical address for cached access
2611	{
2612	dcache_hit_c = r_dcache.read(spc_dpaddr, &dcache_rdata);
2613	}
2614	else // using actual physical address for uncached access
2615	{
2616	dcache_hit_c = false;
2617	}
2618	if ( r_mmu_mode.read() & DATA_TLB_MASK )
2619	{
2620	// Checking access rights
2621	if ( dcache_hit_t )
2622	{
2623	if (!dcache_pte_info.u && (dreq.mode == iss_t::MODE_USER))
2624	{
2625	if ((dreq.type == iss_t::DATA_READ)\|\|(dreq.type == iss_t::DATA_LL))
2626	{
2627	r_dcache_error_type = MMU_READ_PRIVILEGE_VIOLATION;
2628	}
2629	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
2630	{
2631	r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
2632	}
2633	r_dcache_bad_vaddr = dreq.addr;
2634	drsp.valid = true;
2635	drsp.error = true;
2636	drsp.rdata = 0;
2637	r_dcache_fsm = DCACHE_IDLE;
2638	break;
2639	}
2640	if (!dcache_pte_info.w && ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC)))
2641	{
2642	r_dcache_error_type = MMU_WRITE_ACCES_VIOLATION;
2643	r_dcache_bad_vaddr = dreq.addr;
2644	drsp.valid = true;
2645	drsp.error = true;
2646	drsp.rdata = 0;
2647	r_dcache_fsm = DCACHE_IDLE;
2648	break;
2649	}
2650	}
2651
2652	// update LRU, save ppn, vpn and page type
2653	if ( dcache_hit_t ) {
2654	dcache_tlb.setlru(dcache_tlb_way,dcache_tlb_set);
2655	r_dcache_ppn_save = tlb_dpaddr >> PAGE_K_NBITS;
2656	r_dcache_vpn_save = dreq.addr >> PAGE_K_NBITS;
2657	r_dcache_tlb_nline = dcache_tlb_nline;
2658	r_dtlb_translation_valid = true;
2659	}
2660	else
2661	{
2662	r_dtlb_translation_valid = false;
2663	}
2664
2665	} // end if MMU activated
2666
2667	// compute next state
2668	if ( !dcache_hit_p && !dcache_hit_t ) // TLB miss
2669	{
2670	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
2671	r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
2672	m_cpt_data_tlb_miss++;
2673	m_cost_data_tlb_miss_frz++;
2674	}
2675	else if ( dcache_hit_p && !dcache_hit_t ) // TLB Miss with possibility of bypass first level page
2676	{
2677	// walk page table level 2
2678	r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save \|
2679	(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
2680	r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
2681	m_cpt_data_tlb_miss++;
2682	m_cost_data_tlb_miss_frz++;
2683	}
2684	else if ( dcache_hit_t && !dcache_hit_x && dcache_cached )// cached access with an ucorrect speculative physical address
2685	{
2686	r_dcache_hit_p_save = dcache_hit_p;
2687	r_dcache_fsm = DCACHE_BIS;
2688	m_cost_data_tlb_miss_frz++;
2689	}
2690	else // cached or uncached access with a correct speculative physical address
2691	{
2692	switch( dreq.type ) {
2693	case iss_t::DATA_READ:
2694	case iss_t::DATA_LL:
2695	case iss_t::DATA_SC:
2696	m_cpt_read++;
2697	if ( dcache_hit_c )
2698	{
2699	r_dcache_fsm = DCACHE_IDLE;
2700	drsp.valid = true;
2701	drsp.rdata = dcache_rdata;
2702	}
2703	else
2704	{
2705	if ( dcache_cached )
2706	{
2707	r_dcache_miss_req = true;
2708	r_dcache_fsm = DCACHE_MISS_WAIT;
2709	m_cpt_data_miss++;
2710	m_cost_data_miss_frz++;
2711	}
2712	else
2713	{
2714	if ((dreq.type == iss_t::DATA_SC) && !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK))
2715	{
2716	m_cpt_data_tlb_update_dirty++;
2717	m_cost_data_tlb_update_dirty_frz++;
2718	r_dcache_sc_updt_dirty = true;
2719	if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) ) // 2M page size, one level page table
2720	{
2721	r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) \| PTE_D_MASK;
2722	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
2723	r_dcache_tlb_ll_dirty_req = true;
2724	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2725	}
2726	else // 4k page size, two levels page table
2727	{
2728	if (dcache_hit_p)
2729	{
2730	r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) \| PTE_D_MASK;
2731	r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save \| (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
2732	r_dcache_tlb_ll_dirty_req = true;
2733	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2734	}
2735	else // get PTBA to calculate the physical address of PTE
2736	{
2737	data_t ptba;
2738	if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
2739	{
2740	r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) \| PTE_D_MASK;
2741	r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2742	(paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2743	r_dcache_tlb_ll_dirty_req = true;
2744	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2745
2746	}
2747	else
2748	{
2749	r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) \| PTE_D_MASK;
2750	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
2751	r_dcache_tlb_ptba_read = true;
2752	r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
2753	}
2754	}
2755	}
2756	}
2757	else
2758	{
2759	r_dcache_unc_req = true;
2760	r_dcache_fsm = DCACHE_UNC_WAIT;
2761	m_cpt_unc_read++;
2762	}
2763	m_cost_unc_read_frz++;
2764	}
2765	}
2766	break;
2767	/*
2768	case iss_t::DATA_READ:
2769	m_cpt_read++;
2770	if ( dcache_hit_c )
2771	{
2772	r_dcache_buf_unc_valid = false;
2773	r_dcache_fsm = DCACHE_IDLE;
2774	drsp.valid = true;
2775	drsp.rdata = dcache_rdata;
2776	}
2777	else
2778	{
2779	if ( dcache_cached )
2780	{
2781	r_dcache_miss_req = true;
2782	r_dcache_fsm = DCACHE_MISS_WAIT;
2783	m_cpt_data_miss++;
2784	m_cost_data_miss_frz++;
2785	}
2786	else
2787	{
2788	r_dcache_unc_req = true;
2789	r_dcache_fsm = DCACHE_UNC_WAIT;
2790	m_cpt_unc_read++;
2791	m_cost_unc_read_frz++;
2792	}
2793	}
2794	break;
2795	case iss_t::DATA_LL:
2796	if (r_dcache_llsc_reserved && (r_dcache_llsc_addr_save == tlb_dpaddr) && r_dcache_buf_unc_valid)
2797	{
2798	r_dcache_buf_unc_valid = false;
2799	r_dcache_fsm = DCACHE_IDLE;
2800	drsp.valid = true;
2801	drsp.rdata = dcache_rdata;
2802	}
2803	else
2804	{
2805	r_dcache_llsc_reserved = true;
2806	r_dcache_llsc_addr_save = tlb_dpaddr;
2807	r_dcache_unc_req = true;
2808	r_dcache_fsm = DCACHE_UNC_WAIT;
2809	}
2810	break;
2811	case iss_t::DATA_SC:
2812	if (r_dcache_llsc_reserved && (r_dcache_llsc_addr_save == tlb_dpaddr))
2813	{
2814	r_dcache_llsc_reserved = false;
2815	r_dcache_unc_req = true;
2816	r_dcache_fsm = DCACHE_UNC_WAIT;
2817	}
2818	else
2819	{
2820	if ( r_dcache_buf_unc_valid )
2821	{
2822	r_dcache_llsc_reserved = false;
2823	r_dcache_buf_unc_valid = false;
2824	drsp.valid = true;
2825	drsp.rdata = dcache_rdata;
2826	}
2827	r_dcache_fsm = DCACHE_IDLE;
2828	}
2829	break;
2830	*/
2831	case iss_t::DATA_WRITE:
2832	m_cpt_write++;
2833	if ( dcache_cached ) m_cpt_write_cached++;
2834	m_cost_write_frz++;
2835	if ( dcache_hit_c && dcache_cached ) // cache update required
2836	{
2837	r_dcache_fsm = DCACHE_WRITE_UPDT;
2838	}
2839	else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) ) // dirty bit update required
2840	{
2841	m_cpt_data_tlb_update_dirty++;
2842	m_cost_data_tlb_update_dirty_frz++;
2843	if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) ) // 2M page size, one level page table
2844	{
2845	r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) \| PTE_D_MASK;
2846	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
2847	r_dcache_tlb_ll_dirty_req = true;
2848	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2849	}
2850	else // 4k page size, two levels page table
2851	{
2852	if (dcache_hit_p)
2853	{
2854	r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) \| PTE_D_MASK;
2855	r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save \| (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
2856	r_dcache_tlb_ll_dirty_req = true;
2857	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2858	}
2859	else // get PTBA to calculate the physical address of PTE
2860	{
2861	r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) \| PTE_D_MASK;
2862	data_t ptba;
2863	if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
2864	{
2865	r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS \| (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2866	r_dcache_tlb_ll_dirty_req = true;
2867	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2868	}
2869	else
2870	{
2871	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
2872	r_dcache_tlb_ptba_read = true;
2873	r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
2874	}
2875	}
2876	}
2877	}
2878	else // no cache update, not dirty bit update
2879	{
2880	r_dcache_fsm = DCACHE_WRITE_REQ;
2881	drsp.valid = true;
2882	drsp.rdata = 0;
2883	}
2884	break;
2885	default:
2886	break;
2887	} // end switch dreq.type
2888	} // end if next states
2889
2890	// save values for the next states
2891	r_dcache_paddr_save = tlb_dpaddr;
2892	r_dcache_type_save = dreq.type;
2893	r_dcache_wdata_save = dreq.wdata;
2894	r_dcache_be_save = dreq.be;
2895	r_dcache_rdata_save = dcache_rdata;
2896	r_dcache_cached_save = dcache_cached;
2897	r_dcache_dirty_save = dcache_pte_info.d;
2898	r_dcache_tlb_set_save = dcache_tlb_set;
2899	r_dcache_tlb_way_save = dcache_tlb_way;
2900
2901	} // end if dreq.valid
2902	else
2903	{
2904	r_dcache_fsm = DCACHE_IDLE;
2905	}
2906
2907	// processor request are not accepted in the WRITE_REQ state
2908	// when the write buffer is not writeable
2909
2910	if ((r_dcache_fsm == DCACHE_WRITE_REQ) &&
2911	(r_dcache_write_req \|\| !r_wbuf.wok(r_dcache_paddr_save)))
2912	{
2913	drsp.valid = false;
2914	}
2915	break;
2916	}
2917	/////////////////
2918	case DCACHE_BIS:
2919	{
2920	// external cache invalidate request
2921	if ( r_tgt_dcache_req )
2922	{
2923	r_dcache_fsm = DCACHE_CC_CHECK;
2924	r_dcache_fsm_save = r_dcache_fsm;
2925	if ( dreq.valid ) m_cost_data_miss_frz++;
2926	break;
2927	}
2928
2929	// Using tlb entry is invalidated
2930	if ( r_dcache_inval_tlb_rsp )
2931	{
2932	r_dcache_inval_tlb_rsp = false;
2933	r_dcache_fsm = DCACHE_IDLE;
2934	if ( dreq.valid ) m_cost_data_miss_frz++;
2935	break;
2936	}
2937
2938	data_t dcache_rdata = 0;
2939	bool dcache_hit_c = false;
2940	bool dcache_hit_t = false;
2941	paddr_t tlb_dpaddr = 0;
2942
2943	dcache_hit_t = dcache_tlb.translate(dreq.addr, &tlb_dpaddr);
2944
2945	if ( (tlb_dpaddr == r_dcache_paddr_save.read()) && dreq.valid && dcache_hit_t )
2946	{
2947	// acces always cached in this state
2948	dcache_hit_c = r_dcache.read(r_dcache_paddr_save, &dcache_rdata);
2949
2950	if ( dreq.type == iss_t::DATA_READ ) // cached read
2951	{
2952	m_cpt_read++;
2953	if ( !dcache_hit_c )
2954	{
2955	r_dcache_miss_req = true;
2956	r_dcache_fsm = DCACHE_MISS_WAIT;
2957	m_cpt_data_miss++;
2958	m_cost_data_miss_frz++;
2959	}
2960	else
2961	{
2962	r_dcache_fsm = DCACHE_IDLE;
2963	}
2964	drsp.valid = dcache_hit_c;
2965	drsp.error = false;
2966	drsp.rdata = dcache_rdata;
2967	}
2968	else // cached write
2969	{
2970	m_cpt_write++;
2971	m_cpt_write_cached++;
2972	if ( dcache_hit_c ) // cache update required
2973	{
2974	r_dcache_rdata_save = dcache_rdata;
2975	r_dcache_fsm = DCACHE_WRITE_UPDT;
2976	}
2977	else if (!r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK)) // dirty bit update required
2978	{
2979	m_cpt_data_tlb_update_dirty++;
2980	m_cost_data_tlb_update_dirty_frz++;
2981	if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
2982	{
2983	r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) \| PTE_D_MASK;
2984	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
2985	r_dcache_tlb_ll_dirty_req = true;
2986	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2987	}
2988	else
2989	{
2990	if (r_dcache_hit_p_save)
2991	{
2992	r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) \| PTE_D_MASK;
2993	r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save\|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
2994	r_dcache_tlb_ll_dirty_req = true;
2995	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
2996	}
2997	else
2998	{
2999	r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) \| PTE_D_MASK;
3000	data_t ptba;
3001	if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
3002	{
3003	r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS \| (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3004	r_dcache_tlb_ll_dirty_req = true;
3005	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
3006	}
3007	else
3008	{
3009	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
3010	r_dcache_tlb_ptba_read = true;
3011	r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
3012	}
3013	}
3014	}
3015	}
3016	else // no cache update, not dirty bit update
3017	{
3018	r_dcache_fsm = DCACHE_WRITE_REQ;
3019	drsp.valid = true;
3020	drsp.rdata = 0;
3021	}
3022	}
3023	}
3024	else
3025	{
3026	drsp.valid = false;
3027	drsp.error = false;
3028	drsp.rdata = 0;
3029	r_dcache_fsm = DCACHE_IDLE;
3030	}
3031	break;
3032	}
3033	//////////////////////////
3034	case DCACHE_LL_DIRTY_WAIT:
3035	{
3036	m_cost_data_tlb_update_dirty_frz++;
3037
3038	// external cache invalidate request
3039	if ( r_tgt_dcache_req )
3040	{
3041	r_dcache_fsm = DCACHE_CC_CHECK;
3042	r_dcache_fsm_save = r_dcache_fsm;
3043	break;
3044	}
3045
3046	if (!r_dcache_tlb_ll_dirty_req)
3047	{
3048	if ( r_vci_rsp_data_error ) // VCI response ko
3049	{
3050	if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
3051	{
3052	r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
3053	}
3054	else
3055	{
3056	r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
3057	}
3058	r_dcache_bad_vaddr = dreq.addr;
3059	r_dcache_fsm = DCACHE_ERROR;
3060
3061	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3062	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3063	if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
3064	}
3065	else
3066	{
3067	if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) ) // unmapped
3068	{
3069	if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
3070	{
3071	r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
3072	}
3073	else
3074	{
3075	r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
3076	}
3077	r_dcache_bad_vaddr = dreq.addr;
3078	r_dcache_fsm = DCACHE_ERROR;
3079
3080	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3081	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3082	if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
3083	}
3084	else if ( r_dcache_inval_tlb_rsp )
3085	{
3086	r_dcache_inval_tlb_rsp = false;
3087	r_dcache_fsm = DCACHE_IDLE;
3088	if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
3089	}
3090	else if ( r_dcache_inval_rsp )
3091	{
3092	r_dcache_inval_rsp = false;
3093	r_dcache_fsm = DCACHE_IDLE;
3094	if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
3095	}
3096	else
3097	{
3098	r_dcache_tlb_sc_dirty_req = true;
3099	r_dcache_pte_update = r_dcache_miss_buf[0] \| r_dcache_pte_update.read();
3100	r_dcache_fsm = DCACHE_SC_DIRTY_WAIT;
3101	}
3102	}
3103	}
3104	break;
3105	}
3106	//////////////////////////
3107	case DCACHE_SC_DIRTY_WAIT:
3108	{
3109	m_cost_data_tlb_update_dirty_frz++;
3110	// external cache invalidate request
3111	if ( r_tgt_dcache_req )
3112	{
3113	r_dcache_fsm = DCACHE_CC_CHECK;
3114	r_dcache_fsm_save = r_dcache_fsm;
3115	break;
3116	}
3117
3118	if ( !r_dcache_tlb_sc_dirty_req )
3119	{
3120	if ( r_vci_rsp_data_error ) // VCI response ko
3121	{
3122	if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
3123	{
3124	r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
3125	}
3126	else
3127	{
3128	r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
3129	}
3130	r_dcache_bad_vaddr = dreq.addr;
3131	r_dcache_fsm = DCACHE_ERROR;
3132
3133	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3134	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3135	if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
3136	}
3137	else
3138	{
3139	// Using tlb entry is invalidated
3140	if ( r_dcache_inval_tlb_rsp )
3141	{
3142	r_dcache_inval_tlb_rsp = false;
3143	r_dcache_fsm = DCACHE_IDLE;
3144	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
3145	if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
3146	}
3147	else if ( r_dcache_inval_rsp )
3148	{
3149	r_dcache_inval_rsp = false;
3150	r_dcache_fsm = DCACHE_IDLE;
3151	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
3152	if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
3153	}
3154	else if ( r_dcache_tlb_sc_fail )
3155	{
3156	r_dcache_tlb_ll_dirty_req = true;
3157	r_dcache_tlb_sc_fail = false;
3158	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
3159	m_cpt_data_tlb_update_dirty++;
3160	}
3161	else
3162	{
3163	bool write_hit = r_dcache.write(r_dcache_tlb_paddr, r_dcache_pte_update);
3164	assert(write_hit && "Write on miss ignores data for data MMU update dirty bit");
3165	r_dcache_fsm = DCACHE_WRITE_DIRTY;
3166	m_cpt_dcache_data_write++;
3167	}
3168	}
3169	}
3170	break;
3171	}
3172	////////////////////////////
3173	case DCACHE_DTLB1_READ_CACHE:
3174	{
3175	m_cost_data_tlb_miss_frz++;
3176
3177	// external cache invalidate request
3178	if ( r_tgt_dcache_req )
3179	{
3180	r_dcache_fsm = DCACHE_CC_CHECK;
3181	r_dcache_fsm_save = r_dcache_fsm;
3182	break;
3183	}
3184
3185	// Using tlb entry is invalidated
3186	if ( r_dcache_inval_tlb_rsp )
3187	{
3188	r_dcache_inval_tlb_rsp = false;
3189	r_dcache_fsm = DCACHE_IDLE;
3190	if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
3191	break;
3192	}
3193
3194	data_t tlb_data = 0;
3195	bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
3196
3197	// DTLB request hit in cache
3198	if ( tlb_hit_cache )
3199	{
3200	if ( !(tlb_data >> PTE_V_SHIFT) ) // unmapped
3201	{
3202	r_dcache_ptba_ok = false;
3203	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3204	{
3205	r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
3206	}
3207	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3208	{
3209	r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
3210	}
3211	r_dcache_bad_vaddr = dreq.addr;
3212	r_dcache_fsm = DCACHE_ERROR;
3213	}
3214	else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
3215	{
3216	r_dcache_ptba_ok = true;
3217	r_dcache_ptba_save = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;
3218	r_dcache_id1_save = dreq.addr >> PAGE_M_NBITS;
3219	r_dcache_tlb_paddr = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
3220	(paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3221	if ( r_dcache_tlb_ptba_read )
3222	{
3223	paddr_t tlb_dpaddr;
3224	data_t data;
3225	r_dcache_tlb_ptba_read = false;
3226	if (dcache_tlb.translate(dreq.addr, &tlb_dpaddr) && r_dcache.read( (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS \| (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3) ,&data))
3227	{
3228	r_dcache_tlb_ll_dirty_req = true;
3229	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
3230	//m_cpt_dcache_data_write++;
3231	m_cpt_data_tlb_update_dirty++;
3232	m_cost_data_tlb_update_dirty_frz++;
3233	}
3234	else
3235	{
3236	r_dcache_fsm = DCACHE_IDLE;
3237	}
3238	}
3239	else
3240	{
3241	r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
3242	}
3243	}
3244	else // PTE
3245	{
3246	m_cpt_data_tlb_hit_dcache++;
3247	r_dcache_ptba_ok = false;
3248	if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
3249	{
3250	if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
3251	{
3252	r_dcache_pte_update = tlb_data;
3253	r_dcache_fsm = DCACHE_TLB1_UPDT;
3254	}
3255	else
3256	{
3257	r_dcache_pte_update = tlb_data \| PTE_L_MASK;
3258	r_dcache_tlb_ll_acc_req = true;
3259	r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
3260	m_cpt_data_tlb_update_acc++;
3261	m_cost_data_tlb_update_acc_frz++;
3262	}
3263	}
3264	else // remotely
3265	{
3266	if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
3267	{
3268	r_dcache_pte_update = tlb_data;
3269	r_dcache_fsm = DCACHE_TLB1_UPDT;
3270	}
3271	else
3272	{
3273	r_dcache_pte_update = tlb_data \| PTE_R_MASK;
3274	r_dcache_tlb_ll_acc_req = true;
3275	r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
3276	m_cpt_data_tlb_update_acc++;
3277	m_cost_data_tlb_update_acc_frz++;
3278	}
3279	}
3280	}
3281	}
3282	else
3283	{
3284	// DTLB request miss in cache and walk page table level 1
3285	r_dcache_tlb_read_req = true;
3286	r_dcache_fsm = DCACHE_TLB1_READ;
3287	}
3288	break;
3289	}
3290	///////////////////////
3291	case DCACHE_TLB1_LL_WAIT:
3292	{
3293	if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
3294	m_cost_data_tlb_update_acc_frz++;
3295	// external cache invalidate request
3296	if ( r_tgt_dcache_req )
3297	{
3298	r_dcache_fsm = DCACHE_CC_CHECK;
3299	r_dcache_fsm_save = r_dcache_fsm;
3300	break;
3301	}
3302
3303	if (!r_dcache_tlb_ll_acc_req)
3304	{
3305	if ( r_vci_rsp_data_error ) // VCI response ko
3306	{
3307	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3308	{
3309	r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
3310	}
3311	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3312	{
3313	r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
3314	}
3315	r_dcache_bad_vaddr = dreq.addr;
3316	r_dcache_fsm = DCACHE_ERROR;
3317
3318	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3319	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3320	}
3321	else
3322	{
3323	if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) ) // unmapped
3324	{
3325	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3326	{
3327	r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
3328	}
3329	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3330	{
3331	r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
3332	}
3333	r_dcache_bad_vaddr = dreq.addr;
3334	r_dcache_fsm = DCACHE_ERROR;
3335
3336	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3337	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3338	}
3339	else if ( r_dcache_inval_tlb_rsp )
3340	{
3341	r_dcache_inval_tlb_rsp = false;
3342	r_dcache_fsm = DCACHE_IDLE;
3343	}
3344	else if ( r_dcache_inval_rsp )
3345	{
3346	r_dcache_inval_rsp = false;
3347	r_dcache_fsm = DCACHE_IDLE;
3348	}
3349	else
3350	{
3351	r_dcache_tlb_sc_acc_req = true;
3352	r_dcache_pte_update = r_dcache_miss_buf[0] \| r_dcache_pte_update.read();
3353	r_dcache_fsm = DCACHE_TLB1_SC_WAIT;
3354	}
3355	}
3356	}
3357	break;
3358	}
3359	///////////////////////
3360	case DCACHE_TLB1_SC_WAIT:
3361	{
3362	if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
3363	m_cost_data_tlb_update_acc_frz++;
3364	// external cache invalidate request
3365	if ( r_tgt_dcache_req )
3366	{
3367	r_dcache_fsm = DCACHE_CC_CHECK;
3368	r_dcache_fsm_save = r_dcache_fsm;
3369	break;
3370	}
3371
3372	if ( !r_dcache_tlb_sc_acc_req )
3373	{
3374	if ( r_vci_rsp_data_error ) // VCI response ko
3375	{
3376	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3377	{
3378	r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
3379	}
3380	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3381	{
3382	r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
3383	}
3384	r_dcache_bad_vaddr = dreq.addr;
3385	r_dcache_fsm = DCACHE_ERROR;
3386
3387	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3388	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3389	}
3390	else
3391	{
3392	// Using tlb entry is invalidated
3393	if ( r_dcache_inval_tlb_rsp )
3394	{
3395	r_dcache_inval_tlb_rsp = false;
3396	r_dcache_fsm = DCACHE_IDLE;
3397	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
3398	}
3399	else if ( r_dcache_inval_rsp )
3400	{
3401	r_dcache_inval_rsp = false;
3402	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
3403	r_dcache_fsm = DCACHE_IDLE;
3404	}
3405	else if ( r_dcache_tlb_sc_fail )
3406	{
3407	r_dcache_tlb_sc_fail = false;
3408	r_dcache_tlb_ll_acc_req = true;
3409	r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
3410	m_cpt_data_tlb_update_acc++;
3411	}
3412	else
3413	{
3414	bool write_hit = r_dcache.write(r_dcache_tlb_paddr,r_dcache_pte_update);
3415	assert(write_hit && "Write on miss ignores data for data MMU update data access bit");
3416	r_dcache_fsm = DCACHE_TLB1_UPDT;
3417	m_cpt_dcache_data_write++;
3418	}
3419	}
3420	}
3421	break;
3422	}
3423	//////////////////////
3424	case DCACHE_TLB1_READ:
3425	{
3426	if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
3427
3428	// external cache invalidate request
3429	if ( r_tgt_dcache_req )
3430	{
3431	r_dcache_fsm = DCACHE_CC_CHECK;
3432	r_dcache_fsm_save = r_dcache_fsm;
3433	break;
3434	}
3435
3436	if ( !r_dcache_tlb_read_req )
3437	{
3438	if ( r_vci_rsp_data_error ) // VCI response ko
3439	{
3440	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3441	{
3442	r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
3443	}
3444	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3445	{
3446	r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
3447	}
3448	r_dcache_bad_vaddr = dreq.addr;
3449	r_dcache_fsm = DCACHE_ERROR;
3450
3451	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3452	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3453	if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
3454	break;
3455	}
3456
3457	if ( r_dcache_inval_tlb_rsp ) // TLB miss response and invalidation
3458	{
3459	r_dcache_fsm = DCACHE_IDLE;
3460	r_dcache_inval_tlb_rsp = false;
3461	if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
3462	break;
3463	}
3464
3465	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
3466	{
3467	if ( r_dcache_cleanup_req ) break;
3468	r_dcache_cleanup_req = true;
3469	r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3470	m_cpt_cc_cleanup_data++;
3471	r_dcache_fsm = DCACHE_IDLE;
3472	r_dcache_inval_rsp = false;
3473	if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
3474	break;
3475	}
3476
3477	// TLB miss response and no invalidation
3478	r_dcache_fsm = DCACHE_TLB1_READ_UPDT;
3479	}
3480	break;
3481	}
3482	//////////////////////////
3483	case DCACHE_TLB1_READ_UPDT:
3484	{
3485	m_cost_data_tlb_miss_frz++;
3486
3487	// external cache invalidate request
3488	if ( r_tgt_dcache_req )
3489	{
3490	r_dcache_fsm = DCACHE_CC_CHECK;
3491	r_dcache_fsm_save = r_dcache_fsm;
3492	break;
3493	}
3494
3495	// Using tlb entry is invalidated
3496	if ( r_dcache_inval_tlb_rsp )
3497	{
3498	r_dcache_inval_tlb_rsp = false;
3499	r_dcache_fsm = DCACHE_IDLE;
3500	if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
3501	break;
3502	}
3503
3504	if ( !r_dcache_cleanup_req ) // Miss update and no invalidation
3505	{
3506	// update dcache
3507	data_t rsp_dtlb_miss = 0;
3508	paddr_t victim_index = 0;
3509	size_t way = 0;
3510	size_t set = 0;
3511
3512	// Using tlb entry is in the invalidated cache line
3513	if ( r_dcache_inval_rsp )
3514	{
3515	r_dcache_cleanup_req = true;
3516	r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3517	m_cpt_cc_cleanup_data++;
3518	r_dcache_fsm = DCACHE_IDLE;
3519	r_dcache_inval_rsp = false;
3520	if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
3521	break;
3522	}
3523
3524	bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
3525
3526	if ( cleanup_req )
3527	{
3528	// ins tlb invalidate verification
3529	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
3530	r_dcache_itlb_inval_line = victim_index;
3531	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
3532
3533	// data tlb invalidate verification
3534	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
3535	r_dcache_dtlb_inval_line = victim_index;
3536	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
3537
3538	r_dcache_cleanup_req = true;
3539	r_dcache_cleanup_line = victim_index;
3540	m_cpt_cc_cleanup_data++;
3541	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
3542	r_dcache_fsm_save = r_dcache_fsm;
3543	break;
3544	}
3545
3546	r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
3547	r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);
3548	m_cpt_data_tlb_occup_cache++;
3549
3550	if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) ) // unmapped
3551	{
3552	r_dcache_ptba_ok = false;
3553	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3554	{
3555	r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
3556	}
3557	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3558	{
3559	r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
3560	}
3561	r_dcache_bad_vaddr = dreq.addr;
3562	r_dcache_fsm = DCACHE_ERROR;
3563	if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
3564	}
3565	else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
3566	{
3567	r_dcache_ptba_ok = true;
3568	r_dcache_ptba_save = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;
3569	r_dcache_id1_save = dreq.addr >> PAGE_M_NBITS;
3570	r_dcache_tlb_paddr = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
3571	(paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3572	if ( r_dcache_tlb_ptba_read )
3573	{
3574	paddr_t tlb_dpaddr;
3575	data_t data;
3576	r_dcache_tlb_ptba_read = false;
3577	if (dcache_tlb.translate(dreq.addr, &tlb_dpaddr) && r_dcache.read((paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS \| (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3),&data))
3578	{
3579	r_dcache_tlb_ll_dirty_req = true;
3580	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
3581	//m_cpt_dcache_data_write++;
3582	m_cpt_data_tlb_update_dirty++;
3583	m_cost_data_tlb_update_dirty_frz++;
3584	}
3585	else
3586	{
3587	r_dcache_fsm = DCACHE_IDLE;
3588	}
3589	}
3590	else
3591	{
3592	r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
3593	}
3594	}
3595	else // PTE
3596	{
3597	r_dcache_ptba_ok = false;
3598	if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
3599	{
3600	if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
3601	{
3602	r_dcache_pte_update = rsp_dtlb_miss;
3603	r_dcache_fsm = DCACHE_TLB1_UPDT;
3604	}
3605	else
3606	{
3607	r_dcache_pte_update = rsp_dtlb_miss \| PTE_L_MASK;
3608	r_dcache_tlb_ll_acc_req = true;
3609	r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
3610	m_cpt_data_tlb_update_acc++;
3611	m_cost_data_tlb_update_acc_frz++;
3612	}
3613	}
3614	else // remotely
3615	{
3616	if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
3617	{
3618	r_dcache_pte_update = rsp_dtlb_miss;
3619	r_dcache_fsm = DCACHE_TLB1_UPDT;
3620	}
3621	else
3622	{
3623	r_dcache_pte_update = rsp_dtlb_miss \| PTE_R_MASK;
3624	r_dcache_tlb_ll_acc_req = true;
3625	r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
3626	m_cpt_data_tlb_update_acc++;
3627	m_cost_data_tlb_update_acc_frz++;
3628	}
3629	}
3630	}
3631	}
3632	break;
3633	}
3634	//////////////////////
3635	case DCACHE_TLB1_UPDT:
3636	{
3637	m_cost_data_tlb_miss_frz++;
3638
3639	// external cache invalidate request
3640	if ( r_tgt_dcache_req )
3641	{
3642	r_dcache_fsm = DCACHE_CC_CHECK;
3643	r_dcache_fsm_save = r_dcache_fsm;
3644	break;
3645	}
3646
3647	if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
3648	{
3649	paddr_t victim_index = 0;
3650	if (dcache_tlb.update(r_dcache_pte_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
3651	{
3652	r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false);
3653	}
3654	bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
3655	assert(set_hit && "TLB1_UPDT set hit error");
3656	r_dcache_fsm = DCACHE_IDLE;
3657	}
3658	else
3659	{
3660	if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
3661	if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
3662	r_dcache_fsm = DCACHE_IDLE;
3663	}
3664	break;
3665	}
3666	/////////////////////////////
3667	case DCACHE_DTLB2_READ_CACHE:
3668	{
3669	m_cost_data_tlb_miss_frz++;
3670
3671	// external cache invalidate request
3672	if ( r_tgt_dcache_req )
3673	{
3674	r_dcache_fsm = DCACHE_CC_CHECK;
3675	r_dcache_fsm_save = r_dcache_fsm;
3676	break;
3677	}
3678
3679	// Using tlb entry is invalidated
3680	if ( r_dcache_inval_tlb_rsp )
3681	{
3682	r_dcache_inval_tlb_rsp = false;
3683	r_dcache_fsm = DCACHE_IDLE;
3684	break;
3685	}
3686
3687	data_t tlb_data = 0;
3688	data_t tlb_data_ppn = 0;
3689	bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
3690
3691	if ( tlb_hit_cache )
3692	{
3693	bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
3694	assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
3695	}
3696
3697	// DTLB request hit in cache
3698	if ( tlb_hit_cache )
3699	{
3700	if ( !(tlb_data >> PTE_V_SHIFT) ) // unmapped
3701	{
3702	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3703	{
3704	r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
3705	}
3706	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3707	{
3708	r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
3709	}
3710	r_dcache_bad_vaddr = dreq.addr;
3711	r_dcache_fsm = DCACHE_ERROR;
3712	}
3713	else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT ) //PTD
3714	{
3715	r_dcache_pte_update = tlb_data;
3716	r_dcache_ppn_update = tlb_data_ppn;
3717	r_dcache_fsm = DCACHE_TLB2_UPDT;
3718	}
3719	else
3720	{
3721	m_cpt_data_tlb_hit_dcache++;
3722	if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
3723	{
3724	if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
3725	{
3726	r_dcache_pte_update = tlb_data;
3727	r_dcache_ppn_update = tlb_data_ppn;
3728	r_dcache_fsm = DCACHE_TLB2_UPDT;
3729	}
3730	else
3731	{
3732	r_dcache_pte_update = tlb_data \| PTE_L_MASK;
3733	r_dcache_ppn_update = tlb_data_ppn;
3734	r_dcache_tlb_ll_acc_req = true;
3735	r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
3736	m_cpt_data_tlb_update_acc++;
3737	m_cost_data_tlb_update_acc_frz++;
3738	}
3739	}
3740	else // remotely
3741	{
3742	if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
3743	{
3744	r_dcache_pte_update = tlb_data;
3745	r_dcache_ppn_update = tlb_data_ppn;
3746	r_dcache_fsm = DCACHE_TLB2_UPDT;
3747	}
3748	else
3749	{
3750	r_dcache_pte_update = tlb_data \| PTE_R_MASK;
3751	r_dcache_ppn_update = tlb_data_ppn;
3752	r_dcache_tlb_ll_acc_req = true;
3753	r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
3754	m_cpt_data_tlb_update_acc++;
3755	m_cost_data_tlb_update_acc_frz++;
3756	}
3757	}
3758	}
3759	}
3760	else
3761	{
3762	// DTLB request miss in cache and walk page table level 2
3763	r_dcache_tlb_read_req = true;
3764	r_dcache_fsm = DCACHE_TLB2_READ;
3765	}
3766	break;
3767	}
3768	///////////////////////
3769	case DCACHE_TLB2_LL_WAIT:
3770	{
3771	if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
3772	m_cost_data_tlb_update_acc_frz++;
3773
3774	// external cache invalidate request
3775	if ( r_tgt_dcache_req )
3776	{
3777	r_dcache_fsm = DCACHE_CC_CHECK;
3778	r_dcache_fsm_save = r_dcache_fsm;
3779	break;
3780	}
3781
3782	if (!r_dcache_tlb_ll_acc_req)
3783	{
3784	if ( r_vci_rsp_data_error ) // VCI response ko
3785	{
3786	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3787	{
3788	r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
3789	}
3790	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3791	{
3792	r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
3793	}
3794	r_dcache_bad_vaddr = dreq.addr;
3795	r_dcache_fsm = DCACHE_ERROR;
3796
3797	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3798	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3799	}
3800	else
3801	{
3802	if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) ) // unmapped
3803	{
3804	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3805	{
3806	r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
3807	}
3808	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3809	{
3810	r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
3811	}
3812	r_dcache_bad_vaddr = dreq.addr;
3813	r_dcache_fsm = DCACHE_ERROR;
3814
3815	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3816	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3817	}
3818	else if ( r_dcache_inval_tlb_rsp )
3819	{
3820	r_dcache_inval_tlb_rsp = false;
3821	r_dcache_fsm = DCACHE_IDLE;
3822	}
3823	else if ( r_dcache_inval_rsp )
3824	{
3825	r_dcache_inval_rsp = false;
3826	r_dcache_fsm = DCACHE_IDLE;
3827	}
3828	else
3829	{
3830	r_dcache_tlb_sc_acc_req = true;
3831	r_dcache_pte_update = r_dcache_miss_buf[0] \| r_dcache_pte_update.read();
3832	r_dcache_fsm = DCACHE_TLB2_SC_WAIT;
3833	}
3834	}
3835	}
3836	break;
3837	}
3838	///////////////////////
3839	case DCACHE_TLB2_SC_WAIT:
3840	{
3841	if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
3842	m_cost_data_tlb_update_acc_frz++;
3843	// external cache invalidate request
3844	if ( r_tgt_dcache_req )
3845	{
3846	r_dcache_fsm = DCACHE_CC_CHECK;
3847	r_dcache_fsm_save = r_dcache_fsm;
3848	break;
3849	}
3850
3851	if ( !r_dcache_tlb_sc_acc_req )
3852	{
3853	if ( r_vci_rsp_data_error ) // VCI response ko
3854	{
3855	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3856	{
3857	r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
3858	}
3859	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3860	{
3861	r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
3862	}
3863	r_dcache_bad_vaddr = dreq.addr;
3864	r_dcache_fsm = DCACHE_ERROR;
3865
3866	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3867	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3868	}
3869	else
3870	{
3871	// Using tlb entry is invalidated
3872	if ( r_dcache_inval_tlb_rsp )
3873	{
3874	r_dcache_inval_tlb_rsp = false;
3875	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
3876	r_dcache_fsm = DCACHE_IDLE;
3877	}
3878	else if ( r_dcache_inval_rsp )
3879	{
3880	r_dcache_inval_rsp = false;
3881	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
3882	r_dcache_fsm = DCACHE_IDLE;
3883	}
3884	else if ( r_dcache_tlb_sc_fail )
3885	{
3886	r_dcache_tlb_ll_acc_req = true;
3887	r_dcache_tlb_sc_fail = false;
3888	r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
3889	m_cpt_data_tlb_update_acc++;
3890	}
3891	else
3892	{
3893	bool write_hit = r_dcache.write(r_dcache_tlb_paddr,r_dcache_pte_update);
3894	assert(write_hit && "Write on miss ignores data for data MMU update data access bit");
3895	r_dcache_fsm = DCACHE_TLB2_UPDT;
3896	m_cpt_dcache_data_write++;
3897	}
3898	}
3899	}
3900	break;
3901	}
3902	/////////////////////
3903	case DCACHE_TLB2_READ:
3904	{
3905	m_cost_data_tlb_miss_frz++;
3906
3907	// external cache invalidate request
3908	if ( r_tgt_dcache_req )
3909	{
3910	r_dcache_fsm = DCACHE_CC_CHECK;
3911	r_dcache_fsm_save = r_dcache_fsm;
3912	break;
3913	}
3914
3915	if ( !r_dcache_tlb_read_req )
3916	{
3917	if ( r_vci_rsp_data_error ) // VCI response ko
3918	{
3919	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
3920	{
3921	r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
3922	}
3923	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
3924	{
3925	r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
3926	}
3927	r_dcache_bad_vaddr = dreq.addr;
3928	r_dcache_fsm = DCACHE_ERROR;
3929
3930	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
3931	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
3932	break;
3933	}
3934
3935	if ( r_dcache_inval_tlb_rsp ) // TLB miss response and invalidation
3936	{
3937	r_dcache_fsm = DCACHE_IDLE;
3938	r_dcache_inval_tlb_rsp = false;
3939	break;
3940	}
3941
3942	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
3943	{
3944	if ( r_dcache_cleanup_req ) break;
3945	r_dcache_cleanup_req = true;
3946	r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3947	m_cpt_cc_cleanup_data++;
3948	r_dcache_fsm = DCACHE_IDLE;
3949	r_dcache_inval_rsp = false;
3950	break;
3951	}
3952
3953	// TLB miss response and no invalidation
3954	r_dcache_fsm = DCACHE_TLB2_READ_UPDT;
3955	}
3956	break;
3957	}
3958	//////////////////////////
3959	case DCACHE_TLB2_READ_UPDT:
3960	{
3961	m_cost_data_tlb_miss_frz++;
3962
3963	// external cache invalidate request
3964	if ( r_tgt_dcache_req )
3965	{
3966	r_dcache_fsm = DCACHE_CC_CHECK;
3967	r_dcache_fsm_save = r_dcache_fsm;
3968	break;
3969	}
3970
3971	// Using tlb entry is invalidated
3972	if ( r_dcache_inval_tlb_rsp )
3973	{
3974	r_dcache_inval_tlb_rsp = false;
3975	r_dcache_fsm = DCACHE_IDLE;
3976	break;
3977	}
3978
3979	if ( !r_dcache_cleanup_req )
3980	{
3981	// update cache
3982	data_t rsp_dtlb_miss;
3983	data_t tlb_data_ppn;
3984	//bool write_hit = false;
3985	paddr_t victim_index = 0;
3986	size_t way = 0;
3987	size_t set = 0;
3988
3989	// Using tlb entry is in the invalidated cache line
3990	if ( r_dcache_inval_rsp )
3991	{
3992	r_dcache_cleanup_req = true;
3993	r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3994	m_cpt_cc_cleanup_data++;
3995	r_dcache_fsm = DCACHE_IDLE;
3996	r_dcache_inval_rsp = false;
3997	break;
3998	}
3999
4000	bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
4001
4002	if ( cleanup_req )
4003	{
4004	// ins tlb invalidate verification
4005	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
4006	r_dcache_itlb_inval_line = victim_index;
4007	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4008
4009	// data tlb invalidate verification
4010	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
4011	r_dcache_dtlb_inval_line = victim_index;
4012	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4013
4014	r_dcache_cleanup_req = true;
4015	r_dcache_cleanup_line = victim_index;
4016	m_cpt_cc_cleanup_data++;
4017	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
4018	r_dcache_fsm_save = r_dcache_fsm;
4019	break;
4020	}
4021
4022	r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
4023	r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);
4024	m_cpt_data_tlb_occup_cache++;
4025
4026	bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
4027	assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
4028
4029	if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) ) // unmapped
4030	{
4031	if ((r_dcache_type_save == iss_t::DATA_READ)\|\|(r_dcache_type_save == iss_t::DATA_LL))
4032	{
4033	r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
4034	}
4035	else /if ((dreq.type == iss_t::DATA_WRITE)\|\|(dreq.type == iss_t::DATA_SC))/
4036	{
4037	r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
4038	}
4039	r_dcache_bad_vaddr = dreq.addr;
4040	r_dcache_fsm = DCACHE_ERROR;
4041	}
4042	else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
4043	{
4044	r_dcache_pte_update = rsp_dtlb_miss;
4045	r_dcache_ppn_update = tlb_data_ppn;
4046	r_dcache_fsm = DCACHE_TLB2_UPDT;
4047	}
4048	else
4049	{
4050	if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
4051	{
4052	if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
4053	{
4054	r_dcache_pte_update = rsp_dtlb_miss;
4055	r_dcache_ppn_update = tlb_data_ppn;
4056	r_dcache_fsm = DCACHE_TLB2_UPDT;
4057	}
4058	else
4059	{
4060	r_dcache_pte_update = rsp_dtlb_miss \| PTE_L_MASK;
4061	r_dcache_ppn_update = tlb_data_ppn;
4062	r_dcache_tlb_ll_acc_req = true;
4063	r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
4064	m_cpt_data_tlb_update_acc++;
4065	m_cost_data_tlb_update_acc_frz++;
4066	}
4067	}
4068	else // remotely
4069	{
4070	if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
4071	{
4072	r_dcache_pte_update = rsp_dtlb_miss;
4073	r_dcache_ppn_update = tlb_data_ppn;
4074	r_dcache_fsm = DCACHE_TLB2_UPDT;
4075	}
4076	else
4077	{
4078	r_dcache_pte_update = rsp_dtlb_miss \| PTE_R_MASK;
4079	r_dcache_ppn_update = tlb_data_ppn;
4080	r_dcache_tlb_ll_acc_req = true;
4081	r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
4082	m_cpt_data_tlb_update_acc++;
4083	m_cost_data_tlb_update_acc_frz++;
4084	}
4085	}
4086	}
4087	}
4088	break;
4089	}
4090	//////////////////////
4091	case DCACHE_TLB2_UPDT:
4092	{
4093	m_cost_data_tlb_miss_frz++;
4094
4095	// external cache invalidate request
4096	if ( r_tgt_dcache_req )
4097	{
4098	r_dcache_fsm = DCACHE_CC_CHECK;
4099	r_dcache_fsm_save = r_dcache_fsm;
4100	break;
4101	}
4102
4103	if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
4104	{
4105	paddr_t victim_index = 0;
4106	if (dcache_tlb.update(r_dcache_pte_update,r_dcache_ppn_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
4107	{
4108	r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false);
4109	}
4110	bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
4111	assert(set_hit && "TLB2_UPDT set hit error");
4112	r_dcache_fsm = DCACHE_IDLE;
4113	}
4114	else
4115	{
4116	if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
4117	if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
4118	r_dcache_fsm = DCACHE_IDLE;
4119	}
4120	break;
4121	}
4122	///////////////////////
4123	case DCACHE_CTXT_SWITCH:
4124	{
4125	// TLB flush leads to cleanup corresponding data cache line
4126	paddr_t victim_index = 0;
4127	size_t way = 0;
4128	size_t set = 0;
4129
4130	if ( r_dcache_itlb_cleanup_req )
4131	{
4132	r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read() << (uint32_log2(m_dcache_words)+2)), r_dcache_in_itlb, false);
4133	r_dcache_itlb_cleanup_req = false;
4134	}
4135
4136	for ( way = 0; way < m_dtlb_ways; way++)
4137	{
4138	for ( set = 0; set < m_dtlb_sets; set++)
4139	{
4140	if(dcache_tlb.checkcleanup(way, set, &victim_index))
4141	{
4142	r_dcache.setinbit((paddr_t)(victim_index << (uint32_log2(m_dcache_words)+2)), r_dcache_in_dtlb, false);
4143	}
4144	}
4145	}
4146
4147	if ( !r_dcache_xtn_req )
4148	{
4149	r_dcache_fsm = DCACHE_IDLE;
4150	r_dtlb_translation_valid = false;
4151	r_dcache_ptba_ok = false;
4152	drsp.valid = true;
4153	}
4154	break;
4155	}
4156	////////////////////////
4157	case DCACHE_ICACHE_FLUSH:
4158	case DCACHE_ICACHE_INVAL:
4159	case DCACHE_ICACHE_INVAL_PA:
4160	case DCACHE_ITLB_INVAL:
4161	{
4162	// external cache invalidate request
4163	if ( r_tgt_dcache_req )
4164	{
4165	r_dcache_fsm = DCACHE_CC_CHECK;
4166	r_dcache_fsm_save = r_dcache_fsm;
4167	break;
4168	}
4169	if ( !r_dcache_xtn_req )
4170	{
4171	r_dcache_fsm = DCACHE_IDLE;
4172	drsp.valid = true;
4173	}
4174	break;
4175	}
4176	////////////////////////
4177	case DCACHE_DCACHE_FLUSH:
4178	{
4179	// external cache invalidate request
4180	if ( r_tgt_dcache_req )
4181	{
4182	r_dcache_fsm = DCACHE_CC_CHECK;
4183	r_dcache_fsm_save = r_dcache_fsm;
4184	break;
4185	}
4186	size_t way = r_dcache_way;
4187	size_t set = r_dcache_set;
4188	bool clean = false;
4189
4190	// cache flush and send cleanup to external
4191	if ( !r_dcache_cleanup_req )
4192	{
4193	paddr_t victim_index = 0;
4194	for ( ; way < m_dcache_ways; way++ )
4195	{
4196	for ( ; set < m_dcache_sets; set++ )
4197	{
4198	if ( r_dcache.flush(way, set, &victim_index) )
4199	{
4200	clean = true;
4201	r_dcache_cleanup_req = true;
4202	r_dcache_cleanup_line = victim_index;
4203	m_cpt_cc_cleanup_data++;
4204	r_dcache_way = way + ((set+1)/m_dcache_sets);
4205	r_dcache_set = (set+1) % m_dcache_sets;
4206	break;
4207	}
4208	}
4209	if (clean) break;
4210	set = 0;
4211	}
4212
4213	if ((way == m_dcache_ways) && !r_dcache_xtn_req )
4214	{
4215	// data TLB flush
4216	dcache_tlb.flush(true); // global entries are invalidated
4217	r_dtlb_translation_valid = false;
4218	r_dcache_ptba_ok = false;
4219
4220	for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++)
4221	{
4222	r_dcache_in_itlb[line] = false;
4223	r_dcache_in_dtlb[line] = false;
4224	}
4225
4226	r_dcache_fsm = DCACHE_IDLE;
4227	drsp.valid = true;
4228	break;
4229	}
4230	}
4231	break;
4232	}
4233	//////////////////////
4234	case DCACHE_DTLB_INVAL:
4235	{
4236	paddr_t victim_index = 0;
4237	// clean indicate data tlb bit
4238	if ( dcache_tlb.inval(r_dcache_wdata_save, &victim_index) )
4239	{
4240	r_dcache.setinbit((paddr_t)(victim_index << (uint32_log2(m_dcache_words)+2)), r_dcache_in_dtlb, false);
4241	}
4242	r_dtlb_translation_valid = false;
4243	r_dcache_ptba_ok = false;
4244	r_dcache_fsm = DCACHE_IDLE;
4245	drsp.valid = true;
4246	break;
4247	}
4248	////////////////////////
4249	case DCACHE_DCACHE_INVAL:
4250	{
4251	// external cache invalidate request
4252	if ( r_tgt_dcache_req )
4253	{
4254	r_dcache_fsm = DCACHE_CC_CHECK;
4255	r_dcache_fsm_save = r_dcache_fsm;
4256	break;
4257	}
4258
4259	m_cpt_dcache_dir_read += m_dcache_ways;
4260	vaddr_t invadr = dreq.wdata;
4261	paddr_t dpaddr = 0;
4262	bool dcache_hit_t = false;
4263	size_t way = 0;
4264	size_t set = 0;
4265
4266	if ( !r_dcache_cleanup_req )
4267	{
4268	if ( r_mmu_mode.read() & DATA_TLB_MASK )
4269	{
4270	dcache_hit_t = dcache_tlb.translate(invadr, &dpaddr);
4271	}
4272	else
4273	{
4274	dpaddr = invadr;
4275	dcache_hit_t = true;
4276	}
4277
4278	if ( dcache_hit_t )
4279	{
4280	r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
4281	r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
4282	m_cpt_cc_cleanup_data++;
4283
4284	if ( r_dcache_in_itlb[waym_dcache_sets+set] \|\| r_dcache_in_dtlb[waym_dcache_sets+set] )
4285	{
4286	// ins tlb invalidate verification
4287	r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
4288	r_dcache_itlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
4289	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4290
4291	// data tlb invalidate verification
4292	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
4293	r_dcache_dtlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
4294	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4295	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
4296	r_dcache_fsm_save = r_dcache_fsm;
4297	break;
4298	}
4299	}
4300	r_dcache_fsm = DCACHE_IDLE;
4301	drsp.valid = true;
4302	}
4303	break;
4304	}
4305	////////////////////////
4306	case DCACHE_DCACHE_INVAL_PA:
4307	{
4308	// external cache invalidate request
4309	if ( r_tgt_dcache_req )
4310	{
4311	r_dcache_fsm = DCACHE_CC_CHECK;
4312	r_dcache_fsm_save = r_dcache_fsm;
4313	break;
4314	}
4315	m_cpt_dcache_dir_read += m_dcache_ways;
4316	paddr_t dpaddr = (paddr_t)r_mmu_word_hi.read() << 32 \| r_mmu_word_lo.read();
4317	size_t way = 0;
4318	size_t set = 0;
4319
4320	if ( !r_dcache_cleanup_req )
4321	{
4322	r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
4323	r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
4324	m_cpt_cc_cleanup_data++;
4325
4326	if ( r_dcache_in_itlb[waym_dcache_sets+set] \|\| r_dcache_in_dtlb[waym_dcache_sets+set] )
4327	{
4328	// ins tlb invalidate verification
4329	r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
4330	r_dcache_itlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
4331	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4332
4333	// data tlb invalidate verification
4334	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
4335	r_dcache_dtlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
4336	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4337	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
4338	r_dcache_fsm_save = r_dcache_fsm;
4339	break;
4340	}
4341	r_dcache_fsm = DCACHE_IDLE;
4342	drsp.valid = true;
4343	}
4344	break;
4345	}
4346	/////////////////////////
4347	case DCACHE_DCACHE_SYNC:
4348	{
4349	// external cache invalidate request
4350	if ( r_tgt_dcache_req )
4351	{
4352	r_dcache_fsm = DCACHE_CC_CHECK;
4353	r_dcache_fsm_save = r_dcache_fsm;
4354	break;
4355	}
4356	if ( !r_dcache_write_req )
4357	{
4358	r_dcache_write_req = r_wbuf.rok();
4359	drsp.valid = true;
4360	r_dcache_fsm = DCACHE_IDLE;
4361	}
4362	break;
4363	}
4364	/////////////////////
4365	case DCACHE_MISS_WAIT:
4366	{
4367	m_cost_data_miss_frz++;
4368
4369	// external cache invalidate request
4370	if ( r_tgt_dcache_req )
4371	{
4372	r_dcache_fsm = DCACHE_CC_CHECK;
4373	r_dcache_fsm_save = r_dcache_fsm;
4374	break;
4375	}
4376
4377	if ( !r_dcache_miss_req )
4378	{
4379	if ( r_vci_rsp_data_error )
4380	{
4381	r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;
4382	r_dcache_bad_vaddr = dreq.addr;
4383	r_dcache_fsm = DCACHE_ERROR;
4384
4385	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
4386	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
4387	break;
4388	}
4389
4390	if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
4391	{
4392	if ( r_dcache_cleanup_req ) break;
4393	r_dcache_cleanup_req = true;
4394	r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);
4395	m_cpt_cc_cleanup_data++;
4396	r_dcache_fsm = DCACHE_IDLE;
4397	r_dcache_inval_tlb_rsp = false;
4398	if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
4399	break;
4400	}
4401
4402	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
4403	{
4404	if ( r_dcache_cleanup_req ) break;
4405	r_dcache_cleanup_req = true;
4406	r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);
4407	m_cpt_cc_cleanup_data++;
4408	r_dcache_fsm = DCACHE_IDLE;
4409	r_dcache_inval_rsp = false;
4410	break;
4411	}
4412	// Miss read response and no tlb invalidation
4413	r_dcache_fsm = DCACHE_MISS_UPDT;
4414	}
4415	break;
4416	}
4417	/////////////////////
4418	case DCACHE_MISS_UPDT:
4419	{
4420	m_cost_data_miss_frz++;
4421
4422	// external cache invalidate request
4423	if ( r_tgt_dcache_req )
4424	{
4425	r_dcache_fsm = DCACHE_CC_CHECK;
4426	r_dcache_fsm_save = r_dcache_fsm;
4427	break;
4428	}
4429
4430	if ( r_dcache_inval_tlb_rsp ) // tlb invalidation
4431	{
4432	if ( r_dcache_cleanup_req ) break;
4433	r_dcache_cleanup_req = true;
4434	r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);
4435	m_cpt_cc_cleanup_data++;
4436	r_dcache_inval_tlb_rsp = false;
4437	r_dcache_inval_rsp = false;
4438	r_dcache_fsm = DCACHE_IDLE;
4439	break;
4440	}
4441
4442	if (!r_dcache_cleanup_req ) // Miss update and no invalidation
4443	{
4444	paddr_t victim_index = 0;
4445	size_t way = 0;
4446	size_t set = 0;
4447
4448	// Using tlb entry is in the invalidated cache line
4449	if ( r_dcache_inval_rsp )
4450	{
4451	r_dcache_cleanup_req = true;
4452	r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);
4453	m_cpt_cc_cleanup_data++;
4454	r_dcache_fsm = DCACHE_IDLE;
4455	r_dcache_inval_rsp = false;
4456	break;
4457	}
4458
4459	bool cleanup_req = r_dcache.find(r_dcache_paddr_save.read(), r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
4460
4461	if ( cleanup_req )
4462	{
4463	// ins tlb invalidate verification
4464	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
4465	r_dcache_itlb_inval_line = victim_index;
4466	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4467
4468	// data tlb invalidate verification
4469	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
4470	r_dcache_dtlb_inval_line = victim_index;
4471	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4472
4473	r_dcache_cleanup_req = true;
4474	r_dcache_cleanup_line = victim_index;
4475	m_cpt_cc_cleanup_data++;
4476	if ( r_dcache_in_itlb[m_dcache_setsway+set] \|\| r_dcache_in_dtlb[m_dcache_setsway+set] )
4477	{
4478	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
4479	r_dcache_fsm_save = r_dcache_fsm;
4480	break;
4481	}
4482	}
4483	m_cpt_dcache_dir_write++;
4484	m_cpt_dcache_data_write++;
4485	r_dcache.update(r_dcache_paddr_save.read(), way, set, r_dcache_miss_buf);
4486	r_dcache_fsm = DCACHE_IDLE;
4487	}
4488	break;
4489	}
4490	//////////////////////
4491	case DCACHE_UNC_WAIT:
4492	{
4493	m_cost_unc_read_frz++;
4494
4495	// external cache invalidate request
4496	if ( r_tgt_dcache_req )
4497	{
4498	r_dcache_fsm = DCACHE_CC_CHECK;
4499	r_dcache_fsm_save = r_dcache_fsm;
4500	break;
4501	}
4502
4503	if ( !r_dcache_unc_req )
4504	{
4505	if ( r_vci_rsp_data_error )
4506	{
4507	r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;
4508	r_dcache_bad_vaddr = dreq.addr;
4509	r_dcache_fsm = DCACHE_ERROR;
4510
4511	if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
4512	break;
4513	}
4514
4515	if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
4516	{
4517	r_dcache_inval_tlb_rsp = false;
4518	}
4519
4520	drsp.valid = true;
4521	drsp.rdata = r_dcache_miss_buf[0];
4522	r_dcache_fsm = DCACHE_IDLE;
4523	}
4524	break;
4525	}
4526	///////////////////////
4527	case DCACHE_WRITE_UPDT:
4528	{
4529	m_cost_write_frz++;
4530	m_cpt_dcache_data_write++;
4531	size_t way = 0;
4532	size_t set = 0;
4533	bool write_hit = false;
4534	data_t mask = vci_param::be2mask(r_dcache_be_save.read());
4535	data_t wdata = (mask & r_dcache_wdata_save) \| (~mask & r_dcache_rdata_save);
4536	write_hit = r_dcache.write(r_dcache_paddr_save, wdata, &way, &set);
4537	assert(write_hit && "Write on miss ignores data");
4538
4539	if (r_dcache_in_itlb[waym_dcache_sets+set] \|\| r_dcache_in_dtlb[m_dcache_setsway+set])
4540	{
4541	// ins tlb invalidate verification
4542	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
4543	r_dcache_itlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
4544	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4545
4546	// data tlb invalidate verification
4547	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
4548	r_dcache_dtlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
4549	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4550
4551	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
4552	r_dcache_fsm_save = r_dcache_fsm;
4553	break;
4554	}
4555
4556	if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) )
4557	{
4558	m_cpt_data_tlb_update_dirty++;
4559	m_cost_data_tlb_update_dirty_frz++;
4560	if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) ) // 2M page size, one level page table
4561	{
4562	r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) \| PTE_D_MASK;
4563	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
4564	r_dcache_tlb_ll_dirty_req = true;
4565	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
4566	}
4567	else
4568	{
4569	if (r_dcache_hit_p_save)
4570	{
4571	r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) \| PTE_D_MASK;
4572	r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save\|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
4573	r_dcache_tlb_ll_dirty_req = true;
4574	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
4575	}
4576	else
4577	{
4578	r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) \| PTE_D_MASK;
4579	data_t ptba;
4580	if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
4581	{
4582	r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS \| (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
4583	r_dcache_tlb_ll_dirty_req = true;
4584	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
4585
4586	}
4587	else
4588	{
4589	r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) \| (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
4590	r_dcache_tlb_ptba_read = true;
4591	r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
4592	}
4593	}
4594	}
4595	}
4596	else
4597	{
4598	r_dcache_fsm = DCACHE_WRITE_REQ;
4599	drsp.valid = true;
4600	drsp.rdata = 0;
4601	}
4602	break;
4603	}
4604	////////////////////////
4605	case DCACHE_WRITE_DIRTY:
4606	{
4607	m_cost_data_tlb_update_dirty_frz++;
4608
4609	// external cache invalidate request
4610	if ( r_tgt_dcache_req )
4611	{
4612	r_dcache_fsm = DCACHE_CC_CHECK;
4613	r_dcache_fsm_save = r_dcache_fsm;
4614	break;
4615	}
4616
4617	if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
4618	{
4619	r_dcache_fsm = DCACHE_IDLE;
4620	if ( r_dcache_sc_updt_dirty ) r_dcache_sc_updt_dirty = false;
4621	r_dcache_inval_tlb_rsp = false;
4622	break;
4623	}
4624
4625	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
4626	{
4627	r_dcache_fsm = DCACHE_IDLE;
4628	if ( r_dcache_sc_updt_dirty ) r_dcache_sc_updt_dirty = false;
4629	r_dcache_inval_rsp = false;
4630	break;
4631	}
4632
4633	dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save);
4634	if ( r_dcache_sc_updt_dirty )
4635	{
4636	r_dcache_sc_updt_dirty = false;
4637	r_dcache_unc_req = true;
4638	r_dcache_fsm = DCACHE_UNC_WAIT;
4639	m_cpt_unc_read++;
4640	}
4641	else
4642	{
4643	r_dcache_fsm = DCACHE_WRITE_REQ;
4644	drsp.valid = true;
4645	drsp.rdata = 0;
4646	}
4647	break;
4648	}
4649	/////////////////
4650	case DCACHE_ERROR:
4651	{
4652	r_vci_rsp_data_error = false;
4653	drsp.valid = true;
4654	drsp.error = true;
4655	drsp.rdata = 0;
4656	r_dcache_fsm = DCACHE_IDLE;
4657	break;
4658	}
4659	//////////////////////
4660	case DCACHE_ITLB_READ:
4661	{
4662	if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
4663
4664	// external cache invalidate request
4665	if ( r_tgt_dcache_req )
4666	{
4667	r_dcache_fsm = DCACHE_CC_CHECK;
4668	r_dcache_fsm_save = r_dcache_fsm;
4669	break;
4670	}
4671
4672	if ( !r_dcache_itlb_read_req ) // vci response ok
4673	{
4674	if ( r_vci_rsp_data_error )
4675	{
4676	r_dcache_rsp_itlb_error = true;
4677	r_itlb_read_dcache_req = false;
4678	r_vci_rsp_data_error = false;
4679	r_dcache_fsm = DCACHE_IDLE;
4680
4681	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
4682	break;
4683	}
4684
4685	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
4686	{
4687	if ( r_dcache_cleanup_req ) break;
4688	r_dcache_cleanup_req = true;
4689	r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);
4690	m_cpt_cc_cleanup_data++;
4691	r_dcache_fsm = DCACHE_IDLE;
4692	r_dcache_inval_rsp = false;
4693	break;
4694	}
4695
4696	r_dcache_fsm = DCACHE_ITLB_UPDT;
4697	}
4698	break;
4699	}
4700	//////////////////////
4701	case DCACHE_ITLB_UPDT:
4702	{
4703	if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
4704
4705	// external cache invalidate request
4706	if ( r_tgt_dcache_req )
4707	{
4708	r_dcache_fsm = DCACHE_CC_CHECK;
4709	r_dcache_fsm_save = r_dcache_fsm;
4710	break;
4711	}
4712
4713	if ( !r_dcache_cleanup_req )
4714	{
4715	data_t rsp_itlb_miss = 0;
4716	data_t rsp_itlb_ppn = 0;
4717
4718	paddr_t victim_index = 0;
4719	size_t way = 0;
4720	size_t set = 0;
4721
4722	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
4723	{
4724	r_dcache_cleanup_req = true;
4725	r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);
4726	m_cpt_cc_cleanup_data++;
4727	r_dcache_fsm = DCACHE_IDLE;
4728	r_dcache_inval_rsp = false;
4729	break;
4730	}
4731
4732	bool cleanup = r_dcache.find(r_icache_paddr_save, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
4733
4734	if ( cleanup )
4735	{
4736	// ins tlb invalidate verification
4737	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
4738	r_dcache_itlb_inval_line = victim_index;
4739	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4740
4741	// data tlb invalidate verification
4742	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
4743	r_dcache_dtlb_inval_line = victim_index;
4744	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4745
4746	r_dcache_cleanup_req = true;
4747	r_dcache_cleanup_line = victim_index;
4748	m_cpt_cc_cleanup_data++;
4749	if ( r_dcache_in_itlb[m_dcache_setsway+set] \|\| r_dcache_in_dtlb[m_dcache_setsway+set] )
4750	{
4751	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
4752	r_dcache_fsm_save = r_dcache_fsm;
4753	break;
4754	}
4755	}
4756
4757	r_dcache.update(r_icache_paddr_save, way, set, r_dcache_miss_buf);
4758
4759	bool set_hit = r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
4760	assert(set_hit && "ITLB_UPDT set hit error");
4761	bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
4762	m_cpt_ins_tlb_occup_cache++;
4763
4764	if ( r_itlb_k_read_dcache && itlb_hit_dcache )
4765	{
4766	r_itlb_k_read_dcache = false;
4767	bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
4768	assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
4769	}
4770
4771	r_dcache_rsp_itlb_miss = rsp_itlb_miss;
4772	r_dcache_rsp_itlb_ppn = rsp_itlb_ppn;
4773	r_dcache_rsp_itlb_error = false;
4774	r_itlb_read_dcache_req = false;
4775	r_dcache_fsm = DCACHE_IDLE;
4776	}
4777	break;
4778	}
4779	//////////////////////////
4780	case DCACHE_ITLB_LL_WAIT:
4781	{
4782	if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
4783	// external cache invalidate request
4784	if ( r_tgt_dcache_req )
4785	{
4786	r_dcache_fsm = DCACHE_CC_CHECK;
4787	r_dcache_fsm_save = r_dcache_fsm;
4788	break;
4789	}
4790
4791	if (!r_dcache_itlb_ll_acc_req)
4792	{
4793	if ( r_vci_rsp_data_error ) // VCI response ko
4794	{
4795	r_dcache_rsp_itlb_error = true;
4796	r_vci_rsp_data_error = false;
4797	r_itlb_acc_dcache_req = false;
4798	r_dcache_fsm = DCACHE_IDLE;
4799	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
4800	}
4801	else
4802	{
4803	if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) ) // unmapped
4804	{
4805	r_dcache_rsp_itlb_error = true;
4806	r_itlb_acc_dcache_req = false;
4807	r_dcache_fsm = DCACHE_IDLE;
4808	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
4809	}
4810	else if ( r_dcache_inval_rsp )
4811	{
4812	r_dcache_inval_rsp = false;
4813	r_dcache_fsm = DCACHE_IDLE;
4814	}
4815	else
4816	{
4817	r_dcache_itlb_sc_acc_req = true;
4818	r_icache_pte_update = r_dcache_miss_buf[0] \| r_icache_pte_update.read();
4819	r_dcache_fsm = DCACHE_ITLB_SC_WAIT;
4820	}
4821	}
4822	}
4823	break;
4824	}
4825	//////////////////////////
4826	case DCACHE_ITLB_SC_WAIT:
4827	{
4828	if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
4829	// external cache invalidate request
4830	if ( r_tgt_dcache_req )
4831	{
4832	r_dcache_fsm = DCACHE_CC_CHECK;
4833	r_dcache_fsm_save = r_dcache_fsm;
4834	break;
4835	}
4836
4837	if ( !r_dcache_itlb_sc_acc_req )
4838	{
4839	if ( r_vci_rsp_data_error ) // VCI response ko
4840	{
4841	r_dcache_rsp_itlb_error = true;
4842	r_vci_rsp_data_error = false;
4843	r_itlb_acc_dcache_req = false;
4844	r_dcache_fsm = DCACHE_IDLE;
4845	if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
4846	}
4847	else
4848	{
4849	if ( r_dcache_inval_rsp )
4850	{
4851	r_itlb_acc_dcache_req = false;
4852	r_itlb_acc_redo_req = true;
4853	r_dcache_inval_rsp = false;
4854	r_dcache_fsm = DCACHE_IDLE;
4855	if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
4856	}
4857	else if ( r_dcache_tlb_sc_fail )
4858	{
4859	r_dcache_tlb_sc_fail = false;
4860	r_dcache_itlb_ll_acc_req = true;
4861	r_dcache_fsm = DCACHE_ITLB_LL_WAIT;
4862	}
4863	else
4864	{
4865	bool write_hit = r_dcache.write(r_icache_paddr_save, r_icache_pte_update);
4866	assert(write_hit && "Write on miss ignores data for data MMU update ins access bit");
4867	r_itlb_acc_dcache_req = false;
4868	r_dcache_fsm = DCACHE_IDLE;
4869	}
4870	}
4871	}
4872	break;
4873	}
4874	/////////////////////
4875	case DCACHE_CC_CHECK: // read directory in case of invalidate or update request
4876	{
4877	m_cpt_dcache_dir_read += m_dcache_ways;
4878	m_cpt_dcache_data_read += m_dcache_ways;
4879
4880	/* activity counter */
4881	if ( (( r_dcache_fsm_save == DCACHE_BIS ) \|\|( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )
4882	{
4883	m_cost_data_miss_frz++;
4884	}
4885	if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) \|\| ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) \|\|
4886	( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
4887	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
4888	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
4889	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) \|\|
4890	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
4891	{
4892	m_cost_data_tlb_miss_frz++;
4893	}
4894
4895	// DCACHE_TLB1_LL_WAIT DCACHE_TLB1_SC_WAIT DCACHE_LL_DIRTY_WAIT DCACHE_WRITE_DIRTY DCACHE_ITLB_LL_WAIT DCACHE_ITLB_SC_WAIT
4896	// DCACHE_TLB2_LL_WAIT DCACHE_TLB2_SC_WAIT DCACHE_SC_DIRTY_WAIT
4897	if((( /( r_dcache_fsm_save == DCACHE_UNC_WAIT ) \|\|/
4898	( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) &&
4899	( (r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))))
4900	\|\| (( ( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
4901	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) /*\|\|
4902	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT ) \|\|
4903	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
4904	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
4905	( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) \|\|
4906	( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )*/ ) &&
4907	( (r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) )
4908	\|\| (( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) /*\|\| ( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) \|\|
4909	( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT )*/ ) &&
4910	( (r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) )
4911	{
4912	r_dcache_inval_rsp = true;
4913	r_tgt_dcache_req = false;
4914	if ( r_tgt_update )
4915	{ // Also send a cleanup and answer
4916	r_tgt_dcache_rsp = true;
4917	}
4918	else
4919	{ // Also send a cleanup but don't answer
4920	r_tgt_dcache_rsp = false;
4921	}
4922	r_dcache_fsm = r_dcache_fsm_save;
4923	}
4924	else
4925	{
4926	data_t dcache_rdata = 0;
4927	size_t way = 0;
4928	size_t set = 0;
4929
4930	bool dcache_hit = r_dcache.read(r_tgt_addr.read(), &dcache_rdata, &way, &set);
4931
4932	if ( dcache_hit )
4933	{
4934	if (((( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT ) \|\|
4935	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
4936	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
4937	( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) \|\|
4938	( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )) &&
4939	((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)) )) \|\|
4940	((( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) \|\|
4941	( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) ) &&
4942	((r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)))))
4943	{
4944	r_dcache_inval_rsp = true;
4945	}
4946
4947	if ( r_dcache_in_dtlb[m_dcache_setsway+set] \|\| r_dcache_in_itlb[m_dcache_setsway+set] )
4948	{
4949	// ins tlb invalidate verification
4950	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
4951	r_dcache_itlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
4952	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4953
4954	// data tlb invalidate verification
4955	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
4956	r_dcache_dtlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
4957	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4958
4959	r_dcache_cc_check = true;
4960	r_dcache_fsm = DCACHE_TLB_CC_INVAL;
4961	break;
4962	}
4963
4964	if ( r_tgt_update ) // update
4965	{
4966	r_dcache_fsm = DCACHE_CC_UPDT;
4967	}
4968	else // invalidate
4969	{
4970	r_dcache_fsm = DCACHE_CC_INVAL;
4971	}
4972	}
4973	else // nothing
4974	{
4975	r_dcache_fsm = DCACHE_CC_NOP;
4976	}
4977	}
4978	break;
4979	}
4980	///////////////////
4981	case DCACHE_CC_UPDT: // update directory and data cache
4982	{
4983	/* activity counter */
4984	if ( (( r_dcache_fsm_save == DCACHE_BIS ) \|\|( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )
4985	{
4986	m_cost_data_miss_frz++;
4987	}
4988	if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) \|\| ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) \|\|
4989	( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
4990	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
4991	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
4992	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) \|\|
4993	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
4994	{
4995	m_cost_data_tlb_miss_frz++;
4996	}
4997
4998	m_cpt_dcache_dir_write++;
4999	m_cpt_dcache_data_write++;
5000	data_t* buf = r_tgt_buf;
5001	for( size_t i = 0; i < m_dcache_words; i++ )
5002	{
5003	if( r_tgt_val[i] ) r_dcache.write( r_tgt_addr.read() + i*4, buf[i] );
5004	}
5005
5006	r_tgt_dcache_req = false;
5007	r_tgt_dcache_rsp = true;
5008	r_dcache_fsm = r_dcache_fsm_save;
5009	break;
5010	}
5011	/////////////////////
5012	case DCACHE_CC_INVAL: // invalidate a cache line
5013	{
5014	/* activity counter */
5015	if ( (( r_dcache_fsm_save == DCACHE_BIS ) \|\|( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )
5016	{
5017	m_cost_data_miss_frz++;
5018	}
5019	if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) \|\| ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) \|\|
5020	( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
5021	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
5022	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
5023	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) \|\|
5024	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
5025	{
5026	m_cost_data_tlb_miss_frz++;
5027	}
5028
5029	r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read());
5030	r_tgt_dcache_req = false;
5031	r_dcache_fsm = r_dcache_fsm_save;
5032	break;
5033	}
5034	///////////////////
5035	case DCACHE_CC_NOP: // no external hit
5036	{
5037	/* activity counter */
5038	if ( (( r_dcache_fsm_save == DCACHE_BIS ) \|\|( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )
5039	{
5040	m_cost_data_miss_frz++;
5041	}
5042	if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) \|\| ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) \|\|
5043	( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
5044	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
5045	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
5046	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) \|\|
5047	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
5048	{
5049	m_cost_data_tlb_miss_frz++;
5050	}
5051
5052	r_tgt_dcache_req = false;
5053	if ( r_tgt_update )
5054	{
5055	r_tgt_dcache_rsp = true;
5056	}
5057	else
5058	{
5059	r_tgt_dcache_rsp = false;
5060	}
5061
5062	r_dcache_fsm = r_dcache_fsm_save;
5063	break;
5064	}
5065	/////////////////////////
5066	case DCACHE_TLB_CC_INVAL:
5067	{
5068	/* activity counter */
5069	if ( (( r_dcache_fsm_save == DCACHE_BIS ) \|\|( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )
5070	{
5071	m_cost_data_miss_frz++;
5072	}
5073	if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) \|\| ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) \|\|
5074	( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
5075	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
5076	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
5077	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) \|\|
5078	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) )
5079	{
5080	m_cost_data_tlb_miss_frz++;
5081	}
5082
5083	if ( r_dcache_itlb_inval_req \|\| r_dcache_dtlb_inval_req ) break;
5084
5085	if( (( r_dcache_fsm_save == DCACHE_TLB1_READ ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ ) \|\|
5086	( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) \|\|
5087	( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) \|\|
5088	( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) \|\|
5089	( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) \|\| ( r_dcache_fsm_save == DCACHE_TLB2_UPDT ) \|\|
5090	( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) \|\| ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) \|\|
5091	( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) \|\|
5092	( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )) &&
5093	(((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_dtlb_inval_line.read()) )
5094	{
5095	r_dcache_inval_tlb_rsp = true;
5096	}
5097
5098	if (((r_dcache_fsm_save == DCACHE_BIS)\|\|(r_dcache_fsm_save == DCACHE_MISS_WAIT) \|\|
5099	(r_dcache_fsm_save == DCACHE_MISS_UPDT)) &&
5100	(r_dcache_tlb_nline.read() == r_dcache_dtlb_inval_line.read()))
5101	{
5102	r_dcache_inval_tlb_rsp = true;
5103	}
5104
5105	if ( !r_dcache_cc_check )
5106	{
5107	r_dcache_fsm = r_dcache_fsm_save;
5108	}
5109	else
5110	{
5111	r_dcache_fsm = DCACHE_CC_CHECK;
5112	r_dcache_cc_check = false;
5113	}
5114	r_dtlb_translation_valid = false;
5115	r_dcache_ptba_ok = false;
5116	break;
5117	}
5118	/////////////////////////
5119	case DCACHE_ITLB_CLEANUP:
5120	{
5121	if ( dreq.valid ) m_cost_data_miss_frz++;
5122
5123	r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()<<(uint32_log2(m_dcache_words)+2)), r_dcache_in_itlb, false);
5124	r_dcache_itlb_cleanup_req = false;
5125	r_dcache_fsm = DCACHE_IDLE;
5126	break;
5127	}
5128	} // end switch r_dcache_fsm
5129
5130	#ifdef SOCLIB_MODULE_DEBUG
5131	std::cout << name() << " Data Response: " << drsp << std::endl;
5132	#endif
5133
5134	////////////////////////////////////////////////////////////////////////////////////
5135	// INVAL DTLB CHECK FSM
5136	////////////////////////////////////////////////////////////////////////////////////////
5137	switch(r_inval_dtlb_fsm) {
5138	/////////////////////
5139	case INVAL_DTLB_IDLE:
5140	{
5141	if ( r_dcache_dtlb_inval_req )
5142	{
5143	r_ccinval_dtlb_way = 0;
5144	r_ccinval_dtlb_set = 0;
5145	r_inval_dtlb_fsm = INVAL_DTLB_CHECK;
5146	m_cost_data_tlb_inval_frz++;
5147	}
5148	break;
5149	}
5150	////////////////////////////
5151	case INVAL_DTLB_CHECK:
5152	{
5153	m_cost_data_tlb_inval_frz++;
5154
5155	size_t way = r_ccinval_dtlb_way;
5156	size_t set = r_ccinval_dtlb_set;
5157	bool end = false;
5158	bool tlb_hit = dcache_tlb.cccheck(r_dcache_dtlb_inval_line.read(), way, set, &way, &set, &end);
5159
5160	if ( tlb_hit )
5161	{
5162	r_ccinval_dtlb_way = way;
5163	r_ccinval_dtlb_set = set;
5164	r_dtlb_cc_check_end = end;
5165	r_inval_dtlb_fsm = INVAL_DTLB_INVAL;
5166	m_cpt_data_tlb_inval++;
5167	}
5168	else
5169	{
5170	r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;
5171	}
5172	break;
5173	}
5174	/////////////////////////
5175	case INVAL_DTLB_INVAL:
5176	{
5177	m_cost_data_tlb_inval_frz++;
5178
5179	dcache_tlb.ccinval(r_ccinval_dtlb_way, r_ccinval_dtlb_set);
5180
5181	if ( !r_dtlb_cc_check_end )
5182	{
5183	r_inval_dtlb_fsm = INVAL_DTLB_CHECK;
5184	}
5185	else
5186	{
5187	r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;
5188	}
5189	break;
5190	}
5191	////////////////////
5192	case INVAL_DTLB_CLEAR:
5193	{
5194	r_dcache_dtlb_inval_req = false;
5195	r_dtlb_cc_check_end = false;
5196	r_ccinval_dtlb_way = 0;
5197	r_ccinval_dtlb_set = 0;
5198	r_inval_dtlb_fsm = INVAL_DTLB_IDLE;
5199	m_cpt_data_tlb_inval++;
5200	break;
5201	}
5202	} // end switch r_inval_itlb_fsm
5203
5204	/////////// execute one iss cycle /////////////////////////////////
5205	{
5206	uint32_t it = 0;
5207	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
5208	m_iss.executeNCycles(1, irsp, drsp, it);
5209	}
5210
5211	////////////// number of frozen cycles //////////////////////////
5212	if ( (ireq.valid && !irsp.valid) \|\| (dreq.valid && !drsp.valid) )
5213	{
5214	m_cpt_frz_cycles++;
5215	}
5216	if ( dreq.valid && !drsp.valid )
5217	{
5218	m_cpt_dcache_frz_cycles++;
5219	}
5220	for (size_t way = 0; way < m_dcache_ways; way++ )
5221	{
5222	for (size_t set = 0; set < m_dcache_sets; set++ )
5223	{
5224	if (r_dcache_in_itlb[waym_dcache_sets+set] \|\| r_dcache_in_dtlb[waym_dcache_sets+set])
5225	m_cpt_tlb_occup_dcache++;
5226	}
5227	}
5228	////////////////////////////////////////////////////////////////////////////
5229	// VCI_CMD FSM
5230	//
5231	// This FSM handles requests from both the DCACHE controler
5232	// (request registers) and the ICACHE controler (request registers).
5233	// There is 10 VCI transaction types :
5234	// - INS_TLB_READ
5235	// - INS_TLB_WRITE
5236	// - INS_MISS
5237	// - INS_UNC_MISS
5238	// - DATA_TLB_READ
5239	// - DATA_TLB_WRITE
5240	// - DATA_TLB_DIRTY
5241	// - DATA_MISS
5242	// - DATA_UNC
5243	// - DATA_WRITE
5244	// The ICACHE requests have the highest priority.
5245	// There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM and RSP_FSM
5246	// exit simultaneously the IDLE state.
5247	//////////////////////////////////////////////////////////////////////////////
5248
5249	switch (r_vci_cmd_fsm) {
5250
5251	case CMD_IDLE:
5252	if (r_vci_rsp_fsm != RSP_IDLE)
5253	break;
5254
5255	r_vci_cmd_cpt = 0;
5256
5257	if (r_icache_cleanup_req)
5258	{
5259	r_vci_cmd_fsm = CMD_INS_CLEANUP;
5260	m_cpt_icleanup_transaction++;
5261	}
5262	else if (r_dcache_cleanup_req)
5263	{
5264	r_vci_cmd_fsm = CMD_DATA_CLEANUP;
5265	m_cpt_dcleanup_transaction++;
5266	}
5267	else if (r_dcache_itlb_read_req)
5268	{
5269	r_vci_cmd_fsm = CMD_ITLB_READ;
5270	m_cpt_itlbmiss_transaction++;
5271	}
5272	else if (r_dcache_itlb_ll_acc_req)
5273	{
5274	r_vci_cmd_fsm = CMD_ITLB_ACC_LL;
5275	m_cpt_itlb_ll_transaction++;
5276	}
5277	else if (r_dcache_itlb_sc_acc_req)
5278	{
5279	r_vci_cmd_fsm = CMD_ITLB_ACC_SC;
5280	m_cpt_itlb_sc_transaction++;
5281	}
5282	else if (r_icache_miss_req)
5283	{
5284	r_vci_cmd_fsm = CMD_INS_MISS;
5285	m_cpt_imiss_transaction++;
5286	}
5287	else if (r_icache_unc_req)
5288	{
5289	r_vci_cmd_fsm = CMD_INS_UNC;
5290	m_cpt_icache_unc_transaction++;
5291	}
5292	else if (r_dcache_tlb_read_req)
5293	{
5294	r_vci_cmd_fsm = CMD_DTLB_READ;
5295	m_cpt_dtlbmiss_transaction++;
5296	}
5297	else if (r_dcache_tlb_ll_acc_req)
5298	{
5299	r_vci_cmd_fsm = CMD_DTLB_ACC_LL;
5300	m_cpt_dtlb_ll_transaction++;
5301	}
5302	else if (r_dcache_tlb_sc_acc_req)
5303	{
5304	r_vci_cmd_fsm = CMD_DTLB_ACC_SC;
5305	m_cpt_dtlb_sc_transaction++;
5306	}
5307	else if (r_dcache_tlb_ll_dirty_req)
5308	{
5309	r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL;
5310	m_cpt_dtlb_ll_dirty_transaction++;
5311	}
5312	else if (r_dcache_tlb_sc_dirty_req)
5313	{
5314	r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC;
5315	m_cpt_dtlb_sc_dirty_transaction++;
5316	}
5317	else if (r_dcache_write_req)
5318	{
5319	r_vci_cmd_fsm = CMD_DATA_WRITE;
5320	r_vci_cmd_cpt = r_wbuf.getMin();
5321	r_vci_cmd_min = r_wbuf.getMin();
5322	r_vci_cmd_max = r_wbuf.getMax();
5323	m_cpt_write_transaction++;
5324	m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1);
5325	}
5326	else if (r_dcache_miss_req)
5327	{
5328	r_vci_cmd_fsm = CMD_DATA_MISS;
5329	m_cpt_dmiss_transaction++;
5330	}
5331	else if (r_dcache_unc_req)
5332	{
5333	r_vci_cmd_fsm = CMD_DATA_UNC;
5334	m_cpt_unc_transaction++;
5335	}
5336	break;
5337
5338	case CMD_DATA_WRITE:
5339	if ( p_vci_ini_rw.cmdack.read() )
5340	{
5341	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5342	if (r_vci_cmd_cpt == r_vci_cmd_max)
5343	{
5344	r_vci_cmd_fsm = CMD_IDLE;
5345	r_wbuf.reset();
5346	}
5347	}
5348	break;
5349
5350	case CMD_INS_CLEANUP:
5351	case CMD_DATA_CLEANUP:
5352	if ( p_vci_ini_c.cmdack.read() )
5353	{
5354	r_vci_cmd_fsm = CMD_IDLE;
5355	}
5356	break;
5357
5358	default:
5359	if ( p_vci_ini_rw.cmdack.read() )
5360	{
5361	r_vci_cmd_fsm = CMD_IDLE;
5362	}
5363	break;
5364
5365	} // end switch r_vci_cmd_fsm
5366
5367	//////////////////////////////////////////////////////////////////////////
5368	// VCI_RSP FSM
5369	//
5370	// This FSM is synchronized with the VCI_CMD FSM, as both FSMs exit the
5371	// IDLE state simultaneously.
5372	//////////////////////////////////////////////////////////////////////////
5373
5374	switch (r_vci_rsp_fsm) {
5375
5376	case RSP_IDLE:
5377	assert( !p_vci_ini_rw.rspval.read() && !p_vci_ini_c.rspval.read() && "Unexpected response" );
5378
5379	if (r_vci_cmd_fsm != CMD_IDLE)
5380	break;
5381
5382	r_vci_rsp_cpt = 0;
5383	if (r_icache_cleanup_req) // ICACHE cleanup response
5384	{
5385	r_vci_rsp_fsm = RSP_INS_CLEANUP;
5386	}
5387	else if (r_dcache_cleanup_req) // DCACHE cleanup response
5388	{
5389	r_vci_rsp_fsm = RSP_DATA_CLEANUP;
5390	}
5391	else if (r_dcache_itlb_read_req) // ITLB miss response
5392	{
5393	r_vci_rsp_fsm = RSP_ITLB_READ;
5394	}
5395	else if (r_dcache_itlb_ll_acc_req) // ITLB linked load response
5396	{
5397	r_vci_rsp_fsm = RSP_ITLB_ACC_LL;
5398	}
5399	else if (r_dcache_itlb_sc_acc_req) // ITLB store conditional response
5400	{
5401	r_vci_rsp_fsm = RSP_ITLB_ACC_SC;
5402	}
5403	else if (r_icache_miss_req) // ICACHE cached miss response
5404	{
5405	r_vci_rsp_fsm = RSP_INS_MISS;
5406	}
5407	else if (r_icache_unc_req) // ICACHE uncached miss response
5408	{
5409	r_vci_rsp_fsm = RSP_INS_UNC;
5410	}
5411	else if (r_dcache_tlb_read_req) // ITLB miss response
5412	{
5413	r_vci_rsp_fsm = RSP_DTLB_READ;
5414	}
5415	else if (r_dcache_tlb_ll_acc_req) // DTLB access bits linked load response
5416	{
5417	r_vci_rsp_fsm = RSP_DTLB_ACC_LL;
5418	}
5419	else if (r_dcache_tlb_sc_acc_req) // DTLB access bits store conditional response
5420	{
5421	r_vci_rsp_fsm = RSP_DTLB_ACC_SC;
5422	}
5423	else if (r_dcache_tlb_ll_dirty_req) // DTLB dirty bit linked load response
5424	{
5425	r_vci_rsp_fsm = RSP_DTLB_DIRTY_LL;
5426	}
5427	else if (r_dcache_tlb_sc_dirty_req) // DTLB dirty bit store conditional response
5428	{
5429	r_vci_rsp_fsm = RSP_DTLB_DIRTY_SC;
5430	}
5431	else if (r_dcache_write_req) // DCACHE write response
5432	{
5433	r_vci_rsp_fsm = RSP_DATA_WRITE;
5434	}
5435	else if (r_dcache_miss_req) // DCACHE read response
5436	{
5437	r_vci_rsp_fsm = RSP_DATA_MISS;
5438	}
5439	else if (r_dcache_unc_req) // DCACHE uncached read response
5440	{
5441	r_vci_rsp_fsm = RSP_DATA_UNC;
5442	}
5443	break;
5444
5445	case RSP_ITLB_READ:
5446	m_cost_itlbmiss_transaction++;
5447	if ( ! p_vci_ini_rw.rspval.read() )
5448	break;
5449
5450	assert(r_vci_rsp_cpt != m_dcache_words &&
5451	"illegal VCI response packet for data read miss");
5452
5453	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
5454	r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
5455	if ( p_vci_ini_rw.reop.read() )
5456	{
5457	assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
5458	"illegal VCI response packet for data read miss");
5459	r_dcache_itlb_read_req = false;
5460	r_vci_rsp_fsm = RSP_IDLE;
5461	}
5462	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5463	{
5464	r_vci_rsp_data_error = true;
5465	}
5466	break;
5467
5468	case RSP_ITLB_ACC_LL:
5469	m_cost_itlb_ll_transaction++;
5470	if ( ! p_vci_ini_rw.rspval.read() )
5471	break;
5472
5473	assert(p_vci_ini_rw.reop.read() &&
5474	"illegal VCI response packet for ll tlb");
5475
5476	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5477	{
5478	r_vci_rsp_data_error = true;
5479	}
5480	else
5481	{
5482	r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
5483	}
5484	r_dcache_itlb_ll_acc_req = false;
5485	r_vci_rsp_fsm = RSP_IDLE;
5486	break;
5487
5488	case RSP_ITLB_ACC_SC:
5489	m_cost_itlb_sc_transaction++;
5490	if ( ! p_vci_ini_rw.rspval.read() )
5491	break;
5492
5493	assert(p_vci_ini_rw.reop.read() &&
5494	"illegal VCI response packet for sc tlb");
5495
5496	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5497	{
5498	r_vci_rsp_data_error = true;
5499	}
5500	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
5501	{
5502	r_dcache_tlb_sc_fail = true;
5503	//r_dcache_itlb_ll_acc_req = true;
5504	}
5505	r_dcache_itlb_sc_acc_req = false;
5506	r_vci_rsp_fsm = RSP_IDLE;
5507	break;
5508
5509	case RSP_INS_MISS:
5510	m_cost_imiss_transaction++;
5511	if ( ! p_vci_ini_rw.rspval.read() )
5512	break;
5513
5514	assert( (r_vci_rsp_cpt < m_icache_words) &&
5515	"The VCI response packet for instruction miss is too long");
5516	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
5517	r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
5518
5519	if ( p_vci_ini_rw.reop.read() )
5520	{
5521	assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
5522	"The VCI response packet for instruction miss is too short");
5523	r_icache_miss_req = false;
5524	r_vci_rsp_fsm = RSP_IDLE;
5525
5526	}
5527	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5528	{
5529	r_vci_rsp_ins_error = true;
5530	}
5531	break;
5532
5533	case RSP_INS_UNC:
5534	m_cost_icache_unc_transaction++;
5535	if ( ! p_vci_ini_rw.rspval.read() )
5536	break;
5537
5538	assert(p_vci_ini_rw.reop.read() &&
5539	"illegal VCI response packet for uncached instruction");
5540
5541	r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
5542	r_icache_buf_unc_valid = true;
5543	r_icache_unc_req = false;
5544	r_vci_rsp_fsm = RSP_IDLE;
5545
5546	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5547	{
5548	r_vci_rsp_ins_error = true;
5549	}
5550	break;
5551
5552	case RSP_DTLB_READ:
5553	m_cost_dtlbmiss_transaction++;
5554	if ( ! p_vci_ini_rw.rspval.read() )
5555	break;
5556
5557	assert(r_vci_rsp_cpt != m_dcache_words &&
5558	"illegal VCI response packet for data read miss");
5559
5560	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
5561	r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
5562	if ( p_vci_ini_rw.reop.read() )
5563	{
5564	assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
5565	"illegal VCI response packet for data read miss");
5566	r_dcache_tlb_read_req = false;
5567	r_vci_rsp_fsm = RSP_IDLE;
5568	}
5569	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5570	{
5571	r_vci_rsp_data_error = true;
5572	}
5573	break;
5574
5575	case RSP_DTLB_ACC_LL:
5576	m_cost_dtlb_ll_transaction++;
5577	if ( ! p_vci_ini_rw.rspval.read() )
5578	break;
5579
5580	assert(p_vci_ini_rw.reop.read() &&
5581	"illegal VCI response packet for ll tlb");
5582
5583	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5584	{
5585	r_vci_rsp_data_error = true;
5586	}
5587	else
5588	{
5589	r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
5590	}
5591	r_dcache_tlb_ll_acc_req = false;
5592	r_vci_rsp_fsm = RSP_IDLE;
5593	break;
5594
5595	case RSP_DTLB_ACC_SC:
5596	m_cost_dtlb_sc_transaction++;
5597	if ( ! p_vci_ini_rw.rspval.read() )
5598	break;
5599
5600	assert(p_vci_ini_rw.reop.read() &&
5601	"illegal VCI response packet for sc tlb");
5602
5603	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5604	{
5605	r_vci_rsp_data_error = true;
5606	}
5607	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
5608	{
5609	r_dcache_tlb_sc_fail = true;
5610	//r_dcache_tlb_ll_acc_req = true;
5611	}
5612	r_dcache_tlb_sc_acc_req = false;
5613	r_vci_rsp_fsm = RSP_IDLE;
5614	break;
5615
5616	case RSP_DTLB_DIRTY_LL:
5617	m_cost_dtlb_ll_dirty_transaction++;
5618	if ( ! p_vci_ini_rw.rspval.read() )
5619	break;
5620
5621	assert(p_vci_ini_rw.reop.read() &&
5622	"illegal VCI response packet for ll tlb");
5623
5624	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5625	{
5626	r_vci_rsp_data_error = true;
5627	}
5628	else
5629	{
5630	r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
5631	}
5632	r_dcache_tlb_ll_dirty_req = false;
5633	r_vci_rsp_fsm = RSP_IDLE;
5634	break;
5635
5636	case RSP_DTLB_DIRTY_SC:
5637	m_cost_dtlb_sc_dirty_transaction++;
5638	if ( ! p_vci_ini_rw.rspval.read() )
5639	break;
5640
5641	assert(p_vci_ini_rw.reop.read() &&
5642	"illegal VCI response packet for sc tlb");
5643
5644	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5645	{
5646	r_vci_rsp_data_error = true;
5647	}
5648	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
5649	{
5650	r_dcache_tlb_sc_fail = true;
5651	//r_dcache_tlb_ll_dirty_req = true;
5652	}
5653	r_dcache_tlb_sc_dirty_req = false;
5654	r_vci_rsp_fsm = RSP_IDLE;
5655	break;
5656
5657	case RSP_DATA_UNC:
5658	m_cost_unc_transaction++;
5659	if ( ! p_vci_ini_rw.rspval.read() )
5660	break;
5661
5662	assert(p_vci_ini_rw.reop.read() &&
5663	"illegal VCI response packet for data read uncached");
5664
5665	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5666	{
5667	r_vci_rsp_data_error = true;
5668	}
5669	else
5670	{
5671	r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
5672	r_dcache_buf_unc_valid = true;
5673	}
5674	r_dcache_unc_req = false;
5675	r_vci_rsp_fsm = RSP_IDLE;
5676	break;
5677
5678	case RSP_DATA_MISS:
5679	m_cost_dmiss_transaction++;
5680	if ( ! p_vci_ini_rw.rspval.read() )
5681	break;
5682
5683	assert(r_vci_rsp_cpt != m_dcache_words &&
5684	"illegal VCI response packet for data read miss");
5685
5686	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
5687	r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
5688	if ( p_vci_ini_rw.reop.read() )
5689	{
5690	assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
5691	"illegal VCI response packet for data read miss");
5692	r_dcache_miss_req = false;
5693	r_vci_rsp_fsm = RSP_IDLE;
5694	}
5695	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5696	{
5697	r_vci_rsp_data_error = true;
5698	}
5699	break;
5700
5701	case RSP_DATA_WRITE:
5702	m_cost_write_transaction++;
5703	if ( ! p_vci_ini_rw.rspval.read() )
5704	break;
5705
5706	if ( p_vci_ini_rw.reop.read() )
5707	{
5708	r_vci_rsp_fsm = RSP_IDLE;
5709	r_dcache_write_req = false;
5710	}
5711	if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
5712	{
5713	m_iss.setWriteBerr();
5714	}
5715	break;
5716
5717	case RSP_INS_CLEANUP:
5718	case RSP_DATA_CLEANUP:
5719	if ( r_vci_rsp_fsm == RSP_INS_CLEANUP )
5720	{
5721	m_cost_icleanup_transaction++;
5722	}
5723	else
5724	{
5725	m_cost_dcleanup_transaction++;
5726	}
5727
5728	if ( ! p_vci_ini_c.rspval.read() )
5729	break;
5730	assert( p_vci_ini_c.reop.read() &&
5731	"illegal VCI response packet for icache cleanup");
5732	assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&
5733	"error in response packet for icache cleanup");
5734
5735	if ( r_vci_rsp_fsm == RSP_INS_CLEANUP )
5736	{
5737	r_icache_cleanup_req = false;
5738	}
5739	else
5740	{
5741	r_dcache_cleanup_req = false;
5742	}
5743	r_vci_rsp_fsm = RSP_IDLE;
5744	break;
5745
5746	} // end switch r_vci_rsp_fsm
5747	} // end transition()
5748
5749	///////////////////////
5750	tmpl(void)::genMoore()
5751	///////////////////////
5752	{
5753	// VCI initiator response
5754
5755	p_vci_ini_rw.rspack = true;
5756	p_vci_ini_c.rspack = true;
5757
5758	// VCI initiator command
5759
5760	p_vci_ini_rw.pktid = 0;
5761	p_vci_ini_rw.srcid = m_srcid_rw;
5762	p_vci_ini_rw.cons = false;
5763	p_vci_ini_rw.wrap = false;
5764	p_vci_ini_rw.contig = true;
5765	p_vci_ini_rw.clen = 0;
5766	p_vci_ini_rw.cfixed = false;
5767
5768	p_vci_ini_c.cmdval = false;
5769	p_vci_ini_c.address = 0;
5770	p_vci_ini_c.wdata = 0;
5771	p_vci_ini_c.be = 0;
5772	p_vci_ini_c.plen = 0;
5773	p_vci_ini_c.cmd = vci_param::CMD_NOP;
5774	p_vci_ini_c.trdid = 0;
5775	p_vci_ini_c.pktid = 0;
5776	p_vci_ini_c.srcid = 0;
5777	p_vci_ini_c.cons = false;
5778	p_vci_ini_c.wrap = false;
5779	p_vci_ini_c.contig = false;
5780	p_vci_ini_c.clen = 0;
5781	p_vci_ini_c.cfixed = false;
5782	p_vci_ini_c.eop = false;
5783
5784	switch (r_vci_cmd_fsm) {
5785
5786	case CMD_IDLE:
5787	p_vci_ini_rw.cmdval = false;
5788	p_vci_ini_rw.address = 0;
5789	p_vci_ini_rw.wdata = 0;
5790	p_vci_ini_rw.be = 0;
5791	p_vci_ini_rw.trdid = 0;
5792	p_vci_ini_rw.plen = 0;
5793	p_vci_ini_rw.cmd = vci_param::CMD_NOP;
5794	p_vci_ini_rw.eop = false;
5795	break;
5796
5797	case CMD_ITLB_READ:
5798	p_vci_ini_rw.cmdval = true;
5799	p_vci_ini_rw.address = r_icache_paddr_save.read() & m_dcache_yzmask;
5800	p_vci_ini_rw.wdata = 0;
5801	p_vci_ini_rw.be = 0xF;
5802	p_vci_ini_rw.trdid = 1; // via data cache cached read
5803	p_vci_ini_rw.plen = m_dcache_words << 2;
5804	p_vci_ini_rw.cmd = vci_param::CMD_READ;
5805	p_vci_ini_rw.eop = true;
5806	break;
5807
5808	case CMD_ITLB_ACC_LL:
5809	p_vci_ini_rw.cmdval = true;
5810	p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
5811	p_vci_ini_rw.wdata = 0;
5812	p_vci_ini_rw.be = 0xF;
5813	p_vci_ini_rw.trdid = 0; // data cache uncached read
5814	p_vci_ini_rw.plen = 4;
5815	p_vci_ini_rw.cmd = vci_param::CMD_LOCKED_READ;
5816	p_vci_ini_rw.eop = true;
5817	break;
5818
5819	case CMD_ITLB_ACC_SC:
5820	p_vci_ini_rw.cmdval = true;
5821	p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
5822	p_vci_ini_rw.wdata = r_icache_pte_update.read();
5823	p_vci_ini_rw.be = 0xF;
5824	p_vci_ini_rw.trdid = 0; // data cache uncached read
5825	p_vci_ini_rw.plen = 4;
5826	p_vci_ini_rw.cmd = vci_param::CMD_STORE_COND;
5827	p_vci_ini_rw.eop = true;
5828	break;
5829
5830	case CMD_INS_MISS:
5831	p_vci_ini_rw.cmdval = true;
5832	p_vci_ini_rw.address = r_icache_paddr_save.read() & m_icache_yzmask;
5833	p_vci_ini_rw.wdata = 0;
5834	p_vci_ini_rw.be = 0xF;
5835	p_vci_ini_rw.trdid = 3; // ins cache cached read
5836	p_vci_ini_rw.plen = m_icache_words << 2;
5837	p_vci_ini_rw.cmd = vci_param::CMD_READ;
5838	p_vci_ini_rw.eop = true;
5839	break;
5840
5841	case CMD_INS_UNC:
5842	p_vci_ini_rw.cmdval = true;
5843	p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
5844	p_vci_ini_rw.wdata = 0;
5845	p_vci_ini_rw.be = 0xF;
5846	p_vci_ini_rw.trdid = 2; // ins cache uncached read
5847	p_vci_ini_rw.plen = 4;
5848	p_vci_ini_rw.cmd = vci_param::CMD_READ;
5849	p_vci_ini_rw.eop = true;
5850	break;
5851
5852	case CMD_DTLB_READ:
5853	p_vci_ini_rw.cmdval = true;
5854	p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & m_dcache_yzmask;
5855	p_vci_ini_rw.wdata = 0;
5856	p_vci_ini_rw.be = 0xF;
5857	p_vci_ini_rw.trdid = 1; // via dcache cached read
5858	p_vci_ini_rw.plen = m_dcache_words << 2;
5859	p_vci_ini_rw.cmd = vci_param::CMD_READ;
5860	p_vci_ini_rw.eop = true;
5861	break;
5862
5863	case CMD_DTLB_ACC_LL:
5864	p_vci_ini_rw.cmdval = true;
5865	p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
5866	p_vci_ini_rw.wdata = 0;
5867	p_vci_ini_rw.be = 0xF;
5868	p_vci_ini_rw.trdid = 0; // data cache uncached read
5869	p_vci_ini_rw.plen = 4;
5870	p_vci_ini_rw.cmd = vci_param::CMD_LOCKED_READ;
5871	p_vci_ini_rw.eop = true;
5872	break;
5873
5874	case CMD_DTLB_ACC_SC:
5875	p_vci_ini_rw.cmdval = true;
5876	p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
5877	p_vci_ini_rw.wdata = r_dcache_pte_update.read();
5878	p_vci_ini_rw.be = 0xF;
5879	p_vci_ini_rw.trdid = 0; // data cache uncached read
5880	p_vci_ini_rw.plen = 4;
5881	p_vci_ini_rw.cmd = vci_param::CMD_STORE_COND;
5882	p_vci_ini_rw.eop = true;
5883	break;
5884
5885	case CMD_DTLB_DIRTY_LL:
5886	p_vci_ini_rw.cmdval = true;
5887	p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
5888	p_vci_ini_rw.wdata = 0;
5889	p_vci_ini_rw.be = 0xF;
5890	p_vci_ini_rw.trdid = 0; // data cache uncached read
5891	p_vci_ini_rw.plen = 4;
5892	p_vci_ini_rw.cmd = vci_param::CMD_LOCKED_READ;
5893	p_vci_ini_rw.eop = true;
5894	break;
5895
5896	case CMD_DTLB_DIRTY_SC:
5897	p_vci_ini_rw.cmdval = true;
5898	p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
5899	p_vci_ini_rw.wdata = r_dcache_pte_update.read();
5900	p_vci_ini_rw.be = 0xF;
5901	p_vci_ini_rw.trdid = 0; // data cache uncached read
5902	p_vci_ini_rw.plen = 4;
5903	p_vci_ini_rw.cmd = vci_param::CMD_STORE_COND;
5904	p_vci_ini_rw.eop = true;
5905	break;
5906
5907	case CMD_DATA_UNC:
5908	p_vci_ini_rw.cmdval = true;
5909	p_vci_ini_rw.address = r_dcache_paddr_save.read() & ~0x3;
5910	p_vci_ini_rw.trdid = 0; // data cache uncached read
5911	p_vci_ini_rw.plen = 4;
5912	p_vci_ini_rw.eop = true;
5913	switch(r_dcache_type_save) {
5914	case iss_t::DATA_READ:
5915	p_vci_ini_rw.wdata = 0;
5916	p_vci_ini_rw.be = r_dcache_be_save.read();
5917	p_vci_ini_rw.cmd = vci_param::CMD_READ;
5918	break;
5919	case iss_t::DATA_LL:
5920	p_vci_ini_rw.wdata = 0;
5921	p_vci_ini_rw.be = 0xF;
5922	p_vci_ini_rw.cmd = vci_param::CMD_LOCKED_READ;
5923	break;
5924	case iss_t::DATA_SC:
5925	p_vci_ini_rw.wdata = r_dcache_wdata_save.read();
5926	p_vci_ini_rw.be = 0xF;
5927	p_vci_ini_rw.cmd = vci_param::CMD_STORE_COND;
5928	break;
5929	default:
5930	assert("this should not happen");
5931	}
5932	break;
5933
5934	case CMD_DATA_WRITE:
5935	p_vci_ini_rw.cmdval = true;
5936	p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt);
5937	p_vci_ini_rw.wdata = r_wbuf.getData(r_vci_cmd_cpt);
5938	p_vci_ini_rw.be = r_wbuf.getBe(r_vci_cmd_cpt);
5939	p_vci_ini_rw.trdid = 0; // data cache write
5940	p_vci_ini_rw.plen = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
5941	p_vci_ini_rw.cmd = vci_param::CMD_WRITE;
5942	p_vci_ini_rw.eop = (r_vci_cmd_cpt == r_vci_cmd_max);
5943	break;
5944
5945	case CMD_DATA_MISS:
5946	p_vci_ini_rw.cmdval = true;
5947	p_vci_ini_rw.address = r_dcache_paddr_save.read() & m_dcache_yzmask;
5948	p_vci_ini_rw.wdata = 0;
5949	p_vci_ini_rw.be = 0xF;
5950	p_vci_ini_rw.trdid = 1; // data cache cached read
5951	p_vci_ini_rw.plen = m_dcache_words << 2;
5952	p_vci_ini_rw.cmd = vci_param::CMD_READ;
5953	p_vci_ini_rw.eop = true;
5954	break;
5955
5956	case CMD_INS_CLEANUP:
5957	case CMD_DATA_CLEANUP:
5958	p_vci_ini_rw.cmdval = false;
5959	p_vci_ini_rw.address = 0;
5960	p_vci_ini_rw.wdata = 0;
5961	p_vci_ini_rw.be = 0;
5962	p_vci_ini_rw.trdid = 0;
5963	p_vci_ini_rw.plen = 0;
5964	p_vci_ini_rw.cmd = vci_param::CMD_NOP;
5965	p_vci_ini_rw.eop = false;
5966
5967	p_vci_ini_c.cmdval = true;
5968	if ( r_vci_cmd_fsm == CMD_INS_CLEANUP )
5969	{
5970	p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2);
5971	p_vci_ini_c.trdid = 1; // cleanup instruction
5972	}
5973	else
5974	{
5975	p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
5976	p_vci_ini_c.trdid = 0; // cleanup data
5977	}
5978	p_vci_ini_c.wdata = 0;
5979	p_vci_ini_c.be = 0;
5980	p_vci_ini_c.plen = 4;
5981	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
5982	p_vci_ini_c.pktid = 0;
5983	p_vci_ini_c.srcid = m_srcid_c;
5984	p_vci_ini_c.cons = false;
5985	p_vci_ini_c.wrap = false;
5986	p_vci_ini_c.contig = false;
5987	p_vci_ini_c.clen = 0;
5988	p_vci_ini_c.cfixed = false;
5989	p_vci_ini_c.eop = true;
5990	break;
5991
5992	} // end switch r_vci_cmd_fsm
5993
5994	// VCI_TGT
5995	switch ( r_vci_tgt_fsm.read() ) {
5996
5997	case TGT_IDLE:
5998	case TGT_UPDT_WORD:
5999	case TGT_UPDT_DATA:
6000	p_vci_tgt.cmdack = true;
6001	p_vci_tgt.rspval = false;
6002	break;
6003
6004	case TGT_RSP_BROADCAST:
6005	p_vci_tgt.cmdack = false;
6006	p_vci_tgt.rspval = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && ( r_tgt_icache_rsp \| r_tgt_dcache_rsp );
6007	p_vci_tgt.rsrcid = r_tgt_srcid.read();
6008	p_vci_tgt.rpktid = r_tgt_pktid.read();
6009	p_vci_tgt.rtrdid = r_tgt_trdid.read();
6010	p_vci_tgt.rdata = 0;
6011	p_vci_tgt.rerror = 0;
6012	p_vci_tgt.reop = true;
6013	break;
6014
6015	case TGT_RSP_ICACHE:
6016	p_vci_tgt.cmdack = false;
6017	p_vci_tgt.rspval = !r_tgt_icache_req.read() && r_tgt_icache_rsp.read();
6018	p_vci_tgt.rsrcid = r_tgt_srcid.read();
6019	p_vci_tgt.rpktid = r_tgt_pktid.read();
6020	p_vci_tgt.rtrdid = r_tgt_trdid.read();
6021	p_vci_tgt.rdata = 0;
6022	p_vci_tgt.rerror = 0;
6023	p_vci_tgt.reop = true;
6024	break;
6025
6026	case TGT_RSP_DCACHE:
6027	p_vci_tgt.cmdack = false;
6028	p_vci_tgt.rspval = !r_tgt_dcache_req.read() && r_tgt_dcache_rsp.read();
6029	p_vci_tgt.rsrcid = r_tgt_srcid.read();
6030	p_vci_tgt.rpktid = r_tgt_pktid.read();
6031	p_vci_tgt.rtrdid = r_tgt_trdid.read();
6032	p_vci_tgt.rdata = 0;
6033	p_vci_tgt.rerror = 0;
6034	p_vci_tgt.reop = true;
6035	break;
6036
6037	case TGT_REQ_BROADCAST:
6038	case TGT_REQ_ICACHE:
6039	case TGT_REQ_DCACHE:
6040	p_vci_tgt.cmdack = false;
6041	p_vci_tgt.rspval = false;
6042	break;
6043
6044	} // end switch TGT_FSM
6045
6046	#ifdef SOCLIB_MODULE_DEBUG
6047	std::cout << name()
6048	<< " Moore R/W:" << std::hex
6049	<< " p_vci_ini_rw.cmdval: " << p_vci_ini_rw.cmdval
6050	<< " p_vci_ini_rw.address: " << p_vci_ini_rw.address
6051	<< " p_vci_ini_rw.wdata: " << p_vci_ini_rw.wdata
6052	<< " p_vci_ini_rw.cmd: " << p_vci_ini_rw.cmd
6053	<< " p_vci_ini_rw.eop: " << p_vci_ini_rw.eop
6054	<< std::endl;
6055
6056	std::cout << name()
6057	<< " Moore TGT:" << std::hex
6058	<< " p_vci_tgt.rspval: " << p_vci_tgt.rspval
6059	<< std::endl;
6060
6061	std::cout << name()
6062	<< " Moore Cleanup:" << std::hex
6063	<< " p_vci_ini_c.cmdval: " << p_vci_ini_c.cmdval
6064	<< " p_vci_ini_c.address: " << p_vci_ini_c.address
6065	<< " p_vci_ini_c.trdid: " << p_vci_ini_c.trdid
6066	<< " p_vci_ini_c.cmd: " << p_vci_ini_c.cmd
6067	<< " p_vci_ini_c.eop: " << p_vci_ini_c.eop
6068	<< std::endl;
6069	#endif
6070	}
6071
6072	}}
6073
6074	// Local Variables:
6075	// tab-width: 4
6076	// c-basic-offset: 4
6077	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6078	// indent-tabs-mode: nil
6079	// End:
6080
6081	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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