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source: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp @ 194

Last change on this file since 194 was 194, checked in by almaless, 12 years ago
bug-fix
File size: 185.0 KB

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1	/* -- c++ --C
2	* File : vci_cc_vcache_wrapper_v4.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#include <cassert>
28	#include "arithmetics.h"
29	#include "../include/vci_cc_vcache_wrapper_v4.h"
30
31	#define DEBUG_DCACHE 1
32	#define DEBUG_ICACHE 1
33	#define DEBUG_CLEANUP 0
34	#define DEBUG_INVAL_ITLB 1
35	#define DEBUG_INVAL_DTLB 1
36
37	namespace soclib {
38	namespace caba {
39
40	namespace {
41	const char *icache_fsm_state_str[] = {
42	"ICACHE_IDLE",
43
44	"ICACHE_XTN_TLB_FLUSH",
45	"ICACHE_XTN_CACHE_FLUSH",
46	"ICACHE_XTN_TLB_INVAL",
47	"ICACHE_XTN_CACHE_INVAL_VA",
48	"ICACHE_XTN_CACHE_INVAL_PA",
49	"ICACHE_XTN_CACHE_INVAL_GO",
50
51	"ICACHE_TLB_WAIT",
52
53	"ICACHE_MISS_VICTIM",
54	"ICACHE_MISS_INVAL",
55	"ICACHE_MISS_WAIT",
56	"ICACHE_MISS_UPDT",
57
58	"ICACHE_UNC_WAIT",
59
60	"ICACHE_CC_CHECK",
61	"ICACHE_CC_INVAL",
62	"ICACHE_CC_UPDT",
63
64	};
65	const char *dcache_fsm_state_str[] = {
66	"DCACHE_IDLE",
67
68	"DCACHE_TLB_MISS",
69	"DCACHE_TLB_PTE1_GET",
70	"DCACHE_TLB_PTE1_SELECT",
71	"DCACHE_TLB_PTE1_UPDT",
72	"DCACHE_TLB_PTE2_GET",
73	"DCACHE_TLB_PTE2_SELECT",
74	"DCACHE_TLB_PTE2_UPDT",
75	"DCACHE_TLB_SC_UPDT",
76	"DCACHE_TLB_SC_WAIT",
77	"DCACHE_TLB_RETURN",
78
79	"DCACHE_XTN_SWITCH",
80	"DCACHE_XTN_SYNC",
81	"DCACHE_XTN_IC_INVAL_VA",
82	"DCACHE_XTN_IC_FLUSH",
83	"DCACHE_XTN_IC_INVAL_PA",
84	"DCACHE_XTN_IT_INVAL",
85	"DCACHE_XTN_DC_FLUSH",
86	"DCACHE_XTN_DC_INVAL_VA",
87	"DCACHE_XTN_DC_INVAL_PA",
88	"DCACHE_XTN_DC_INVAL_WAIT",
89	"DCACHE_XTN_DC_INVAL_GO",
90	"DCACHE_XTN_DT_INVAL",
91
92	"DCACHE_WRITE_TLB_DIRTY",
93	"DCACHE_WRITE_CACHE_DIRTY",
94	"DCACHE_WRITE_SC_WAIT",
95	"DCACHE_WRITE_UNC_WAIT",
96
97	"DCACHE_MISS_VICTIM",
98	"DCACHE_MISS_INVAL",
99	"DCACHE_MISS_INVAL_WAIT",
100	"DCACHE_MISS_WAIT",
101	"DCACHE_MISS_UPDT",
102
103	"DCACHE_UNC_WAIT",
104
105	"DCACHE_CC_CHECK",
106	"DCACHE_CC_INVAL",
107	"DCACHE_CC_UPDT",
108	"DCACHE_CC_WAIT",
109	};
110	const char *cmd_fsm_state_str[] = {
111	"CMD_IDLE",
112	"CMD_INS_MISS",
113	"CMD_INS_UNC",
114	"CMD_DATA_MISS",
115	"CMD_DATA_UNC",
116	"CMD_DATA_WRITE",
117	"CMD_DATA_SC",
118	};
119	const char *rsp_fsm_state_str[] = {
120	"RSP_IDLE",
121	"RSP_INS_MISS",
122	"RSP_INS_UNC",
123	"RSP_DATA_MISS",
124	"RSP_DATA_UNC",
125	"RSP_DATA_WRITE",
126	};
127	const char *cleanup_fsm_state_str[] = {
128	"CLEANUP_DATA_IDLE",
129	"CLEANUP_DATA_GO",
130	"CLEANUP_INS_IDLE",
131	"CLEANUP_INS_GO",
132	};
133	const char *tgt_fsm_state_str[] = {
134	"TGT_IDLE",
135	"TGT_UPDT_WORD",
136	"TGT_UPDT_DATA",
137	"TGT_REQ_BROADCAST",
138	"TGT_REQ_ICACHE",
139	"TGT_REQ_DCACHE",
140	"TGT_RSP_BROADCAST",
141	"TGT_RSP_ICACHE",
142	"TGT_RSP_DCACHE",
143	};
144	const char *inval_itlb_fsm_state_str[] = {
145	"INVAL_ITLB_IDLE",
146	"INVAL_ITLB_SCAN",
147	};
148	const char *inval_dtlb_fsm_state_str[] = {
149	"INVAL_DTLB_IDLE",
150	"INVAL_DTLB_SCAN",
151	};
152	}
153
154	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t>
155
156	using soclib::common::uint32_log2;
157
158	/////////////////////////////////
159	tmpl(/**/)::VciCcVCacheWrapperV4(
160	sc_module_name name,
161	int proc_id,
162	const soclib::common::MappingTable &mtp,
163	const soclib::common::MappingTable &mtc,
164	const soclib::common::IntTab &initiator_index_d,
165	const soclib::common::IntTab &initiator_index_c,
166	const soclib::common::IntTab &target_index_d,
167	size_t itlb_ways,
168	size_t itlb_sets,
169	size_t dtlb_ways,
170	size_t dtlb_sets,
171	size_t icache_ways,
172	size_t icache_sets,
173	size_t icache_words,
174	size_t dcache_ways,
175	size_t dcache_sets,
176	size_t dcache_words,
177	size_t wbuf_nlines,
178	size_t wbuf_nwords,
179	uint32_t max_frozen_cycles,
180	uint32_t debug_start_cycle,
181	bool debug_ok)
182	: soclib::caba::BaseModule(name),
183
184	p_clk("clk"),
185	p_resetn("resetn"),
186	p_vci_ini_d("vci_ini_d"),
187	p_vci_ini_c("vci_ini_c"),
188	p_vci_tgt_c("vci_tgt_d"),
189
190	m_cacheability_table(mtp.getCacheabilityTable()),
191	m_segment(mtc.getSegment(target_index_d)),
192	m_srcid_d(mtp.indexForId(initiator_index_d)),
193	m_srcid_c(mtp.indexForId(initiator_index_c)),
194
195	m_itlb_ways(itlb_ways),
196	m_itlb_sets(itlb_sets),
197
198	m_dtlb_ways(dtlb_ways),
199	m_dtlb_sets(dtlb_sets),
200
201	m_icache_ways(icache_ways),
202	m_icache_sets(icache_sets),
203	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
204	m_icache_words(icache_words),
205
206	m_dcache_ways(dcache_ways),
207	m_dcache_sets(dcache_sets),
208	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
209	m_dcache_words(dcache_words),
210
211	m_max_frozen_cycles(max_frozen_cycles),
212
213	m_paddr_nbits(vci_param::N),
214
215	m_debug_start_cycle(debug_start_cycle),
216	m_debug_ok(debug_ok),
217
218	r_mmu_ptpr("r_mmu_ptpr"),
219	r_mmu_mode("r_mmu_mode"),
220	r_mmu_word_lo("r_mmu_word_lo"),
221	r_mmu_word_hi("r_mmu_word_hi"),
222	r_mmu_ibvar("r_mmu_ibvar"),
223	r_mmu_dbvar("r_mmu_dbvar"),
224	r_mmu_ietr("r_mmu_ietr"),
225	r_mmu_detr("r_mmu_detr"),
226
227	r_icache_fsm("r_icache_fsm"),
228	r_icache_fsm_save("r_icache_fsm_save"),
229	r_icache_vci_paddr("r_icache_vci_paddr"),
230	r_icache_vaddr_save("r_icache_vaddr_save"),
231
232	r_icache_miss_way("r_icache_miss_way"),
233	r_icache_miss_set("r_icache_miss_set"),
234	r_icache_miss_word("r_icache_miss_word"),
235	r_icache_miss_inval("r_icache_miss_inval"),
236
237	r_icache_cc_way("r_icache_cc_way"),
238	r_icache_cc_set("r_icache_cc_set"),
239	r_icache_cc_word("r_icache_cc_word"),
240
241	r_icache_flush_count("r_icache_flush_count"),
242
243	r_icache_miss_req("r_icache_miss_req"),
244	r_icache_unc_req("r_icache_unc_req"),
245
246	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
247	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
248
249	r_icache_cleanup_req("r_icache_cleanup_req"),
250	r_icache_cleanup_line("r_icache_cleanup_line"),
251
252	r_dcache_fsm("r_dcache_fsm"),
253	r_dcache_fsm_save("r_dcache_fsm_save"),
254
255	r_dcache_p0_valid("r_dcache_p0_valid"),
256	r_dcache_p0_vaddr("r_dcache_p0_vaddr"),
257	r_dcache_p0_wdata("r_dcache_p0_wdata"),
258	r_dcache_p0_be("r_dcache_p0_be"),
259	r_dcache_p0_paddr("r_dcache_p0_paddr"),
260	r_dcache_p0_cacheable("r_dcache_p0_cacheable"),
261	r_dcache_p0_tlb_way("r_dcache_p0_tlb_way"),
262	r_dcache_p0_tlb_set("r_dcache_p0_tlb_set"),
263	r_dcache_p0_tlb_nline("r_dcache_p0_tlb_nline"),
264	r_dcache_p0_tlb_dirty("r_dcache_p0_tlb_dirty"),
265	r_dcache_p0_tlb_big("r_dcache_p0_tlb_big"),
266
267	r_dcache_p1_valid("r_dcache_p1_valid"),
268	r_dcache_p1_updt_cache("r_dcache_p1_updt_cache"),
269	r_dcache_p1_set_dirty("r_dcache_p1_set_dirty"),
270	r_dcache_p1_vaddr("r_dcache_p1_vaddr"),
271	r_dcache_p1_wdata("r_dcache_p1_wdata"),
272	r_dcache_p1_be("r_dcache_p1_be"),
273	r_dcache_p1_paddr("r_dcache_p1_paddr"),
274	r_dcache_p1_cache_way("r_dcache_p1_cache_way"),
275	r_dcache_p1_cache_set("r_dcache_p1_cache_set"),
276	r_dcache_p1_cache_word("r_dcache_p1_word_save"),
277	r_dcache_p1_tlb_way("r_dcache_p1_tlb_way"),
278	r_dcache_p1_tlb_set("r_dcache_p1_tlb_set"),
279	r_dcache_p1_tlb_nline("r_dcache_p1_tlb_nline"),
280
281	r_dcache_p2_vaddr("r_dcache_p2_vaddr"),
282	r_dcache_p2_tlb_way("r_dcache_p2_tlb_way"),
283	r_dcache_p2_tlb_set("r_dcache_p2_tlb_set"),
284	r_dcache_p2_set_dirty("r_dcache_p2_set_dirty"),
285	r_dcache_p2_pte_paddr("r_dcache_p2_pte_paddr"),
286	r_dcache_p2_pte_way("r_dcache_p2_pte_way"),
287	r_dcache_p2_pte_set("r_dcache_p2_pte_set"),
288	r_dcache_p2_pte_word("r_dcache_p2_pte_word"),
289	r_dcache_p2_pte_flags("r_dcache_p2_pte_flags"),
290
291	r_dcache_vci_paddr("r_dcache_vci_paddr"),
292	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
293	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
294	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
295	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
296	r_dcache_vci_sc_old("r_dcache_vci_sc_old"),
297	r_dcache_vci_sc_new("r_dcache_vci_sc_new"),
298
299	r_dcache_xtn_way("r_dcache_xtn_way"),
300	r_dcache_xtn_set("r_dcache_xtn_set"),
301
302	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
303
304	r_dcache_miss_type("r_dcache_miss_type"),
305	r_dcache_miss_word("r_dcache_miss_word"),
306	r_dcache_miss_way("r_dcache_miss_way"),
307	r_dcache_miss_set("r_dcache_miss_set"),
308	r_dcache_miss_inval("r_dcache_miss_inval"),
309
310	r_dcache_cc_way("r_dcache_cc_way"),
311	r_dcache_cc_set("r_dcache_cc_set"),
312	r_dcache_cc_word("r_dcache_cc_word"),
313
314	r_dcache_flush_count("r_dcache_flush_count"),
315
316	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
317	r_dcache_tlb_ins("r_dcache_tlb_ins"),
318	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
319	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
320	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
321	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
322	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
323	r_dcache_tlb_way("r_dcache_tlb_way"),
324	r_dcache_tlb_set("r_dcache_tlb_set"),
325
326	r_dcache_ll_valid("r_dcache_ll_valid"),
327	r_dcache_ll_data("r_dcache_ll_data"),
328	r_dcache_ll_vaddr("r_dcache_ll_vaddr"),
329
330	r_dcache_itlb_inval_req("r_dcache_itlb_inval_req"),
331	r_dcache_dtlb_inval_req("r_dcache_dtlb_inval_req"),
332	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
333
334	r_dcache_xtn_req("r_dcache_xtn_req"),
335	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
336
337	r_dcache_cleanup_req("r_dcache_cleanup_req"),
338	r_dcache_cleanup_line("r_dcache_cleanup_line"),
339
340	r_vci_cmd_fsm("r_vci_cmd_fsm"),
341	r_vci_cmd_min("r_vci_cmd_min"),
342	r_vci_cmd_max("r_vci_cmd_max"),
343	r_vci_cmd_cpt("r_vci_cmd_cpt"),
344	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
345
346	r_vci_rsp_fsm("r_vci_rsp_fsm"),
347	r_vci_rsp_cpt("r_vci_rsp_cpt"),
348	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
349	r_vci_rsp_data_error("r_vci_rsp_data_error"),
350	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
351	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
352
353	r_cleanup_fsm("r_cleanup_fsm"),
354	r_cleanup_trdid("r_cleanup_trdid"),
355	r_cleanup_buffer(4), // up to 4 simultaneous cleanups
356
357	r_tgt_fsm("r_tgt_fsm"),
358	r_tgt_paddr("r_tgt_paddr"),
359	r_tgt_word_count("r_tgt_word_count"),
360	r_tgt_word_min("r_tgt_word_min"),
361	r_tgt_word_max("r_tgt_word_max"),
362	r_tgt_update("r_tgt_update"),
363	r_tgt_update_data("r_tgt_update_data"),
364	r_tgt_srcid("r_tgt_srcid"),
365	r_tgt_pktid("r_tgt_pktid"),
366	r_tgt_trdid("r_tgt_trdid"),
367
368	r_tgt_icache_req("r_tgt_icache_req"),
369	r_tgt_dcache_req("r_tgt_dcache_req"),
370	r_tgt_icache_rsp("r_tgt_icache_rsp"),
371	r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
372
373	r_inval_itlb_fsm("r_inval_itlb_fsm"),
374	r_inval_itlb_count("r_inval_itlb_count"),
375
376	r_inval_dtlb_fsm("r_inval_dtlb_fsm"),
377	r_inval_dtlb_count("r_inval_dtlb_count"),
378
379	r_iss(this->name(), proc_id),
380	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
381	r_icache("icache", icache_ways, icache_sets, icache_words),
382	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
383	r_itlb(itlb_ways,itlb_sets,vci_param::N),
384	r_dtlb(dtlb_ways,dtlb_sets,vci_param::N)
385	{
386	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
387	"Need more PLEN bits.");
388
389	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
390	"Need more TRDID bits.");
391
392	assert( (icache_words == dcache_words) and
393	"icache_words and dcache_words parameters must be equal");
394
395	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
396	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
397	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
398	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
399	(uint32_log2(m_icache_words<<2));
400
401	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
402
403	r_tgt_buf = new uint32_t[dcache_words];
404	r_tgt_be = new vci_be_t[dcache_words];
405	r_dcache_in_itlb = new bool[dcache_ways*dcache_sets];
406	r_dcache_in_dtlb = new bool[dcache_ways*dcache_sets];
407
408	SC_METHOD(transition);
409	dont_initialize();
410	sensitive << p_clk.pos();
411
412	SC_METHOD(genMoore);
413	dont_initialize();
414	sensitive << p_clk.neg();
415
416	typename iss_t::CacheInfo cache_info;
417	cache_info.has_mmu = true;
418	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
419	cache_info.icache_assoc = icache_ways;
420	cache_info.icache_n_lines = icache_sets;
421	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
422	cache_info.dcache_assoc = dcache_ways;
423	cache_info.dcache_n_lines = dcache_sets;
424	r_iss.setCacheInfo(cache_info);
425	}
426
427	/////////////////////////////////////
428	tmpl(/**/)::~VciCcVCacheWrapperV4()
429	/////////////////////////////////////
430	{
431	delete [] r_tgt_be;
432	delete [] r_tgt_buf;
433	delete [] r_dcache_in_itlb;
434	delete [] r_dcache_in_dtlb;
435	}
436
437	////////////////////////
438	tmpl(void)::print_cpi()
439	////////////////////////
440	{
441	std::cout << name() << " CPI = "
442	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
443	}
444
445	////////////////////////////////////
446	tmpl(void)::print_trace(size_t mode)
447	////////////////////////////////////
448	{
449	// b0 : write buffer print trace
450	// b1 : write buffer verbose
451	// b2 : dcache print trace
452	// b3 : icache print trace
453
454	typename iss_t::InstructionRequest ireq;
455	typename iss_t::InstructionResponse irsp;
456	typename iss_t::DataRequest dreq;
457	typename iss_t::DataResponse drsp;
458
459	ireq.valid = m_ireq_valid;
460	ireq.addr = m_ireq_addr;
461	ireq.mode = m_ireq_mode;
462
463	irsp.valid = m_irsp_valid;
464	irsp.instruction = m_irsp_instruction;
465	irsp.error = m_irsp_error;
466
467	dreq.valid = m_dreq_valid;
468	dreq.addr = m_dreq_addr;
469	dreq.mode = m_dreq_mode;
470	dreq.type = m_dreq_type;
471	dreq.wdata = m_dreq_wdata;
472	dreq.be = m_dreq_be;
473
474	drsp.valid = m_drsp_valid;
475	drsp.rdata = m_drsp_rdata;
476	drsp.error = m_drsp_error;
477
478	std::cout << std::dec << "PROC " << name() << std::endl;
479
480	std::cout << " " << ireq << std::endl;
481	std::cout << " " << irsp << std::endl;
482	std::cout << " " << dreq << std::endl;
483	std::cout << " " << drsp << std::endl;
484
485	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
486	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
487	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
488	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
489	<< " \| " << tgt_fsm_state_str[r_tgt_fsm.read()] << std::endl;
490	std::cout << " " << cleanup_fsm_state_str[r_cleanup_fsm.read()]
491	<< " \| " << inval_itlb_fsm_state_str[r_inval_itlb_fsm]
492	<< " \| " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm];
493	if (r_dcache_p0_valid.read() ) std::cout << " \| P1_WRITE";
494	if (r_dcache_p1_valid.read() ) std::cout << " \| P2_WRITE";
495	std::cout << std::endl;
496
497	if(mode & 0x1)
498	{
499	r_wbuf.printTrace((mode>>1)&1);
500	}
501	if(mode & 0x4)
502	{
503	std::cout << " Data cache" << std::endl;
504	r_dcache.printTrace();
505	}
506	if(mode & 0x8)
507	{
508	std::cout << " Instruction cache" << std::endl;
509	r_icache.printTrace();
510	}
511	}
512
513	//////////////////////////////////////////
514	tmpl(void)::cache_monitor( paddr_t addr )
515	//////////////////////////////////////////
516	{
517	size_t cache_way;
518	size_t cache_set;
519	size_t cache_word;
520	uint32_t cache_rdata;
521	bool cache_hit = r_dcache.read( addr,
522	&cache_rdata,
523	&cache_way,
524	&cache_set,
525	&cache_word );
526	if ( cache_hit != m_debug_previous_hit )
527	{
528	std::cout << "PROC " << name()
529	<< " cache change at cycle " << std::dec << m_cpt_total_cycles
530	<< " for adresse " << std::hex << addr
531	<< " / HIT = " << cache_hit << std::endl;
532	}
533	m_debug_previous_hit = cache_hit;
534	}
535
536
537
538	/*
539	////////////////////////
540	tmpl(void)::print_stats()
541	////////////////////////
542	{
543	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
544	std::cout << name() << std::endl
545	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
546	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
547	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
548	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
549	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
550	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
551	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
552	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
553	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
554	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
555	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
556	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
557	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
558	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
559	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
560	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
561	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
562	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
563	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
564	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
565	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
566	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
567	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
568	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
569	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
570	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
571	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
572	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
573	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
574	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
575	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
576	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
577	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
578	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
579	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
580	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
581	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
582	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
583	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
584	}
585
586	////////////////////////
587	tmpl(void)::clear_stats()
588	////////////////////////
589	{
590	m_cpt_dcache_data_read = 0;
591	m_cpt_dcache_data_write = 0;
592	m_cpt_dcache_dir_read = 0;
593	m_cpt_dcache_dir_write = 0;
594	m_cpt_icache_data_read = 0;
595	m_cpt_icache_data_write = 0;
596	m_cpt_icache_dir_read = 0;
597	m_cpt_icache_dir_write = 0;
598
599	m_cpt_frz_cycles = 0;
600	m_cpt_dcache_frz_cycles = 0;
601	m_cpt_total_cycles = 0;
602
603	m_cpt_read = 0;
604	m_cpt_write = 0;
605	m_cpt_data_miss = 0;
606	m_cpt_ins_miss = 0;
607	m_cpt_unc_read = 0;
608	m_cpt_write_cached = 0;
609	m_cpt_ins_read = 0;
610
611	m_cost_write_frz = 0;
612	m_cost_data_miss_frz = 0;
613	m_cost_unc_read_frz = 0;
614	m_cost_ins_miss_frz = 0;
615
616	m_cpt_imiss_transaction = 0;
617	m_cpt_dmiss_transaction = 0;
618	m_cpt_unc_transaction = 0;
619	m_cpt_write_transaction = 0;
620	m_cpt_icache_unc_transaction = 0;
621
622	m_cost_imiss_transaction = 0;
623	m_cost_dmiss_transaction = 0;
624	m_cost_unc_transaction = 0;
625	m_cost_write_transaction = 0;
626	m_cost_icache_unc_transaction = 0;
627	m_length_write_transaction = 0;
628
629	m_cpt_ins_tlb_read = 0;
630	m_cpt_ins_tlb_miss = 0;
631	m_cpt_ins_tlb_update_acc = 0;
632
633	m_cpt_data_tlb_read = 0;
634	m_cpt_data_tlb_miss = 0;
635	m_cpt_data_tlb_update_acc = 0;
636	m_cpt_data_tlb_update_dirty = 0;
637	m_cpt_ins_tlb_hit_dcache = 0;
638	m_cpt_data_tlb_hit_dcache = 0;
639	m_cpt_ins_tlb_occup_cache = 0;
640	m_cpt_data_tlb_occup_cache = 0;
641
642	m_cost_ins_tlb_miss_frz = 0;
643	m_cost_data_tlb_miss_frz = 0;
644	m_cost_ins_tlb_update_acc_frz = 0;
645	m_cost_data_tlb_update_acc_frz = 0;
646	m_cost_data_tlb_update_dirty_frz = 0;
647	m_cost_ins_tlb_occup_cache_frz = 0;
648	m_cost_data_tlb_occup_cache_frz = 0;
649
650	m_cpt_itlbmiss_transaction = 0;
651	m_cpt_itlb_ll_transaction = 0;
652	m_cpt_itlb_sc_transaction = 0;
653	m_cpt_dtlbmiss_transaction = 0;
654	m_cpt_dtlb_ll_transaction = 0;
655	m_cpt_dtlb_sc_transaction = 0;
656	m_cpt_dtlb_ll_dirty_transaction = 0;
657	m_cpt_dtlb_sc_dirty_transaction = 0;
658
659	m_cost_itlbmiss_transaction = 0;
660	m_cost_itlb_ll_transaction = 0;
661	m_cost_itlb_sc_transaction = 0;
662	m_cost_dtlbmiss_transaction = 0;
663	m_cost_dtlb_ll_transaction = 0;
664	m_cost_dtlb_sc_transaction = 0;
665	m_cost_dtlb_ll_dirty_transaction = 0;
666	m_cost_dtlb_sc_dirty_transaction = 0;
667
668	m_cpt_cc_update_data = 0;
669	m_cpt_cc_inval_ins = 0;
670	m_cpt_cc_inval_data = 0;
671	m_cpt_cc_broadcast = 0;
672
673	m_cost_updt_data_frz = 0;
674	m_cost_inval_ins_frz = 0;
675	m_cost_inval_data_frz = 0;
676	m_cost_broadcast_frz = 0;
677
678	m_cpt_cc_cleanup_data = 0;
679	m_cpt_cc_cleanup_ins = 0;
680	}
681
682	*/
683
684	/////////////////////////
685	tmpl(void)::transition()
686	/////////////////////////
687	{
688	if ( not p_resetn.read() )
689	{
690	r_iss.reset();
691	r_wbuf.reset();
692	r_icache.reset();
693	r_dcache.reset();
694	r_itlb.reset();
695	r_dtlb.reset();
696
697	r_dcache_fsm = DCACHE_IDLE;
698	r_icache_fsm = ICACHE_IDLE;
699	r_vci_cmd_fsm = CMD_IDLE;
700	r_vci_rsp_fsm = RSP_IDLE;
701	r_tgt_fsm = TGT_IDLE;
702	r_inval_itlb_fsm = INVAL_ITLB_IDLE;
703	r_inval_dtlb_fsm = INVAL_DTLB_IDLE;
704	r_cleanup_fsm = CLEANUP_DATA_IDLE;
705
706	std::memset(r_dcache_in_itlb, 0, sizeof(r_dcache_in_itlb)m_icache_ways*m_icache_sets);
707	std::memset(r_dcache_in_dtlb, 0, sizeof(r_dcache_in_dtlb)m_dcache_ways*m_dcache_sets);
708
709
710	// Response FIFOs and cleanup buffer
711	r_vci_rsp_fifo_icache.init();
712	r_vci_rsp_fifo_dcache.init();
713	r_cleanup_buffer.reset();
714
715	// ICACHE & DCACHE activated
716	r_mmu_mode = 0x3;
717
718	// No request from ICACHE FSM to CMD FSM
719	r_icache_miss_req = false;
720	r_icache_unc_req = false;
721
722	// No request from ICACHE_FSM to DCACHE FSM
723	r_icache_tlb_miss_req = false;
724
725	// No request from ICACHE_FSM to CLEANUP FSMs
726	r_icache_cleanup_req = false;
727
728	// No pending write in pipeline
729	r_dcache_p0_valid = false;
730	r_dcache_p1_valid = false;
731
732	// No request from DCACHE_FSM to CMD_FSM
733	r_dcache_vci_miss_req = false;
734	r_dcache_vci_unc_req = false;
735	r_dcache_vci_sc_req = false;
736
737	// No uncacheable write pending
738	r_dcache_pending_unc_write = false;
739
740	// No LL reservation
741	r_dcache_ll_valid = false;
742
743	// No request from DCACHE FSM to INVAL TLB FSMs
744	r_dcache_itlb_inval_req = false;
745	r_dcache_dtlb_inval_req = false;
746
747	// No processor XTN request pending
748	r_dcache_xtn_req = false;
749
750	// No request from DCACHE FSM to CLEANUP FSMs
751	r_dcache_cleanup_req = false;
752
753	// No request from TGT FSM to ICACHE/DCACHE FSMs
754	r_tgt_icache_req = false;
755	r_tgt_dcache_req = false;
756
757	// No signalisation of a coherence request matching a pending miss
758	r_icache_miss_inval = false;
759	r_dcache_miss_inval = false;
760
761	// No signalisation of errors
762	r_vci_rsp_ins_error = false;
763	r_vci_rsp_data_error = false;
764
765	// Debug variables
766	m_debug_previous_hit = false;
767	m_debug_dcache_fsm = false;
768	m_debug_icache_fsm = false;
769	m_debug_cleanup_fsm = false;
770	m_debug_inval_itlb_fsm = false;
771	m_debug_inval_dtlb_fsm = false;
772
773	/*
774	// activity counters
775	m_cpt_dcache_data_read = 0;
776	m_cpt_dcache_data_write = 0;
777	m_cpt_dcache_dir_read = 0;
778	m_cpt_dcache_dir_write = 0;
779	m_cpt_icache_data_read = 0;
780	m_cpt_icache_data_write = 0;
781	m_cpt_icache_dir_read = 0;
782	m_cpt_icache_dir_write = 0;
783
784	m_cpt_frz_cycles = 0;
785	m_cpt_dcache_frz_cycles = 0;
786	m_cpt_total_cycles = 0;
787
788	m_cpt_read = 0;
789	m_cpt_write = 0;
790	m_cpt_data_miss = 0;
791	m_cpt_ins_miss = 0;
792	m_cpt_unc_read = 0;
793	m_cpt_write_cached = 0;
794	m_cpt_ins_read = 0;
795
796	m_cost_write_frz = 0;
797	m_cost_data_miss_frz = 0;
798	m_cost_unc_read_frz = 0;
799	m_cost_ins_miss_frz = 0;
800
801	m_cpt_imiss_transaction = 0;
802	m_cpt_dmiss_transaction = 0;
803	m_cpt_unc_transaction = 0;
804	m_cpt_write_transaction = 0;
805	m_cpt_icache_unc_transaction = 0;
806
807	m_cost_imiss_transaction = 0;
808	m_cost_dmiss_transaction = 0;
809	m_cost_unc_transaction = 0;
810	m_cost_write_transaction = 0;
811	m_cost_icache_unc_transaction = 0;
812	m_length_write_transaction = 0;
813
814	m_cpt_ins_tlb_read = 0;
815	m_cpt_ins_tlb_miss = 0;
816	m_cpt_ins_tlb_update_acc = 0;
817
818	m_cpt_data_tlb_read = 0;
819	m_cpt_data_tlb_miss = 0;
820	m_cpt_data_tlb_update_acc = 0;
821	m_cpt_data_tlb_update_dirty = 0;
822	m_cpt_ins_tlb_hit_dcache = 0;
823	m_cpt_data_tlb_hit_dcache = 0;
824	m_cpt_ins_tlb_occup_cache = 0;
825	m_cpt_data_tlb_occup_cache = 0;
826
827	m_cost_ins_tlb_miss_frz = 0;
828	m_cost_data_tlb_miss_frz = 0;
829	m_cost_ins_tlb_update_acc_frz = 0;
830	m_cost_data_tlb_update_acc_frz = 0;
831	m_cost_data_tlb_update_dirty_frz = 0;
832	m_cost_ins_tlb_occup_cache_frz = 0;
833	m_cost_data_tlb_occup_cache_frz = 0;
834
835	m_cpt_ins_tlb_inval = 0;
836	m_cpt_data_tlb_inval = 0;
837	m_cost_ins_tlb_inval_frz = 0;
838	m_cost_data_tlb_inval_frz = 0;
839
840	m_cpt_cc_update_data = 0;
841	m_cpt_cc_inval_ins = 0;
842	m_cpt_cc_inval_data = 0;
843	m_cpt_cc_broadcast = 0;
844
845	m_cost_updt_data_frz = 0;
846	m_cost_inval_ins_frz = 0;
847	m_cost_inval_data_frz = 0;
848	m_cost_broadcast_frz = 0;
849
850	m_cpt_cc_cleanup_data = 0;
851	m_cpt_cc_cleanup_ins = 0;
852
853	m_cpt_itlbmiss_transaction = 0;
854	m_cpt_itlb_ll_transaction = 0;
855	m_cpt_itlb_sc_transaction = 0;
856	m_cpt_dtlbmiss_transaction = 0;
857	m_cpt_dtlb_ll_transaction = 0;
858	m_cpt_dtlb_sc_transaction = 0;
859	m_cpt_dtlb_ll_dirty_transaction = 0;
860	m_cpt_dtlb_sc_dirty_transaction = 0;
861
862	m_cost_itlbmiss_transaction = 0;
863	m_cost_itlb_ll_transaction = 0;
864	m_cost_itlb_sc_transaction = 0;
865	m_cost_dtlbmiss_transaction = 0;
866	m_cost_dtlb_ll_transaction = 0;
867	m_cost_dtlb_sc_transaction = 0;
868	m_cost_dtlb_ll_dirty_transaction = 0;
869	m_cost_dtlb_sc_dirty_transaction = 0;
870
871	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
872	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
873	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
874	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
875	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0;
876	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0;
877	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0;
878
879	*/
880	return;
881	}
882
883	// Response FIFOs default values
884	bool vci_rsp_fifo_icache_get = false;
885	bool vci_rsp_fifo_icache_put = false;
886	uint32_t vci_rsp_fifo_icache_data = 0;
887
888	bool vci_rsp_fifo_dcache_get = false;
889	bool vci_rsp_fifo_dcache_put = false;
890	uint32_t vci_rsp_fifo_dcache_data = 0;
891
892	#ifdef INSTRUMENTATION
893	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
894	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
895	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
896	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
897	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
898	m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++;
899	#endif
900
901	m_cpt_total_cycles++;
902
903	m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
904	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
905	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
906	m_debug_inval_itlb_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
907	m_debug_inval_dtlb_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
908
909	/////////////////////////////////////////////////////////////////////
910	// The TGT_FSM controls the following ressources:
911	// - r_tgt_fsm
912	// - r_tgt_buf[nwords]
913	// - r_tgt_be[nwords]
914	// - r_tgt_update
915	// - r_tgt_word_min
916	// - r_tgt_word_max
917	// - r_tgt_word_count
918	// - r_tgt_paddr
919	// - r_tgt_srcid
920	// - r_tgt_trdid
921	// - r_tgt_pktid
922	// - r_tgt_icache_req (set)
923	// - r_tgt_dcache_req (set)
924	//
925	// All VCI commands must be CMD_WRITE.
926	// - If the 2 LSB bits of the VCI address are 11, it is a broadcast request.
927	// It is a multicast request otherwise.
928	// - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS
929	// (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes
930	// INVAL/UPDATE (0 for invalidate / 1 for UPDATE).
931	//
932	// For all types of coherence request, the line index (i.e. the Z & Y fields)
933	// is coded on 34 bits, and is contained in the WDATA and BE fields
934	// of the first VCI flit.
935	// - for a multicast invalidate or for a broadcast invalidate request
936	// the VCI packet length is 1 word.
937	// - for an update request the VCI packet length is (n+2) words.
938	// The WDATA field of the second VCI word contains the word index.
939	// The WDATA field of the n following words contains the values.
940	// - for all transaction types, the VCI response is one single word.
941	// In case of errors in the VCI command packet, the simulation
942	// is stopped with an error message.
943	//
944	// This FSM is NOT pipelined : It consumes a new coherence request
945	// on the VCI port only when the previous request is completed.
946	//
947	// The VCI_TGT FSM stores the external request arguments in the
948	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
949	// and/or the r_tgt_dcache_req flip-flops to signal the coherence request
950	// to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST
951	// states. It waits the completion of the coherence request by polling the
952	// r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST
953	// states. These flip-flops are reset by the ICACHE and DCACHE FSMs.
954	// These two FSMs signal if a VCI answer must be send by setting
955	// the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops.
956	///////////////////////////////////////////////////////////////////////////////
957
958	switch( r_tgt_fsm.read() )
959	{
960	//////////////
961	case TGT_IDLE:
962	{
963	if ( p_vci_tgt_c.cmdval.read() )
964	{
965	paddr_t address = p_vci_tgt_c.address.read();
966
967	// command checking
968	if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE)
969	{
970	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
971	std::cout << "the received VCI coherence command is not a write" << std::endl;
972	exit(0);
973	}
974
975	// address checking
976	if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) )
977	{
978	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
979	std::cout << "out of segment VCI coherence command received" << std::endl;
980	exit(0);
981	}
982
983	r_tgt_srcid = p_vci_tgt_c.srcid.read();
984	r_tgt_trdid = p_vci_tgt_c.trdid.read();
985	r_tgt_pktid = p_vci_tgt_c.pktid.read();
986
987	r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 \|
988	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
989
990	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
991	{
992	if ( not p_vci_tgt_c.eop.read() )
993	{
994	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
995	std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl;
996	exit(0);
997	}
998	r_tgt_update = false;
999	r_tgt_fsm = TGT_REQ_BROADCAST;
1000
1001	#ifdef INSTRUMENTATION
1002	m_cpt_cc_broadcast++;
1003	#endif
1004	}
1005	else // multi-update or multi-invalidate for data type
1006	{
1007	paddr_t cell = address - m_segment.baseAddress();
1008
1009	if (cell == 0) // invalidate data
1010	{
1011	if ( not p_vci_tgt_c.eop.read() )
1012	{
1013	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1014	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1015	exit(0);
1016	}
1017	r_tgt_update = false;
1018	r_tgt_fsm = TGT_REQ_DCACHE;
1019
1020	#ifdef INSTRUMENTATION
1021	m_cpt_cc_inval_dcache++;
1022	#endif
1023	}
1024	else if (cell == 4) // invalidate instruction
1025	{
1026	if ( not p_vci_tgt_c.eop.read() )
1027	{
1028	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1029	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1030	exit(0);
1031	}
1032	r_tgt_update = false;
1033	r_tgt_fsm = TGT_REQ_ICACHE;
1034
1035	#ifdef INSTRUMENTATION
1036	m_cpt_cc_inval_icache++;
1037	#endif
1038	}
1039	else if (cell == 8) // update data
1040	{
1041	if ( p_vci_tgt_c.eop.read() )
1042	{
1043	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1044	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1045	exit(0);
1046	}
1047	r_tgt_update = true;
1048	r_tgt_update_data = true;
1049	r_tgt_fsm = TGT_UPDT_WORD;
1050
1051	#ifdef INSTRUMENTATION
1052	m_cpt_cc_update_dcache++;
1053	#endif
1054	}
1055	else // update instruction
1056	{
1057	if ( p_vci_tgt_c.eop.read() )
1058	{
1059	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1060	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1061	exit(0);
1062	}
1063	r_tgt_update = true;
1064	r_tgt_update_data = false;
1065	r_tgt_fsm = TGT_UPDT_WORD;
1066
1067	#ifdef INSTRUMENTATION
1068	m_cpt_cc_update_icache++;
1069	#endif
1070	}
1071	} // end if multi
1072	} // end if cmdval
1073	break;
1074	}
1075	///////////////////
1076	case TGT_UPDT_WORD: // first word index acquisition
1077	{
1078	if (p_vci_tgt_c.cmdval.read())
1079	{
1080	if ( p_vci_tgt_c.eop.read() )
1081	{
1082	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1083	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1084	exit(0);
1085	}
1086	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false;
1087
1088	r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index
1089	r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index
1090	r_tgt_fsm = TGT_UPDT_DATA;
1091	}
1092	break;
1093	}
1094	///////////////////
1095	case TGT_UPDT_DATA:
1096	{
1097	if (p_vci_tgt_c.cmdval.read())
1098	{
1099	size_t word = r_tgt_word_count.read();
1100	if (word >= m_dcache_words)
1101	{
1102	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1103	std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl;
1104	exit(0);
1105	}
1106	r_tgt_buf[word] = p_vci_tgt_c.wdata.read();
1107	r_tgt_be[word] = p_vci_tgt_c.be.read();
1108	r_tgt_word_count = word + 1;
1109
1110	if (p_vci_tgt_c.eop.read()) // last word
1111	{
1112	r_tgt_word_max = word;
1113	if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE;
1114	else r_tgt_fsm = TGT_REQ_ICACHE;
1115	}
1116	}
1117	break;
1118	}
1119	///////////////////////
1120	case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs
1121	{
1122	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() )
1123	{
1124	r_tgt_fsm = TGT_RSP_BROADCAST;
1125	r_tgt_icache_req = true;
1126	r_tgt_dcache_req = true;
1127	}
1128	break;
1129	}
1130	/////////////////////
1131	case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending)
1132	{
1133	if ( not r_tgt_icache_req.read() )
1134	{
1135	r_tgt_fsm = TGT_RSP_ICACHE;
1136	r_tgt_icache_req = true;
1137	}
1138	break;
1139	}
1140	////////////////////
1141	case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending)
1142	{
1143	if ( not r_tgt_dcache_req.read() )
1144	{
1145	r_tgt_fsm = TGT_RSP_DCACHE;
1146	r_tgt_dcache_req = true;
1147	}
1148	break;
1149	}
1150	///////////////////////
1151	case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs
1152	// no response when r_tgt_*cache_rsp is false
1153	{
1154	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed
1155	{
1156	if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response
1157	{
1158	if ( p_vci_tgt_c.rspack.read() )
1159	{
1160	// reset dcache first if activated
1161	if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false;
1162	else r_tgt_icache_rsp = false;
1163	}
1164	}
1165	else
1166	{
1167	r_tgt_fsm = TGT_IDLE;
1168	}
1169	}
1170	break;
1171	}
1172	////////////////////
1173	case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM
1174	{
1175	// no response when r_tgt_icache_rsp is false
1176	if ( not r_tgt_icache_req.read() and p_vci_tgt_c.rspack.read() )
1177	{
1178	r_tgt_fsm = TGT_IDLE;
1179	r_tgt_icache_rsp = false;
1180	}
1181	break;
1182	}
1183	////////////////////
1184	case TGT_RSP_DCACHE:
1185	{
1186	// no response when r_tgt_dcache_rsp is false
1187	if ( not r_tgt_dcache_req.read() and p_vci_tgt_c.rspack.read() )
1188	{
1189	r_tgt_fsm = TGT_IDLE;
1190	r_tgt_dcache_rsp = false;
1191	}
1192	break;
1193	}
1194	} // end switch TGT_FSM
1195
1196	/////////////////////////////////////////////////////////////////////
1197	// Get data and instruction requests from processor
1198	///////////////////////////////////////////////////////////////////////
1199
1200	typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
1201	typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
1202
1203	r_iss.getRequests(ireq, dreq);
1204
1205	////////////////////////////////////////////////////////////////////////////////////
1206	// ICACHE_FSM
1207	//
1208	// There is 9 conditions to exit the IDLE state:
1209	// One condition is a coherence request from TGT FSM :
1210	// - Coherence operation => ICACHE_CC_CHEK
1211	// Five configurations corresponding to XTN processor requests sent by DCACHE FSM :
1212	// - Flush TLB => ICACHE_XTN_TLB_FLUSH
1213	// - Flush cache => ICACHE_XTN_CACHE_FLUSH
1214	// - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL
1215	// - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@
1216	// - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA
1217	// three configurations corresponding to instruction processor requests :
1218	// - tlb miss => ICACHE_TLB_WAIT
1219	// - cacheable read miss => ICACHE_MISS_VICTIM
1220	// - uncacheable read miss => ICACHE_UNC_REQ
1221	//
1222	// In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM
1223	// using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the
1224	// transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM
1225	// state to select a slot and request a VCI transaction to the CLEANUP FSM.
1226	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM.
1227	// The availability of the missing cache line is signaled by the response fifo,
1228	// and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state.
1229	//
1230	// In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
1231	// to CMD FSM usig the r_icache_unc_req flip-flop, that reset this flip-flop
1232	// when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
1233	// the response from the RSP FSM, through the response fifo. The missing instruction
1234	// is directly returned to processor in this state.
1235	//
1236	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb
1237	// using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register,
1238	// and goes to the ICACHE_TLB_WAIT state.
1239	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until
1240	// the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
1241	//
1242	// The DCACHE FSM signals XTN processor requests using the r_dcache_xtn_req flip-flop.
1243	// The request opcode and the address to be invalidated are transmitted
1244	// in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
1245	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1246	// is completed.
1247	//
1248	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1249	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1250	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1251	////////////////////////////////////////////////////////////////////////////////////////
1252
1253	// The default value for irsp.valid is false
1254	typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
1255
1256	switch( r_icache_fsm.read() )
1257	{
1258	/////////////////
1259	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent
1260	// by DCACHE FSM, and coherence requests with a fixed priority:
1261	// coherence > XTN > instruction
1262	// We access the itlb and dcache in parallel with the virtual address
1263	// for itlb, and with a speculative physical address for icache,
1264	// computed during the previous cycle.
1265	{
1266	// coherence request from the target FSM
1267	if ( r_tgt_icache_req.read() )
1268	{
1269	r_icache_fsm = ICACHE_CC_CHECK;
1270	r_icache_fsm_save = r_icache_fsm.read();
1271	break;
1272	}
1273
1274	// Decoding processor XTN requests sent by DCACHE FSM
1275	// These request are not executed in this IDLE state, because
1276	// they require access to icache or itlb, that are already accessed
1277	if ( r_dcache_xtn_req.read() )
1278	{
1279	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1280	{
1281	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1282	break;
1283	}
1284	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1285	{
1286	r_icache_flush_count = 0;
1287	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1288	break;
1289	}
1290	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1291	{
1292	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1293	break;
1294	}
1295	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1296	{
1297	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1298	break;
1299	}
1300	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1301	{
1302	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1303	(paddr_t)r_mmu_word_lo.read();
1304	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1305	break;
1306	}
1307	} // end if xtn_req
1308
1309	// processor request
1310	if ( ireq.valid )
1311	{
1312	bool cacheable;
1313	paddr_t paddr;
1314
1315	// We register processor request
1316	r_icache_vaddr_save = ireq.addr;
1317
1318	// speculative icache access (if cache activated)
1319	// we use the speculative PPN computed during the previous cycle
1320
1321	uint32_t cache_inst = 0;
1322	bool cache_hit = false;
1323
1324	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1325	{
1326	paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) \|
1327	((paddr_t)ireq.addr & PAGE_K_MASK);
1328
1329	#ifdef INSTRUMENTATION
1330	m_cpt_icache_data_read++;
1331	m_cpt_icache_dir_read++;
1332	#endif
1333	cache_hit = r_icache.read( spc_paddr,
1334	&cache_inst );
1335	}
1336
1337	// systematic itlb access (if tlb activated)
1338	// we use the virtual address
1339
1340	paddr_t tlb_paddr;
1341	pte_info_t tlb_flags;
1342	size_t tlb_way;
1343	size_t tlb_set;
1344	paddr_t tlb_nline;
1345	bool tlb_hit = false;;
1346
1347	if ( r_mmu_mode.read() & INS_TLB_MASK )
1348	{
1349
1350	#ifdef INSTRUMENTATION
1351	m_cpt_itlb_read++;
1352	#endif
1353	tlb_hit = r_itlb.translate( ireq.addr,
1354	&tlb_paddr,
1355	&tlb_flags,
1356	&tlb_nline, // unused
1357	&tlb_way, // unused
1358	&tlb_set ); // unused
1359	}
1360
1361	// We compute cacheability, physical address and check access rights:
1362	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1363	// the physical address is obtained from the TLB, and the access rights are
1364	// defined by the U and X bits in the PTE.
1365	// - If MMU not activated : cacheability is defined by the segment table,
1366	// the physical address is equal to the virtual address (identity mapping)
1367	// and there is no access rights checking
1368
1369	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1370	{
1371	// cacheability
1372	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1373	else cacheable = m_cacheability_table[ireq.addr];
1374
1375	// physical address
1376	paddr = (paddr_t)ireq.addr;
1377	}
1378	else // itlb activated
1379	{
1380	if ( tlb_hit ) // tlb hit
1381	{
1382	// cacheability
1383	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1384	else cacheable = tlb_flags.c;
1385
1386	// physical address
1387	paddr = tlb_paddr;
1388
1389	// access rights checking
1390	if ( not tlb_flags.u && (ireq.mode == iss_t::MODE_USER) )
1391	{
1392	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1393	r_mmu_ibvar = ireq.addr;
1394	irsp.valid = true;
1395	irsp.error = true;
1396	irsp.instruction = 0;
1397	break;
1398	}
1399	else if ( not tlb_flags.x )
1400	{
1401	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1402	r_mmu_ibvar = ireq.addr;
1403	irsp.valid = true;
1404	irsp.error = true;
1405	irsp.instruction = 0;
1406	break;
1407	}
1408	}
1409	// in case of TLB miss we send an itlb miss request to DCACHE FSM and break
1410	else
1411	{
1412
1413	#ifdef INSTRUMENTATION
1414	m_cpt_itlb_miss++;
1415	#endif
1416	r_icache_fsm = ICACHE_TLB_WAIT;
1417	r_icache_tlb_miss_req = true;
1418	break;
1419	}
1420	} // end if itlb activated
1421
1422	// physical address registration (for next cycle)
1423	r_icache_vci_paddr = paddr;
1424
1425	// Finally, we get the instruction depending on cacheability
1426	if ( cacheable ) // cacheable read
1427	{
1428	if ( not cache_hit ) // cache miss
1429	{
1430	// in case of icache miss we send a request to CMD FSM, but we are
1431	// blocked in IDLE state if the previous cleanup is not completed
1432	if ( not r_icache_cleanup_req.read() )
1433	{
1434
1435	#ifdef INSTRUMENTATION
1436	m_cpt_icache_miss++;
1437	#endif
1438	r_icache_fsm = ICACHE_MISS_VICTIM;
1439	r_icache_miss_req = true;
1440	}
1441	}
1442	else // cache hit
1443	{
1444	if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK)
1445	!= (paddr & ~PAGE_K_MASK) ) // speculative access KO
1446	{
1447
1448	#ifdef INSTRUMENTATION
1449	m_cpt_icache_spc_miss++;
1450	#endif
1451	// we return an invalid response
1452	// and the cache access will cost one extra cycle.
1453	break;
1454	}
1455	else // speculative access OK
1456	{
1457
1458	#ifdef INSTRUMENTATION
1459	m_cpt_ins_read++;
1460	#endif
1461	irsp.valid = true;
1462	irsp.instruction = cache_inst;
1463	}
1464	}
1465	}
1466	else // non cacheable read
1467	{
1468	r_icache_unc_req = true;
1469	r_icache_fsm = ICACHE_UNC_WAIT;
1470	}
1471	} // end if ireq.valid
1472	break;
1473	}
1474	/////////////////////
1475	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1476	// the itlb is udated by the DCACHE FSM, as well as the
1477	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1478	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1479	// reset the r_icache_tlb_miss_req flip-flop
1480	// external coherence request are accepted in this state.
1481	{
1482	// external coherence request
1483	if ( r_tgt_icache_req.read() )
1484	{
1485	r_icache_fsm = ICACHE_CC_CHECK;
1486	r_icache_fsm_save = r_icache_fsm.read();
1487	break;
1488	}
1489
1490	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1491
1492	// DCACHE FSM signals response by reseting the request flip-flop
1493	if ( not r_icache_tlb_miss_req.read() )
1494	{
1495	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1496	{
1497	r_icache_tlb_rsp_error = false;
1498	irsp.error = true;
1499	irsp.valid = true;
1500	r_icache_fsm = ICACHE_IDLE;
1501	}
1502	else // tlb updated : return to IDLE state
1503	{
1504	r_icache_fsm = ICACHE_IDLE;
1505	}
1506	}
1507	break;
1508	}
1509	//////////////////////////
1510	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1511	{
1512	r_itlb.flush();
1513	r_dcache_xtn_req = false;
1514	r_icache_fsm = ICACHE_IDLE;
1515	break;
1516	}
1517	////////////////////////////
1518	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using
1519	// the r_icache_flush_count register as a slot counter.
1520	// We loop in this state until all slots have been visited.
1521	// A cleanup request is generated for each valid line
1522	// and we are blocked until the previous cleanup is completed
1523	{
1524	if ( not r_icache_cleanup_req.read() )
1525	{
1526	size_t way = r_icache_flush_count.read()/m_icache_sets;
1527	size_t set = r_icache_flush_count.read()%m_icache_sets;
1528	paddr_t nline;
1529	bool cleanup_req = r_icache.inval( way,
1530	set,
1531	&nline );
1532	if ( cleanup_req )
1533	{
1534	r_icache_cleanup_req = true;
1535	r_icache_cleanup_line = nline;
1536	}
1537	r_icache_flush_count = r_icache_flush_count.read() + 1;
1538	}
1539
1540	if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) )
1541	{
1542	r_dcache_xtn_req = false;
1543	r_icache_fsm = ICACHE_IDLE;
1544	}
1545	break;
1546	}
1547	//////////////////////////
1548	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1549	// stored in the r_dcache_p0_wdata register
1550	{
1551	r_itlb.inval(r_dcache_p0_wdata.read());
1552	r_dcache_xtn_req = false;
1553	r_icache_fsm = ICACHE_IDLE;
1554	break;
1555	}
1556	///////////////////////////////
1557	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1558	// requires 3 cycles (in case of hit on itlb and icache).
1559	// In this state, we access TLB to translate virtual address
1560	// stored in the r_dcache_p0_wdata register.
1561	{
1562	paddr_t paddr;
1563	bool hit;
1564
1565	// read physical address in TLB when MMU activated
1566	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1567	{
1568
1569	#ifdef INSTRUMENTATION
1570	m_cpt_itlb_read++;
1571	#endif
1572	hit = r_itlb.translate(r_dcache_p0_wdata.read(),
1573	&paddr);
1574	}
1575	else // itlb not activated
1576	{
1577	paddr = (paddr_t)r_dcache_p0_wdata.read();
1578	hit = true;
1579	}
1580
1581	if ( hit ) // continue the selective inval process
1582	{
1583	r_icache_vci_paddr = paddr;
1584	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1585	}
1586	else // miss : send a request to DCACHE FSM
1587	{
1588
1589	#ifdef INSTRUMENTATION
1590	m_cpt_itlb_miss++;
1591	#endif
1592	r_icache_tlb_miss_req = true;
1593	r_icache_fsm = ICACHE_TLB_WAIT;
1594	}
1595	break;
1596	}
1597	///////////////////////////////
1598	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1599	// require 2 cycles. In this state, we read dcache,
1600	// with address stored in r_icache_vci_paddr register.
1601	{
1602	uint32_t data;
1603	size_t way;
1604	size_t set;
1605	size_t word;
1606	bool hit = r_icache.read(r_icache_vci_paddr.read(),
1607	&data,
1608	&way,
1609	&set,
1610	&word);
1611	if ( hit ) // inval to be done
1612	{
1613	r_icache_miss_way = way;
1614	r_icache_miss_set = set;
1615	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1616	}
1617	else // miss : acknowlege the XTN request and return
1618	{
1619	r_dcache_xtn_req = false;
1620	r_icache_fsm = ICACHE_IDLE;
1621	}
1622	break;
1623	}
1624	///////////////////////////////
1625	case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup.
1626	// We are blocked if the previous cleanup is not completed
1627	{
1628	paddr_t nline;
1629
1630	if ( not r_icache_cleanup_req.read() )
1631	{
1632	r_icache.inval( r_icache_miss_way.read(),
1633	r_icache_miss_set.read(),
1634	&nline );
1635
1636	// request cleanup
1637	r_icache_cleanup_req = true;
1638	r_icache_cleanup_line = nline;
1639	// acknowledge the XTN request and return
1640	r_dcache_xtn_req = false;
1641	r_icache_fsm = ICACHE_IDLE;
1642	}
1643	break;
1644	}
1645
1646	////////////////////////
1647	case ICACHE_MISS_VICTIM: // Selects a victim line
1648	// Set the r_icache_cleanup_req flip-flop
1649	// when the selected slot is not empty
1650	{
1651	if ( ireq.valid ) m_cost_ins_miss_frz++;
1652
1653	bool valid;
1654	size_t way;
1655	size_t set;
1656	paddr_t victim;
1657
1658	valid = r_icache.victim_select(r_icache_vci_paddr.read(),
1659	&victim,
1660	&way,
1661	&set);
1662	r_icache_miss_way = way;
1663	r_icache_miss_set = set;
1664
1665	if ( valid )
1666	{
1667	r_icache_cleanup_req = true;
1668	r_icache_cleanup_line = victim;
1669	r_icache_fsm = ICACHE_MISS_INVAL;
1670	}
1671	else
1672	{
1673	r_icache_fsm = ICACHE_MISS_WAIT;
1674	}
1675	break;
1676	}
1677	///////////////////////
1678	case ICACHE_MISS_INVAL: // invalidate the victim line
1679	{
1680	paddr_t nline;
1681
1682	r_icache.inval( r_icache_miss_way.read(),
1683	r_icache_miss_set.read(),
1684	&nline ); // unused
1685
1686	r_icache_fsm = ICACHE_MISS_WAIT;
1687	break;
1688	}
1689	//////////////////////
1690	case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM
1691	{
1692	if ( ireq.valid ) m_cost_ins_miss_frz++;
1693
1694	// external coherence request
1695	if ( r_tgt_icache_req.read() )
1696	{
1697	r_icache_fsm = ICACHE_CC_CHECK;
1698	r_icache_fsm_save = r_icache_fsm.read();
1699	break;
1700	}
1701
1702	if ( r_vci_rsp_ins_error.read() ) // bus error
1703	{
1704	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1705	r_mmu_ibvar = r_icache_vaddr_save.read();
1706	irsp.valid = true;
1707	irsp.error = true;
1708	r_vci_rsp_ins_error = false;
1709	r_icache_fsm = ICACHE_IDLE;
1710	}
1711	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1712	{
1713	r_icache_miss_word = 0;
1714	r_icache_fsm = ICACHE_MISS_UPDT;
1715	}
1716	break;
1717	}
1718	//////////////////////
1719	case ICACHE_MISS_UPDT: // update the cache (one word per cycle)
1720	{
1721	if ( ireq.valid ) m_cost_ins_miss_frz++;
1722
1723	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1724	{
1725	if ( r_icache_miss_inval ) // Matching coherence request
1726	// We pop the response FIFO, without updating the cache
1727	// We send a cleanup for the missing line at the last word
1728	// Blocked if the previous cleanup is not completed
1729	{
1730	if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word
1731	{
1732	vci_rsp_fifo_icache_get = true;
1733	r_icache_miss_word = r_icache_miss_word.read() + 1;
1734	}
1735	else // last word
1736	{
1737	if ( not r_icache_cleanup_req.read() ) // no pending cleanup
1738	{
1739	vci_rsp_fifo_icache_get = true;
1740	r_icache_cleanup_req = true;
1741	r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2));
1742	r_icache_miss_inval = false;
1743	r_icache_fsm = ICACHE_IDLE;
1744	}
1745	}
1746	}
1747	else // No matching coherence request
1748	// We pop the FIFO and update the cache
1749	// We update the directory at the last word
1750	{
1751
1752	#ifdef INSTRUMENTATION
1753	m_cpt_icache_data_write++;
1754	#endif
1755	r_icache.write( r_icache_miss_way.read(),
1756	r_icache_miss_set.read(),
1757	r_icache_miss_word.read(),
1758	r_vci_rsp_fifo_icache.read() );
1759	vci_rsp_fifo_icache_get = true;
1760	r_icache_miss_word = r_icache_miss_word.read() + 1;
1761	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1762	{
1763
1764	#ifdef INSTRUMENTATION
1765	m_cpt_icache_dir_write++;
1766	#endif
1767	r_icache.victim_update_tag( r_icache_vci_paddr.read(),
1768	r_icache_miss_way.read(),
1769	r_icache_miss_set.read() );
1770	r_icache_fsm = ICACHE_IDLE;
1771	}
1772	}
1773	}
1774	break;
1775	}
1776	////////////////////
1777	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1778	//
1779	{
1780	// external coherence request
1781	if ( r_tgt_icache_req.read() )
1782	{
1783	r_icache_fsm = ICACHE_CC_CHECK;
1784	r_icache_fsm_save = r_icache_fsm.read();
1785	break;
1786	}
1787
1788	if ( r_vci_rsp_ins_error.read() ) // bus error
1789	{
1790	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1791	r_mmu_ibvar = ireq.addr;
1792	r_vci_rsp_ins_error = false;
1793	irsp.valid = true;
1794	irsp.error = true;
1795	r_icache_fsm = ICACHE_IDLE;
1796	}
1797	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1798	{
1799	vci_rsp_fifo_icache_get = true;
1800	r_icache_fsm = ICACHE_IDLE;
1801	if ( ireq.valid and (ireq.addr == r_icache_vaddr_save.read()) ) // request not modified
1802	{
1803	irsp.valid = true;
1804	irsp.instruction = r_vci_rsp_fifo_icache.read();
1805	}
1806	}
1807	break;
1808	}
1809	/////////////////////
1810	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1811	// handling coherence requests.
1812	// the return state is defined in r_icache_fsm_save.
1813	{
1814	paddr_t paddr = r_tgt_paddr.read();
1815	paddr_t mask = ~((m_icache_words<<2)-1);
1816
1817	if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and
1818	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss
1819	{
1820	r_icache_miss_inval = true; // signaling the matching
1821	r_tgt_icache_req = false; // coherence request completed
1822	r_tgt_icache_rsp = r_tgt_update.read(); // response required if update
1823	r_icache_fsm = r_icache_fsm_save.read();
1824	}
1825	else // no match
1826	{
1827
1828	#ifdef INSTRUMENTATION
1829	m_cpt_icache_dir_read++;
1830	#endif
1831	uint32_t inst;
1832	size_t way;
1833	size_t set;
1834	size_t word;
1835	bool hit = r_icache.read(paddr,
1836	&inst,
1837	&way,
1838	&set,
1839	&word);
1840	r_icache_cc_way = way;
1841	r_icache_cc_set = set;
1842
1843	if ( hit and r_tgt_update.read() ) // hit update
1844	{
1845	r_icache_fsm = ICACHE_CC_UPDT;
1846	r_icache_cc_word = r_tgt_word_min.read();
1847	}
1848	else if ( hit and not r_tgt_update.read() ) // hit inval
1849	{
1850	r_icache_fsm = ICACHE_CC_INVAL;
1851	}
1852	else // miss can happen
1853	{
1854	r_tgt_icache_req = false;
1855	r_tgt_icache_rsp = r_tgt_update.read();
1856	r_icache_fsm = r_icache_fsm_save.read();
1857	}
1858	}
1859	break;
1860	}
1861
1862	/////////////////////
1863	case ICACHE_CC_INVAL: // invalidate a cache line
1864	{
1865	paddr_t nline;
1866	r_icache.inval( r_icache_cc_way.read(),
1867	r_icache_cc_set.read(),
1868	&nline );
1869
1870	r_tgt_icache_req = false;
1871	r_tgt_icache_rsp = true;
1872	r_icache_fsm = r_icache_fsm_save.read();
1873	break;
1874	}
1875	////////////////////
1876	case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
1877	{
1878	size_t word = r_icache_cc_word.read();
1879	size_t way = r_icache_cc_way.read();
1880	size_t set = r_icache_cc_set.read();
1881
1882	r_icache.write( way,
1883	set,
1884	word,
1885	r_tgt_buf[word],
1886	r_tgt_be[word] );
1887
1888	r_icache_cc_word = word+1;
1889
1890	if ( word == r_tgt_word_max.read() ) // last word
1891	{
1892	r_tgt_icache_req = false;
1893	r_tgt_icache_rsp = true;
1894	r_icache_fsm = r_icache_fsm_save.read();
1895	}
1896	break;
1897	}
1898
1899	} // end switch r_icache_fsm
1900
1901	// save the IREQ and IRSP fields for the print_trace() function
1902	m_ireq_valid = ireq.valid;
1903	m_ireq_addr = ireq.addr;
1904	m_ireq_mode = ireq.mode;
1905
1906	m_irsp_valid = irsp.valid;
1907	m_irsp_instruction = irsp.instruction;
1908	m_irsp_error = irsp.error;
1909
1910	////////////////////////////////////////////////////////////////////////////////////
1911	// INVAL ITLB FSM
1912	// This FSM works in parallel with the ICACHE FSM.
1913	// When the r_dcache_itlb_inval_req flip-flop is activated by the DCACHE FSM
1914	// it scans sequencially all entries in the ITLB, and invalidates the
1915	// entries matching the evicted line.
1916	// It signals the completion of invalidation by reseting r_dcache_itlb_inval_req.
1917	////////////////////////////////////////////////////////////////////////////////////
1918
1919	switch(r_inval_itlb_fsm)
1920	{
1921	/////////////////////
1922	case INVAL_ITLB_IDLE:
1923	{
1924	if ( r_dcache_itlb_inval_req.read() )
1925	{
1926	r_itlb.reset_bypass(r_dcache_tlb_inval_line.read());
1927	r_inval_itlb_count = 0;
1928	r_inval_itlb_fsm = INVAL_ITLB_SCAN;
1929
1930	#if DEBUG_INVAL_ITLB
1931	if ( m_debug_inval_itlb_fsm )
1932	{
1933	std::cout << " <PROC.INVAL_ITLB_IDLE> Invalidate request for line "
1934	<< std::hex << r_dcache_tlb_inval_line.read() << std::endl;
1935	r_itlb.print();
1936	}
1937	#endif
1938	}
1939	break;
1940	}
1941	/////////////////////
1942	case INVAL_ITLB_SCAN:
1943	{
1944	paddr_t line = r_dcache_tlb_inval_line.read(); // nline
1945	size_t way = r_inval_itlb_count.read()/m_itlb_sets; // way
1946	size_t set = r_inval_itlb_count.read()%m_itlb_sets; // set
1947
1948	bool ok = r_itlb.inval( line,
1949	way,
1950	set );
1951
1952	#if DEBUG_INVAL_ITLB
1953	if ( m_debug_inval_itlb_fsm )
1954	{
1955	std::cout << " <PROC.INVAL_ITLB_SCAN>" << std::hex
1956	<< " line = " << line << std::dec
1957	<< " / set = " << set
1958	<< " / way = " << way;
1959	if ( ok ) std::cout << " / HIT" << std::endl;
1960	else std::cout << " / MISS" << std::endl;
1961	}
1962	#endif
1963
1964	r_inval_itlb_count = r_inval_itlb_count.read() + 1;
1965	if ( r_inval_itlb_count.read() == (m_itlb_sets*m_itlb_ways - 1) )
1966	{
1967	r_inval_itlb_fsm = INVAL_ITLB_IDLE;
1968	r_dcache_itlb_inval_req = false;
1969	}
1970	break;
1971	}
1972	} // end switch r_inval_itlb_fsm
1973
1974	////////////////////////////////////////////////////////////////////////////////////
1975	// DCACHE FSM
1976	//
1977	// Both the Cacheability Table, and the MMU cacheable bit are used to define
1978	// the cacheability, depending on the MMU mode.
1979	//
1980	// 1/ Coherence requests :
1981	// There is a coherence request when the tgt_dcache_req flip-flop is set,
1982	// requesting a line invalidation or a line update.
1983	// Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states.
1984	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
1985	// goes to the CC_CHECK state to execute the requested action, and returns to the
1986	// pre-empted state.
1987	//
1988	// 2/ processor requests :
1989	// Processor READ, WRITE, LL or SC requests are taken in IDLE state only.
1990	// The IDLE state implements a three stages pipe-line to handle write bursts:
1991	// - The physical address is computed by dtlb in stage P0.
1992	// - The registration in wbuf and the dcache hit are computed in stage P1.
1993	// - The dcache update is done in stage P2.
1994	// A write operation can require a fourth stage if the dirty bit must be updated,
1995	// or if the TLBs must be cleared, but these "long write" operation requires
1996	// to exit the IDLE stage
1997	// If there is no write in the pipe, dcache and dtlb are accessed in parallel,
1998	// (virtual address for itlb, and speculative physical address computed during
1999	// previous cycle for dcache) in order to return the data in one cycle for a read.
2000	// We just pay an extra cycle when the speculative access is illegal.
2001	//
2002	// 3/ Atomic instructions LL/SC
2003	// The LL/SC address can be cacheable or non cacheable.
2004	// The reservation registers (r_dcache_ll_valid, r_dcache_ll_vaddr and
2005	// r_dcache_ll_data are stored in the L1 cache controller, and not in the
2006	// memory controller.
2007	// - LL requests from the processor are transmitted as standard VCI
2008	// READ transactions (one word / one line, depending on the cacheability).
2009	// - SC requests from the processor are systematically transmitted to the
2010	// memory cache as COMPARE&swap requests (both the data value stored in the
2011	// r_dcache_ll_data register and the new value).
2012	//
2013	// 4/ Non cacheable access:
2014	// This component implement a strong order between non cacheable access
2015	// (read or write) : A new non cacheable VCI transaction starts only when
2016	// the previous non cacheable transaction is completed. Both cacheable and
2017	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2018	// a non cacheable write transaction posted in the write buffer by setting the
2019	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2020	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2021	// pending non cacheable write transaction completes).
2022	//
2023	// 5/ Error handling:
2024	// When the MMU is not activated, Read Bus Errors are synchronous events,
2025	// but Write Bus Errors are asynchronous events (processor is not frozen).
2026	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2027	// r_vci_rsp_data_error flip-flop, without writing any data in the
2028	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2029	// by the DCACHE FSM.
2030	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2031	// the asynchronous error using the setWriteBerr() method.
2032	// When the MMU is activated bus error are rare events, as the MMU
2033	// checks the physical address before the VCI transaction starts.
2034	////////////////////////////////////////////////////////////////////////////////////////
2035
2036	// The default value for drsp.valid is false
2037	typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
2038
2039	switch ( r_dcache_fsm.read() )
2040	{
2041	case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state :
2042	// 1) Long write request (DCACHE FSM) => DCACHE_WRITE_***
2043	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2044	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2045	// 4) XTN request (processor) => DCACHE_XTN_*
2046	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2047	// 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM
2048	// 7) Uncacheable read (processor) => DCACHE_UNC_REQ
2049	// 8) SC access (processor) => DCACHE_SC
2050	// There is 4 configurations to access the cache,
2051	// depending on the pipe-line state, defined
2052	// by the r_dcache_p0_valid flip-flop (P1 stage activated)
2053	// and r_dcache_p1_valid flip-flop (P2 stage activated) :
2054	// V0 / V1 / Data / Directory / comment
2055	// 0 / 0 / read(A0) / read(A0) / read speculative access
2056	// 0 / 1 / write(A2) / nop / read request delayed
2057	// 1 / 0 / nop / read(A1) / read request delayed
2058	// 1 / 1 / write(A2) / read(A1) / read request delayed
2059	{
2060	////////////////////////////////////////////////////////////////////////////////
2061	// Handling P2 pipe-line stage
2062	// Inputs are r_dcache_p1_* registers.
2063	// Three actions are executed in this P2 stage:
2064	// - If r_dcache_p1_updt_cache is true, we update the local copy in dcache.
2065	// - If the modified cache line has copies in itlb (resp. dtlb), and if the
2066	// INVAL_ITLB (resp. INVAL_DTLB) FSM is idle, we launch the TLB invalidate
2067	// operation. This operation is NOT blocking for the processor: the DCACHE FSM
2068	// doesn't wait the TLB invalidate completion to handle processor requests.
2069	// If the INVAL_ITLB (resp INVAL_DTLB) FSM is already processintg a previous
2070	// invalidation request, the DCACHE FSM is frosen until completion of the
2071	// previous TLB invalidate operation.
2072	// - If the PTE dirty bit must be updated, we start a "long write", that is
2073	// blocking for the processor, because we switch to the DCACHE_WRITE_SET_DIRTY
2074	// state, and the number of cycles can be large...
2075
2076	bool long_write_set_dirty = false;
2077	bool tlb_inval_frozen = false;
2078
2079	if ( r_dcache_p1_valid.read() ) // P2 stage activated
2080	{
2081	bool cache_updt = r_dcache_p1_updt_cache.read();
2082	size_t cache_way = r_dcache_p1_cache_way.read();
2083	size_t cache_set = r_dcache_p1_cache_set.read();
2084	size_t cache_word = r_dcache_p1_cache_word.read();
2085	uint32_t wdata = r_dcache_p1_wdata.read();
2086	vci_be_t be = r_dcache_p1_be.read();
2087
2088	// The PTE address is used when the PTE dirty bit must be set.
2089	// It is the concatenation of the nline value (from dtlb)
2090	// and the word index (from virtual address)
2091	paddr_t pte_paddr = (paddr_t)(r_dcache_p1_tlb_nline.read()*(m_dcache_words<<2))
2092	\| (paddr_t)(r_dcache_p1_vaddr.read()%(m_dcache_words<<2));
2093
2094	// The line index is used when a TLB inval is required
2095	paddr_t inval_line = r_dcache_p1_paddr.read()>>(uint32_log2(m_dcache_words<<2));
2096
2097	// checking dcache update
2098	if ( cache_updt )
2099	{
2100	r_dcache.write( cache_way,
2101	cache_set,
2102	cache_word,
2103	wdata,
2104	be );
2105	#ifdef INSTRUMENTATION
2106	m_cpt_dcache_data_write++;
2107	#endif
2108
2109	// Checking copies in TLBs
2110	bool itlb_inval = ( (r_mmu_mode.read() & INS_TLB_MASK) and
2111	r_dcache_in_itlb[cache_way*m_dcache_sets+cache_set] );
2112	bool dtlb_inval = ( (r_mmu_mode.read() & DATA_TLB_MASK) and
2113	r_dcache_in_dtlb[cache_way*m_dcache_sets+cache_set] );
2114
2115	if ( (dtlb_inval and r_dcache_dtlb_inval_req.read() ) or
2116	(itlb_inval and r_dcache_itlb_inval_req.read() ) ) // at least one FSM not idle
2117	{
2118	tlb_inval_frozen = true;
2119	}
2120	else // requested FSM idle
2121	{
2122	r_dcache_tlb_inval_line = inval_line;
2123	r_dcache_itlb_inval_req = itlb_inval;
2124	r_dcache_dtlb_inval_req = dtlb_inval;
2125	r_dcache_in_itlb[cache_way*m_dcache_sets+cache_set] = false;
2126	r_dcache_in_dtlb[cache_way*m_dcache_sets+cache_set] = false;
2127	}
2128	} // end dcache update
2129
2130	// checking dirty bit update
2131	if ( r_dcache_p1_set_dirty.read() )
2132	{
2133	long_write_set_dirty = true;
2134	r_dcache_p2_vaddr = r_dcache_p1_vaddr.read();
2135	r_dcache_p2_set_dirty = r_dcache_p1_set_dirty.read();
2136	r_dcache_p2_tlb_way = r_dcache_p1_tlb_way.read();
2137	r_dcache_p2_tlb_set = r_dcache_p1_tlb_set.read();
2138	r_dcache_p2_pte_paddr = pte_paddr;
2139	}
2140
2141	#if DEBUG_DCACHE
2142	if ( m_debug_dcache_fsm )
2143	{
2144	if ( cache_updt )
2145	std::cout << " <PROC.DCACHE_IDLE> P2 stage: cache update" << std::dec
2146	<< " / way = " << cache_way
2147	<< " / set = " << cache_set
2148	<< " / word = " << cache_word << std::hex
2149	<< " / wdata = " << wdata
2150	<< " / be = " << be << std::endl;
2151	if ( long_write_set_dirty )
2152	std::cout << " <PROC.DCACHE_IDLE> P2 stage: dirty bit update required"
2153	<< " / pte_paddr = " << std::hex << pte_paddr << std::endl;
2154	}
2155	#endif
2156	} // end P2 stage
2157
2158	///////////////////////////////////////////////////////////////////////////
2159	// Handling P1 pipe-line stage
2160	// Inputs are r_dcache_p0_* registers.
2161	// - We must write into wbuf and test the hit in dcache.
2162	// If the write request is not cacheable, and there is a pending
2163	// non cacheable write, or if the write buffer is full, we break:
2164	// The P0 and P1 pipe-line stages are frozen until the write
2165	// request registration is possible, but the P2 stage is not frozen.
2166	// - The r_dcache_p1_valid bit activating the P2 pipe-line stage
2167	// must be computed at all cycles. The P2 stage must be activated
2168	// if there is local copy in dcache, or if the PTE dirty bit must be set.
2169
2170	if ( r_dcache_p0_valid.read() and not tlb_inval_frozen ) // P1 stage activated
2171	{
2172	// write not cacheable, and previous non cacheable write registered
2173	if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() )
2174	{
2175	r_dcache_p1_valid = false;
2176	break;
2177	}
2178
2179	// try a registration into write buffer
2180	bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
2181	r_dcache_p0_be.read(),
2182	r_dcache_p0_wdata.read(),
2183	r_dcache_p0_cacheable.read() );
2184	#ifdef INSTRUMENTATION
2185	m_cpt_wbuf_write++;
2186	#endif
2187	// write buffer full
2188	if ( not wok )
2189	{
2190	r_dcache_p1_valid = false;
2191	break;
2192	}
2193	// update the write_buffer state extension
2194	r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
2195
2196	// read directory to detect local copy
2197	size_t cache_way;
2198	size_t cache_set;
2199	size_t cache_word;
2200	bool local_copy;
2201	if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated
2202	{
2203	local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
2204	&cache_way,
2205	&cache_set,
2206	&cache_word );
2207	#ifdef INSTRUMENTATION
2208	m_cpt_dcache_dir_read++;
2209	#endif
2210	}
2211	else
2212	{
2213	local_copy = false;
2214	}
2215
2216	// dirty bit update requested
2217	bool dirty_req = (r_mmu_mode.read() & DATA_TLB_MASK) and not r_dcache_p0_tlb_dirty.read();
2218
2219	// if there is a local copy or a dirty bit update requested
2220	if ( local_copy or dirty_req )
2221	{
2222	r_dcache_p1_valid = true;
2223	r_dcache_p1_set_dirty = dirty_req;
2224	r_dcache_p1_updt_cache = local_copy;
2225	r_dcache_p1_vaddr = r_dcache_p0_vaddr.read();
2226	r_dcache_p1_wdata = r_dcache_p0_wdata.read();
2227	r_dcache_p1_be = r_dcache_p0_be.read();
2228	r_dcache_p1_paddr = r_dcache_p0_paddr.read();
2229	r_dcache_p1_tlb_way = r_dcache_p0_tlb_way;
2230	r_dcache_p1_tlb_set = r_dcache_p0_tlb_set;
2231	r_dcache_p1_tlb_nline = r_dcache_p0_tlb_nline;
2232	r_dcache_p1_cache_way = cache_way;
2233	r_dcache_p1_cache_set = cache_set;
2234	r_dcache_p1_cache_word = cache_word;
2235	}
2236	else
2237	{
2238	r_dcache_p1_valid = false;
2239	}
2240	}
2241	else // P1 stage not activated
2242	{
2243	r_dcache_p1_valid = false;
2244	} // end P1 stage
2245
2246	/////////////////////////////////////////////////////////////////////////////
2247	// handling P0 write pipe-line stage
2248	// This stage is controlling the DCACHE FSM state register:
2249	// - the FSM is frozen if a TLB invalidate operation must be delayed,
2250	// - the long write requests have the highest priority,
2251	// - then the external coherence requests,
2252	// - then the itlb miss requests,
2253	// - and finally the processor requests.
2254	// A processor read request generate a dcache access using speculative PPN
2255	// only if the write pipe-line is empty. There is an unconditionnal access
2256	// to the dtlb, using virtual address from processor.
2257	// The r_dcache_p0_valid value must be computed at all cycles.
2258
2259	bool p0_valid = false; // default value
2260
2261	// TLB inval delayed
2262	if ( tlb_inval_frozen )
2263	{
2264	break;
2265	}
2266
2267	// long write request
2268	else if ( long_write_set_dirty )
2269	{
2270	r_dcache_fsm = DCACHE_WRITE_TLB_DIRTY;
2271	}
2272
2273	// external coherence request
2274	else if ( r_tgt_dcache_req.read() )
2275	{
2276	r_dcache_fsm = DCACHE_CC_CHECK;
2277	r_dcache_fsm_save = DCACHE_IDLE;
2278	}
2279
2280	// itlb miss request
2281	else if ( r_icache_tlb_miss_req.read() )
2282	{
2283	r_dcache_tlb_ins = true;
2284	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2285	r_dcache_fsm = DCACHE_TLB_MISS;
2286	}
2287
2288	// processor request
2289	else if (dreq.valid )
2290	{
2291	// dcache access using speculative PPN only if pipe-line empty
2292	paddr_t cache_paddr;
2293	size_t cache_way;
2294	size_t cache_set;
2295	size_t cache_word;
2296	uint32_t cache_rdata;
2297	bool cache_hit;
2298
2299	if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated
2300	not r_dcache_p0_valid.read() and
2301	not r_dcache_p1_valid.read() ) // pipe-line empty
2302	{
2303	cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) \|
2304	((paddr_t)dreq.addr & PAGE_K_MASK);
2305
2306	cache_hit = r_dcache.read( cache_paddr,
2307	&cache_rdata,
2308	&cache_way,
2309	&cache_set,
2310	&cache_word );
2311	#ifdef INSTRUMENTATION
2312	m_cpt_dcache_dir_read++;
2313	m_cpt_dcache_data_read++;
2314	#endif
2315	}
2316	else
2317	{
2318	cache_hit = false;
2319	} // end dcache access
2320
2321	// systematic dtlb access using virtual address
2322
2323	paddr_t tlb_paddr;
2324	pte_info_t tlb_flags;
2325	size_t tlb_way;
2326	size_t tlb_set;
2327	paddr_t tlb_nline;
2328	bool tlb_hit;
2329
2330	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // TLB activated
2331	{
2332	tlb_hit = r_dtlb.translate( dreq.addr,
2333	&tlb_paddr,
2334	&tlb_flags,
2335	&tlb_nline,
2336	&tlb_way,
2337	&tlb_set );
2338	#ifdef INSTRUMENTATION
2339	m_cpt_dtlb_read++;
2340	#endif
2341	// register dtlb outputs
2342	r_dcache_p0_tlb_nline = tlb_nline;
2343	r_dcache_p0_tlb_way = tlb_way;
2344	r_dcache_p0_tlb_set = tlb_set;
2345	r_dcache_p0_tlb_dirty = tlb_flags.d;
2346	r_dcache_p0_tlb_big = tlb_flags.b;
2347	}
2348	else
2349	{
2350	tlb_hit = false;
2351	} // end dtlb access
2352
2353	// register the processor request
2354	r_dcache_p0_vaddr = dreq.addr;
2355	r_dcache_p0_be = dreq.be;
2356	r_dcache_p0_wdata = dreq.wdata;
2357
2358	// Handling READ XTN requests from processor
2359	// They are executed in this DCACHE_IDLE state.
2360	// The processor must not be in user mode
2361	if (dreq.type == iss_t::XTN_READ)
2362	{
2363	int xtn_opcode = (int)dreq.addr/4;
2364
2365	// checking processor mode:
2366	if (dreq.mode == iss_t::MODE_USER)
2367	{
2368	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2369	r_mmu_dbvar = dreq.addr;
2370	drsp.valid = true;
2371	drsp.error = true;
2372	r_dcache_fsm = DCACHE_IDLE;
2373	}
2374	else
2375	{
2376	switch( xtn_opcode )
2377	{
2378	case iss_t::XTN_INS_ERROR_TYPE:
2379	drsp.rdata = r_mmu_ietr.read();
2380	drsp.valid = true;
2381	break;
2382
2383	case iss_t::XTN_DATA_ERROR_TYPE:
2384	drsp.rdata = r_mmu_detr.read();
2385	drsp.valid = true;
2386	break;
2387
2388	case iss_t::XTN_INS_BAD_VADDR:
2389	drsp.rdata = r_mmu_ibvar.read();
2390	drsp.valid = true;
2391	break;
2392
2393	case iss_t::XTN_DATA_BAD_VADDR:
2394	drsp.rdata = r_mmu_dbvar.read();
2395	drsp.valid = true;
2396	break;
2397
2398	case iss_t::XTN_PTPR:
2399	drsp.rdata = r_mmu_ptpr.read();
2400	drsp.valid = true;
2401	break;
2402
2403	case iss_t::XTN_TLB_MODE:
2404	drsp.rdata = r_mmu_mode.read();
2405	drsp.valid = true;
2406	break;
2407
2408	case iss_t::XTN_MMU_PARAMS:
2409	drsp.rdata = r_mmu_params.read();
2410	drsp.valid = true;
2411	break;
2412
2413	case iss_t::XTN_MMU_RELEASE:
2414	drsp.rdata = r_mmu_release.read();
2415	drsp.valid = true;
2416	break;
2417
2418	case iss_t::XTN_MMU_WORD_LO:
2419	drsp.rdata = r_mmu_word_lo.read();
2420	drsp.valid = true;
2421	break;
2422
2423	case iss_t::XTN_MMU_WORD_HI:
2424	drsp.rdata = r_mmu_word_hi.read();
2425	drsp.valid = true;
2426	break;
2427
2428	default:
2429	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2430	r_mmu_dbvar = dreq.addr;
2431	drsp.valid = true;
2432	drsp.error = true;
2433	break;
2434	} // end switch xtn_opcode
2435	} // end else
2436	} // end if XTN_READ
2437
2438	// Handling WRITE XTN requests from processor.
2439	// They are not executed in this DCACHE_IDLE state,
2440	// if they require access to the caches or the TLBs
2441	// that are already accessed for speculative read.
2442	// Caches can be invalidated or flushed in user mode,
2443	// and the sync instruction can be executed in user mode
2444	else if (dreq.type == iss_t::XTN_WRITE)
2445	{
2446	int xtn_opcode = (int)dreq.addr/4;
2447	r_dcache_xtn_opcode = xtn_opcode;
2448
2449	// checking processor mode:
2450	if ( (dreq.mode == iss_t::MODE_USER) &&
2451	(xtn_opcode != iss_t:: XTN_SYNC) &&
2452	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2453	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2454	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2455	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2456	{
2457	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2458	r_mmu_dbvar = dreq.addr;
2459	drsp.valid = true;
2460	drsp.error = true;
2461	r_dcache_fsm = DCACHE_IDLE;
2462	}
2463	else
2464	{
2465	switch( xtn_opcode )
2466	{
2467	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2468	r_mmu_ptpr = dreq.wdata;
2469	r_dcache_xtn_req = true;
2470	r_dcache_fsm = DCACHE_XTN_SWITCH;
2471	break;
2472
2473	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2474	r_mmu_mode = dreq.wdata;
2475	drsp.valid = true;
2476	r_dcache_fsm = DCACHE_IDLE;
2477	break;
2478
2479	case iss_t::XTN_DTLB_INVAL: // dtlb access
2480	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2481	break;
2482
2483	case iss_t::XTN_ITLB_INVAL: // itlb access
2484	r_dcache_xtn_req = true;
2485	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2486	break;
2487
2488	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2489	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2490	break;
2491
2492	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2493	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2494	r_dcache_p0_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2495	(paddr_t)r_mmu_word_lo.read();
2496	break;
2497
2498	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2499	r_dcache_flush_count = 0;
2500	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2501	break;
2502
2503	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2504	r_dcache_xtn_req = true;
2505	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2506	break;
2507
2508	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2509	r_dcache_xtn_req = true;
2510	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2511	break;
2512
2513	case iss_t::XTN_ICACHE_FLUSH: // icache access
2514	r_dcache_xtn_req = true;
2515	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2516	break;
2517
2518	case iss_t::XTN_SYNC: // wait until write buffer empty
2519	r_dcache_fsm = DCACHE_XTN_SYNC;
2520	break;
2521
2522	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2523	r_mmu_word_lo = dreq.wdata;
2524	drsp.valid = true;
2525	r_dcache_fsm = DCACHE_IDLE;
2526	break;
2527
2528	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2529	r_mmu_word_hi = dreq.wdata;
2530	drsp.valid = true;
2531	r_dcache_fsm = DCACHE_IDLE;
2532	break;
2533
2534	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2535	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2536	drsp.valid = true;
2537	r_dcache_fsm = DCACHE_IDLE;
2538	break;
2539
2540	default:
2541	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2542	r_mmu_dbvar = dreq.addr;
2543	drsp.valid = true;
2544	drsp.error = true;
2545	r_dcache_fsm = DCACHE_IDLE;
2546	break;
2547	} // end switch xtn_opcode
2548	} // end else
2549	} // end if XTN_WRITE
2550
2551	// Handling read/write processor requests.
2552	// The dtlb and dcache can be activated or not.
2553	// We compute the physical address, the cacheability, and check processor request.
2554	// - If DTLB not activated : cacheability is defined by the segment table,
2555	// the physical address is equal to the virtual address (identity mapping)
2556	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2557	// the physical address is obtained from the TLB, and the U & W bits
2558	// of the PTE are checked.
2559	// The processor request is decoded only if the TLB is not activated or if
2560	// the virtual address hits in tLB and access rights are OK.
2561	// We call the TLB_MISS sub-fsm in case of dtlb miss.
2562	else
2563	{
2564	bool valid_req = false;
2565	bool cacheable = false;
2566	paddr_t paddr = 0;
2567
2568	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2569	{
2570	valid_req = true;
2571
2572	// cacheability
2573	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2574	else cacheable = m_cacheability_table[dreq.addr];
2575
2576	// physical address
2577	paddr = (paddr_t)dreq.addr;
2578	}
2579	else // dtlb activated
2580	{
2581	if ( tlb_hit ) // tlb hit
2582	{
2583	// cacheability
2584	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2585	else cacheable = tlb_flags.c;
2586
2587	// access rights checking
2588	if ( not tlb_flags.u and (dreq.mode == iss_t::MODE_USER))
2589	{
2590	if ( (dreq.type == iss_t::DATA_READ) or (dreq.type == iss_t::DATA_LL) )
2591	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2592	else
2593	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2594
2595	r_mmu_dbvar = dreq.addr;
2596	drsp.valid = true;
2597	drsp.error = true;
2598	drsp.rdata = 0;
2599	}
2600	else if ( not tlb_flags.w and
2601	((dreq.type == iss_t::DATA_WRITE) or
2602	(dreq.type == iss_t::DATA_SC)) )
2603	{
2604	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2605	r_mmu_dbvar = dreq.addr;
2606	drsp.valid = true;
2607	drsp.error = true;
2608	drsp.rdata = 0;
2609	}
2610	else
2611	{
2612	valid_req = true;
2613	}
2614
2615	// physical address
2616	paddr = tlb_paddr;
2617	}
2618	else // tlb miss
2619	{
2620	r_dcache_tlb_vaddr = dreq.addr;
2621	r_dcache_tlb_ins = false;
2622	r_dcache_fsm = DCACHE_TLB_MISS;
2623	}
2624	} // end DTLB activated
2625
2626	if ( valid_req ) // processor request is valid
2627	{
2628	// physical address and cacheability registration
2629	r_dcache_p0_paddr = paddr;
2630	r_dcache_p0_cacheable = cacheable;
2631
2632	// READ or LL request
2633	// The read requests are taken only if the write pipe-line is empty.
2634	// If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle.
2635	// If speculative access is KO we just pay one extra cycle.
2636	// If dcache miss, we go to DCACHE_MISS_VICTIM state.
2637	// If uncacheable, we go to DCACHE_UNC_WAIT state.
2638	if ( ((dreq.type == iss_t::DATA_READ) or (dreq.type == iss_t::DATA_LL)) and
2639	not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2640	{
2641	if ( cacheable ) // cacheable read
2642	{
2643	// if the speculative access is illegal, we pay an extra cycle
2644	if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK)
2645	!= (paddr & ~PAGE_K_MASK))
2646	{
2647	#ifdef INSTRUMENTATION
2648	m_cpt_dcache_spec_miss++;
2649	#endif
2650	}
2651	// if cache miss, try to get the missing line
2652	else if ( not cache_hit )
2653	{
2654	#ifdef INSTRUMENTATION
2655	m_cpt_dcache_miss++;
2656	#endif
2657	// blocked in IDLE state if previous cleanup not completed
2658	if ( not r_dcache_cleanup_req.read() )
2659	{
2660	r_dcache_vci_paddr = paddr;
2661	r_dcache_vci_miss_req = true;
2662	r_dcache_miss_type = PROC_MISS;
2663	r_dcache_fsm = DCACHE_MISS_VICTIM;
2664	}
2665	}
2666	// if cache hit return the data
2667	else
2668	{
2669	#ifdef INSTRUMENTATION
2670	m_cpt_data_read++;
2671	#endif
2672	drsp.valid = true;
2673	drsp.rdata = cache_rdata;
2674	}
2675	}
2676	else // uncacheable read
2677	{
2678	r_dcache_vci_paddr = paddr;
2679	r_dcache_vci_unc_be = dreq.be;
2680	r_dcache_vci_unc_req = true;
2681	r_dcache_fsm = DCACHE_UNC_WAIT;
2682	}
2683
2684	// makes reservation in case of LL
2685	if ( dreq.type == iss_t::DATA_LL )
2686	{
2687	r_dcache_ll_valid = true;
2688	r_dcache_ll_data = cache_rdata;
2689	r_dcache_ll_vaddr = dreq.addr;
2690	}
2691	} // end READ or LL
2692
2693	// WRITE request:
2694	// The write request arguments have been registered.
2695	// The physical address has been computed and registered.
2696	// We acknowledge the processor request and activate the P1 pipeline stage.
2697	else if ( dreq.type == iss_t::DATA_WRITE )
2698	{
2699
2700	#ifdef INSTRUMENTATION
2701	m_cpt_data_write++;
2702	#endif
2703	p0_valid = true;
2704	drsp.valid = true;
2705	drsp.rdata = 0;
2706	} // end WRITE
2707
2708	// SC request:
2709	// - if a valid LL reservation (with the same address) is registered,
2710	// we request a SC transaction to CMD FSM and go to the DCACHE_SC_WAIT state
2711	// that will directly return the response to the processor, and invalidate
2712	// the LL reservation. We don't check a possible hit in dcache, as this is
2713	// done by the coherence transaction...
2714	// - if there is no registerd LL, we just stay in IDLE state, invalidate
2715	// the LL reservation, and return 1 (atomic access failed)
2716	else if ( dreq.type == iss_t::DATA_SC )
2717	{
2718	#ifdef INSTRUMENTATION
2719	m_cpt_data_sc++;
2720	#endif
2721	// test if valid registered LL
2722	if ( r_dcache_ll_valid.read() and (r_dcache_ll_vaddr.read() == dreq.addr))
2723	{
2724	r_dcache_vci_paddr = paddr;
2725	r_dcache_vci_sc_req = true;
2726	r_dcache_vci_sc_old = r_dcache_ll_data.read();
2727	r_dcache_vci_sc_new = dreq.wdata;
2728	r_dcache_fsm = DCACHE_UNC_WAIT;
2729	}
2730	else // no registered LL
2731	{
2732	drsp.valid = true;
2733	drsp.rdata = 1;
2734	r_dcache_ll_valid = false;
2735	}
2736	} // end SC
2737	} // end valid_req
2738	} // end if read/write request
2739	} // end P0 pipe stage
2740
2741	r_dcache_p0_valid = p0_valid;
2742	break;
2743	}
2744	/////////////////////
2745	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling tlb miss.
2746	// - Input arguments are r_dcache_tlb_vaddr & r_dcache_tlb_ins
2747	// - It try to find the missing TLB entry in dcache,
2748	// and activates the cache miss procedure in case of miss.
2749	// - It bypass the first level page table access if possible.
2750	// - It uses atomic access to update the R/L access bits
2751	// in the page table if required.
2752	// - It directly updates the itlb or dtlb, and writes into the
2753	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2754	{
2755	uint32_t ptba = 0;
2756	bool bypass;
2757	paddr_t paddr;
2758
2759	// evaluate bypass in order to skip first level page table access
2760	if ( r_dcache_tlb_ins.read() ) // itlb miss
2761	{
2762	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2763	}
2764	else // dtlb miss
2765	{
2766	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2767	}
2768
2769	if ( not bypass ) // Try to read the PTE1/PTD1 in dcache
2770	{
2771	paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2772	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2773	r_dcache_tlb_paddr = paddr;
2774	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2775	}
2776	else // Try to read directly the PTE2 in dcache
2777	{
2778	paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2779	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2780	r_dcache_tlb_paddr = paddr;
2781	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2782	}
2783
2784	#if DEBUG_DCACHE
2785	if ( m_debug_dcache_fsm )
2786	{
2787	if ( r_dcache_tlb_ins.read() )
2788	std::cout << " <PROC.DCACHE_TLB_MISS> ITLB miss request:";
2789	else
2790	std::cout << " <PROC.DCACHE_TLB_MISS> DTLB miss request:";
2791	std::cout << " vaddr = " << std::hex << r_dcache_tlb_vaddr.read()
2792	<< " / bypass = " << bypass
2793	<< " / PTE address = " << paddr << std::endl;
2794	}
2795	#endif
2796
2797	break;
2798	}
2799	/////////////////////////
2800	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2801	{
2802	uint32_t entry;
2803	size_t way;
2804	size_t set;
2805	size_t word;
2806
2807	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2808	&entry,
2809	&way,
2810	&set,
2811	&word );
2812	#ifdef INSTRUMENTATION
2813	m_cpt_dcache_data_read++;
2814	m_cpt_dcache_dir_read++;
2815	#endif
2816	if ( hit ) // request hit in dcache
2817	{
2818	if ( not (entry & PTE_V_MASK) ) // unmapped
2819	{
2820	if ( r_dcache_tlb_ins.read() )
2821	{
2822	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2823	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2824	r_icache_tlb_miss_req = false;
2825	r_icache_tlb_rsp_error = true;
2826	}
2827	else
2828	{
2829	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2830	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2831	drsp.valid = true;
2832	drsp.error = true;
2833	}
2834	r_dcache_fsm = DCACHE_IDLE;
2835
2836	#if DEBUG_DCACHE
2837	if ( m_debug_dcache_fsm )
2838	{
2839	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped:"
2840	<< std::dec << " way = " << way
2841	<< std::dec << " / set = " << set
2842	<< std::dec << " / word = " << word
2843	<< std::hex << " / PTE1 = " << entry << std::endl;
2844	}
2845	#endif
2846
2847	}
2848	else if( entry & PTE_T_MASK ) // PTD : access PT2
2849	{
2850	// register bypass
2851	if ( r_dcache_tlb_ins.read() ) // itlb
2852	{
2853	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2854	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2855	r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2)));
2856	}
2857	else // dtlb
2858	{
2859	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2860	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2861	r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2));
2862	}
2863	r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2864	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2865	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2866
2867	#if DEBUG_DCACHE
2868	if ( m_debug_dcache_fsm )
2869	{
2870	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache "
2871	<< std::dec << " way = " << way
2872	<< std::dec << " / set = " << set
2873	<< std::dec << " / word = " << word
2874	<< std::hex << " / PTD = " << entry << std::endl;
2875	}
2876	#endif
2877	}
2878	else // PTE1 : update the TLB
2879	{
2880	if ( r_dcache_tlb_ins.read() )
2881	r_dcache_in_itlb[m_icache_sets*way+set] = true;
2882	else
2883	r_dcache_in_dtlb[m_dcache_sets*way+set] = true;
2884	r_dcache_tlb_pte_flags = entry;
2885	r_dcache_tlb_cache_way = way;
2886	r_dcache_tlb_cache_set = set;
2887	r_dcache_tlb_cache_word = word;
2888	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2889
2890	#if DEBUG_DCACHE
2891	if ( m_debug_dcache_fsm )
2892	{
2893	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache:"
2894	<< std::dec << " way = " << way
2895	<< std::dec << " / set = " << set
2896	<< std::dec << " / word = " << word
2897	<< std::hex << " / PTE1 = " << entry << std::endl;
2898	}
2899	#endif
2900	}
2901	}
2902	else // we must load the missing cache line in dcache
2903	{
2904	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2905	r_dcache_miss_type = PTE1_MISS;
2906	r_dcache_fsm = DCACHE_MISS_VICTIM;
2907	r_dcache_vci_miss_req = true;
2908
2909	#if DEBUG_DCACHE
2910	if ( m_debug_dcache_fsm )
2911	{
2912	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:"
2913	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2914	}
2915	#endif
2916	}
2917	break;
2918	}
2919	////////////////////////////
2920	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2921	{
2922	size_t way;
2923	size_t set;
2924
2925	if ( r_dcache_tlb_ins.read() )
2926	{
2927	r_itlb.select( r_dcache_tlb_vaddr.read(),
2928	true, // PTE1
2929	&way,
2930	&set );
2931	#ifdef INSTRUMENTATION
2932	m_cpt_itlb_read++;
2933	#endif
2934	}
2935	else
2936	{
2937	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2938	true, // PTE1
2939	&way,
2940	&set );
2941	#ifdef INSTRUMENTATION
2942	m_cpt_dtlb_read++;
2943	#endif
2944	}
2945	r_dcache_tlb_way = way;
2946	r_dcache_tlb_set = set;
2947	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
2948
2949	#if DEBUG_DCACHE
2950	if ( m_debug_dcache_fsm )
2951	{
2952	if ( r_dcache_tlb_ins.read() )
2953	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
2954	else
2955	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
2956	std::cout << " way = " << std::dec << way
2957	<< " / set = " << set << std::endl;
2958	}
2959	#endif
2960	break;
2961	}
2962	//////////////////////////
2963	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
2964	// if L/R bit already set, exit the sub-fsm
2965	// if not, the page table must be updated
2966	{
2967	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
2968	uint32_t pte = r_dcache_tlb_pte_flags.read();
2969	bool updt = false;
2970
2971	// test the access bits L/R, depending on the physical address locality
2972	// we must use the 10 MSB bits of the 19 bits PPN1 to obtain the target index
2973	// we must use the 10 MSB bits of the SRCID to obtain the local index
2974	// set the r_dcache_vci_sc_old and r_dcache_vci_sc_new registers if SC required
2975
2976	uint32_t target = (pte >> 9) & 0x3FF;
2977	uint32_t local = m_srcid_d >> 4;
2978
2979	if ( local == target ) // local_address
2980	{
2981	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
2982	{
2983	updt = true;
2984	r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read();
2985	r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() \| PTE_L_MASK;
2986	}
2987	}
2988	else // remote address
2989	{
2990	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
2991	{
2992	updt = true;
2993	r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read();
2994	r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() \| PTE_R_MASK;
2995	}
2996	}
2997
2998	// update TLB
2999	if ( r_dcache_tlb_ins.read() )
3000	{
3001	r_itlb.write( pte,
3002	r_dcache_tlb_vaddr.read(),
3003	r_dcache_tlb_way.read(),
3004	r_dcache_tlb_set.read(),
3005	nline );
3006	#ifdef INSTRUMENTATION
3007	m_cpt_itlb_write++;
3008	#endif
3009	}
3010	else
3011	{
3012	r_dtlb.write( pte,
3013	r_dcache_tlb_vaddr.read(),
3014	r_dcache_tlb_way.read(),
3015	r_dcache_tlb_set.read(),
3016	nline );
3017	#ifdef INSTRUMENTATION
3018	m_cpt_dtlb_write++;
3019	#endif
3020	}
3021	// next state
3022	if ( updt ) r_dcache_fsm = DCACHE_TLB_SC_UPDT; // dcache and page table update
3023	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3024
3025	#if DEBUG_DCACHE
3026	if ( m_debug_dcache_fsm )
3027	{
3028	if ( r_dcache_tlb_ins.read() )
3029	{
3030	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB:";
3031	std::cout << " way = " << std::dec << r_dcache_tlb_way.read()
3032	<< " / set = " << r_dcache_tlb_set.read() << std::endl;
3033	r_itlb.print();
3034	}
3035	else
3036	{
3037	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB:";
3038	std::cout << " way = " << std::dec << r_dcache_tlb_way.read()
3039	<< " / set = " << r_dcache_tlb_set.read() << std::endl;
3040	r_dtlb.print();
3041	}
3042
3043	}
3044	#endif
3045	break;
3046	}
3047	/////////////////////////
3048	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3049	{
3050	uint32_t pte_flags;
3051	uint32_t pte_ppn;
3052	size_t way;
3053	size_t set;
3054	size_t word;
3055
3056	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
3057	&pte_flags,
3058	&pte_ppn,
3059	&way,
3060	&set,
3061	&word );
3062	#ifdef INSTRUMENTATION
3063	m_cpt_dcache_data_read++;
3064	m_cpt_dcache_dir_read++;
3065	#endif
3066	if ( hit ) // request hits in dcache
3067	{
3068	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3069	{
3070	if ( r_dcache_tlb_ins.read() )
3071	{
3072	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3073	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3074	r_icache_tlb_miss_req = false;
3075	r_icache_tlb_rsp_error = true;
3076	}
3077	else
3078	{
3079	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3080	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3081	drsp.valid = true;
3082	drsp.error = true;
3083	}
3084	r_dcache_fsm = DCACHE_IDLE;
3085
3086	#if DEBUG_DCACHE
3087	if ( m_debug_dcache_fsm )
3088	{
3089	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3090	<< " PTE_FLAGS = " << std::hex << pte_flags
3091	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3092	}
3093	#endif
3094	}
3095	else // mapped : update the TLB
3096	{
3097	if ( r_dcache_tlb_ins.read() ) r_dcache_in_itlb[m_icache_sets*way+set] = true;
3098	else r_dcache_in_dtlb[m_dcache_sets*way+set] = true;
3099	r_dcache_tlb_pte_flags = pte_flags;
3100	r_dcache_tlb_pte_ppn = pte_ppn;
3101	r_dcache_tlb_cache_way = way;
3102	r_dcache_tlb_cache_set = set;
3103	r_dcache_tlb_cache_word = word;
3104	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3105
3106	#if DEBUG_DCACHE
3107	if ( m_debug_dcache_fsm )
3108	{
3109	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:"
3110	<< " PTE_FLAGS = " << std::hex << pte_flags
3111	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3112	}
3113	#endif
3114	}
3115	}
3116	else // we must load the missing cache line in dcache
3117	{
3118	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3119	r_dcache_miss_type = PTE2_MISS;
3120	r_dcache_fsm = DCACHE_MISS_VICTIM;
3121	r_dcache_vci_miss_req = true;
3122
3123	#if DEBUG_DCACHE
3124	if ( m_debug_dcache_fsm )
3125	{
3126	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:"
3127	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3128	}
3129	#endif
3130	}
3131	break;
3132	}
3133	////////////////////////////
3134	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3135	{
3136	size_t way;
3137	size_t set;
3138
3139	if ( r_dcache_tlb_ins.read() )
3140	{
3141	r_itlb.select( r_dcache_tlb_vaddr.read(),
3142	false, // PTE2
3143	&way,
3144	&set );
3145	#ifdef INSTRUMENTATION
3146	m_cpt_itlb_read++;
3147	#endif
3148	}
3149	else
3150	{
3151	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3152	false, // PTE2
3153	&way,
3154	&set );
3155	#ifdef INSTRUMENTATION
3156	m_cpt_dtlb_read++;
3157	#endif
3158	}
3159	r_dcache_tlb_way = way;
3160	r_dcache_tlb_set = set;
3161	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3162	break;
3163	}
3164	//////////////////////////
3165	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3166	// if L/R bit already set exit the sub-fsm
3167	// if not, the page table must be updated by an atomic access
3168	{
3169	paddr_t nline = r_dcache_p0_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3170	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3171	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3172	bool updt = false; // page table update required
3173
3174	// test the access bit L/R, depending on the physical address locality
3175	// we must use the 10 MSB bits of the 28 bits PPN2 to obtain the target cluster index
3176	// we must use the 10 MSB bits of the SRCID to obtain the local cluster index
3177	// set the r_dcache_vci_sc_old and r_dcache_vci_sc_new registers if SC required.
3178
3179	uint32_t target = (pte_ppn >> 18) & 0x3FF;
3180	uint32_t local = m_srcid_d >> 4;
3181
3182	if ( local == target ) // local address
3183	{
3184	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3185	{
3186	updt = true;
3187	r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read();
3188	r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() \| PTE_L_MASK;
3189	}
3190	}
3191	else // remote address
3192	{
3193	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3194	{
3195	updt = true;
3196	r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read();
3197	r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() \| PTE_R_MASK;
3198	}
3199	}
3200
3201	// update TLB for a PTE2
3202	if ( r_dcache_tlb_ins.read() )
3203	{
3204	r_itlb.write( pte_flags,
3205	pte_ppn,
3206	r_dcache_tlb_vaddr.read(),
3207	r_dcache_tlb_way.read(),
3208	r_dcache_tlb_set.read(),
3209	nline );
3210	#ifdef INSTRUMENTATION
3211	m_cpt_itlb_write++;
3212	#endif
3213	}
3214	else
3215	{
3216	r_dtlb.write( pte_flags,
3217	pte_ppn,
3218	r_dcache_tlb_vaddr.read(),
3219	r_dcache_tlb_way.read(),
3220	r_dcache_tlb_set.read(),
3221	nline );
3222	#ifdef INSTRUMENTATION
3223	m_cpt_dtlb_write++;
3224	#endif
3225	}
3226
3227	#if DEBUG_DCACHE
3228	if ( m_debug_dcache_fsm )
3229	{
3230	if ( r_dcache_tlb_ins.read() )
3231	{
3232	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB:";
3233	std::cout << " way = " << std::dec << r_dcache_tlb_way.read()
3234	<< " / set = " << r_dcache_tlb_set.read() << std::endl;
3235	r_itlb.print();
3236	}
3237	else
3238	{
3239	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB:";
3240	std::cout << " way = " << std::dec << r_dcache_tlb_way.read()
3241	<< " / set = " << r_dcache_tlb_set.read() << std::endl;
3242	r_dtlb.print();
3243	}
3244	}
3245	#endif
3246	// next state
3247	if ( updt ) r_dcache_fsm = DCACHE_TLB_SC_UPDT; // dcache and page table update
3248	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3249	break;
3250	}
3251	////////////////////////
3252	case DCACHE_TLB_SC_UPDT: // update the dcache after a tlb miss (L/R bit),
3253	// request a SC transaction to CMD FSM
3254	{
3255	r_dcache.write(r_dcache_tlb_cache_way.read(),
3256	r_dcache_tlb_cache_set.read(),
3257	r_dcache_tlb_cache_word.read(),
3258	r_dcache_tlb_pte_flags.read());
3259	#ifdef INSTRUMENTATION
3260	m_cpt_dcache_data_write++;
3261	#endif
3262	// r_dcache_vci_sc_old & r_dcache_vci_sc_new registers are already set
3263	r_dcache_vci_sc_req = true;
3264	r_dcache_fsm = DCACHE_TLB_SC_WAIT;
3265	break;
3266	}
3267	////////////////////////
3268	case DCACHE_TLB_SC_WAIT: // wait response to SC transaction from RSP FSM
3269	// we consume the response, and exit the sub-fsm.
3270	// we don't analyse the response, because
3271	// we don't care if the L/R bit update is not done
3272	{
3273	if ( not r_dcache_vci_sc_req.read() ) // response available
3274	{
3275	if ( r_vci_rsp_data_error.read() ) r_vci_rsp_data_error = false;
3276	else if ( r_vci_rsp_fifo_dcache.rok() ) vci_rsp_fifo_dcache_get = true;
3277	else
3278	{
3279	assert( false and "rsp_fifo should not be empty in DCACHE_TLB_SC_WAIT state" );
3280	}
3281	r_dcache_fsm = DCACHE_TLB_RETURN;
3282	}
3283	break;
3284	}
3285	///////////////////////
3286	case DCACHE_TLB_RETURN: // return to caller state depending on the tlb miss type
3287	{
3288	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3289	r_dcache_fsm = DCACHE_IDLE;
3290	break;
3291	}
3292	///////////////////////
3293	case DCACHE_XTN_SWITCH: // Both itlb and dtlb must be flushed
3294	{
3295	if ( r_dcache_xtn_req.read() )
3296	{
3297	r_dtlb.flush();
3298	r_dcache_fsm = DCACHE_IDLE;
3299	drsp.valid = true;
3300	}
3301	break;
3302	}
3303	/////////////////////
3304	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3305	{
3306	if ( r_wbuf.empty() )
3307	{
3308	drsp.valid = true;
3309	r_dcache_fsm = DCACHE_IDLE;
3310	}
3311	break;
3312	}
3313	////////////////////////
3314	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3315	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3316	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3317	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss...
3318	{
3319	// external coherence request
3320	if ( r_tgt_dcache_req )
3321	{
3322	r_dcache_fsm = DCACHE_CC_CHECK;
3323	r_dcache_fsm_save = r_dcache_fsm;
3324	break;
3325	}
3326
3327	// itlb miss request
3328	if ( r_icache_tlb_miss_req.read() )
3329	{
3330	r_dcache_tlb_ins = true;
3331	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3332	r_dcache_fsm = DCACHE_TLB_MISS;
3333	break;
3334	}
3335
3336	// test if XTN request to icache completed
3337	if ( not r_dcache_xtn_req.read() )
3338	{
3339	r_dcache_fsm = DCACHE_IDLE;
3340	drsp.valid = true;
3341	}
3342	break;
3343	}
3344	/////////////////////////
3345	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3346	// the r_dcache_flush counter as a slot counter.
3347	// We loop in this state until all slots have been visited.
3348	// A cleanup request is generated for each valid line
3349	// and we are blocked until the previous cleanup is completed
3350	// Finally, both the itlb and dtlb are reset, because
3351	// all TLB entries (including global entries) must be invalidated.
3352	{
3353	if ( not r_dcache_cleanup_req )
3354	{
3355	paddr_t nline;
3356	size_t way = r_dcache_flush_count.read()/m_icache_sets;
3357	size_t set = r_dcache_flush_count.read()%m_icache_sets;
3358
3359	bool cleanup_req = r_dcache.inval( way,
3360	set,
3361	&nline );
3362	if ( cleanup_req )
3363	{
3364	r_dcache_cleanup_req = true;
3365	r_dcache_cleanup_line = nline;
3366	}
3367
3368	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3369
3370	if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last slot
3371	{
3372	r_dtlb.reset(); // global entries are invalidated
3373	r_itlb.reset(); // global entries are invalidated
3374	for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++)
3375	{
3376	r_dcache_in_itlb[line] = false;
3377	r_dcache_in_dtlb[line] = false;
3378	}
3379	r_dcache_fsm = DCACHE_IDLE;
3380	drsp.valid = true;
3381	}
3382	}
3383	break;
3384	}
3385	/////////////////////////
3386	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3387	{
3388	r_dtlb.inval(r_dcache_p0_wdata.read());
3389	r_dcache_fsm = DCACHE_IDLE;
3390	drsp.valid = true;
3391	break;
3392	}
3393	////////////////////////////
3394	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3395	// requires 3 cycles: access tlb, read cache, inval cache
3396	// we compute the physical address in this state
3397	{
3398	paddr_t paddr;
3399	bool hit;
3400
3401	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3402	{
3403	#ifdef INSTRUMENTATION
3404	m_cpt_dtlb_read++;
3405	#endif
3406	hit = r_dtlb.translate( r_dcache_p0_wdata.read(),
3407	&paddr );
3408	}
3409	else // dtlb not activated
3410	{
3411	paddr = (paddr_t)r_dcache_p0_wdata.read();
3412	hit = true;
3413	}
3414
3415	if ( hit ) // tlb hit
3416	{
3417	r_dcache_p0_paddr = paddr;
3418	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3419	}
3420	else // tlb miss
3421	{
3422	#ifdef INSTRUMENTATION
3423	m_cpt_dtlb_miss++;
3424	#endif
3425	r_dcache_tlb_ins = false; // dtlb
3426	r_dcache_tlb_vaddr = r_dcache_p0_wdata.read();
3427	r_dcache_fsm = DCACHE_TLB_MISS;
3428	}
3429	break;
3430	}
3431	////////////////////////////
3432	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3433	// requires 2 cycles: read cache / inval cache
3434	// In this state we read dcache.
3435	{
3436	uint32_t data;
3437	size_t way;
3438	size_t set;
3439	size_t word;
3440	bool hit = r_dcache.read( r_dcache_p0_paddr.read(),
3441	&data,
3442	&way,
3443	&set,
3444	&word );
3445	#ifdef INSTRUMENTATION
3446	m_cpt_dcache_data_read++;
3447	m_cpt_dcache_dir_read++;
3448	#endif
3449	if ( hit ) // inval to be done
3450	{
3451	r_dcache_xtn_way = way;
3452	r_dcache_xtn_set = set;
3453	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3454	}
3455	else // miss : nothing to do
3456	{
3457	r_dcache_fsm = DCACHE_IDLE;
3458	drsp.valid = true;
3459	}
3460	break;
3461	}
3462	////////////////////////////
3463	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line & cleanup
3464	// Blocked if previous cleanup not completed
3465
3466	{
3467	if ( not r_dcache_cleanup_req.read() )
3468	{
3469	paddr_t nline;
3470	size_t way = r_dcache_xtn_way.read();
3471	size_t set = r_dcache_xtn_set.read();
3472	bool inval_tlb = false;
3473
3474	r_icache.inval( way,
3475	set,
3476	&nline );
3477
3478	// request cleanup
3479	r_dcache_cleanup_req = true;
3480	r_dcache_cleanup_line = nline;
3481
3482	// possible itlb & dtlb invalidate requests
3483	r_dcache_tlb_inval_line = nline;
3484
3485	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and
3486	r_dcache_in_dtlb[way*m_dcache_sets+set] )
3487	{
3488	r_dcache_dtlb_inval_req = true;
3489	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
3490	inval_tlb = true;
3491	}
3492	if ( (r_mmu_mode.read() & INS_TLB_MASK) and
3493	r_dcache_in_itlb[m_dcache_sets*way+set] )
3494	{
3495	r_dcache_itlb_inval_req = true;
3496	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
3497	inval_tlb = true;
3498	}
3499
3500	// no valid response until itlb & dtlb invalidated
3501	if (inval_tlb )
3502	{
3503	r_dcache_fsm = DCACHE_XTN_DC_INVAL_WAIT;
3504	}
3505	else
3506	{
3507	r_dcache_fsm = DCACHE_IDLE;
3508	drsp.valid = true;
3509	}
3510	}
3511	break;
3512	}
3513	//////////////////////////////
3514	case DCACHE_XTN_DC_INVAL_WAIT: // waiting completion of itlb and dtlb invalidate
3515	{
3516	if ( not (r_dcache_itlb_inval_req.read() or r_dcache_dtlb_inval_req.read()) )
3517	{
3518	r_dcache_fsm = DCACHE_IDLE;
3519	drsp.valid = true;
3520	}
3521	break;
3522	}
3523	////////////////////////
3524	case DCACHE_MISS_VICTIM: // Selects a victim line
3525	// Set the r_dcache_cleanup_req flip-flop
3526	// when the selected slot is not empty
3527	{
3528	bool valid;
3529	size_t way;
3530	size_t set;
3531	paddr_t victim;
3532
3533	valid = r_dcache.victim_select( r_dcache_vci_paddr.read(),
3534	&victim,
3535	&way,
3536	&set );
3537	r_dcache_miss_way = way;
3538	r_dcache_miss_set = set;
3539
3540	if ( valid )
3541	{
3542	r_dcache_cleanup_req = true;
3543	r_dcache_cleanup_line = victim;
3544	r_dcache_fsm = DCACHE_MISS_INVAL;
3545	}
3546	else
3547	{
3548	r_dcache_fsm = DCACHE_MISS_WAIT;
3549	}
3550
3551	#if DEBUG_DCACHE
3552	if ( m_debug_dcache_fsm )
3553	{
3554	std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:"
3555	<< " / way = " << way
3556	<< " / set = " << set
3557	<< " / valid = " << valid
3558	<< " / line = " << victim << std::endl;
3559	}
3560	#endif
3561	break;
3562	}
3563	///////////////////////
3564	case DCACHE_MISS_INVAL: // invalidate the victim line
3565	// and possibly request itlb or dtlb invalidate
3566	{
3567	paddr_t nline;
3568	size_t way = r_dcache_miss_way.read();
3569	size_t set = r_dcache_miss_way.read();
3570
3571	r_dcache.inval( way,
3572	set,
3573	&nline );
3574
3575	// if itlb & dtlb invalidate are required
3576	// the miss response is not handled before invalidate completed
3577	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and
3578	( r_dcache_in_itlb[way*m_dcache_sets+set] or
3579	r_dcache_in_dtlb[m_dcache_sets*way+set] ) )
3580	{
3581	r_dcache_tlb_inval_line = r_dcache_vci_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3582	r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
3583	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
3584	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
3585	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
3586	r_dcache_fsm = DCACHE_MISS_INVAL_WAIT;
3587	}
3588	else
3589	{
3590	r_dcache_fsm = DCACHE_MISS_WAIT;
3591	}
3592	break;
3593	}
3594	////////////////////////////
3595	case DCACHE_MISS_INVAL_WAIT: // waiting completion of itlb / dtlb invalidate
3596	{
3597	if ( (not r_dcache_itlb_inval_req.read()) or (not r_dcache_dtlb_inval_req.read()) )
3598	{
3599	r_dcache_fsm = DCACHE_MISS_WAIT;
3600	}
3601	break;
3602	}
3603	//////////////////////
3604	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3605	// This state is in charge of error signaling
3606	// There is 5 types of error depending on the requester
3607	{
3608	// external coherence request
3609	if ( r_tgt_dcache_req )
3610	{
3611	r_dcache_fsm = DCACHE_CC_CHECK;
3612	r_dcache_fsm_save = r_dcache_fsm;
3613	break;
3614	}
3615
3616	if ( r_vci_rsp_data_error.read() ) // bus error
3617	{
3618	switch ( r_dcache_miss_type.read() )
3619	{
3620	case PROC_MISS:
3621	{
3622	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3623	r_mmu_dbvar = r_dcache_p0_vaddr.read();
3624	drsp.valid = true;
3625	drsp.error = true;
3626	r_dcache_fsm = DCACHE_IDLE;
3627	break;
3628	}
3629	case PTE1_MISS:
3630	{
3631	if ( r_dcache_tlb_ins.read() )
3632	{
3633	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3634	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3635	r_icache_tlb_miss_req = false;
3636	r_icache_tlb_rsp_error = true;
3637	}
3638	else
3639	{
3640	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3641	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3642	drsp.valid = true;
3643	drsp.error = true;
3644	}
3645	r_dcache_fsm = DCACHE_IDLE;
3646	break;
3647	}
3648	case PTE2_MISS:
3649	{
3650	if ( r_dcache_tlb_ins.read() )
3651	{
3652	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3653	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3654	r_icache_tlb_miss_req = false;
3655	r_icache_tlb_rsp_error = true;
3656	}
3657	else
3658	{
3659	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3660	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3661	drsp.valid = true;
3662	drsp.error = true;
3663	}
3664	r_dcache_fsm = DCACHE_IDLE;
3665	break;
3666	}
3667	} // end switch type
3668	r_vci_rsp_data_error = false;
3669	}
3670	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3671	{
3672	r_dcache_miss_word = 0;
3673	r_dcache_fsm = DCACHE_MISS_UPDT;
3674	}
3675	break;
3676	}
3677	//////////////////////
3678	case DCACHE_MISS_UPDT: // update the dcache (one word per cycle)
3679	// returns the response depending on the miss type
3680	{
3681	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3682	{
3683	if ( r_dcache_miss_inval.read() ) // Matching coherence request
3684	// pop the FIFO, without cache update
3685	// send a cleanup for the missing line
3686	// if the previous cleanup is completed
3687	{
3688	if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last
3689	{
3690	vci_rsp_fifo_dcache_get = true;
3691	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3692	}
3693	else // last word
3694	{
3695	if ( not r_dcache_cleanup_req.read() ) // no pending cleanup
3696	{
3697	vci_rsp_fifo_dcache_get = true;
3698	r_dcache_cleanup_req = true;
3699	r_dcache_cleanup_line = r_dcache_vci_paddr.read() >>
3700	(uint32_log2(m_dcache_words)+2);
3701	r_dcache_miss_inval = false;
3702	r_dcache_fsm = DCACHE_IDLE;
3703	}
3704	}
3705	}
3706	else // No matching coherence request
3707	// pop the FIFO and update the cache
3708	// update the directory at the last word
3709	// send a response to ICACHE FSM
3710	// in case of itlb miss
3711	{
3712
3713	#ifdef INSTRUMENTATION
3714	m_cpt_dcache_data_write++;
3715	#endif
3716	r_dcache.write( r_dcache_miss_way.read(),
3717	r_dcache_miss_set.read(),
3718	r_dcache_miss_word.read(),
3719	r_vci_rsp_fifo_dcache.read());
3720
3721	vci_rsp_fifo_dcache_get = true;
3722	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3723
3724	// if last word, update directory, set in_itlb & in_dtlb bits
3725	if ( r_dcache_miss_word.read() == (m_dcache_words - 1) )
3726	{
3727
3728	#ifdef INSTRUMENTATION
3729	m_cpt_dcache_dir_write++;
3730	#endif
3731	r_dcache.victim_update_tag( r_dcache_vci_paddr.read(),
3732	r_dcache_miss_way.read(),
3733	r_dcache_miss_set.read() );
3734
3735	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3736	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3737	else r_dcache_fsm = DCACHE_IDLE;
3738	}
3739	}
3740
3741	#if DEBUG_DCACHE
3742	if ( m_debug_dcache_fsm )
3743	{
3744	if ( r_dcache_miss_inval.read() )
3745	{
3746	if ( r_dcache_miss_word.read() < m_dcache_words-1 )
3747	{
3748	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3749	<< " pop the FIFO, don't update the cache" << std::endl;
3750	}
3751	else
3752	{
3753	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3754	<< " last word : send a cleanup request " << std::endl;
3755	}
3756	}
3757	else
3758	{
3759	std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:"
3760	<< " address = " << r_dcache_vci_paddr.read()
3761	<< " / data = " << r_vci_rsp_fifo_dcache.read()
3762	<< " / way = " << r_dcache_miss_way.read()
3763	<< " / set = " << r_dcache_miss_set.read()
3764	<< " / word = " << r_dcache_miss_word.read() << std::endl;
3765	}
3766	}
3767	#endif
3768
3769	} // end if rok
3770	break;
3771	}
3772	/////////////////////
3773	case DCACHE_UNC_WAIT:
3774	{
3775	// external coherence request
3776	if ( r_tgt_dcache_req.read() )
3777	{
3778	r_dcache_fsm = DCACHE_CC_CHECK;
3779	r_dcache_fsm_save = r_dcache_fsm;
3780	break;
3781	}
3782
3783	if ( r_vci_rsp_data_error.read() ) // bus error
3784	{
3785	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3786	r_mmu_dbvar = dreq.addr;
3787	r_vci_rsp_data_error = false;
3788	drsp.error = true;
3789	drsp.valid = true;
3790	r_dcache_fsm = DCACHE_IDLE;
3791	break;
3792	}
3793	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
3794	{
3795	vci_rsp_fifo_dcache_get = true;
3796	r_dcache_fsm = DCACHE_IDLE;
3797	// we acknowledge the processor request if it has not been modified
3798	if ( dreq.valid and (dreq.addr == r_dcache_p0_vaddr.read()) )
3799	{
3800	drsp.valid = true;
3801	drsp.rdata = r_vci_rsp_fifo_dcache.read();
3802	}
3803	}
3804	break;
3805	}
3806	////////////////////////////
3807	case DCACHE_WRITE_TLB_DIRTY: // set PTE dirty bit in dtlb
3808	{
3809	// set dirty bit in dtlb
3810	r_dtlb.set_dirty( r_dcache_p2_tlb_way.read(),
3811	r_dcache_p2_tlb_set.read() );
3812
3813	// get PTE in dcache
3814	uint32_t pte_flags = 0;
3815	size_t way;
3816	size_t set;
3817	size_t word;
3818	bool hit = r_dcache.read( r_dcache_p2_pte_paddr.read(),
3819	&pte_flags,
3820	&way,
3821	&set,
3822	&word );
3823	#ifdef INSTRUMENTATION
3824	m_cpt_dcache_data_read++;
3825	m_cpt_dcache_dir_read++;
3826	#endif;
3827
3828	#if DEBUG_DCACHE
3829	if ( m_debug_dcache_fsm )
3830	{
3831	std::cout << " <PROC.DCACHE_WRITE_TLB_DIRTY> Set PTE dirty bit in dtlb:"
3832	<< " paddr = " << r_dcache_p2_pte_paddr.read()
3833	<< " / tlb_way = " << r_dcache_p2_tlb_way.read()
3834	<< " / tlb_set = " << r_dcache_p2_tlb_set.read() << std::endl;
3835	}
3836	#endif
3837	assert( hit and "error in DCACHE_WRITE_TLB_DIRTY: the PTE should be in dcache" );
3838
3839	r_dcache_p2_pte_way = way; // register pte way in dcache
3840	r_dcache_p2_pte_set = set; // register pte set in dcache;
3841	r_dcache_p2_pte_word = word; // register pte word in dcache;
3842	r_dcache_p2_pte_flags = pte_flags; // register pte value
3843	r_dcache_fsm = DCACHE_WRITE_CACHE_DIRTY;
3844	break;
3845	}
3846	//////////////////////////////
3847	case DCACHE_WRITE_CACHE_DIRTY: // set PTE dirty bit in dcache
3848	// request SC tranansaction to CMD FSM
3849	{
3850	// set PTE dirty bit in dcache
3851	r_dcache.write( r_dcache_p2_pte_way.read(),
3852	r_dcache_p2_pte_set.read(),
3853	r_dcache_p2_pte_word.read(),
3854	r_dcache_p2_pte_flags.read() \| PTE_D_MASK,
3855	0xF );
3856
3857	#ifdef INSTRUMENTATION
3858	m_cpt_dcache_data_write++;
3859	#endif
3860
3861	#if DEBUG_DCACHE
3862	if ( m_debug_dcache_fsm )
3863	{
3864	std::cout << " <PROC.DCACHE_WRITE_CACHE_DIRTY> Set PTE dirty bit in dcache:"
3865	<< " / way = " << r_dcache_p2_pte_way.read()
3866	<< " / set = " << r_dcache_p2_pte_set.read()
3867	<< " / word = " << r_dcache_p2_pte_word.read() << std::endl;
3868	}
3869	#endif
3870	// request sc transaction to CMD_FSM
3871	r_dcache_vci_sc_req = true;
3872	r_dcache_vci_sc_old = r_dcache_p2_pte_flags.read();
3873	r_dcache_vci_sc_new = r_dcache_p2_pte_flags.read() \| PTE_D_MASK;
3874	r_dcache_fsm = DCACHE_WRITE_SC_WAIT;
3875	break;
3876	}
3877	//////////////////////////
3878	case DCACHE_WRITE_SC_WAIT: // wait completion of SC
3879	// if atomic, write completed : return to IDLE state
3880	// else, makes an uncacheable read to retry the SC
3881	{
3882	// external coherence request
3883	if ( r_tgt_dcache_req )
3884	{
3885	r_dcache_fsm = DCACHE_CC_CHECK;
3886	r_dcache_fsm_save = r_dcache_fsm;
3887	break;
3888	}
3889
3890	if ( r_vci_rsp_data_error.read() ) // bus error
3891	{
3892	r_mmu_detr = MMU_WRITE_PT2_ILLEGAL_ACCESS;
3893	r_mmu_dbvar = r_dcache_p2_vaddr;
3894	drsp.valid = true;
3895	drsp.error = true;
3896	r_dcache_fsm = DCACHE_IDLE;
3897	break;
3898	}
3899	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3900	{
3901	if ( r_vci_rsp_fifo_dcache.read() == 0 ) // atomic
3902	{
3903	drsp.valid = true; // acknowledge the initial write
3904	r_dcache_fsm = DCACHE_IDLE;
3905	}
3906	else
3907	{
3908	r_dcache_vci_paddr = r_dcache_p2_pte_paddr;
3909	r_dcache_vci_unc_req = true;
3910	r_dcache_vci_unc_be = 0xF;
3911	r_dcache_fsm = DCACHE_WRITE_UNC_WAIT;
3912	}
3913	}
3914	break;
3915	}
3916	///////////////////////////
3917	case DCACHE_WRITE_UNC_WAIT: // wait completion of uncacheable read
3918	// in case of success we retry a SC request to
3919	// set the dirty bit in the PTE
3920	{
3921	// external coherence request
3922	if ( r_tgt_dcache_req )
3923	{
3924	r_dcache_fsm = DCACHE_CC_CHECK;
3925	r_dcache_fsm_save = r_dcache_fsm;
3926	break;
3927	}
3928
3929	if ( r_vci_rsp_data_error.read() ) // bus error
3930	{
3931	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3932	r_mmu_dbvar = r_dcache_p2_vaddr;
3933	drsp.valid = true;
3934	drsp.error = true;
3935	r_dcache_fsm = DCACHE_IDLE;
3936	break;
3937	}
3938	if ( r_vci_rsp_fifo_dcache.rok() ) // PTE available
3939	{
3940	r_dcache_vci_sc_req = true;
3941	r_dcache_vci_sc_old = r_vci_rsp_fifo_dcache.read();
3942	r_dcache_vci_sc_new = r_vci_rsp_fifo_dcache.read() \| PTE_D_MASK;
3943	r_dcache_fsm = DCACHE_WRITE_SC_WAIT;
3944	}
3945	break;
3946	}
3947	/////////////////////
3948	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
3949	// handling coherence requests.
3950	// If there is a matching pending miss on the modified cache
3951	// line this is signaled in the r_dcache_miss inval flip-flop.
3952	// If the updated (or invalidated) cache line has copies in TLBs
3953	// these TLB copies are invalidated.
3954	// The return state is defined in r_dcache_fsm_save
3955	{
3956	paddr_t paddr = r_tgt_paddr.read();
3957	paddr_t mask = ~((m_dcache_words<<2)-1);
3958
3959
3960	if( (r_dcache_fsm_save == DCACHE_MISS_WAIT) and
3961	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss
3962	{
3963	r_dcache_miss_inval = true; // signaling the match
3964	r_tgt_dcache_req = false; // coherence request completed
3965	r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update
3966	r_dcache_fsm = r_dcache_fsm_save;
3967
3968	#if DEBUG_DCACHE
3969	if ( m_debug_dcache_fsm )
3970	{
3971	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:"
3972	<< " address = " << std::hex << paddr << std::endl;
3973	}
3974	#endif
3975
3976	}
3977	else // no match
3978	{
3979	uint32_t rdata;
3980	size_t way;
3981	size_t set;
3982	size_t word;
3983
3984	bool hit = r_dcache.read(paddr,
3985	&rdata, // unused
3986	&way,
3987	&set,
3988	&word); // unused
3989	#ifdef INSTRUMENTATION
3990	m_cpt_dcache_data_read++;
3991	m_cpt_dcache_dir_read++;
3992	#endif
3993	r_dcache_cc_way = way;
3994	r_dcache_cc_set = set;
3995
3996	if ( hit and r_tgt_update.read() ) // hit update
3997	{
3998	r_dcache_fsm = DCACHE_CC_UPDT;
3999	r_dcache_cc_word = r_tgt_word_min.read();
4000	}
4001	else if ( hit and not r_tgt_update.read() ) // hit inval
4002	{
4003	r_dcache_fsm = DCACHE_CC_INVAL;
4004	}
4005	else // miss can happen
4006	{
4007	r_tgt_dcache_req = false;
4008	r_tgt_dcache_rsp = r_tgt_update.read();
4009	r_dcache_fsm = r_dcache_fsm_save.read();
4010	}
4011
4012	#if DEBUG_DCACHE
4013	if ( m_debug_dcache_fsm )
4014	{
4015
4016	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request received :"
4017	<< " address = " << std::hex << paddr << std::dec;
4018	if ( hit )
4019	{
4020	std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl;
4021	}
4022	else
4023	{
4024	std::cout << " / MISS" << std::endl;
4025	}
4026	}
4027	#endif
4028
4029	}
4030	break;
4031	}
4032	/////////////////////
4033	case DCACHE_CC_INVAL: // invalidate one cache line
4034	// and test possible copies in TLBs
4035	{
4036	paddr_t nline;
4037	size_t way = r_dcache_cc_way.read();
4038	size_t set = r_dcache_cc_set.read();
4039	bool inval_tlb = false;
4040
4041	r_dcache.inval( way,
4042	set,
4043	&nline );
4044
4045	// possible itlb & dtlb invalidate requests
4046	r_dcache_tlb_inval_line = nline;
4047
4048	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and
4049	r_dcache_in_dtlb[way*m_dcache_sets+set] )
4050	{
4051	r_dcache_dtlb_inval_req = true;
4052	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4053	inval_tlb = true;
4054	}
4055	if ( (r_mmu_mode.read() & INS_TLB_MASK) and
4056	r_dcache_in_itlb[m_dcache_sets*way+set] )
4057	{
4058	r_dcache_itlb_inval_req = true;
4059	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4060	inval_tlb = true;
4061	}
4062
4063	// no valid response until itlb & dtlb invalidated
4064	if (inval_tlb )
4065	{
4066	r_dcache_fsm = DCACHE_CC_WAIT;
4067	}
4068	else
4069	{
4070	r_tgt_dcache_rsp = true;
4071	r_tgt_dcache_req = false;
4072	r_dcache_fsm = r_dcache_fsm_save.read();
4073	}
4074
4075	#if DEBUG_DCACHE
4076	if ( m_debug_dcache_fsm )
4077	{
4078	std::cout << " <PROC.DCACHE_CC_INVAL> Invalidate cache line :" << std::dec
4079	<< " way = " << way
4080	<< " / set = " << set << std::endl;
4081	}
4082	#endif
4083
4084	break;
4085	}
4086	///////////////////
4087	case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
4088	// and test possible copies in TLBs
4089	{
4090	size_t word = r_dcache_cc_word.read();
4091	size_t way = r_dcache_cc_way.read();
4092	size_t set = r_dcache_cc_set.read();
4093
4094	r_dcache.write( way,
4095	set,
4096	word,
4097	r_tgt_buf[word],
4098	r_tgt_be[word] );
4099	#ifdef INSTRUMENTATION
4100	m_cpt_dcache_data_write++;
4101	#endif
4102	r_dcache_cc_word = word + 1;
4103
4104	if ( word == r_tgt_word_max.read() ) // last word
4105	{
4106	// invalidate copies in TLBs
4107	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and
4108	( r_dcache_in_itlb[way*m_dcache_sets+set] or
4109	r_dcache_in_dtlb[m_dcache_sets*way+set] ) )
4110	{
4111	r_dcache_tlb_inval_line = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
4112	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
4113	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4114	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
4115	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4116	r_dcache_fsm = DCACHE_CC_WAIT;
4117	}
4118	else
4119	{
4120	r_tgt_dcache_rsp = true;
4121	r_tgt_dcache_req = false;
4122	r_dcache_fsm = r_dcache_fsm_save.read();
4123	}
4124	}
4125
4126	#if DEBUG_DCACHE
4127	if ( m_debug_dcache_fsm )
4128	{
4129	std::cout << " <PROC.DCACHE_CC_UPDT> Update one word :" << std::dec
4130	<< " way = " << way
4131	<< " / set = " << set
4132	<< " / word = " << word
4133	<< " / value = " << std::hex << r_tgt_buf[word] << std::endl;
4134	}
4135	#endif
4136
4137	break;
4138	}
4139	////////////////////
4140	case DCACHE_CC_WAIT: // wait completion of TLB invalidate
4141	{
4142	if ( not r_dcache_itlb_inval_req.read() and not r_dcache_dtlb_inval_req.read() )
4143	{
4144	r_tgt_dcache_rsp = true;
4145	r_tgt_dcache_req = false;
4146	r_dcache_fsm = r_dcache_fsm_save.read();
4147	}
4148	}
4149	} // end switch r_dcache_fsm
4150
4151
4152	//////////////////// save DREQ and DRSP fields for print_trace() ////////////////
4153	m_dreq_valid = dreq.valid;
4154	m_dreq_addr = dreq.addr;
4155	m_dreq_mode = dreq.mode;
4156	m_dreq_type = dreq.type;
4157	m_dreq_wdata = dreq.wdata;
4158	m_dreq_be = dreq.be;
4159
4160	m_drsp_valid = drsp.valid;
4161	m_drsp_rdata = drsp.rdata;
4162	m_drsp_error = drsp.error;
4163
4164	///////////////// wbuf update //////////////////////////////////////////////////////
4165	r_wbuf.update();
4166
4167	////////////////////////////////////////////////////////////////////////////////////
4168	// INVAL DTLB FSM
4169	// This FSM works in parallel with the DCACHE FSM.
4170	// When the r_dcache_dtlb_inval_req flip-flop is activated by the DCACHE FSM
4171	// it scans sequencially all entries in the DTLB, and invalidates the
4172	// entries matching the evicted line.
4173	// It signals the completion of invalidation by reseting r_dcache_itlb_inval_req.
4174	////////////////////////////////////////////////////////////////////////////////////
4175
4176	switch(r_inval_dtlb_fsm)
4177	{
4178	/////////////////////
4179	case INVAL_DTLB_IDLE:
4180	{
4181	if ( r_dcache_dtlb_inval_req.read() )
4182	{
4183	r_dtlb.reset_bypass(r_dcache_tlb_inval_line.read());
4184	r_inval_dtlb_count = 0;
4185	r_inval_dtlb_fsm = INVAL_DTLB_SCAN;
4186
4187	#if DEBUG_INVAL_DTLB
4188	if ( m_debug_inval_dtlb_fsm )
4189	{
4190	std::cout << " <PROC.INVAL_DTLB_IDLE> Invalidate request for line "
4191	<< std::hex << r_dcache_tlb_inval_line.read() << std::endl;
4192	r_dtlb.print();
4193	}
4194	#endif
4195	}
4196	break;
4197	}
4198	/////////////////////
4199	case INVAL_DTLB_SCAN:
4200	{
4201	paddr_t line = r_dcache_tlb_inval_line.read(); // nline
4202	size_t way = r_inval_dtlb_count.read()/m_itlb_sets; // way
4203	size_t set = r_inval_dtlb_count.read()%m_itlb_sets; // set
4204
4205	bool ok = r_dtlb.inval( line,
4206	way,
4207	set );
4208
4209	#if DEBUG_INVAL_DTLB
4210	if ( m_debug_inval_dtlb_fsm )
4211	{
4212	std::cout << " <PROC.INVAL_DTLB_SCAN>" << std::hex
4213	<< " line = " << line << std::dec
4214	<< " / set = " << set
4215	<< " / way = " << way;
4216	if ( ok ) std::cout << " / HIT" << std::endl;
4217	else std::cout << " / MISS" << std::endl;
4218	}
4219	#endif
4220
4221	r_inval_dtlb_count = r_inval_dtlb_count.read() + 1;
4222	if ( r_inval_dtlb_count.read() == (m_dtlb_sets*m_dtlb_ways - 1) )
4223	{
4224	r_inval_dtlb_fsm = INVAL_DTLB_IDLE;
4225	r_dcache_dtlb_inval_req = false;
4226	}
4227	break;
4228	}
4229	} // end switch r_inval_dtlb_fsm
4230
4231	/////////// test processor frozen /////////////////////////////////////////////
4232	// The simulation exit if the number of consecutive frozen cycles
4233	// is larger than the m_max_frozen_cycles (constructor parameter)
4234	if ( (ireq.valid and not irsp.valid) or (dreq.valid and not drsp.valid) )
4235	{
4236	m_cpt_frz_cycles++; // used for instrumentation
4237	m_cpt_stop_simulation++; // used for debug
4238	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4239	{
4240	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4241	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4242	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4243	<< std::endl;
4244	exit(1);
4245	}
4246	}
4247	else
4248	{
4249	m_cpt_stop_simulation = 0;
4250	}
4251
4252	/////////// execute one iss cycle /////////////////////////////////
4253	{
4254	uint32_t it = 0;
4255	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4256	r_iss.executeNCycles(1, irsp, drsp, it);
4257	}
4258
4259	////////////////////////////////////////////////////////////////////////////
4260	// The VCI_CMD FSM controls the following ressources:
4261	// - r_vci_cmd_fsm
4262	// - r_vci_cmd_min
4263	// - r_vci_cmd_max
4264	// - r_vci_cmd_cpt
4265	// - r_vci_cmd_imiss_prio
4266	// - wbuf (reset)
4267	// - r_icache_miss_req (reset)
4268	// - r_icache_unc_req (reset)
4269	// - r_dcache_vci_miss_req (reset)
4270	// - r_dcache_vci_unc_req (reset)
4271	// - r_dcache_vci_sc_req (reset)
4272	//
4273	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4274	// There is 6 request types, with the following priorities :
4275	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4276	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4277	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4278	// 4 - Instruction Uncachable : r_icache_unc_req
4279	// 5 - Data Write : r_wbuf.rok()
4280	// 6 - Data Store Conditionnal: r_dcache_vci_sc_req
4281	//
4282	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4283	// and the VCI_RSP_FSM are fully desynchronized.
4284	//
4285	// VCI formats:
4286	// According to the VCI advanced specification, all read requests packets
4287	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4288	// are one word packets.
4289	// For write burst packets, all words are in the same cache line,
4290	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4291	// The sc command packet implements actually a compare-and-swap mechanism
4292	// and the packet contains two flits.
4293	////////////////////////////////////////////////////////////////////////////////////
4294
4295	switch ( r_vci_cmd_fsm.read() )
4296	{
4297	//////////////
4298	case CMD_IDLE:
4299	{
4300	// r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access
4301	// to check a possible pending write on the same cache line.
4302	// As there is only one possible access per cycle to write buffer, we implement
4303	// a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop.
4304
4305	size_t wbuf_min;
4306	size_t wbuf_max;
4307
4308	bool dcache_miss_req = r_dcache_vci_miss_req.read()
4309	and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4310	bool icache_miss_req = r_icache_miss_req.read()
4311	and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );
4312
4313	// 1 - Data Read Miss
4314	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4315	{
4316	r_vci_cmd_fsm = CMD_DATA_MISS;
4317	r_dcache_vci_miss_req = false;
4318	r_vci_cmd_imiss_prio = true;
4319	// m_cpt_dmiss_transaction++;
4320	}
4321	// 2 - Data Read Uncachable
4322	else if ( r_dcache_vci_unc_req.read() )
4323	{
4324	r_vci_cmd_fsm = CMD_DATA_UNC;
4325	r_dcache_vci_unc_req = false;
4326	// m_cpt_dunc_transaction++;
4327	}
4328	// 3 - Instruction Miss
4329	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4330	{
4331	r_vci_cmd_fsm = CMD_INS_MISS;
4332	r_icache_miss_req = false;
4333	r_vci_cmd_imiss_prio = false;
4334	// m_cpt_imiss_transaction++;
4335	}
4336	// 4 - Instruction Uncachable
4337	else if ( r_icache_unc_req.read() )
4338	{
4339	r_vci_cmd_fsm = CMD_INS_UNC;
4340	r_icache_unc_req = false;
4341	// m_cpt_iunc_transaction++;
4342	}
4343	// 5 - Data Write
4344	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4345	{
4346	r_vci_cmd_fsm = CMD_DATA_WRITE;
4347	r_vci_cmd_cpt = wbuf_min;
4348	r_vci_cmd_min = wbuf_min;
4349	r_vci_cmd_max = wbuf_max;
4350	// m_cpt_write_transaction++;
4351	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4352	}
4353	// 6 - Data Store Conditionnal
4354	else if ( r_dcache_vci_sc_req.read() )
4355	{
4356	r_vci_cmd_fsm = CMD_DATA_SC;
4357	r_dcache_vci_sc_req = false;
4358	r_vci_cmd_cpt = 0;
4359	// m_cpt_sc_transaction++;
4360	}
4361	break;
4362	}
4363	////////////////////
4364	case CMD_DATA_WRITE:
4365	{
4366	if ( p_vci_ini_d.cmdack.read() )
4367	{
4368	// m_conso_wbuf_read++;
4369	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4370	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4371	{
4372	r_vci_cmd_fsm = CMD_IDLE ;
4373	r_wbuf.sent() ;
4374	}
4375	}
4376	break;
4377	}
4378	/////////////////
4379	case CMD_DATA_SC:
4380	{
4381	// The SC VCI command contains two flits
4382	if ( p_vci_ini_d.cmdack.read() )
4383	{
4384	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4385	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4386	}
4387	break;
4388	}
4389	//////////////////
4390	case CMD_INS_MISS:
4391	case CMD_INS_UNC:
4392	case CMD_DATA_MISS:
4393	case CMD_DATA_UNC:
4394	{
4395	// all read VCI commands contain one single flit
4396	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4397	break;
4398	}
4399
4400	} // end switch r_vci_cmd_fsm
4401
4402	//////////////////////////////////////////////////////////////////////////
4403	// The VCI_RSP FSM controls the following ressources:
4404	// - r_vci_rsp_fsm:
4405	// - r_vci_rsp_fifo_icache (push)
4406	// - r_vci_rsp_fifo_dcache (push)
4407	// - r_vci_rsp_data_error (set)
4408	// - r_vci_rsp_ins_error (set)
4409	// - r_vci_rsp_cpt
4410	//
4411	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4412	// simultaneous VCI transactions, this FSM uses the VCI TRDID field
4413	// to identify the transactions.
4414	//
4415	// VCI vormat:
4416	// This component checks the response packet length and accepts only
4417	// single word packets for write response packets.
4418	//
4419	// Error handling:
4420	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
4421	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
4422	// flip_flop and the error is signaled by the DCACHE FSM.
4423	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
4424	// flip_flop and the error is signaled by the ICACHE FSM.
4425	// In case of Cleanup Error, the simulation stops with an error message...
4426	//////////////////////////////////////////////////////////////////////////
4427
4428	switch ( r_vci_rsp_fsm.read() )
4429	{
4430	//////////////
4431	case RSP_IDLE:
4432	{
4433	if ( p_vci_ini_d.rspval.read() )
4434	{
4435	r_vci_rsp_cpt = 0;
4436
4437	if ( (p_vci_ini_d.rtrdid.read() >> (vci_param::T-1)) != 0 ) // Write transaction
4438	{
4439	r_vci_rsp_fsm = RSP_DATA_WRITE;
4440	}
4441	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS )
4442	{
4443	r_vci_rsp_fsm = RSP_INS_MISS;
4444	}
4445	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC )
4446	{
4447	r_vci_rsp_fsm = RSP_INS_UNC;
4448	}
4449	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS )
4450	{
4451	r_vci_rsp_fsm = RSP_DATA_MISS;
4452	}
4453	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC )
4454	{
4455	r_vci_rsp_fsm = RSP_DATA_UNC;
4456	}
4457	else
4458	{
4459	assert(false and "Unexpected VCI response");
4460	}
4461	}
4462	break;
4463	}
4464	//////////////////
4465	case RSP_INS_MISS:
4466	{
4467	if ( p_vci_ini_d.rspval.read() )
4468	{
4469	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4470	{
4471	r_vci_rsp_ins_error = true;
4472	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4473	}
4474	else // no error reported
4475	{
4476	if ( r_vci_rsp_fifo_icache.wok() )
4477	{
4478	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
4479	"The VCI response packet for instruction miss is too long" );
4480
4481	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4482	vci_rsp_fifo_icache_put = true,
4483	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4484	if ( p_vci_ini_d.reop.read() )
4485	{
4486	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
4487	"The VCI response packet for instruction miss is too short");
4488
4489	r_vci_rsp_fsm = RSP_IDLE;
4490	}
4491	}
4492	}
4493	}
4494	break;
4495	}
4496	/////////////////
4497	case RSP_INS_UNC:
4498	{
4499	if (p_vci_ini_d.rspval.read() )
4500	{
4501	assert( p_vci_ini_d.reop.read() and
4502	"illegal VCI response packet for uncachable instruction");
4503
4504	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4505	{
4506	r_vci_rsp_ins_error = true;
4507	r_vci_rsp_fsm = RSP_IDLE;
4508	}
4509	else // no error reported
4510	{
4511	if ( r_vci_rsp_fifo_icache.wok())
4512	{
4513	vci_rsp_fifo_icache_put = true;
4514	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4515	r_vci_rsp_fsm = RSP_IDLE;
4516	}
4517	}
4518	}
4519	break;
4520	}
4521	///////////////////
4522	case RSP_DATA_MISS:
4523	{
4524	if ( p_vci_ini_d.rspval.read() )
4525	{
4526	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4527	{
4528	r_vci_rsp_data_error = true;
4529	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4530	}
4531	else // no error reported
4532	{
4533	if ( r_vci_rsp_fifo_dcache.wok() )
4534	{
4535	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
4536	"The VCI response packet for data miss is too long");
4537
4538	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4539	vci_rsp_fifo_dcache_put = true,
4540	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4541	if ( p_vci_ini_d.reop.read() )
4542	{
4543	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
4544	"The VCI response packet for data miss is too short");
4545
4546	r_vci_rsp_fsm = RSP_IDLE;
4547	}
4548	}
4549	}
4550	}
4551	break;
4552	}
4553	//////////////////
4554	case RSP_DATA_UNC:
4555	{
4556	if (p_vci_ini_d.rspval.read() )
4557	{
4558	assert( p_vci_ini_d.reop.read() and
4559	"illegal VCI response packet for uncachable read data");
4560
4561	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4562	{
4563	r_vci_rsp_data_error = true;
4564	r_vci_rsp_fsm = RSP_IDLE;
4565	}
4566	else // no error reported
4567	{
4568	if ( r_vci_rsp_fifo_dcache.wok())
4569	{
4570	vci_rsp_fifo_dcache_put = true;
4571	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4572	r_vci_rsp_fsm = RSP_IDLE;
4573	}
4574	}
4575	}
4576	break;
4577	}
4578	////////////////////
4579	case RSP_DATA_WRITE:
4580	{
4581	if (p_vci_ini_d.rspval.read())
4582	{
4583	assert( p_vci_ini_d.reop.read() and
4584	"a VCI response packet must contain one flit for a write transaction");
4585
4586	r_vci_rsp_fsm = RSP_IDLE;
4587	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1));
4588	bool cacheable = r_wbuf.completed(wbuf_index);
4589	if ( not cacheable ) r_dcache_pending_unc_write = false;
4590	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
4591	}
4592	break;
4593	}
4594	} // end switch r_vci_rsp_fsm
4595
4596	////////////////////////////////////////////////////////////////////////////////
4597	// The CLEANUP FSM send the cleanup commands on the coherence network,
4598	// and supports simultaneous cleanup transactions, but two simultaneous
4599	// transactions mut address different cache lines.
4600	// Therefore, the line number is registered in an associative
4601	// registration buffer (Content Adressable Memory) by the CLEANUP FSM,
4602	// and the corresponding slot (identified by the VCI TRDID field) is cleared
4603	// when the cleanup transaction response is received.
4604	// It handles cleanup requests from both the DCACHE FSM & ICACHE FSM
4605	// with a round robin priority, and can support up to 4 simultaneous
4606	// cleanup transactions (4 slots in the registration buffer).
4607	// The r_dcache_cleanup_req (or r_icache_cleanup_req) flip-flops are reset
4608	// when the command has been sent.
4609	// The VCI TRDID field is used to distinguish data/instruction cleanups:
4610	// - if data cleanup : TRDID = 2*index + 0
4611	// - if instruction cleanup : TRDID = 2*index + 1
4612	////////////////////////////////////////////////////////////////////////////
4613
4614	switch ( r_cleanup_fsm.read() )
4615	{
4616	///////////////////////
4617	case CLEANUP_DATA_IDLE: // dcache has highest priority
4618	{
4619	size_t index = 0;
4620	bool ok;
4621	if ( r_dcache_cleanup_req.read() ) // dcache request
4622	{
4623	ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(),
4624	&index );
4625	if ( ok ) // successful registration
4626	{
4627	r_cleanup_fsm = CLEANUP_DATA_GO;
4628	r_cleanup_trdid = index<<1;
4629	}
4630	}
4631	else if ( r_icache_cleanup_req.read() ) // icache request
4632	{
4633	ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(),
4634	&index );
4635	if ( ok ) // successful registration
4636	{
4637	r_cleanup_fsm = CLEANUP_INS_GO;
4638	r_cleanup_trdid = (index<<1) + 1;
4639	}
4640	}
4641	break;
4642	}
4643	//////////////////////
4644	case CLEANUP_INS_IDLE: // icache has highest priority
4645	{
4646	size_t index = 0;
4647	bool ok;
4648	if ( r_icache_cleanup_req.read() ) // icache request
4649	{
4650	ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(),
4651	&index );
4652	if ( ok ) // successful registration
4653	{
4654	r_cleanup_fsm = CLEANUP_INS_GO;
4655	r_cleanup_trdid = (index<<1) + 1;
4656	}
4657	}
4658	else if ( r_dcache_cleanup_req.read() ) // dcache request
4659	{
4660	ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(),
4661	&index );
4662	if ( ok ) // successful registration
4663	{
4664	r_cleanup_fsm = CLEANUP_DATA_GO;
4665	r_cleanup_trdid = index<<1;
4666	}
4667	}
4668	break;
4669	}
4670	/////////////////////
4671	case CLEANUP_DATA_GO:
4672	{
4673	if ( p_vci_ini_c.cmdack.read() )
4674	{
4675	r_dcache_cleanup_req = false;
4676	r_cleanup_fsm = CLEANUP_INS_IDLE;
4677
4678	#if DEBUG_CLEANUP
4679	if ( m_debug_cleanup_fsm )
4680	{
4681	std::cout << " <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
4682	<< " address = " << (r_dcache_cleanup_line.read()m_dcache_words4)
4683	<< " / trdid = " << r_cleanup_trdid.read() << std::endl;
4684	}
4685	#endif
4686	}
4687	}
4688	////////////////////////
4689	case CLEANUP_INS_GO:
4690	{
4691	if ( p_vci_ini_c.cmdack.read() )
4692	{
4693	r_icache_cleanup_req = false;
4694	r_cleanup_fsm = CLEANUP_DATA_IDLE;
4695
4696	#if DEBUG_CLEANUP
4697	if ( m_debug_cleanup_fsm )
4698	{
4699	std::cout << " <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
4700	<< " address = " << (r_icache_cleanup_line.read()m_icache_words4)
4701	<< " / trdid = " << r_cleanup_trdid.read() << std::endl;
4702	}
4703	#endif
4704	}
4705	}
4706	} // end switch CLEANUP FSM
4707
4708	//////////////// Handling cleanup responses //////////////////
4709	if ( p_vci_ini_c.rspval.read() ) // valid response
4710	{
4711	r_cleanup_buffer.cancel_index( p_vci_ini_c.rtrdid.read() >> 1);
4712	}
4713
4714	///////////////// Response FIFOs update //////////////////////
4715	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
4716	vci_rsp_fifo_icache_put,
4717	vci_rsp_fifo_icache_data);
4718
4719	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
4720	vci_rsp_fifo_dcache_put,
4721	vci_rsp_fifo_dcache_data);
4722	} // end transition()
4723
4724	///////////////////////
4725	tmpl(void)::genMoore()
4726	///////////////////////
4727	{
4728	////////////////////////////////////////////////////////////////
4729	// VCI initiator command on the coherence network (cleanup)
4730	// it depends on the CLEANUP FSM state
4731
4732	paddr_t address;
4733
4734	if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
4735	address = r_dcache_cleanup_line.read()m_dcache_words4;
4736	else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
4737	address = r_icache_cleanup_line.read()m_icache_words4;
4738	else
4739	address = 0;
4740
4741	p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
4742	(r_cleanup_fsm.read() == CLEANUP_INS_GO) );
4743	p_vci_ini_c.address = address;
4744	p_vci_ini_c.wdata = 0;
4745	p_vci_ini_c.be = 0xF;
4746	p_vci_ini_c.plen = 4;
4747	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
4748	p_vci_ini_c.trdid = r_cleanup_trdid.read();
4749	p_vci_ini_c.pktid = 0;
4750	p_vci_ini_c.srcid = m_srcid_c;
4751	p_vci_ini_c.cons = false;
4752	p_vci_ini_c.wrap = false;
4753	p_vci_ini_c.contig = false;
4754	p_vci_ini_c.clen = 0;
4755	p_vci_ini_c.cfixed = false;
4756	p_vci_ini_c.eop = true;
4757
4758	/////////////////////////////////////////////////////////////////
4759	// VCI initiator response on the coherence network (cleanup)
4760	// We always consume the response, and we don't use it.
4761
4762	p_vci_ini_c.rspack = true;
4763
4764	/////////////////////////////////////////////////////////////////
4765	// VCI initiator command on the direct network
4766	// it depends on the CMD FSM state
4767
4768	p_vci_ini_d.pktid = 0;
4769	p_vci_ini_d.srcid = m_srcid_d;
4770	p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4771	p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4772	p_vci_ini_d.wrap = false;
4773	p_vci_ini_d.clen = 0;
4774	p_vci_ini_d.cfixed = false;
4775
4776	switch ( r_vci_cmd_fsm.read() ) {
4777
4778	case CMD_IDLE:
4779	p_vci_ini_d.cmdval = false;
4780	p_vci_ini_d.address = 0;
4781	p_vci_ini_d.wdata = 0;
4782	p_vci_ini_d.be = 0;
4783	p_vci_ini_d.trdid = 0;
4784	p_vci_ini_d.plen = 0;
4785	p_vci_ini_d.cmd = vci_param::CMD_NOP;
4786	p_vci_ini_d.eop = false;
4787	break;
4788
4789	case CMD_INS_MISS:
4790	p_vci_ini_d.cmdval = true;
4791	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
4792	p_vci_ini_d.wdata = 0;
4793	p_vci_ini_d.be = 0xF;
4794	p_vci_ini_d.trdid = TYPE_INS_MISS;
4795	p_vci_ini_d.plen = m_icache_words<<2;
4796	p_vci_ini_d.cmd = vci_param::CMD_READ;
4797	p_vci_ini_d.eop = true;
4798	break;
4799
4800	case CMD_INS_UNC:
4801	p_vci_ini_d.cmdval = true;
4802	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
4803	p_vci_ini_d.wdata = 0;
4804	p_vci_ini_d.be = 0xF;
4805	p_vci_ini_d.trdid = TYPE_INS_UNC;
4806	p_vci_ini_d.plen = 4;
4807	p_vci_ini_d.cmd = vci_param::CMD_READ;
4808	p_vci_ini_d.eop = true;
4809	break;
4810
4811	case CMD_DATA_MISS:
4812	p_vci_ini_d.cmdval = true;
4813	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
4814	p_vci_ini_d.wdata = 0;
4815	p_vci_ini_d.be = 0xF;
4816	p_vci_ini_d.trdid = TYPE_DATA_MISS;
4817	p_vci_ini_d.plen = m_dcache_words << 2;
4818	p_vci_ini_d.cmd = vci_param::CMD_READ;
4819	p_vci_ini_d.eop = true;
4820	break;
4821
4822	case CMD_DATA_UNC:
4823	p_vci_ini_d.cmdval = true;
4824	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4825	p_vci_ini_d.wdata = 0;
4826	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
4827	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4828	p_vci_ini_d.plen = 4;
4829	p_vci_ini_d.cmd = vci_param::CMD_READ;
4830	p_vci_ini_d.eop = true;
4831	break;
4832
4833	case CMD_DATA_WRITE:
4834	p_vci_ini_d.cmdval = true;
4835	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
4836	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
4837	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
4838	p_vci_ini_d.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1));
4839	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
4840	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
4841	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
4842	break;
4843
4844	case CMD_DATA_SC:
4845	p_vci_ini_d.cmdval = true;
4846	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4847	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_sc_old.read();
4848	else p_vci_ini_d.wdata = r_dcache_vci_sc_new.read();
4849	p_vci_ini_d.be = 0xF;
4850	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4851	p_vci_ini_d.plen = 8;
4852	p_vci_ini_d.cmd = vci_param::CMD_STORE_COND;
4853	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
4854	break;
4855	} // end switch r_vci_cmd_fsm
4856
4857	//////////////////////////////////////////////////////////
4858	// VCI initiator response on the direct network
4859	// it depends on the VCI RSP state
4860
4861	switch (r_vci_rsp_fsm.read() )
4862	{
4863	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
4864	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4865	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4866	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4867	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4868	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
4869	} // end switch r_vci_rsp_fsm
4870
4871	////////////////////////////////////////////////////////////////
4872	// VCI target command and response on the coherence network
4873	switch ( r_tgt_fsm.read() )
4874	{
4875	case TGT_IDLE:
4876	case TGT_UPDT_WORD:
4877	case TGT_UPDT_DATA:
4878	p_vci_tgt_c.cmdack = true;
4879	p_vci_tgt_c.rspval = false;
4880	break;
4881
4882	case TGT_RSP_BROADCAST:
4883	p_vci_tgt_c.cmdack = false;
4884	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()
4885	and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() );
4886	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4887	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4888	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4889	p_vci_tgt_c.rdata = 0;
4890	p_vci_tgt_c.rerror = 0;
4891	p_vci_tgt_c.reop = true;
4892	break;
4893
4894	case TGT_RSP_ICACHE:
4895	p_vci_tgt_c.cmdack = false;
4896	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
4897	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4898	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4899	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4900	p_vci_tgt_c.rdata = 0;
4901	p_vci_tgt_c.rerror = 0;
4902	p_vci_tgt_c.reop = true;
4903	break;
4904
4905	case TGT_RSP_DCACHE:
4906	p_vci_tgt_c.cmdack = false;
4907	p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
4908	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4909	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4910	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4911	p_vci_tgt_c.rdata = 0;
4912	p_vci_tgt_c.rerror = 0;
4913	p_vci_tgt_c.reop = true;
4914	break;
4915
4916	case TGT_REQ_BROADCAST:
4917	case TGT_REQ_ICACHE:
4918	case TGT_REQ_DCACHE:
4919	p_vci_tgt_c.cmdack = false;
4920	p_vci_tgt_c.rspval = false;
4921	break;
4922
4923	} // end switch TGT_FSM
4924	} // end genMoore
4925
4926	}}
4927
4928	// Local Variables:
4929	// tab-width: 4
4930	// c-basic-offset: 4
4931	// c-file-offsets:((innamespace . 0)(inline-open . 0))
4932	// indent-tabs-mode: nil
4933	// End:
4934
4935	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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