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source: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp @ 196

Last change on this file since 196 was 196, checked in by alain, 12 years ago
Fixing 2 bugs: 1/ The coherence requests must be taken in state DCACHE_XTN_WRITE to avoid dead-locks. 2/ Completion of the ITLB flush was not properly handled in the DCACHE_XTN_SWITCH state.
File size: 185.4 KB

Line
1	/* -- c++ --C
2	* File : vci_cc_vcache_wrapper_v4.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#include <cassert>
28	#include "arithmetics.h"
29	#include "../include/vci_cc_vcache_wrapper_v4.h"
30
31	#define DEBUG_DCACHE 1
32	#define DEBUG_ICACHE 1
33	#define DEBUG_CLEANUP 0
34	#define DEBUG_INVAL_ITLB 1
35	#define DEBUG_INVAL_DTLB 1
36
37	namespace soclib {
38	namespace caba {
39
40	namespace {
41	const char *icache_fsm_state_str[] = {
42	"ICACHE_IDLE",
43
44	"ICACHE_XTN_TLB_FLUSH",
45	"ICACHE_XTN_CACHE_FLUSH",
46	"ICACHE_XTN_TLB_INVAL",
47	"ICACHE_XTN_CACHE_INVAL_VA",
48	"ICACHE_XTN_CACHE_INVAL_PA",
49	"ICACHE_XTN_CACHE_INVAL_GO",
50
51	"ICACHE_TLB_WAIT",
52
53	"ICACHE_MISS_VICTIM",
54	"ICACHE_MISS_INVAL",
55	"ICACHE_MISS_WAIT",
56	"ICACHE_MISS_UPDT",
57
58	"ICACHE_UNC_WAIT",
59
60	"ICACHE_CC_CHECK",
61	"ICACHE_CC_INVAL",
62	"ICACHE_CC_UPDT",
63
64	};
65	const char *dcache_fsm_state_str[] = {
66	"DCACHE_IDLE",
67
68	"DCACHE_TLB_MISS",
69	"DCACHE_TLB_PTE1_GET",
70	"DCACHE_TLB_PTE1_SELECT",
71	"DCACHE_TLB_PTE1_UPDT",
72	"DCACHE_TLB_PTE2_GET",
73	"DCACHE_TLB_PTE2_SELECT",
74	"DCACHE_TLB_PTE2_UPDT",
75	"DCACHE_TLB_SC_UPDT",
76	"DCACHE_TLB_SC_WAIT",
77	"DCACHE_TLB_RETURN",
78
79	"DCACHE_XTN_SWITCH",
80	"DCACHE_XTN_SYNC",
81	"DCACHE_XTN_IC_INVAL_VA",
82	"DCACHE_XTN_IC_FLUSH",
83	"DCACHE_XTN_IC_INVAL_PA",
84	"DCACHE_XTN_IT_INVAL",
85	"DCACHE_XTN_DC_FLUSH",
86	"DCACHE_XTN_DC_INVAL_VA",
87	"DCACHE_XTN_DC_INVAL_PA",
88	"DCACHE_XTN_DC_INVAL_WAIT",
89	"DCACHE_XTN_DC_INVAL_GO",
90	"DCACHE_XTN_DT_INVAL",
91
92	"DCACHE_WRITE_TLB_DIRTY",
93	"DCACHE_WRITE_CACHE_DIRTY",
94	"DCACHE_WRITE_SC_WAIT",
95	"DCACHE_WRITE_UNC_WAIT",
96
97	"DCACHE_MISS_VICTIM",
98	"DCACHE_MISS_INVAL",
99	"DCACHE_MISS_INVAL_WAIT",
100	"DCACHE_MISS_WAIT",
101	"DCACHE_MISS_UPDT",
102
103	"DCACHE_UNC_WAIT",
104
105	"DCACHE_CC_CHECK",
106	"DCACHE_CC_INVAL",
107	"DCACHE_CC_UPDT",
108	"DCACHE_CC_WAIT",
109	};
110	const char *cmd_fsm_state_str[] = {
111	"CMD_IDLE",
112	"CMD_INS_MISS",
113	"CMD_INS_UNC",
114	"CMD_DATA_MISS",
115	"CMD_DATA_UNC",
116	"CMD_DATA_WRITE",
117	"CMD_DATA_SC",
118	};
119	const char *rsp_fsm_state_str[] = {
120	"RSP_IDLE",
121	"RSP_INS_MISS",
122	"RSP_INS_UNC",
123	"RSP_DATA_MISS",
124	"RSP_DATA_UNC",
125	"RSP_DATA_WRITE",
126	};
127	const char *cleanup_fsm_state_str[] = {
128	"CLEANUP_DATA_IDLE",
129	"CLEANUP_DATA_GO",
130	"CLEANUP_INS_IDLE",
131	"CLEANUP_INS_GO",
132	};
133	const char *tgt_fsm_state_str[] = {
134	"TGT_IDLE",
135	"TGT_UPDT_WORD",
136	"TGT_UPDT_DATA",
137	"TGT_REQ_BROADCAST",
138	"TGT_REQ_ICACHE",
139	"TGT_REQ_DCACHE",
140	"TGT_RSP_BROADCAST",
141	"TGT_RSP_ICACHE",
142	"TGT_RSP_DCACHE",
143	};
144	const char *inval_itlb_fsm_state_str[] = {
145	"INVAL_ITLB_IDLE",
146	"INVAL_ITLB_SCAN",
147	};
148	const char *inval_dtlb_fsm_state_str[] = {
149	"INVAL_DTLB_IDLE",
150	"INVAL_DTLB_SCAN",
151	};
152	}
153
154	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t>
155
156	using soclib::common::uint32_log2;
157
158	/////////////////////////////////
159	tmpl(/**/)::VciCcVCacheWrapperV4(
160	sc_module_name name,
161	int proc_id,
162	const soclib::common::MappingTable &mtp,
163	const soclib::common::MappingTable &mtc,
164	const soclib::common::IntTab &initiator_index_d,
165	const soclib::common::IntTab &initiator_index_c,
166	const soclib::common::IntTab &target_index_d,
167	size_t itlb_ways,
168	size_t itlb_sets,
169	size_t dtlb_ways,
170	size_t dtlb_sets,
171	size_t icache_ways,
172	size_t icache_sets,
173	size_t icache_words,
174	size_t dcache_ways,
175	size_t dcache_sets,
176	size_t dcache_words,
177	size_t wbuf_nlines,
178	size_t wbuf_nwords,
179	uint32_t max_frozen_cycles,
180	uint32_t debug_start_cycle,
181	bool debug_ok)
182	: soclib::caba::BaseModule(name),
183
184	p_clk("clk"),
185	p_resetn("resetn"),
186	p_vci_ini_d("vci_ini_d"),
187	p_vci_ini_c("vci_ini_c"),
188	p_vci_tgt_c("vci_tgt_d"),
189
190	m_cacheability_table(mtp.getCacheabilityTable()),
191	m_segment(mtc.getSegment(target_index_d)),
192	m_srcid_d(mtp.indexForId(initiator_index_d)),
193	m_srcid_c(mtp.indexForId(initiator_index_c)),
194
195	m_itlb_ways(itlb_ways),
196	m_itlb_sets(itlb_sets),
197
198	m_dtlb_ways(dtlb_ways),
199	m_dtlb_sets(dtlb_sets),
200
201	m_icache_ways(icache_ways),
202	m_icache_sets(icache_sets),
203	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
204	m_icache_words(icache_words),
205
206	m_dcache_ways(dcache_ways),
207	m_dcache_sets(dcache_sets),
208	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
209	m_dcache_words(dcache_words),
210
211	m_max_frozen_cycles(max_frozen_cycles),
212
213	m_paddr_nbits(vci_param::N),
214
215	m_debug_start_cycle(debug_start_cycle),
216	m_debug_ok(debug_ok),
217
218	r_mmu_ptpr("r_mmu_ptpr"),
219	r_mmu_mode("r_mmu_mode"),
220	r_mmu_word_lo("r_mmu_word_lo"),
221	r_mmu_word_hi("r_mmu_word_hi"),
222	r_mmu_ibvar("r_mmu_ibvar"),
223	r_mmu_dbvar("r_mmu_dbvar"),
224	r_mmu_ietr("r_mmu_ietr"),
225	r_mmu_detr("r_mmu_detr"),
226
227	r_icache_fsm("r_icache_fsm"),
228	r_icache_fsm_save("r_icache_fsm_save"),
229	r_icache_vci_paddr("r_icache_vci_paddr"),
230	r_icache_vaddr_save("r_icache_vaddr_save"),
231
232	r_icache_miss_way("r_icache_miss_way"),
233	r_icache_miss_set("r_icache_miss_set"),
234	r_icache_miss_word("r_icache_miss_word"),
235	r_icache_miss_inval("r_icache_miss_inval"),
236
237	r_icache_cc_way("r_icache_cc_way"),
238	r_icache_cc_set("r_icache_cc_set"),
239	r_icache_cc_word("r_icache_cc_word"),
240
241	r_icache_flush_count("r_icache_flush_count"),
242
243	r_icache_miss_req("r_icache_miss_req"),
244	r_icache_unc_req("r_icache_unc_req"),
245
246	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
247	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
248
249	r_icache_cleanup_req("r_icache_cleanup_req"),
250	r_icache_cleanup_line("r_icache_cleanup_line"),
251
252	r_dcache_fsm("r_dcache_fsm"),
253	r_dcache_fsm_save("r_dcache_fsm_save"),
254
255	r_dcache_p0_valid("r_dcache_p0_valid"),
256	r_dcache_p0_vaddr("r_dcache_p0_vaddr"),
257	r_dcache_p0_wdata("r_dcache_p0_wdata"),
258	r_dcache_p0_be("r_dcache_p0_be"),
259	r_dcache_p0_paddr("r_dcache_p0_paddr"),
260	r_dcache_p0_cacheable("r_dcache_p0_cacheable"),
261	r_dcache_p0_tlb_way("r_dcache_p0_tlb_way"),
262	r_dcache_p0_tlb_set("r_dcache_p0_tlb_set"),
263	r_dcache_p0_tlb_nline("r_dcache_p0_tlb_nline"),
264	r_dcache_p0_tlb_dirty("r_dcache_p0_tlb_dirty"),
265	r_dcache_p0_tlb_big("r_dcache_p0_tlb_big"),
266
267	r_dcache_p1_valid("r_dcache_p1_valid"),
268	r_dcache_p1_updt_cache("r_dcache_p1_updt_cache"),
269	r_dcache_p1_set_dirty("r_dcache_p1_set_dirty"),
270	r_dcache_p1_vaddr("r_dcache_p1_vaddr"),
271	r_dcache_p1_wdata("r_dcache_p1_wdata"),
272	r_dcache_p1_be("r_dcache_p1_be"),
273	r_dcache_p1_paddr("r_dcache_p1_paddr"),
274	r_dcache_p1_cache_way("r_dcache_p1_cache_way"),
275	r_dcache_p1_cache_set("r_dcache_p1_cache_set"),
276	r_dcache_p1_cache_word("r_dcache_p1_word_save"),
277	r_dcache_p1_tlb_way("r_dcache_p1_tlb_way"),
278	r_dcache_p1_tlb_set("r_dcache_p1_tlb_set"),
279	r_dcache_p1_tlb_nline("r_dcache_p1_tlb_nline"),
280
281	r_dcache_p2_vaddr("r_dcache_p2_vaddr"),
282	r_dcache_p2_tlb_way("r_dcache_p2_tlb_way"),
283	r_dcache_p2_tlb_set("r_dcache_p2_tlb_set"),
284	r_dcache_p2_set_dirty("r_dcache_p2_set_dirty"),
285	r_dcache_p2_pte_paddr("r_dcache_p2_pte_paddr"),
286	r_dcache_p2_pte_way("r_dcache_p2_pte_way"),
287	r_dcache_p2_pte_set("r_dcache_p2_pte_set"),
288	r_dcache_p2_pte_word("r_dcache_p2_pte_word"),
289	r_dcache_p2_pte_flags("r_dcache_p2_pte_flags"),
290
291	r_dcache_vci_paddr("r_dcache_vci_paddr"),
292	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
293	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
294	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
295	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
296	r_dcache_vci_sc_old("r_dcache_vci_sc_old"),
297	r_dcache_vci_sc_new("r_dcache_vci_sc_new"),
298
299	r_dcache_xtn_way("r_dcache_xtn_way"),
300	r_dcache_xtn_set("r_dcache_xtn_set"),
301
302	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
303
304	r_dcache_miss_type("r_dcache_miss_type"),
305	r_dcache_miss_word("r_dcache_miss_word"),
306	r_dcache_miss_way("r_dcache_miss_way"),
307	r_dcache_miss_set("r_dcache_miss_set"),
308	r_dcache_miss_inval("r_dcache_miss_inval"),
309
310	r_dcache_cc_way("r_dcache_cc_way"),
311	r_dcache_cc_set("r_dcache_cc_set"),
312	r_dcache_cc_word("r_dcache_cc_word"),
313
314	r_dcache_flush_count("r_dcache_flush_count"),
315
316	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
317	r_dcache_tlb_ins("r_dcache_tlb_ins"),
318	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
319	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
320	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
321	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
322	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
323	r_dcache_tlb_way("r_dcache_tlb_way"),
324	r_dcache_tlb_set("r_dcache_tlb_set"),
325
326	r_dcache_ll_valid("r_dcache_ll_valid"),
327	r_dcache_ll_data("r_dcache_ll_data"),
328	r_dcache_ll_vaddr("r_dcache_ll_vaddr"),
329
330	r_dcache_itlb_inval_req("r_dcache_itlb_inval_req"),
331	r_dcache_dtlb_inval_req("r_dcache_dtlb_inval_req"),
332	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
333
334	r_dcache_xtn_req("r_dcache_xtn_req"),
335	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
336
337	r_dcache_cleanup_req("r_dcache_cleanup_req"),
338	r_dcache_cleanup_line("r_dcache_cleanup_line"),
339
340	r_vci_cmd_fsm("r_vci_cmd_fsm"),
341	r_vci_cmd_min("r_vci_cmd_min"),
342	r_vci_cmd_max("r_vci_cmd_max"),
343	r_vci_cmd_cpt("r_vci_cmd_cpt"),
344	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
345
346	r_vci_rsp_fsm("r_vci_rsp_fsm"),
347	r_vci_rsp_cpt("r_vci_rsp_cpt"),
348	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
349	r_vci_rsp_data_error("r_vci_rsp_data_error"),
350	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
351	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
352
353	r_cleanup_fsm("r_cleanup_fsm"),
354	r_cleanup_trdid("r_cleanup_trdid"),
355	r_cleanup_buffer(4), // up to 4 simultaneous cleanups
356
357	r_tgt_fsm("r_tgt_fsm"),
358	r_tgt_paddr("r_tgt_paddr"),
359	r_tgt_word_count("r_tgt_word_count"),
360	r_tgt_word_min("r_tgt_word_min"),
361	r_tgt_word_max("r_tgt_word_max"),
362	r_tgt_update("r_tgt_update"),
363	r_tgt_update_data("r_tgt_update_data"),
364	r_tgt_srcid("r_tgt_srcid"),
365	r_tgt_pktid("r_tgt_pktid"),
366	r_tgt_trdid("r_tgt_trdid"),
367
368	r_tgt_icache_req("r_tgt_icache_req"),
369	r_tgt_dcache_req("r_tgt_dcache_req"),
370	r_tgt_icache_rsp("r_tgt_icache_rsp"),
371	r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
372
373	r_inval_itlb_fsm("r_inval_itlb_fsm"),
374	r_inval_itlb_count("r_inval_itlb_count"),
375
376	r_inval_dtlb_fsm("r_inval_dtlb_fsm"),
377	r_inval_dtlb_count("r_inval_dtlb_count"),
378
379	r_iss(this->name(), proc_id),
380	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
381	r_icache("icache", icache_ways, icache_sets, icache_words),
382	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
383	r_itlb(itlb_ways,itlb_sets,vci_param::N),
384	r_dtlb(dtlb_ways,dtlb_sets,vci_param::N)
385	{
386	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
387	"Need more PLEN bits.");
388
389	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
390	"Need more TRDID bits.");
391
392	assert( (icache_words == dcache_words) and
393	"icache_words and dcache_words parameters must be equal");
394
395	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
396	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
397	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
398	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
399	(uint32_log2(m_icache_words<<2));
400
401	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
402
403	r_tgt_buf = new uint32_t[dcache_words];
404	r_tgt_be = new vci_be_t[dcache_words];
405	r_dcache_in_itlb = new bool[dcache_ways*dcache_sets];
406	r_dcache_in_dtlb = new bool[dcache_ways*dcache_sets];
407
408	SC_METHOD(transition);
409	dont_initialize();
410	sensitive << p_clk.pos();
411
412	SC_METHOD(genMoore);
413	dont_initialize();
414	sensitive << p_clk.neg();
415
416	typename iss_t::CacheInfo cache_info;
417	cache_info.has_mmu = true;
418	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
419	cache_info.icache_assoc = icache_ways;
420	cache_info.icache_n_lines = icache_sets;
421	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
422	cache_info.dcache_assoc = dcache_ways;
423	cache_info.dcache_n_lines = dcache_sets;
424	r_iss.setCacheInfo(cache_info);
425	}
426
427	/////////////////////////////////////
428	tmpl(/**/)::~VciCcVCacheWrapperV4()
429	/////////////////////////////////////
430	{
431	delete [] r_tgt_be;
432	delete [] r_tgt_buf;
433	delete [] r_dcache_in_itlb;
434	delete [] r_dcache_in_dtlb;
435	}
436
437	////////////////////////
438	tmpl(void)::print_cpi()
439	////////////////////////
440	{
441	std::cout << name() << " CPI = "
442	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
443	}
444
445	////////////////////////////////////
446	tmpl(void)::print_trace(size_t mode)
447	////////////////////////////////////
448	{
449	// b0 : write buffer print trace
450	// b1 : write buffer verbose
451	// b2 : dcache print trace
452	// b3 : icache print trace
453
454	typename iss_t::InstructionRequest ireq;
455	typename iss_t::InstructionResponse irsp;
456	typename iss_t::DataRequest dreq;
457	typename iss_t::DataResponse drsp;
458
459	ireq.valid = m_ireq_valid;
460	ireq.addr = m_ireq_addr;
461	ireq.mode = m_ireq_mode;
462
463	irsp.valid = m_irsp_valid;
464	irsp.instruction = m_irsp_instruction;
465	irsp.error = m_irsp_error;
466
467	dreq.valid = m_dreq_valid;
468	dreq.addr = m_dreq_addr;
469	dreq.mode = m_dreq_mode;
470	dreq.type = m_dreq_type;
471	dreq.wdata = m_dreq_wdata;
472	dreq.be = m_dreq_be;
473
474	drsp.valid = m_drsp_valid;
475	drsp.rdata = m_drsp_rdata;
476	drsp.error = m_drsp_error;
477
478	std::cout << std::dec << "PROC " << name() << std::endl;
479
480	std::cout << " " << ireq << std::endl;
481	std::cout << " " << irsp << std::endl;
482	std::cout << " " << dreq << std::endl;
483	std::cout << " " << drsp << std::endl;
484
485	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
486	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
487	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
488	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
489	<< " \| " << tgt_fsm_state_str[r_tgt_fsm.read()] << std::endl;
490	std::cout << " " << cleanup_fsm_state_str[r_cleanup_fsm.read()]
491	<< " \| " << inval_itlb_fsm_state_str[r_inval_itlb_fsm]
492	<< " \| " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm];
493	if (r_dcache_p0_valid.read() ) std::cout << " \| P1_WRITE";
494	if (r_dcache_p1_valid.read() ) std::cout << " \| P2_WRITE";
495	std::cout << std::endl;
496
497	if(mode & 0x1)
498	{
499	r_wbuf.printTrace((mode>>1)&1);
500	}
501	if(mode & 0x4)
502	{
503	std::cout << " Data cache" << std::endl;
504	r_dcache.printTrace();
505	}
506	if(mode & 0x8)
507	{
508	std::cout << " Instruction cache" << std::endl;
509	r_icache.printTrace();
510	}
511	}
512
513	//////////////////////////////////////////
514	tmpl(void)::cache_monitor( paddr_t addr )
515	//////////////////////////////////////////
516	{
517	size_t cache_way;
518	size_t cache_set;
519	size_t cache_word;
520	uint32_t cache_rdata;
521	bool cache_hit = r_dcache.read( addr,
522	&cache_rdata,
523	&cache_way,
524	&cache_set,
525	&cache_word );
526	if ( cache_hit != m_debug_previous_hit )
527	{
528	std::cout << "PROC " << name()
529	<< " cache change at cycle " << std::dec << m_cpt_total_cycles
530	<< " for adresse " << std::hex << addr
531	<< " / HIT = " << cache_hit << std::endl;
532	}
533	m_debug_previous_hit = cache_hit;
534	}
535
536
537
538	/*
539	////////////////////////
540	tmpl(void)::print_stats()
541	////////////////////////
542	{
543	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
544	std::cout << name() << std::endl
545	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
546	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
547	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
548	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
549	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
550	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
551	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
552	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
553	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
554	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
555	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
556	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
557	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
558	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
559	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
560	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
561	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
562	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
563	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
564	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
565	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
566	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
567	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
568	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
569	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
570	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
571	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
572	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
573	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
574	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
575	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
576	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
577	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
578	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
579	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
580	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
581	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
582	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
583	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
584	}
585
586	////////////////////////
587	tmpl(void)::clear_stats()
588	////////////////////////
589	{
590	m_cpt_dcache_data_read = 0;
591	m_cpt_dcache_data_write = 0;
592	m_cpt_dcache_dir_read = 0;
593	m_cpt_dcache_dir_write = 0;
594	m_cpt_icache_data_read = 0;
595	m_cpt_icache_data_write = 0;
596	m_cpt_icache_dir_read = 0;
597	m_cpt_icache_dir_write = 0;
598
599	m_cpt_frz_cycles = 0;
600	m_cpt_dcache_frz_cycles = 0;
601	m_cpt_total_cycles = 0;
602
603	m_cpt_read = 0;
604	m_cpt_write = 0;
605	m_cpt_data_miss = 0;
606	m_cpt_ins_miss = 0;
607	m_cpt_unc_read = 0;
608	m_cpt_write_cached = 0;
609	m_cpt_ins_read = 0;
610
611	m_cost_write_frz = 0;
612	m_cost_data_miss_frz = 0;
613	m_cost_unc_read_frz = 0;
614	m_cost_ins_miss_frz = 0;
615
616	m_cpt_imiss_transaction = 0;
617	m_cpt_dmiss_transaction = 0;
618	m_cpt_unc_transaction = 0;
619	m_cpt_write_transaction = 0;
620	m_cpt_icache_unc_transaction = 0;
621
622	m_cost_imiss_transaction = 0;
623	m_cost_dmiss_transaction = 0;
624	m_cost_unc_transaction = 0;
625	m_cost_write_transaction = 0;
626	m_cost_icache_unc_transaction = 0;
627	m_length_write_transaction = 0;
628
629	m_cpt_ins_tlb_read = 0;
630	m_cpt_ins_tlb_miss = 0;
631	m_cpt_ins_tlb_update_acc = 0;
632
633	m_cpt_data_tlb_read = 0;
634	m_cpt_data_tlb_miss = 0;
635	m_cpt_data_tlb_update_acc = 0;
636	m_cpt_data_tlb_update_dirty = 0;
637	m_cpt_ins_tlb_hit_dcache = 0;
638	m_cpt_data_tlb_hit_dcache = 0;
639	m_cpt_ins_tlb_occup_cache = 0;
640	m_cpt_data_tlb_occup_cache = 0;
641
642	m_cost_ins_tlb_miss_frz = 0;
643	m_cost_data_tlb_miss_frz = 0;
644	m_cost_ins_tlb_update_acc_frz = 0;
645	m_cost_data_tlb_update_acc_frz = 0;
646	m_cost_data_tlb_update_dirty_frz = 0;
647	m_cost_ins_tlb_occup_cache_frz = 0;
648	m_cost_data_tlb_occup_cache_frz = 0;
649
650	m_cpt_itlbmiss_transaction = 0;
651	m_cpt_itlb_ll_transaction = 0;
652	m_cpt_itlb_sc_transaction = 0;
653	m_cpt_dtlbmiss_transaction = 0;
654	m_cpt_dtlb_ll_transaction = 0;
655	m_cpt_dtlb_sc_transaction = 0;
656	m_cpt_dtlb_ll_dirty_transaction = 0;
657	m_cpt_dtlb_sc_dirty_transaction = 0;
658
659	m_cost_itlbmiss_transaction = 0;
660	m_cost_itlb_ll_transaction = 0;
661	m_cost_itlb_sc_transaction = 0;
662	m_cost_dtlbmiss_transaction = 0;
663	m_cost_dtlb_ll_transaction = 0;
664	m_cost_dtlb_sc_transaction = 0;
665	m_cost_dtlb_ll_dirty_transaction = 0;
666	m_cost_dtlb_sc_dirty_transaction = 0;
667
668	m_cpt_cc_update_data = 0;
669	m_cpt_cc_inval_ins = 0;
670	m_cpt_cc_inval_data = 0;
671	m_cpt_cc_broadcast = 0;
672
673	m_cost_updt_data_frz = 0;
674	m_cost_inval_ins_frz = 0;
675	m_cost_inval_data_frz = 0;
676	m_cost_broadcast_frz = 0;
677
678	m_cpt_cc_cleanup_data = 0;
679	m_cpt_cc_cleanup_ins = 0;
680	}
681
682	*/
683
684	/////////////////////////
685	tmpl(void)::transition()
686	/////////////////////////
687	{
688	if ( not p_resetn.read() )
689	{
690	r_iss.reset();
691	r_wbuf.reset();
692	r_icache.reset();
693	r_dcache.reset();
694	r_itlb.reset();
695	r_dtlb.reset();
696
697	r_dcache_fsm = DCACHE_IDLE;
698	r_icache_fsm = ICACHE_IDLE;
699	r_vci_cmd_fsm = CMD_IDLE;
700	r_vci_rsp_fsm = RSP_IDLE;
701	r_tgt_fsm = TGT_IDLE;
702	r_inval_itlb_fsm = INVAL_ITLB_IDLE;
703	r_inval_dtlb_fsm = INVAL_DTLB_IDLE;
704	r_cleanup_fsm = CLEANUP_DATA_IDLE;
705
706	std::memset(r_dcache_in_itlb, 0, sizeof(r_dcache_in_itlb)m_icache_ways*m_icache_sets);
707	std::memset(r_dcache_in_dtlb, 0, sizeof(r_dcache_in_dtlb)m_dcache_ways*m_dcache_sets);
708
709
710	// Response FIFOs and cleanup buffer
711	r_vci_rsp_fifo_icache.init();
712	r_vci_rsp_fifo_dcache.init();
713	r_cleanup_buffer.reset();
714
715	// ICACHE & DCACHE activated
716	r_mmu_mode = 0x3;
717
718	// No request from ICACHE FSM to CMD FSM
719	r_icache_miss_req = false;
720	r_icache_unc_req = false;
721
722	// No request from ICACHE_FSM to DCACHE FSM
723	r_icache_tlb_miss_req = false;
724
725	// No request from ICACHE_FSM to CLEANUP FSMs
726	r_icache_cleanup_req = false;
727
728	// No pending write in pipeline
729	r_dcache_p0_valid = false;
730	r_dcache_p1_valid = false;
731
732	// No request from DCACHE_FSM to CMD_FSM
733	r_dcache_vci_miss_req = false;
734	r_dcache_vci_unc_req = false;
735	r_dcache_vci_sc_req = false;
736
737	// No uncacheable write pending
738	r_dcache_pending_unc_write = false;
739
740	// No LL reservation
741	r_dcache_ll_valid = false;
742
743	// No request from DCACHE FSM to INVAL TLB FSMs
744	r_dcache_itlb_inval_req = false;
745	r_dcache_dtlb_inval_req = false;
746
747	// No processor XTN request pending
748	r_dcache_xtn_req = false;
749
750	// No request from DCACHE FSM to CLEANUP FSMs
751	r_dcache_cleanup_req = false;
752
753	// No request from TGT FSM to ICACHE/DCACHE FSMs
754	r_tgt_icache_req = false;
755	r_tgt_dcache_req = false;
756
757	// No signalisation of a coherence request matching a pending miss
758	r_icache_miss_inval = false;
759	r_dcache_miss_inval = false;
760
761	// No signalisation of errors
762	r_vci_rsp_ins_error = false;
763	r_vci_rsp_data_error = false;
764
765	// Debug variables
766	m_debug_previous_hit = false;
767	m_debug_dcache_fsm = false;
768	m_debug_icache_fsm = false;
769	m_debug_cleanup_fsm = false;
770	m_debug_inval_itlb_fsm = false;
771	m_debug_inval_dtlb_fsm = false;
772
773	/*
774	// activity counters
775	m_cpt_dcache_data_read = 0;
776	m_cpt_dcache_data_write = 0;
777	m_cpt_dcache_dir_read = 0;
778	m_cpt_dcache_dir_write = 0;
779	m_cpt_icache_data_read = 0;
780	m_cpt_icache_data_write = 0;
781	m_cpt_icache_dir_read = 0;
782	m_cpt_icache_dir_write = 0;
783
784	m_cpt_frz_cycles = 0;
785	m_cpt_dcache_frz_cycles = 0;
786	m_cpt_total_cycles = 0;
787
788	m_cpt_read = 0;
789	m_cpt_write = 0;
790	m_cpt_data_miss = 0;
791	m_cpt_ins_miss = 0;
792	m_cpt_unc_read = 0;
793	m_cpt_write_cached = 0;
794	m_cpt_ins_read = 0;
795
796	m_cost_write_frz = 0;
797	m_cost_data_miss_frz = 0;
798	m_cost_unc_read_frz = 0;
799	m_cost_ins_miss_frz = 0;
800
801	m_cpt_imiss_transaction = 0;
802	m_cpt_dmiss_transaction = 0;
803	m_cpt_unc_transaction = 0;
804	m_cpt_write_transaction = 0;
805	m_cpt_icache_unc_transaction = 0;
806
807	m_cost_imiss_transaction = 0;
808	m_cost_dmiss_transaction = 0;
809	m_cost_unc_transaction = 0;
810	m_cost_write_transaction = 0;
811	m_cost_icache_unc_transaction = 0;
812	m_length_write_transaction = 0;
813
814	m_cpt_ins_tlb_read = 0;
815	m_cpt_ins_tlb_miss = 0;
816	m_cpt_ins_tlb_update_acc = 0;
817
818	m_cpt_data_tlb_read = 0;
819	m_cpt_data_tlb_miss = 0;
820	m_cpt_data_tlb_update_acc = 0;
821	m_cpt_data_tlb_update_dirty = 0;
822	m_cpt_ins_tlb_hit_dcache = 0;
823	m_cpt_data_tlb_hit_dcache = 0;
824	m_cpt_ins_tlb_occup_cache = 0;
825	m_cpt_data_tlb_occup_cache = 0;
826
827	m_cost_ins_tlb_miss_frz = 0;
828	m_cost_data_tlb_miss_frz = 0;
829	m_cost_ins_tlb_update_acc_frz = 0;
830	m_cost_data_tlb_update_acc_frz = 0;
831	m_cost_data_tlb_update_dirty_frz = 0;
832	m_cost_ins_tlb_occup_cache_frz = 0;
833	m_cost_data_tlb_occup_cache_frz = 0;
834
835	m_cpt_ins_tlb_inval = 0;
836	m_cpt_data_tlb_inval = 0;
837	m_cost_ins_tlb_inval_frz = 0;
838	m_cost_data_tlb_inval_frz = 0;
839
840	m_cpt_cc_update_data = 0;
841	m_cpt_cc_inval_ins = 0;
842	m_cpt_cc_inval_data = 0;
843	m_cpt_cc_broadcast = 0;
844
845	m_cost_updt_data_frz = 0;
846	m_cost_inval_ins_frz = 0;
847	m_cost_inval_data_frz = 0;
848	m_cost_broadcast_frz = 0;
849
850	m_cpt_cc_cleanup_data = 0;
851	m_cpt_cc_cleanup_ins = 0;
852
853	m_cpt_itlbmiss_transaction = 0;
854	m_cpt_itlb_ll_transaction = 0;
855	m_cpt_itlb_sc_transaction = 0;
856	m_cpt_dtlbmiss_transaction = 0;
857	m_cpt_dtlb_ll_transaction = 0;
858	m_cpt_dtlb_sc_transaction = 0;
859	m_cpt_dtlb_ll_dirty_transaction = 0;
860	m_cpt_dtlb_sc_dirty_transaction = 0;
861
862	m_cost_itlbmiss_transaction = 0;
863	m_cost_itlb_ll_transaction = 0;
864	m_cost_itlb_sc_transaction = 0;
865	m_cost_dtlbmiss_transaction = 0;
866	m_cost_dtlb_ll_transaction = 0;
867	m_cost_dtlb_sc_transaction = 0;
868	m_cost_dtlb_ll_dirty_transaction = 0;
869	m_cost_dtlb_sc_dirty_transaction = 0;
870
871	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
872	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
873	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
874	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
875	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0;
876	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0;
877	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0;
878
879	*/
880	return;
881	}
882
883	// Response FIFOs default values
884	bool vci_rsp_fifo_icache_get = false;
885	bool vci_rsp_fifo_icache_put = false;
886	uint32_t vci_rsp_fifo_icache_data = 0;
887
888	bool vci_rsp_fifo_dcache_get = false;
889	bool vci_rsp_fifo_dcache_put = false;
890	uint32_t vci_rsp_fifo_dcache_data = 0;
891
892	#ifdef INSTRUMENTATION
893	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
894	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
895	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
896	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
897	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
898	m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++;
899	#endif
900
901	m_cpt_total_cycles++;
902
903	m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
904	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
905	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
906	m_debug_inval_itlb_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
907	m_debug_inval_dtlb_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
908
909	/////////////////////////////////////////////////////////////////////
910	// The TGT_FSM controls the following ressources:
911	// - r_tgt_fsm
912	// - r_tgt_buf[nwords]
913	// - r_tgt_be[nwords]
914	// - r_tgt_update
915	// - r_tgt_word_min
916	// - r_tgt_word_max
917	// - r_tgt_word_count
918	// - r_tgt_paddr
919	// - r_tgt_srcid
920	// - r_tgt_trdid
921	// - r_tgt_pktid
922	// - r_tgt_icache_req (set)
923	// - r_tgt_dcache_req (set)
924	//
925	// All VCI commands must be CMD_WRITE.
926	// - If the 2 LSB bits of the VCI address are 11, it is a broadcast request.
927	// It is a multicast request otherwise.
928	// - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS
929	// (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes
930	// INVAL/UPDATE (0 for invalidate / 1 for UPDATE).
931	//
932	// For all types of coherence request, the line index (i.e. the Z & Y fields)
933	// is coded on 34 bits, and is contained in the WDATA and BE fields
934	// of the first VCI flit.
935	// - for a multicast invalidate or for a broadcast invalidate request
936	// the VCI packet length is 1 word.
937	// - for an update request the VCI packet length is (n+2) words.
938	// The WDATA field of the second VCI word contains the word index.
939	// The WDATA field of the n following words contains the values.
940	// - for all transaction types, the VCI response is one single word.
941	// In case of errors in the VCI command packet, the simulation
942	// is stopped with an error message.
943	//
944	// This FSM is NOT pipelined : It consumes a new coherence request
945	// on the VCI port only when the previous request is completed.
946	//
947	// The VCI_TGT FSM stores the external request arguments in the
948	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
949	// and/or the r_tgt_dcache_req flip-flops to signal the coherence request
950	// to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST
951	// states. It waits the completion of the coherence request by polling the
952	// r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST
953	// states. These flip-flops are reset by the ICACHE and DCACHE FSMs.
954	// These two FSMs signal if a VCI answer must be send by setting
955	// the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops.
956	///////////////////////////////////////////////////////////////////////////////
957
958	switch( r_tgt_fsm.read() )
959	{
960	//////////////
961	case TGT_IDLE:
962	{
963	if ( p_vci_tgt_c.cmdval.read() )
964	{
965	paddr_t address = p_vci_tgt_c.address.read();
966
967	// command checking
968	if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE)
969	{
970	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
971	std::cout << "the received VCI coherence command is not a write" << std::endl;
972	exit(0);
973	}
974
975	// address checking
976	if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) )
977	{
978	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
979	std::cout << "out of segment VCI coherence command received" << std::endl;
980	exit(0);
981	}
982
983	r_tgt_srcid = p_vci_tgt_c.srcid.read();
984	r_tgt_trdid = p_vci_tgt_c.trdid.read();
985	r_tgt_pktid = p_vci_tgt_c.pktid.read();
986
987	r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 \|
988	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
989
990	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
991	{
992	if ( not p_vci_tgt_c.eop.read() )
993	{
994	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
995	std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl;
996	exit(0);
997	}
998	r_tgt_update = false;
999	r_tgt_fsm = TGT_REQ_BROADCAST;
1000
1001	#ifdef INSTRUMENTATION
1002	m_cpt_cc_broadcast++;
1003	#endif
1004	}
1005	else // multi-update or multi-invalidate for data type
1006	{
1007	paddr_t cell = address - m_segment.baseAddress();
1008
1009	if (cell == 0) // invalidate data
1010	{
1011	if ( not p_vci_tgt_c.eop.read() )
1012	{
1013	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1014	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1015	exit(0);
1016	}
1017	r_tgt_update = false;
1018	r_tgt_fsm = TGT_REQ_DCACHE;
1019
1020	#ifdef INSTRUMENTATION
1021	m_cpt_cc_inval_dcache++;
1022	#endif
1023	}
1024	else if (cell == 4) // invalidate instruction
1025	{
1026	if ( not p_vci_tgt_c.eop.read() )
1027	{
1028	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1029	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1030	exit(0);
1031	}
1032	r_tgt_update = false;
1033	r_tgt_fsm = TGT_REQ_ICACHE;
1034
1035	#ifdef INSTRUMENTATION
1036	m_cpt_cc_inval_icache++;
1037	#endif
1038	}
1039	else if (cell == 8) // update data
1040	{
1041	if ( p_vci_tgt_c.eop.read() )
1042	{
1043	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1044	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1045	exit(0);
1046	}
1047	r_tgt_update = true;
1048	r_tgt_update_data = true;
1049	r_tgt_fsm = TGT_UPDT_WORD;
1050
1051	#ifdef INSTRUMENTATION
1052	m_cpt_cc_update_dcache++;
1053	#endif
1054	}
1055	else // update instruction
1056	{
1057	if ( p_vci_tgt_c.eop.read() )
1058	{
1059	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1060	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1061	exit(0);
1062	}
1063	r_tgt_update = true;
1064	r_tgt_update_data = false;
1065	r_tgt_fsm = TGT_UPDT_WORD;
1066
1067	#ifdef INSTRUMENTATION
1068	m_cpt_cc_update_icache++;
1069	#endif
1070	}
1071	} // end if multi
1072	} // end if cmdval
1073	break;
1074	}
1075	///////////////////
1076	case TGT_UPDT_WORD: // first word index acquisition
1077	{
1078	if (p_vci_tgt_c.cmdval.read())
1079	{
1080	if ( p_vci_tgt_c.eop.read() )
1081	{
1082	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1083	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1084	exit(0);
1085	}
1086	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false;
1087
1088	r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index
1089	r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index
1090	r_tgt_fsm = TGT_UPDT_DATA;
1091	}
1092	break;
1093	}
1094	///////////////////
1095	case TGT_UPDT_DATA:
1096	{
1097	if (p_vci_tgt_c.cmdval.read())
1098	{
1099	size_t word = r_tgt_word_count.read();
1100	if (word >= m_dcache_words)
1101	{
1102	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1103	std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl;
1104	exit(0);
1105	}
1106	r_tgt_buf[word] = p_vci_tgt_c.wdata.read();
1107	r_tgt_be[word] = p_vci_tgt_c.be.read();
1108	r_tgt_word_count = word + 1;
1109
1110	if (p_vci_tgt_c.eop.read()) // last word
1111	{
1112	r_tgt_word_max = word;
1113	if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE;
1114	else r_tgt_fsm = TGT_REQ_ICACHE;
1115	}
1116	}
1117	break;
1118	}
1119	///////////////////////
1120	case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs
1121	{
1122	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() )
1123	{
1124	r_tgt_fsm = TGT_RSP_BROADCAST;
1125	r_tgt_icache_req = true;
1126	r_tgt_dcache_req = true;
1127	}
1128	break;
1129	}
1130	/////////////////////
1131	case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending)
1132	{
1133	if ( not r_tgt_icache_req.read() )
1134	{
1135	r_tgt_fsm = TGT_RSP_ICACHE;
1136	r_tgt_icache_req = true;
1137	}
1138	break;
1139	}
1140	////////////////////
1141	case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending)
1142	{
1143	if ( not r_tgt_dcache_req.read() )
1144	{
1145	r_tgt_fsm = TGT_RSP_DCACHE;
1146	r_tgt_dcache_req = true;
1147	}
1148	break;
1149	}
1150	///////////////////////
1151	case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs
1152	// no response when r_tgt_*cache_rsp is false
1153	{
1154	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed
1155	{
1156	if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response
1157	{
1158	if ( p_vci_tgt_c.rspack.read() )
1159	{
1160	// reset dcache first if activated
1161	if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false;
1162	else r_tgt_icache_rsp = false;
1163	}
1164	}
1165	else
1166	{
1167	r_tgt_fsm = TGT_IDLE;
1168	}
1169	}
1170	break;
1171	}
1172	////////////////////
1173	case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM
1174	{
1175	// no response when r_tgt_icache_rsp is false
1176	if ( not r_tgt_icache_req.read() and p_vci_tgt_c.rspack.read() )
1177	{
1178	r_tgt_fsm = TGT_IDLE;
1179	r_tgt_icache_rsp = false;
1180	}
1181	break;
1182	}
1183	////////////////////
1184	case TGT_RSP_DCACHE:
1185	{
1186	// no response when r_tgt_dcache_rsp is false
1187	if ( not r_tgt_dcache_req.read() and p_vci_tgt_c.rspack.read() )
1188	{
1189	r_tgt_fsm = TGT_IDLE;
1190	r_tgt_dcache_rsp = false;
1191	}
1192	break;
1193	}
1194	} // end switch TGT_FSM
1195
1196	/////////////////////////////////////////////////////////////////////
1197	// Get data and instruction requests from processor
1198	///////////////////////////////////////////////////////////////////////
1199
1200	typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
1201	typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
1202
1203	r_iss.getRequests(ireq, dreq);
1204
1205	////////////////////////////////////////////////////////////////////////////////////
1206	// ICACHE_FSM
1207	//
1208	// There is 9 conditions to exit the IDLE state:
1209	// One condition is a coherence request from TGT FSM :
1210	// - Coherence operation => ICACHE_CC_CHEK
1211	// Five configurations corresponding to XTN processor requests sent by DCACHE FSM :
1212	// - Flush TLB => ICACHE_XTN_TLB_FLUSH
1213	// - Flush cache => ICACHE_XTN_CACHE_FLUSH
1214	// - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL
1215	// - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@
1216	// - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA
1217	// three configurations corresponding to instruction processor requests :
1218	// - tlb miss => ICACHE_TLB_WAIT
1219	// - cacheable read miss => ICACHE_MISS_VICTIM
1220	// - uncacheable read miss => ICACHE_UNC_REQ
1221	//
1222	// In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM
1223	// using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the
1224	// transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM
1225	// state to select a slot and request a VCI transaction to the CLEANUP FSM.
1226	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM.
1227	// The availability of the missing cache line is signaled by the response fifo,
1228	// and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state.
1229	//
1230	// In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
1231	// to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop
1232	// when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
1233	// the response from the RSP FSM, through the response fifo. The missing instruction
1234	// is directly returned to processor in this state.
1235	//
1236	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb
1237	// using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register,
1238	// and goes to the ICACHE_TLB_WAIT state.
1239	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until
1240	// the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
1241	//
1242	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1243	// using the r_dcache_xtn_req flip-flop.
1244	// The request opcode and the address to be invalidated are transmitted
1245	// in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
1246	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1247	// is completed.
1248	//
1249	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1250	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1251	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1252	////////////////////////////////////////////////////////////////////////////////////////
1253
1254	// The default value for irsp.valid is false
1255	typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
1256
1257	switch( r_icache_fsm.read() )
1258	{
1259	/////////////////
1260	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent
1261	// by DCACHE FSM, and coherence requests with a fixed priority:
1262	// coherence > XTN > instruction
1263	// We access the itlb and dcache in parallel with the virtual address
1264	// for itlb, and with a speculative physical address for icache,
1265	// computed during the previous cycle.
1266	{
1267	// coherence request from the target FSM
1268	if ( r_tgt_icache_req.read() )
1269	{
1270	r_icache_fsm = ICACHE_CC_CHECK;
1271	r_icache_fsm_save = r_icache_fsm.read();
1272	break;
1273	}
1274
1275	// Decoding processor XTN requests sent by DCACHE FSM
1276	// These request are not executed in this IDLE state, because
1277	// they require access to icache or itlb, that are already accessed
1278	if ( r_dcache_xtn_req.read() )
1279	{
1280	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1281	{
1282	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1283	break;
1284	}
1285	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1286	{
1287	r_icache_flush_count = 0;
1288	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1289	break;
1290	}
1291	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1292	{
1293	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1294	break;
1295	}
1296	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1297	{
1298	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1299	break;
1300	}
1301	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1302	{
1303	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1304	(paddr_t)r_mmu_word_lo.read();
1305	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1306	break;
1307	}
1308	} // end if xtn_req
1309
1310	// processor request
1311	if ( ireq.valid )
1312	{
1313	bool cacheable;
1314	paddr_t paddr;
1315
1316	// We register processor request
1317	r_icache_vaddr_save = ireq.addr;
1318
1319	// speculative icache access (if cache activated)
1320	// we use the speculative PPN computed during the previous cycle
1321
1322	uint32_t cache_inst = 0;
1323	bool cache_hit = false;
1324
1325	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1326	{
1327	paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) \|
1328	((paddr_t)ireq.addr & PAGE_K_MASK);
1329
1330	#ifdef INSTRUMENTATION
1331	m_cpt_icache_data_read++;
1332	m_cpt_icache_dir_read++;
1333	#endif
1334	cache_hit = r_icache.read( spc_paddr,
1335	&cache_inst );
1336	}
1337
1338	// systematic itlb access (if tlb activated)
1339	// we use the virtual address
1340
1341	paddr_t tlb_paddr;
1342	pte_info_t tlb_flags;
1343	size_t tlb_way;
1344	size_t tlb_set;
1345	paddr_t tlb_nline;
1346	bool tlb_hit = false;;
1347
1348	if ( r_mmu_mode.read() & INS_TLB_MASK )
1349	{
1350
1351	#ifdef INSTRUMENTATION
1352	m_cpt_itlb_read++;
1353	#endif
1354	tlb_hit = r_itlb.translate( ireq.addr,
1355	&tlb_paddr,
1356	&tlb_flags,
1357	&tlb_nline, // unused
1358	&tlb_way, // unused
1359	&tlb_set ); // unused
1360	}
1361
1362	// We compute cacheability, physical address and check access rights:
1363	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1364	// the physical address is obtained from the TLB, and the access rights are
1365	// defined by the U and X bits in the PTE.
1366	// - If MMU not activated : cacheability is defined by the segment table,
1367	// the physical address is equal to the virtual address (identity mapping)
1368	// and there is no access rights checking
1369
1370	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1371	{
1372	// cacheability
1373	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1374	else cacheable = m_cacheability_table[ireq.addr];
1375
1376	// physical address
1377	paddr = (paddr_t)ireq.addr;
1378	}
1379	else // itlb activated
1380	{
1381	if ( tlb_hit ) // tlb hit
1382	{
1383	// cacheability
1384	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1385	else cacheable = tlb_flags.c;
1386
1387	// physical address
1388	paddr = tlb_paddr;
1389
1390	// access rights checking
1391	if ( not tlb_flags.u && (ireq.mode == iss_t::MODE_USER) )
1392	{
1393	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1394	r_mmu_ibvar = ireq.addr;
1395	irsp.valid = true;
1396	irsp.error = true;
1397	irsp.instruction = 0;
1398	break;
1399	}
1400	else if ( not tlb_flags.x )
1401	{
1402	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1403	r_mmu_ibvar = ireq.addr;
1404	irsp.valid = true;
1405	irsp.error = true;
1406	irsp.instruction = 0;
1407	break;
1408	}
1409	}
1410	// in case of TLB miss we send an itlb miss request to DCACHE FSM and break
1411	else
1412	{
1413
1414	#ifdef INSTRUMENTATION
1415	m_cpt_itlb_miss++;
1416	#endif
1417	r_icache_fsm = ICACHE_TLB_WAIT;
1418	r_icache_tlb_miss_req = true;
1419	break;
1420	}
1421	} // end if itlb activated
1422
1423	// physical address registration (for next cycle)
1424	r_icache_vci_paddr = paddr;
1425
1426	// Finally, we get the instruction depending on cacheability
1427	if ( cacheable ) // cacheable read
1428	{
1429	if ( not cache_hit ) // cache miss
1430	{
1431	// in case of icache miss we send a request to CMD FSM, but we are
1432	// blocked in IDLE state if the previous cleanup is not completed
1433	if ( not r_icache_cleanup_req.read() )
1434	{
1435
1436	#ifdef INSTRUMENTATION
1437	m_cpt_icache_miss++;
1438	#endif
1439	r_icache_fsm = ICACHE_MISS_VICTIM;
1440	r_icache_miss_req = true;
1441	}
1442	}
1443	else // cache hit
1444	{
1445	if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK)
1446	!= (paddr & ~PAGE_K_MASK) ) // speculative access KO
1447	{
1448
1449	#ifdef INSTRUMENTATION
1450	m_cpt_icache_spc_miss++;
1451	#endif
1452	// we return an invalid response
1453	// and the cache access will cost one extra cycle.
1454	break;
1455	}
1456	else // speculative access OK
1457	{
1458
1459	#ifdef INSTRUMENTATION
1460	m_cpt_ins_read++;
1461	#endif
1462	irsp.valid = true;
1463	irsp.instruction = cache_inst;
1464	}
1465	}
1466	}
1467	else // non cacheable read
1468	{
1469	r_icache_unc_req = true;
1470	r_icache_fsm = ICACHE_UNC_WAIT;
1471	}
1472	} // end if ireq.valid
1473	break;
1474	}
1475	/////////////////////
1476	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1477	// the itlb is udated by the DCACHE FSM, as well as the
1478	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1479	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1480	// reset the r_icache_tlb_miss_req flip-flop
1481	// external coherence request are accepted in this state.
1482	{
1483	// external coherence request
1484	if ( r_tgt_icache_req.read() )
1485	{
1486	r_icache_fsm = ICACHE_CC_CHECK;
1487	r_icache_fsm_save = r_icache_fsm.read();
1488	break;
1489	}
1490
1491	if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
1492
1493	// DCACHE FSM signals response by reseting the request flip-flop
1494	if ( not r_icache_tlb_miss_req.read() )
1495	{
1496	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1497	{
1498	r_icache_tlb_rsp_error = false;
1499	irsp.error = true;
1500	irsp.valid = true;
1501	r_icache_fsm = ICACHE_IDLE;
1502	}
1503	else // tlb updated : return to IDLE state
1504	{
1505	r_icache_fsm = ICACHE_IDLE;
1506	}
1507	}
1508	break;
1509	}
1510	//////////////////////////
1511	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1512	{
1513	r_itlb.flush();
1514	r_dcache_xtn_req = false;
1515	r_icache_fsm = ICACHE_IDLE;
1516	break;
1517	}
1518	////////////////////////////
1519	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using
1520	// the r_icache_flush_count register as a slot counter.
1521	// We loop in this state until all slots have been visited.
1522	// A cleanup request is generated for each valid line
1523	// and we are blocked until the previous cleanup is completed
1524	{
1525	if ( not r_icache_cleanup_req.read() )
1526	{
1527	size_t way = r_icache_flush_count.read()/m_icache_sets;
1528	size_t set = r_icache_flush_count.read()%m_icache_sets;
1529	paddr_t nline;
1530	bool cleanup_req = r_icache.inval( way,
1531	set,
1532	&nline );
1533	if ( cleanup_req )
1534	{
1535	r_icache_cleanup_req = true;
1536	r_icache_cleanup_line = nline;
1537	}
1538	r_icache_flush_count = r_icache_flush_count.read() + 1;
1539	}
1540
1541	if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) )
1542	{
1543	r_dcache_xtn_req = false;
1544	r_icache_fsm = ICACHE_IDLE;
1545	}
1546	break;
1547	}
1548	//////////////////////////
1549	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1550	// stored in the r_dcache_p0_wdata register
1551	{
1552	r_itlb.inval(r_dcache_p0_wdata.read());
1553	r_dcache_xtn_req = false;
1554	r_icache_fsm = ICACHE_IDLE;
1555	break;
1556	}
1557	///////////////////////////////
1558	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1559	// requires 3 cycles (in case of hit on itlb and icache).
1560	// In this state, we access TLB to translate virtual address
1561	// stored in the r_dcache_p0_wdata register.
1562	{
1563	paddr_t paddr;
1564	bool hit;
1565
1566	// read physical address in TLB when MMU activated
1567	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1568	{
1569
1570	#ifdef INSTRUMENTATION
1571	m_cpt_itlb_read++;
1572	#endif
1573	hit = r_itlb.translate(r_dcache_p0_wdata.read(),
1574	&paddr);
1575	}
1576	else // itlb not activated
1577	{
1578	paddr = (paddr_t)r_dcache_p0_wdata.read();
1579	hit = true;
1580	}
1581
1582	if ( hit ) // continue the selective inval process
1583	{
1584	r_icache_vci_paddr = paddr;
1585	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1586	}
1587	else // miss : send a request to DCACHE FSM
1588	{
1589
1590	#ifdef INSTRUMENTATION
1591	m_cpt_itlb_miss++;
1592	#endif
1593	r_icache_tlb_miss_req = true;
1594	r_icache_fsm = ICACHE_TLB_WAIT;
1595	}
1596	break;
1597	}
1598	///////////////////////////////
1599	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1600	// require 2 cycles. In this state, we read dcache,
1601	// with address stored in r_icache_vci_paddr register.
1602	{
1603	uint32_t data;
1604	size_t way;
1605	size_t set;
1606	size_t word;
1607	bool hit = r_icache.read(r_icache_vci_paddr.read(),
1608	&data,
1609	&way,
1610	&set,
1611	&word);
1612	if ( hit ) // inval to be done
1613	{
1614	r_icache_miss_way = way;
1615	r_icache_miss_set = set;
1616	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1617	}
1618	else // miss : acknowlege the XTN request and return
1619	{
1620	r_dcache_xtn_req = false;
1621	r_icache_fsm = ICACHE_IDLE;
1622	}
1623	break;
1624	}
1625	///////////////////////////////
1626	case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup.
1627	// We are blocked if the previous cleanup is not completed
1628	{
1629	paddr_t nline;
1630
1631	if ( not r_icache_cleanup_req.read() )
1632	{
1633	r_icache.inval( r_icache_miss_way.read(),
1634	r_icache_miss_set.read(),
1635	&nline );
1636
1637	// request cleanup
1638	r_icache_cleanup_req = true;
1639	r_icache_cleanup_line = nline;
1640	// acknowledge the XTN request and return
1641	r_dcache_xtn_req = false;
1642	r_icache_fsm = ICACHE_IDLE;
1643	}
1644	break;
1645	}
1646
1647	////////////////////////
1648	case ICACHE_MISS_VICTIM: // Selects a victim line
1649	// Set the r_icache_cleanup_req flip-flop
1650	// when the selected slot is not empty
1651	{
1652	if ( ireq.valid ) m_cost_ins_miss_frz++;
1653
1654	bool valid;
1655	size_t way;
1656	size_t set;
1657	paddr_t victim;
1658
1659	valid = r_icache.victim_select(r_icache_vci_paddr.read(),
1660	&victim,
1661	&way,
1662	&set);
1663	r_icache_miss_way = way;
1664	r_icache_miss_set = set;
1665
1666	if ( valid )
1667	{
1668	r_icache_cleanup_req = true;
1669	r_icache_cleanup_line = victim;
1670	r_icache_fsm = ICACHE_MISS_INVAL;
1671	}
1672	else
1673	{
1674	r_icache_fsm = ICACHE_MISS_WAIT;
1675	}
1676	break;
1677	}
1678	///////////////////////
1679	case ICACHE_MISS_INVAL: // invalidate the victim line
1680	{
1681	paddr_t nline;
1682
1683	r_icache.inval( r_icache_miss_way.read(),
1684	r_icache_miss_set.read(),
1685	&nline ); // unused
1686
1687	r_icache_fsm = ICACHE_MISS_WAIT;
1688	break;
1689	}
1690	//////////////////////
1691	case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM
1692	{
1693	if ( ireq.valid ) m_cost_ins_miss_frz++;
1694
1695	// external coherence request
1696	if ( r_tgt_icache_req.read() )
1697	{
1698	r_icache_fsm = ICACHE_CC_CHECK;
1699	r_icache_fsm_save = r_icache_fsm.read();
1700	break;
1701	}
1702
1703	if ( r_vci_rsp_ins_error.read() ) // bus error
1704	{
1705	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1706	r_mmu_ibvar = r_icache_vaddr_save.read();
1707	irsp.valid = true;
1708	irsp.error = true;
1709	r_vci_rsp_ins_error = false;
1710	r_icache_fsm = ICACHE_IDLE;
1711	}
1712	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1713	{
1714	r_icache_miss_word = 0;
1715	r_icache_fsm = ICACHE_MISS_UPDT;
1716	}
1717	break;
1718	}
1719	//////////////////////
1720	case ICACHE_MISS_UPDT: // update the cache (one word per cycle)
1721	{
1722	if ( ireq.valid ) m_cost_ins_miss_frz++;
1723
1724	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1725	{
1726	if ( r_icache_miss_inval ) // Matching coherence request
1727	// We pop the response FIFO, without updating the cache
1728	// We send a cleanup for the missing line at the last word
1729	// Blocked if the previous cleanup is not completed
1730	{
1731	if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word
1732	{
1733	vci_rsp_fifo_icache_get = true;
1734	r_icache_miss_word = r_icache_miss_word.read() + 1;
1735	}
1736	else // last word
1737	{
1738	if ( not r_icache_cleanup_req.read() ) // no pending cleanup
1739	{
1740	vci_rsp_fifo_icache_get = true;
1741	r_icache_cleanup_req = true;
1742	r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2));
1743	r_icache_miss_inval = false;
1744	r_icache_fsm = ICACHE_IDLE;
1745	}
1746	}
1747	}
1748	else // No matching coherence request
1749	// We pop the FIFO and update the cache
1750	// We update the directory at the last word
1751	{
1752
1753	#ifdef INSTRUMENTATION
1754	m_cpt_icache_data_write++;
1755	#endif
1756	r_icache.write( r_icache_miss_way.read(),
1757	r_icache_miss_set.read(),
1758	r_icache_miss_word.read(),
1759	r_vci_rsp_fifo_icache.read() );
1760	vci_rsp_fifo_icache_get = true;
1761	r_icache_miss_word = r_icache_miss_word.read() + 1;
1762	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1763	{
1764
1765	#ifdef INSTRUMENTATION
1766	m_cpt_icache_dir_write++;
1767	#endif
1768	r_icache.victim_update_tag( r_icache_vci_paddr.read(),
1769	r_icache_miss_way.read(),
1770	r_icache_miss_set.read() );
1771	r_icache_fsm = ICACHE_IDLE;
1772	}
1773	}
1774	}
1775	break;
1776	}
1777	////////////////////
1778	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1779	//
1780	{
1781	// external coherence request
1782	if ( r_tgt_icache_req.read() )
1783	{
1784	r_icache_fsm = ICACHE_CC_CHECK;
1785	r_icache_fsm_save = r_icache_fsm.read();
1786	break;
1787	}
1788
1789	if ( r_vci_rsp_ins_error.read() ) // bus error
1790	{
1791	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1792	r_mmu_ibvar = ireq.addr;
1793	r_vci_rsp_ins_error = false;
1794	irsp.valid = true;
1795	irsp.error = true;
1796	r_icache_fsm = ICACHE_IDLE;
1797	}
1798	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1799	{
1800	vci_rsp_fifo_icache_get = true;
1801	r_icache_fsm = ICACHE_IDLE;
1802	if ( ireq.valid and (ireq.addr == r_icache_vaddr_save.read()) ) // request not modified
1803	{
1804	irsp.valid = true;
1805	irsp.instruction = r_vci_rsp_fifo_icache.read();
1806	}
1807	}
1808	break;
1809	}
1810	/////////////////////
1811	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1812	// handling coherence requests.
1813	// the return state is defined in r_icache_fsm_save.
1814	{
1815	paddr_t paddr = r_tgt_paddr.read();
1816	paddr_t mask = ~((m_icache_words<<2)-1);
1817
1818	if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and
1819	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss
1820	{
1821	r_icache_miss_inval = true; // signaling the matching
1822	r_tgt_icache_req = false; // coherence request completed
1823	r_tgt_icache_rsp = r_tgt_update.read(); // response required if update
1824	r_icache_fsm = r_icache_fsm_save.read();
1825	}
1826	else // no match
1827	{
1828
1829	#ifdef INSTRUMENTATION
1830	m_cpt_icache_dir_read++;
1831	#endif
1832	uint32_t inst;
1833	size_t way;
1834	size_t set;
1835	size_t word;
1836	bool hit = r_icache.read(paddr,
1837	&inst,
1838	&way,
1839	&set,
1840	&word);
1841	r_icache_cc_way = way;
1842	r_icache_cc_set = set;
1843
1844	if ( hit and r_tgt_update.read() ) // hit update
1845	{
1846	r_icache_fsm = ICACHE_CC_UPDT;
1847	r_icache_cc_word = r_tgt_word_min.read();
1848	}
1849	else if ( hit and not r_tgt_update.read() ) // hit inval
1850	{
1851	r_icache_fsm = ICACHE_CC_INVAL;
1852	}
1853	else // miss can happen
1854	{
1855	r_tgt_icache_req = false;
1856	r_tgt_icache_rsp = r_tgt_update.read();
1857	r_icache_fsm = r_icache_fsm_save.read();
1858	}
1859	}
1860	break;
1861	}
1862
1863	/////////////////////
1864	case ICACHE_CC_INVAL: // invalidate a cache line
1865	{
1866	paddr_t nline;
1867	r_icache.inval( r_icache_cc_way.read(),
1868	r_icache_cc_set.read(),
1869	&nline );
1870
1871	r_tgt_icache_req = false;
1872	r_tgt_icache_rsp = true;
1873	r_icache_fsm = r_icache_fsm_save.read();
1874	break;
1875	}
1876	////////////////////
1877	case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
1878	{
1879	size_t word = r_icache_cc_word.read();
1880	size_t way = r_icache_cc_way.read();
1881	size_t set = r_icache_cc_set.read();
1882
1883	r_icache.write( way,
1884	set,
1885	word,
1886	r_tgt_buf[word],
1887	r_tgt_be[word] );
1888
1889	r_icache_cc_word = word+1;
1890
1891	if ( word == r_tgt_word_max.read() ) // last word
1892	{
1893	r_tgt_icache_req = false;
1894	r_tgt_icache_rsp = true;
1895	r_icache_fsm = r_icache_fsm_save.read();
1896	}
1897	break;
1898	}
1899
1900	} // end switch r_icache_fsm
1901
1902	// save the IREQ and IRSP fields for the print_trace() function
1903	m_ireq_valid = ireq.valid;
1904	m_ireq_addr = ireq.addr;
1905	m_ireq_mode = ireq.mode;
1906
1907	m_irsp_valid = irsp.valid;
1908	m_irsp_instruction = irsp.instruction;
1909	m_irsp_error = irsp.error;
1910
1911	////////////////////////////////////////////////////////////////////////////////////
1912	// INVAL ITLB FSM
1913	// This FSM works in parallel with the ICACHE FSM.
1914	// When the r_dcache_itlb_inval_req flip-flop is activated by the DCACHE FSM
1915	// it scans sequencially all entries in the ITLB, and invalidates the
1916	// entries matching the evicted line.
1917	// It signals the completion of invalidation by reseting r_dcache_itlb_inval_req.
1918	////////////////////////////////////////////////////////////////////////////////////
1919
1920	switch(r_inval_itlb_fsm)
1921	{
1922	/////////////////////
1923	case INVAL_ITLB_IDLE:
1924	{
1925	if ( r_dcache_itlb_inval_req.read() )
1926	{
1927	r_itlb.reset_bypass(r_dcache_tlb_inval_line.read());
1928	r_inval_itlb_count = 0;
1929	r_inval_itlb_fsm = INVAL_ITLB_SCAN;
1930
1931	#if DEBUG_INVAL_ITLB
1932	if ( m_debug_inval_itlb_fsm )
1933	{
1934	std::cout << " <PROC.INVAL_ITLB_IDLE> Invalidate request for line "
1935	<< std::hex << r_dcache_tlb_inval_line.read() << std::endl;
1936	r_itlb.print();
1937	}
1938	#endif
1939	}
1940	break;
1941	}
1942	/////////////////////
1943	case INVAL_ITLB_SCAN:
1944	{
1945	paddr_t line = r_dcache_tlb_inval_line.read(); // nline
1946	size_t way = r_inval_itlb_count.read()/m_itlb_sets; // way
1947	size_t set = r_inval_itlb_count.read()%m_itlb_sets; // set
1948
1949	bool ok = r_itlb.inval( line,
1950	way,
1951	set );
1952
1953	#if DEBUG_INVAL_ITLB
1954	if ( m_debug_inval_itlb_fsm )
1955	{
1956	std::cout << " <PROC.INVAL_ITLB_SCAN>" << std::hex
1957	<< " line = " << line << std::dec
1958	<< " / set = " << set
1959	<< " / way = " << way;
1960	if ( ok ) std::cout << " / HIT" << std::endl;
1961	else std::cout << " / MISS" << std::endl;
1962	}
1963	#endif
1964
1965	r_inval_itlb_count = r_inval_itlb_count.read() + 1;
1966	if ( r_inval_itlb_count.read() == (m_itlb_sets*m_itlb_ways - 1) )
1967	{
1968	r_inval_itlb_fsm = INVAL_ITLB_IDLE;
1969	r_dcache_itlb_inval_req = false;
1970	}
1971	break;
1972	}
1973	} // end switch r_inval_itlb_fsm
1974
1975	////////////////////////////////////////////////////////////////////////////////////
1976	// DCACHE FSM
1977	//
1978	// Both the Cacheability Table, and the MMU cacheable bit are used to define
1979	// the cacheability, depending on the MMU mode.
1980	//
1981	// 1/ Coherence requests :
1982	// There is a coherence request when the tgt_dcache_req flip-flop is set,
1983	// requesting a line invalidation or a line update.
1984	// Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states.
1985	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
1986	// goes to the CC_CHECK state to execute the requested action, and returns to the
1987	// pre-empted state.
1988	//
1989	// 2/ processor requests :
1990	// Processor READ, WRITE, LL or SC requests are taken in IDLE state only.
1991	// The IDLE state implements a three stages pipe-line to handle write bursts:
1992	// - The physical address is computed by dtlb in stage P0.
1993	// - The registration in wbuf and the dcache hit are computed in stage P1.
1994	// - The dcache update is done in stage P2.
1995	// A write operation can require a fourth stage if the dirty bit must be updated,
1996	// or if the TLBs must be cleared, but these "long write" operation requires
1997	// to exit the IDLE stage
1998	// If there is no write in the pipe, dcache and dtlb are accessed in parallel,
1999	// (virtual address for itlb, and speculative physical address computed during
2000	// previous cycle for dcache) in order to return the data in one cycle for a read.
2001	// We just pay an extra cycle when the speculative access is illegal.
2002	//
2003	// 3/ Atomic instructions LL/SC
2004	// The LL/SC address can be cacheable or non cacheable.
2005	// The reservation registers (r_dcache_ll_valid, r_dcache_ll_vaddr and
2006	// r_dcache_ll_data are stored in the L1 cache controller, and not in the
2007	// memory controller.
2008	// - LL requests from the processor are transmitted as standard VCI
2009	// READ transactions (one word / one line, depending on the cacheability).
2010	// - SC requests from the processor are systematically transmitted to the
2011	// memory cache as COMPARE&swap requests (both the data value stored in the
2012	// r_dcache_ll_data register and the new value).
2013	//
2014	// 4/ Non cacheable access:
2015	// This component implement a strong order between non cacheable access
2016	// (read or write) : A new non cacheable VCI transaction starts only when
2017	// the previous non cacheable transaction is completed. Both cacheable and
2018	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2019	// a non cacheable write transaction posted in the write buffer by setting the
2020	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2021	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2022	// pending non cacheable write transaction completes).
2023	//
2024	// 5/ Error handling:
2025	// When the MMU is not activated, Read Bus Errors are synchronous events,
2026	// but Write Bus Errors are asynchronous events (processor is not frozen).
2027	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2028	// r_vci_rsp_data_error flip-flop, without writing any data in the
2029	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2030	// by the DCACHE FSM.
2031	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2032	// the asynchronous error using the setWriteBerr() method.
2033	// When the MMU is activated bus error are rare events, as the MMU
2034	// checks the physical address before the VCI transaction starts.
2035	////////////////////////////////////////////////////////////////////////////////////////
2036
2037	// The default value for drsp.valid is false
2038	typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
2039
2040	switch ( r_dcache_fsm.read() )
2041	{
2042	case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state :
2043	// 1) Long write request (DCACHE FSM) => DCACHE_WRITE_***
2044	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2045	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2046	// 4) XTN request (processor) => DCACHE_XTN_*
2047	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2048	// 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM
2049	// 7) Uncacheable read (processor) => DCACHE_UNC_REQ
2050	// 8) SC access (processor) => DCACHE_SC
2051	// There is 4 configurations to access the cache,
2052	// depending on the pipe-line state, defined
2053	// by the r_dcache_p0_valid flip-flop (P1 stage activated)
2054	// and r_dcache_p1_valid flip-flop (P2 stage activated) :
2055	// V0 / V1 / Data / Directory / comment
2056	// 0 / 0 / read(A0) / read(A0) / read speculative access
2057	// 0 / 1 / write(A2) / nop / read request delayed
2058	// 1 / 0 / nop / read(A1) / read request delayed
2059	// 1 / 1 / write(A2) / read(A1) / read request delayed
2060	{
2061	////////////////////////////////////////////////////////////////////////////////
2062	// Handling P2 pipe-line stage
2063	// Inputs are r_dcache_p1_* registers.
2064	// Three actions are executed in this P2 stage:
2065	// - If r_dcache_p1_updt_cache is true, we update the local copy in dcache.
2066	// - If the modified cache line has copies in itlb (resp. dtlb), and if the
2067	// INVAL_ITLB (resp. INVAL_DTLB) FSM is idle, we launch the TLB invalidate
2068	// operation. This operation is NOT blocking for the processor: the DCACHE FSM
2069	// doesn't wait the TLB invalidate completion to handle processor requests.
2070	// If the INVAL_ITLB (resp INVAL_DTLB) FSM is already processintg a previous
2071	// invalidation request, the DCACHE FSM is frosen until completion of the
2072	// previous TLB invalidate operation.
2073	// - If the PTE dirty bit must be updated, we start a "long write", that is
2074	// blocking for the processor, because we switch to the DCACHE_WRITE_SET_DIRTY
2075	// state, and the number of cycles can be large...
2076
2077	bool long_write_set_dirty = false;
2078	bool tlb_inval_frozen = false;
2079
2080	if ( r_dcache_p1_valid.read() ) // P2 stage activated
2081	{
2082	bool cache_updt = r_dcache_p1_updt_cache.read();
2083	size_t cache_way = r_dcache_p1_cache_way.read();
2084	size_t cache_set = r_dcache_p1_cache_set.read();
2085	size_t cache_word = r_dcache_p1_cache_word.read();
2086	uint32_t wdata = r_dcache_p1_wdata.read();
2087	vci_be_t be = r_dcache_p1_be.read();
2088
2089	// The PTE address is used when the PTE dirty bit must be set.
2090	// It is the concatenation of the nline value (from dtlb)
2091	// and the word index (from virtual address)
2092	paddr_t pte_paddr = (paddr_t)(r_dcache_p1_tlb_nline.read()*(m_dcache_words<<2))
2093	\| (paddr_t)(r_dcache_p1_vaddr.read()%(m_dcache_words<<2));
2094
2095	// The line index is used when a TLB inval is required
2096	paddr_t inval_line = r_dcache_p1_paddr.read()>>(uint32_log2(m_dcache_words<<2));
2097
2098	// checking dcache update
2099	if ( cache_updt )
2100	{
2101	r_dcache.write( cache_way,
2102	cache_set,
2103	cache_word,
2104	wdata,
2105	be );
2106	#ifdef INSTRUMENTATION
2107	m_cpt_dcache_data_write++;
2108	#endif
2109
2110	// Checking copies in TLBs
2111	bool itlb_inval = ( (r_mmu_mode.read() & INS_TLB_MASK) and
2112	r_dcache_in_itlb[cache_way*m_dcache_sets+cache_set] );
2113	bool dtlb_inval = ( (r_mmu_mode.read() & DATA_TLB_MASK) and
2114	r_dcache_in_dtlb[cache_way*m_dcache_sets+cache_set] );
2115
2116	if ( (dtlb_inval and r_dcache_dtlb_inval_req.read() ) or
2117	(itlb_inval and r_dcache_itlb_inval_req.read() ) ) // at least one FSM not idle
2118	{
2119	tlb_inval_frozen = true;
2120	}
2121	else // requested FSM idle
2122	{
2123	r_dcache_tlb_inval_line = inval_line;
2124	r_dcache_itlb_inval_req = itlb_inval;
2125	r_dcache_dtlb_inval_req = dtlb_inval;
2126	r_dcache_in_itlb[cache_way*m_dcache_sets+cache_set] = false;
2127	r_dcache_in_dtlb[cache_way*m_dcache_sets+cache_set] = false;
2128	}
2129	} // end dcache update
2130
2131	// checking dirty bit update
2132	if ( r_dcache_p1_set_dirty.read() )
2133	{
2134	long_write_set_dirty = true;
2135	r_dcache_p2_vaddr = r_dcache_p1_vaddr.read();
2136	r_dcache_p2_set_dirty = r_dcache_p1_set_dirty.read();
2137	r_dcache_p2_tlb_way = r_dcache_p1_tlb_way.read();
2138	r_dcache_p2_tlb_set = r_dcache_p1_tlb_set.read();
2139	r_dcache_p2_pte_paddr = pte_paddr;
2140	}
2141
2142	#if DEBUG_DCACHE
2143	if ( m_debug_dcache_fsm )
2144	{
2145	if ( cache_updt )
2146	std::cout << " <PROC.DCACHE_IDLE> P2 stage: cache update" << std::dec
2147	<< " / way = " << cache_way
2148	<< " / set = " << cache_set
2149	<< " / word = " << cache_word << std::hex
2150	<< " / wdata = " << wdata
2151	<< " / be = " << be << std::endl;
2152	if ( long_write_set_dirty )
2153	std::cout << " <PROC.DCACHE_IDLE> P2 stage: dirty bit update required"
2154	<< " / pte_paddr = " << std::hex << pte_paddr << std::endl;
2155	}
2156	#endif
2157	} // end P2 stage
2158
2159	///////////////////////////////////////////////////////////////////////////
2160	// Handling P1 pipe-line stage
2161	// Inputs are r_dcache_p0_* registers.
2162	// - We must write into wbuf and test the hit in dcache.
2163	// If the write request is not cacheable, and there is a pending
2164	// non cacheable write, or if the write buffer is full, we break:
2165	// The P0 and P1 pipe-line stages are frozen until the write
2166	// request registration is possible, but the P2 stage is not frozen.
2167	// - The r_dcache_p1_valid bit activating the P2 pipe-line stage
2168	// must be computed at all cycles. The P2 stage must be activated
2169	// if there is local copy in dcache, or if the PTE dirty bit must be set.
2170
2171	if ( r_dcache_p0_valid.read() and not tlb_inval_frozen ) // P1 stage activated
2172	{
2173	// write not cacheable, and previous non cacheable write registered
2174	if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() )
2175	{
2176	r_dcache_p1_valid = false;
2177	break;
2178	}
2179
2180	// try a registration into write buffer
2181	bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
2182	r_dcache_p0_be.read(),
2183	r_dcache_p0_wdata.read(),
2184	r_dcache_p0_cacheable.read() );
2185	#ifdef INSTRUMENTATION
2186	m_cpt_wbuf_write++;
2187	#endif
2188	// write buffer full
2189	if ( not wok )
2190	{
2191	r_dcache_p1_valid = false;
2192	break;
2193	}
2194	// update the write_buffer state extension
2195	r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
2196
2197	// read directory to detect local copy
2198	size_t cache_way;
2199	size_t cache_set;
2200	size_t cache_word;
2201	bool local_copy;
2202	if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated
2203	{
2204	local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
2205	&cache_way,
2206	&cache_set,
2207	&cache_word );
2208	#ifdef INSTRUMENTATION
2209	m_cpt_dcache_dir_read++;
2210	#endif
2211	}
2212	else
2213	{
2214	local_copy = false;
2215	}
2216
2217	// dirty bit update requested
2218	bool dirty_req = (r_mmu_mode.read() & DATA_TLB_MASK) and not r_dcache_p0_tlb_dirty.read();
2219
2220	// if there is a local copy or a dirty bit update requested
2221	if ( local_copy or dirty_req )
2222	{
2223	r_dcache_p1_valid = true;
2224	r_dcache_p1_set_dirty = dirty_req;
2225	r_dcache_p1_updt_cache = local_copy;
2226	r_dcache_p1_vaddr = r_dcache_p0_vaddr.read();
2227	r_dcache_p1_wdata = r_dcache_p0_wdata.read();
2228	r_dcache_p1_be = r_dcache_p0_be.read();
2229	r_dcache_p1_paddr = r_dcache_p0_paddr.read();
2230	r_dcache_p1_tlb_way = r_dcache_p0_tlb_way;
2231	r_dcache_p1_tlb_set = r_dcache_p0_tlb_set;
2232	r_dcache_p1_tlb_nline = r_dcache_p0_tlb_nline;
2233	r_dcache_p1_cache_way = cache_way;
2234	r_dcache_p1_cache_set = cache_set;
2235	r_dcache_p1_cache_word = cache_word;
2236	}
2237	else
2238	{
2239	r_dcache_p1_valid = false;
2240	}
2241	}
2242	else // P1 stage not activated
2243	{
2244	r_dcache_p1_valid = false;
2245	} // end P1 stage
2246
2247	/////////////////////////////////////////////////////////////////////////////
2248	// handling P0 write pipe-line stage
2249	// This stage is controlling the DCACHE FSM state register:
2250	// - the FSM is frozen if a TLB invalidate operation must be delayed,
2251	// - the long write requests have the highest priority,
2252	// - then the external coherence requests,
2253	// - then the itlb miss requests,
2254	// - and finally the processor requests.
2255	// A processor read request generate a dcache access using speculative PPN
2256	// only if the write pipe-line is empty. There is an unconditionnal access
2257	// to the dtlb, using virtual address from processor.
2258	// The r_dcache_p0_valid value must be computed at all cycles.
2259
2260	bool p0_valid = false; // default value
2261
2262	// TLB inval delayed
2263	if ( tlb_inval_frozen )
2264	{
2265	break;
2266	}
2267
2268	// long write request
2269	else if ( long_write_set_dirty )
2270	{
2271	r_dcache_fsm = DCACHE_WRITE_TLB_DIRTY;
2272	}
2273
2274	// external coherence request
2275	else if ( r_tgt_dcache_req.read() )
2276	{
2277	r_dcache_fsm = DCACHE_CC_CHECK;
2278	r_dcache_fsm_save = DCACHE_IDLE;
2279	}
2280
2281	// itlb miss request
2282	else if ( r_icache_tlb_miss_req.read() )
2283	{
2284	r_dcache_tlb_ins = true;
2285	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2286	r_dcache_fsm = DCACHE_TLB_MISS;
2287	}
2288
2289	// processor request
2290	else if (dreq.valid )
2291	{
2292	// dcache access using speculative PPN only if pipe-line empty
2293	paddr_t cache_paddr;
2294	size_t cache_way;
2295	size_t cache_set;
2296	size_t cache_word;
2297	uint32_t cache_rdata;
2298	bool cache_hit;
2299
2300	if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated
2301	not r_dcache_p0_valid.read() and
2302	not r_dcache_p1_valid.read() ) // pipe-line empty
2303	{
2304	cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) \|
2305	((paddr_t)dreq.addr & PAGE_K_MASK);
2306
2307	cache_hit = r_dcache.read( cache_paddr,
2308	&cache_rdata,
2309	&cache_way,
2310	&cache_set,
2311	&cache_word );
2312	#ifdef INSTRUMENTATION
2313	m_cpt_dcache_dir_read++;
2314	m_cpt_dcache_data_read++;
2315	#endif
2316	}
2317	else
2318	{
2319	cache_hit = false;
2320	} // end dcache access
2321
2322	// systematic dtlb access using virtual address
2323
2324	paddr_t tlb_paddr;
2325	pte_info_t tlb_flags;
2326	size_t tlb_way;
2327	size_t tlb_set;
2328	paddr_t tlb_nline;
2329	bool tlb_hit;
2330
2331	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // TLB activated
2332	{
2333	tlb_hit = r_dtlb.translate( dreq.addr,
2334	&tlb_paddr,
2335	&tlb_flags,
2336	&tlb_nline,
2337	&tlb_way,
2338	&tlb_set );
2339	#ifdef INSTRUMENTATION
2340	m_cpt_dtlb_read++;
2341	#endif
2342	// register dtlb outputs
2343	r_dcache_p0_tlb_nline = tlb_nline;
2344	r_dcache_p0_tlb_way = tlb_way;
2345	r_dcache_p0_tlb_set = tlb_set;
2346	r_dcache_p0_tlb_dirty = tlb_flags.d;
2347	r_dcache_p0_tlb_big = tlb_flags.b;
2348	}
2349	else
2350	{
2351	tlb_hit = false;
2352	} // end dtlb access
2353
2354	// register the processor request
2355	r_dcache_p0_vaddr = dreq.addr;
2356	r_dcache_p0_be = dreq.be;
2357	r_dcache_p0_wdata = dreq.wdata;
2358
2359	// Handling READ XTN requests from processor
2360	// They are executed in this DCACHE_IDLE state.
2361	// The processor must not be in user mode
2362	if (dreq.type == iss_t::XTN_READ)
2363	{
2364	int xtn_opcode = (int)dreq.addr/4;
2365
2366	// checking processor mode:
2367	if (dreq.mode == iss_t::MODE_USER)
2368	{
2369	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2370	r_mmu_dbvar = dreq.addr;
2371	drsp.valid = true;
2372	drsp.error = true;
2373	r_dcache_fsm = DCACHE_IDLE;
2374	}
2375	else
2376	{
2377	switch( xtn_opcode )
2378	{
2379	case iss_t::XTN_INS_ERROR_TYPE:
2380	drsp.rdata = r_mmu_ietr.read();
2381	drsp.valid = true;
2382	break;
2383
2384	case iss_t::XTN_DATA_ERROR_TYPE:
2385	drsp.rdata = r_mmu_detr.read();
2386	drsp.valid = true;
2387	break;
2388
2389	case iss_t::XTN_INS_BAD_VADDR:
2390	drsp.rdata = r_mmu_ibvar.read();
2391	drsp.valid = true;
2392	break;
2393
2394	case iss_t::XTN_DATA_BAD_VADDR:
2395	drsp.rdata = r_mmu_dbvar.read();
2396	drsp.valid = true;
2397	break;
2398
2399	case iss_t::XTN_PTPR:
2400	drsp.rdata = r_mmu_ptpr.read();
2401	drsp.valid = true;
2402	break;
2403
2404	case iss_t::XTN_TLB_MODE:
2405	drsp.rdata = r_mmu_mode.read();
2406	drsp.valid = true;
2407	break;
2408
2409	case iss_t::XTN_MMU_PARAMS:
2410	drsp.rdata = r_mmu_params.read();
2411	drsp.valid = true;
2412	break;
2413
2414	case iss_t::XTN_MMU_RELEASE:
2415	drsp.rdata = r_mmu_release.read();
2416	drsp.valid = true;
2417	break;
2418
2419	case iss_t::XTN_MMU_WORD_LO:
2420	drsp.rdata = r_mmu_word_lo.read();
2421	drsp.valid = true;
2422	break;
2423
2424	case iss_t::XTN_MMU_WORD_HI:
2425	drsp.rdata = r_mmu_word_hi.read();
2426	drsp.valid = true;
2427	break;
2428
2429	default:
2430	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2431	r_mmu_dbvar = dreq.addr;
2432	drsp.valid = true;
2433	drsp.error = true;
2434	break;
2435	} // end switch xtn_opcode
2436	} // end else
2437	} // end if XTN_READ
2438
2439	// Handling WRITE XTN requests from processor.
2440	// They are not executed in this DCACHE_IDLE state,
2441	// if they require access to the caches or the TLBs
2442	// that are already accessed for speculative read.
2443	// Caches can be invalidated or flushed in user mode,
2444	// and the sync instruction can be executed in user mode
2445	else if (dreq.type == iss_t::XTN_WRITE)
2446	{
2447	int xtn_opcode = (int)dreq.addr/4;
2448	r_dcache_xtn_opcode = xtn_opcode;
2449
2450	// checking processor mode:
2451	if ( (dreq.mode == iss_t::MODE_USER) &&
2452	(xtn_opcode != iss_t:: XTN_SYNC) &&
2453	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2454	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2455	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2456	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2457	{
2458	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2459	r_mmu_dbvar = dreq.addr;
2460	drsp.valid = true;
2461	drsp.error = true;
2462	r_dcache_fsm = DCACHE_IDLE;
2463	}
2464	else
2465	{
2466	switch( xtn_opcode )
2467	{
2468	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2469	r_mmu_ptpr = dreq.wdata;
2470	r_dcache_xtn_req = true;
2471	r_dcache_fsm = DCACHE_XTN_SWITCH;
2472	break;
2473
2474	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2475	r_mmu_mode = dreq.wdata;
2476	drsp.valid = true;
2477	r_dcache_fsm = DCACHE_IDLE;
2478	break;
2479
2480	case iss_t::XTN_DTLB_INVAL: // dtlb access
2481	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2482	break;
2483
2484	case iss_t::XTN_ITLB_INVAL: // itlb access
2485	r_dcache_xtn_req = true;
2486	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2487	break;
2488
2489	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2490	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2491	break;
2492
2493	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2494	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2495	r_dcache_p0_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2496	(paddr_t)r_mmu_word_lo.read();
2497	break;
2498
2499	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2500	r_dcache_flush_count = 0;
2501	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2502	break;
2503
2504	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2505	r_dcache_xtn_req = true;
2506	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2507	break;
2508
2509	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2510	r_dcache_xtn_req = true;
2511	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2512	break;
2513
2514	case iss_t::XTN_ICACHE_FLUSH: // icache access
2515	r_dcache_xtn_req = true;
2516	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2517	break;
2518
2519	case iss_t::XTN_SYNC: // wait until write buffer empty
2520	r_dcache_fsm = DCACHE_XTN_SYNC;
2521	break;
2522
2523	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2524	r_mmu_word_lo = dreq.wdata;
2525	drsp.valid = true;
2526	r_dcache_fsm = DCACHE_IDLE;
2527	break;
2528
2529	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2530	r_mmu_word_hi = dreq.wdata;
2531	drsp.valid = true;
2532	r_dcache_fsm = DCACHE_IDLE;
2533	break;
2534
2535	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2536	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2537	drsp.valid = true;
2538	r_dcache_fsm = DCACHE_IDLE;
2539	break;
2540
2541	default:
2542	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2543	r_mmu_dbvar = dreq.addr;
2544	drsp.valid = true;
2545	drsp.error = true;
2546	r_dcache_fsm = DCACHE_IDLE;
2547	break;
2548	} // end switch xtn_opcode
2549	} // end else
2550	} // end if XTN_WRITE
2551
2552	// Handling read/write processor requests.
2553	// The dtlb and dcache can be activated or not.
2554	// We compute the physical address, the cacheability, and check processor request.
2555	// - If DTLB not activated : cacheability is defined by the segment table,
2556	// the physical address is equal to the virtual address (identity mapping)
2557	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2558	// the physical address is obtained from the TLB, and the U & W bits
2559	// of the PTE are checked.
2560	// The processor request is decoded only if the TLB is not activated or if
2561	// the virtual address hits in tLB and access rights are OK.
2562	// We call the TLB_MISS sub-fsm in case of dtlb miss.
2563	else
2564	{
2565	bool valid_req = false;
2566	bool cacheable = false;
2567	paddr_t paddr = 0;
2568
2569	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2570	{
2571	valid_req = true;
2572
2573	// cacheability
2574	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2575	else cacheable = m_cacheability_table[dreq.addr];
2576
2577	// physical address
2578	paddr = (paddr_t)dreq.addr;
2579	}
2580	else // dtlb activated
2581	{
2582	if ( tlb_hit ) // tlb hit
2583	{
2584	// cacheability
2585	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2586	else cacheable = tlb_flags.c;
2587
2588	// access rights checking
2589	if ( not tlb_flags.u and (dreq.mode == iss_t::MODE_USER))
2590	{
2591	if ( (dreq.type == iss_t::DATA_READ) or (dreq.type == iss_t::DATA_LL) )
2592	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2593	else
2594	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2595
2596	r_mmu_dbvar = dreq.addr;
2597	drsp.valid = true;
2598	drsp.error = true;
2599	drsp.rdata = 0;
2600	}
2601	else if ( not tlb_flags.w and
2602	((dreq.type == iss_t::DATA_WRITE) or
2603	(dreq.type == iss_t::DATA_SC)) )
2604	{
2605	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2606	r_mmu_dbvar = dreq.addr;
2607	drsp.valid = true;
2608	drsp.error = true;
2609	drsp.rdata = 0;
2610	}
2611	else
2612	{
2613	valid_req = true;
2614	}
2615
2616	// physical address
2617	paddr = tlb_paddr;
2618	}
2619	else // tlb miss
2620	{
2621	r_dcache_tlb_vaddr = dreq.addr;
2622	r_dcache_tlb_ins = false;
2623	r_dcache_fsm = DCACHE_TLB_MISS;
2624	}
2625	} // end DTLB activated
2626
2627	if ( valid_req ) // processor request is valid
2628	{
2629	// physical address and cacheability registration
2630	r_dcache_p0_paddr = paddr;
2631	r_dcache_p0_cacheable = cacheable;
2632
2633	// READ or LL request
2634	// The read requests are taken only if the write pipe-line is empty.
2635	// If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle.
2636	// If speculative access is KO we just pay one extra cycle.
2637	// If dcache miss, we go to DCACHE_MISS_VICTIM state.
2638	// If uncacheable, we go to DCACHE_UNC_WAIT state.
2639	if ( ((dreq.type == iss_t::DATA_READ) or (dreq.type == iss_t::DATA_LL)) and
2640	not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2641	{
2642	if ( cacheable ) // cacheable read
2643	{
2644	// if the speculative access is illegal, we pay an extra cycle
2645	if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK)
2646	!= (paddr & ~PAGE_K_MASK))
2647	{
2648	#ifdef INSTRUMENTATION
2649	m_cpt_dcache_spec_miss++;
2650	#endif
2651	}
2652	// if cache miss, try to get the missing line
2653	else if ( not cache_hit )
2654	{
2655	#ifdef INSTRUMENTATION
2656	m_cpt_dcache_miss++;
2657	#endif
2658	// blocked in IDLE state if previous cleanup not completed
2659	if ( not r_dcache_cleanup_req.read() )
2660	{
2661	r_dcache_vci_paddr = paddr;
2662	r_dcache_vci_miss_req = true;
2663	r_dcache_miss_type = PROC_MISS;
2664	r_dcache_fsm = DCACHE_MISS_VICTIM;
2665	}
2666	}
2667	// if cache hit return the data
2668	else
2669	{
2670	#ifdef INSTRUMENTATION
2671	m_cpt_data_read++;
2672	#endif
2673	drsp.valid = true;
2674	drsp.rdata = cache_rdata;
2675	}
2676	}
2677	else // uncacheable read
2678	{
2679	r_dcache_vci_paddr = paddr;
2680	r_dcache_vci_unc_be = dreq.be;
2681	r_dcache_vci_unc_req = true;
2682	r_dcache_fsm = DCACHE_UNC_WAIT;
2683	}
2684
2685	// makes reservation in case of LL
2686	if ( dreq.type == iss_t::DATA_LL )
2687	{
2688	r_dcache_ll_valid = true;
2689	r_dcache_ll_data = cache_rdata;
2690	r_dcache_ll_vaddr = dreq.addr;
2691	}
2692	} // end READ or LL
2693
2694	// WRITE request:
2695	// The write request arguments have been registered.
2696	// The physical address has been computed and registered.
2697	// We acknowledge the processor request and activate the P1 pipeline stage.
2698	else if ( dreq.type == iss_t::DATA_WRITE )
2699	{
2700
2701	#ifdef INSTRUMENTATION
2702	m_cpt_data_write++;
2703	#endif
2704	p0_valid = true;
2705	drsp.valid = true;
2706	drsp.rdata = 0;
2707	} // end WRITE
2708
2709	// SC request:
2710	// - if a valid LL reservation (with the same address) is registered,
2711	// we request a SC transaction to CMD FSM and go to the DCACHE_SC_WAIT state
2712	// that will directly return the response to the processor, and invalidate
2713	// the LL reservation. We don't check a possible hit in dcache, as this is
2714	// done by the coherence transaction...
2715	// - if there is no registerd LL, we just stay in IDLE state, invalidate
2716	// the LL reservation, and return 1 (atomic access failed)
2717	else if ( dreq.type == iss_t::DATA_SC )
2718	{
2719	#ifdef INSTRUMENTATION
2720	m_cpt_data_sc++;
2721	#endif
2722	// test if valid registered LL
2723	if ( r_dcache_ll_valid.read() and (r_dcache_ll_vaddr.read() == dreq.addr))
2724	{
2725	r_dcache_vci_paddr = paddr;
2726	r_dcache_vci_sc_req = true;
2727	r_dcache_vci_sc_old = r_dcache_ll_data.read();
2728	r_dcache_vci_sc_new = dreq.wdata;
2729	r_dcache_fsm = DCACHE_UNC_WAIT;
2730	}
2731	else // no registered LL
2732	{
2733	drsp.valid = true;
2734	drsp.rdata = 1;
2735	r_dcache_ll_valid = false;
2736	}
2737	} // end SC
2738	} // end valid_req
2739	} // end if read/write request
2740	} // end P0 pipe stage
2741
2742	r_dcache_p0_valid = p0_valid;
2743	break;
2744	}
2745	/////////////////////
2746	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling tlb miss.
2747	// - Input arguments are r_dcache_tlb_vaddr & r_dcache_tlb_ins
2748	// - It try to find the missing TLB entry in dcache,
2749	// and activates the cache miss procedure in case of miss.
2750	// - It bypass the first level page table access if possible.
2751	// - It uses atomic access to update the R/L access bits
2752	// in the page table if required.
2753	// - It directly updates the itlb or dtlb, and writes into the
2754	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2755	{
2756	uint32_t ptba = 0;
2757	bool bypass;
2758	paddr_t paddr;
2759
2760	// evaluate bypass in order to skip first level page table access
2761	if ( r_dcache_tlb_ins.read() ) // itlb miss
2762	{
2763	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2764	}
2765	else // dtlb miss
2766	{
2767	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2768	}
2769
2770	if ( not bypass ) // Try to read the PTE1/PTD1 in dcache
2771	{
2772	paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2773	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2774	r_dcache_tlb_paddr = paddr;
2775	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2776	}
2777	else // Try to read directly the PTE2 in dcache
2778	{
2779	paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2780	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2781	r_dcache_tlb_paddr = paddr;
2782	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2783	}
2784
2785	#if DEBUG_DCACHE
2786	if ( m_debug_dcache_fsm )
2787	{
2788	if ( r_dcache_tlb_ins.read() )
2789	std::cout << " <PROC.DCACHE_TLB_MISS> ITLB miss request:";
2790	else
2791	std::cout << " <PROC.DCACHE_TLB_MISS> DTLB miss request:";
2792	std::cout << " vaddr = " << std::hex << r_dcache_tlb_vaddr.read()
2793	<< " / bypass = " << bypass
2794	<< " / PTE address = " << paddr << std::endl;
2795	}
2796	#endif
2797
2798	break;
2799	}
2800	/////////////////////////
2801	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2802	{
2803	uint32_t entry;
2804	size_t way;
2805	size_t set;
2806	size_t word;
2807
2808	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2809	&entry,
2810	&way,
2811	&set,
2812	&word );
2813	#ifdef INSTRUMENTATION
2814	m_cpt_dcache_data_read++;
2815	m_cpt_dcache_dir_read++;
2816	#endif
2817	if ( hit ) // request hit in dcache
2818	{
2819	if ( not (entry & PTE_V_MASK) ) // unmapped
2820	{
2821	if ( r_dcache_tlb_ins.read() )
2822	{
2823	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2824	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2825	r_icache_tlb_miss_req = false;
2826	r_icache_tlb_rsp_error = true;
2827	}
2828	else
2829	{
2830	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2831	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2832	drsp.valid = true;
2833	drsp.error = true;
2834	}
2835	r_dcache_fsm = DCACHE_IDLE;
2836
2837	#if DEBUG_DCACHE
2838	if ( m_debug_dcache_fsm )
2839	{
2840	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped:"
2841	<< std::dec << " way = " << way
2842	<< std::dec << " / set = " << set
2843	<< std::dec << " / word = " << word
2844	<< std::hex << " / PTE1 = " << entry << std::endl;
2845	}
2846	#endif
2847
2848	}
2849	else if( entry & PTE_T_MASK ) // PTD : access PT2
2850	{
2851	// register bypass
2852	if ( r_dcache_tlb_ins.read() ) // itlb
2853	{
2854	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2855	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2856	r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2)));
2857	}
2858	else // dtlb
2859	{
2860	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2861	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2862	r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2));
2863	}
2864	r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2865	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2866	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2867
2868	#if DEBUG_DCACHE
2869	if ( m_debug_dcache_fsm )
2870	{
2871	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache "
2872	<< std::dec << " way = " << way
2873	<< std::dec << " / set = " << set
2874	<< std::dec << " / word = " << word
2875	<< std::hex << " / PTD = " << entry << std::endl;
2876	}
2877	#endif
2878	}
2879	else // PTE1 : update the TLB
2880	{
2881	if ( r_dcache_tlb_ins.read() )
2882	r_dcache_in_itlb[m_icache_sets*way+set] = true;
2883	else
2884	r_dcache_in_dtlb[m_dcache_sets*way+set] = true;
2885	r_dcache_tlb_pte_flags = entry;
2886	r_dcache_tlb_cache_way = way;
2887	r_dcache_tlb_cache_set = set;
2888	r_dcache_tlb_cache_word = word;
2889	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2890
2891	#if DEBUG_DCACHE
2892	if ( m_debug_dcache_fsm )
2893	{
2894	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache:"
2895	<< std::dec << " way = " << way
2896	<< std::dec << " / set = " << set
2897	<< std::dec << " / word = " << word
2898	<< std::hex << " / PTE1 = " << entry << std::endl;
2899	}
2900	#endif
2901	}
2902	}
2903	else // we must load the missing cache line in dcache
2904	{
2905	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2906	r_dcache_miss_type = PTE1_MISS;
2907	r_dcache_fsm = DCACHE_MISS_VICTIM;
2908	r_dcache_vci_miss_req = true;
2909
2910	#if DEBUG_DCACHE
2911	if ( m_debug_dcache_fsm )
2912	{
2913	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:"
2914	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2915	}
2916	#endif
2917	}
2918	break;
2919	}
2920	////////////////////////////
2921	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2922	{
2923	size_t way;
2924	size_t set;
2925
2926	if ( r_dcache_tlb_ins.read() )
2927	{
2928	r_itlb.select( r_dcache_tlb_vaddr.read(),
2929	true, // PTE1
2930	&way,
2931	&set );
2932	#ifdef INSTRUMENTATION
2933	m_cpt_itlb_read++;
2934	#endif
2935	}
2936	else
2937	{
2938	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2939	true, // PTE1
2940	&way,
2941	&set );
2942	#ifdef INSTRUMENTATION
2943	m_cpt_dtlb_read++;
2944	#endif
2945	}
2946	r_dcache_tlb_way = way;
2947	r_dcache_tlb_set = set;
2948	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
2949
2950	#if DEBUG_DCACHE
2951	if ( m_debug_dcache_fsm )
2952	{
2953	if ( r_dcache_tlb_ins.read() )
2954	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
2955	else
2956	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
2957	std::cout << " way = " << std::dec << way
2958	<< " / set = " << set << std::endl;
2959	}
2960	#endif
2961	break;
2962	}
2963	//////////////////////////
2964	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
2965	// if L/R bit already set, exit the sub-fsm
2966	// if not, the page table must be updated
2967	{
2968	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
2969	uint32_t pte = r_dcache_tlb_pte_flags.read();
2970	bool updt = false;
2971
2972	// test the access bits L/R, depending on the physical address locality
2973	// we must use the 10 MSB bits of the 19 bits PPN1 to obtain the target index
2974	// we must use the 10 MSB bits of the SRCID to obtain the local index
2975	// set the r_dcache_vci_sc_old and r_dcache_vci_sc_new registers if SC required
2976
2977	uint32_t target = (pte >> 9) & 0x3FF;
2978	uint32_t local = m_srcid_d >> 4;
2979
2980	if ( local == target ) // local_address
2981	{
2982	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
2983	{
2984	updt = true;
2985	r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read();
2986	r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() \| PTE_L_MASK;
2987	}
2988	}
2989	else // remote address
2990	{
2991	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
2992	{
2993	updt = true;
2994	r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read();
2995	r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() \| PTE_R_MASK;
2996	}
2997	}
2998
2999	// update TLB
3000	if ( r_dcache_tlb_ins.read() )
3001	{
3002	r_itlb.write( pte,
3003	r_dcache_tlb_vaddr.read(),
3004	r_dcache_tlb_way.read(),
3005	r_dcache_tlb_set.read(),
3006	nline );
3007	#ifdef INSTRUMENTATION
3008	m_cpt_itlb_write++;
3009	#endif
3010	}
3011	else
3012	{
3013	r_dtlb.write( pte,
3014	r_dcache_tlb_vaddr.read(),
3015	r_dcache_tlb_way.read(),
3016	r_dcache_tlb_set.read(),
3017	nline );
3018	#ifdef INSTRUMENTATION
3019	m_cpt_dtlb_write++;
3020	#endif
3021	}
3022	// next state
3023	if ( updt ) r_dcache_fsm = DCACHE_TLB_SC_UPDT; // dcache and page table update
3024	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3025
3026	#if DEBUG_DCACHE
3027	if ( m_debug_dcache_fsm )
3028	{
3029	if ( r_dcache_tlb_ins.read() )
3030	{
3031	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB:";
3032	std::cout << " way = " << std::dec << r_dcache_tlb_way.read()
3033	<< " / set = " << r_dcache_tlb_set.read() << std::endl;
3034	r_itlb.print();
3035	}
3036	else
3037	{
3038	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB:";
3039	std::cout << " way = " << std::dec << r_dcache_tlb_way.read()
3040	<< " / set = " << r_dcache_tlb_set.read() << std::endl;
3041	r_dtlb.print();
3042	}
3043
3044	}
3045	#endif
3046	break;
3047	}
3048	/////////////////////////
3049	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3050	{
3051	uint32_t pte_flags;
3052	uint32_t pte_ppn;
3053	size_t way;
3054	size_t set;
3055	size_t word;
3056
3057	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
3058	&pte_flags,
3059	&pte_ppn,
3060	&way,
3061	&set,
3062	&word );
3063	#ifdef INSTRUMENTATION
3064	m_cpt_dcache_data_read++;
3065	m_cpt_dcache_dir_read++;
3066	#endif
3067	if ( hit ) // request hits in dcache
3068	{
3069	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3070	{
3071	if ( r_dcache_tlb_ins.read() )
3072	{
3073	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3074	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3075	r_icache_tlb_miss_req = false;
3076	r_icache_tlb_rsp_error = true;
3077	}
3078	else
3079	{
3080	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3081	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3082	drsp.valid = true;
3083	drsp.error = true;
3084	}
3085	r_dcache_fsm = DCACHE_IDLE;
3086
3087	#if DEBUG_DCACHE
3088	if ( m_debug_dcache_fsm )
3089	{
3090	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3091	<< " PTE_FLAGS = " << std::hex << pte_flags
3092	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3093	}
3094	#endif
3095	}
3096	else // mapped : update the TLB
3097	{
3098	if ( r_dcache_tlb_ins.read() ) r_dcache_in_itlb[m_icache_sets*way+set] = true;
3099	else r_dcache_in_dtlb[m_dcache_sets*way+set] = true;
3100	r_dcache_tlb_pte_flags = pte_flags;
3101	r_dcache_tlb_pte_ppn = pte_ppn;
3102	r_dcache_tlb_cache_way = way;
3103	r_dcache_tlb_cache_set = set;
3104	r_dcache_tlb_cache_word = word;
3105	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3106
3107	#if DEBUG_DCACHE
3108	if ( m_debug_dcache_fsm )
3109	{
3110	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:"
3111	<< " PTE_FLAGS = " << std::hex << pte_flags
3112	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3113	}
3114	#endif
3115	}
3116	}
3117	else // we must load the missing cache line in dcache
3118	{
3119	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3120	r_dcache_miss_type = PTE2_MISS;
3121	r_dcache_fsm = DCACHE_MISS_VICTIM;
3122	r_dcache_vci_miss_req = true;
3123
3124	#if DEBUG_DCACHE
3125	if ( m_debug_dcache_fsm )
3126	{
3127	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:"
3128	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3129	}
3130	#endif
3131	}
3132	break;
3133	}
3134	////////////////////////////
3135	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3136	{
3137	size_t way;
3138	size_t set;
3139
3140	if ( r_dcache_tlb_ins.read() )
3141	{
3142	r_itlb.select( r_dcache_tlb_vaddr.read(),
3143	false, // PTE2
3144	&way,
3145	&set );
3146	#ifdef INSTRUMENTATION
3147	m_cpt_itlb_read++;
3148	#endif
3149	}
3150	else
3151	{
3152	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3153	false, // PTE2
3154	&way,
3155	&set );
3156	#ifdef INSTRUMENTATION
3157	m_cpt_dtlb_read++;
3158	#endif
3159	}
3160	r_dcache_tlb_way = way;
3161	r_dcache_tlb_set = set;
3162	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3163	break;
3164	}
3165	//////////////////////////
3166	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3167	// if L/R bit already set exit the sub-fsm
3168	// if not, the page table must be updated by an atomic access
3169	{
3170	paddr_t nline = r_dcache_p0_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3171	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3172	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3173	bool updt = false; // page table update required
3174
3175	// test the access bit L/R, depending on the physical address locality
3176	// we must use the 10 MSB bits of the 28 bits PPN2 to obtain the target cluster index
3177	// we must use the 10 MSB bits of the SRCID to obtain the local cluster index
3178	// set the r_dcache_vci_sc_old and r_dcache_vci_sc_new registers if SC required.
3179
3180	uint32_t target = (pte_ppn >> 18) & 0x3FF;
3181	uint32_t local = m_srcid_d >> 4;
3182
3183	if ( local == target ) // local address
3184	{
3185	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3186	{
3187	updt = true;
3188	r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read();
3189	r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() \| PTE_L_MASK;
3190	}
3191	}
3192	else // remote address
3193	{
3194	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3195	{
3196	updt = true;
3197	r_dcache_vci_sc_old = r_dcache_tlb_pte_flags.read();
3198	r_dcache_vci_sc_new = r_dcache_tlb_pte_flags.read() \| PTE_R_MASK;
3199	}
3200	}
3201
3202	// update TLB for a PTE2
3203	if ( r_dcache_tlb_ins.read() )
3204	{
3205	r_itlb.write( pte_flags,
3206	pte_ppn,
3207	r_dcache_tlb_vaddr.read(),
3208	r_dcache_tlb_way.read(),
3209	r_dcache_tlb_set.read(),
3210	nline );
3211	#ifdef INSTRUMENTATION
3212	m_cpt_itlb_write++;
3213	#endif
3214	}
3215	else
3216	{
3217	r_dtlb.write( pte_flags,
3218	pte_ppn,
3219	r_dcache_tlb_vaddr.read(),
3220	r_dcache_tlb_way.read(),
3221	r_dcache_tlb_set.read(),
3222	nline );
3223	#ifdef INSTRUMENTATION
3224	m_cpt_dtlb_write++;
3225	#endif
3226	}
3227
3228	#if DEBUG_DCACHE
3229	if ( m_debug_dcache_fsm )
3230	{
3231	if ( r_dcache_tlb_ins.read() )
3232	{
3233	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB:";
3234	std::cout << " way = " << std::dec << r_dcache_tlb_way.read()
3235	<< " / set = " << r_dcache_tlb_set.read() << std::endl;
3236	r_itlb.print();
3237	}
3238	else
3239	{
3240	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB:";
3241	std::cout << " way = " << std::dec << r_dcache_tlb_way.read()
3242	<< " / set = " << r_dcache_tlb_set.read() << std::endl;
3243	r_dtlb.print();
3244	}
3245	}
3246	#endif
3247	// next state
3248	if ( updt ) r_dcache_fsm = DCACHE_TLB_SC_UPDT; // dcache and page table update
3249	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3250	break;
3251	}
3252	////////////////////////
3253	case DCACHE_TLB_SC_UPDT: // update the dcache after a tlb miss (L/R bit),
3254	// request a SC transaction to CMD FSM
3255	{
3256	r_dcache.write(r_dcache_tlb_cache_way.read(),
3257	r_dcache_tlb_cache_set.read(),
3258	r_dcache_tlb_cache_word.read(),
3259	r_dcache_tlb_pte_flags.read());
3260	#ifdef INSTRUMENTATION
3261	m_cpt_dcache_data_write++;
3262	#endif
3263	// r_dcache_vci_sc_old & r_dcache_vci_sc_new registers are already set
3264	r_dcache_vci_sc_req = true;
3265	r_dcache_fsm = DCACHE_TLB_SC_WAIT;
3266	break;
3267	}
3268	////////////////////////
3269	case DCACHE_TLB_SC_WAIT: // wait response to SC transaction from RSP FSM
3270	// we consume the response, and exit the sub-fsm.
3271	// we don't analyse the response, because
3272	// we don't care if the L/R bit update is not done
3273	{
3274	if ( not r_dcache_vci_sc_req.read() ) // response available
3275	{
3276	if ( r_vci_rsp_data_error.read() ) r_vci_rsp_data_error = false;
3277	else if ( r_vci_rsp_fifo_dcache.rok() ) vci_rsp_fifo_dcache_get = true;
3278	else
3279	{
3280	assert( false and "rsp_fifo should not be empty in DCACHE_TLB_SC_WAIT state" );
3281	}
3282	r_dcache_fsm = DCACHE_TLB_RETURN;
3283	}
3284	break;
3285	}
3286	///////////////////////
3287	case DCACHE_TLB_RETURN: // return to caller state depending on the tlb miss type
3288	{
3289	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3290	r_dcache_fsm = DCACHE_IDLE;
3291	break;
3292	}
3293	///////////////////////
3294	case DCACHE_XTN_SWITCH: // Both itlb and dtlb must be flushed
3295	{
3296	if ( not r_dcache_xtn_req.read() )
3297	{
3298	r_dtlb.flush();
3299	r_dcache_fsm = DCACHE_IDLE;
3300	drsp.valid = true;
3301	}
3302	break;
3303	}
3304	/////////////////////
3305	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3306	// The coherence request must be taken
3307	// as there is a risk of dead-lock
3308	{
3309	// external coherence request
3310	if ( r_tgt_dcache_req.read() )
3311	{
3312	r_dcache_fsm = DCACHE_CC_CHECK;
3313	r_dcache_fsm_save = DCACHE_XTN_SYNC;
3314	}
3315
3316	if ( r_wbuf.empty() )
3317	{
3318	drsp.valid = true;
3319	r_dcache_fsm = DCACHE_IDLE;
3320	}
3321	break;
3322	}
3323	////////////////////////
3324	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3325	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3326	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3327	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss...
3328	{
3329	// external coherence request
3330	if ( r_tgt_dcache_req )
3331	{
3332	r_dcache_fsm = DCACHE_CC_CHECK;
3333	r_dcache_fsm_save = r_dcache_fsm;
3334	break;
3335	}
3336
3337	// itlb miss request
3338	if ( r_icache_tlb_miss_req.read() )
3339	{
3340	r_dcache_tlb_ins = true;
3341	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3342	r_dcache_fsm = DCACHE_TLB_MISS;
3343	break;
3344	}
3345
3346	// test if XTN request to icache completed
3347	if ( not r_dcache_xtn_req.read() )
3348	{
3349	r_dcache_fsm = DCACHE_IDLE;
3350	drsp.valid = true;
3351	}
3352	break;
3353	}
3354	/////////////////////////
3355	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3356	// the r_dcache_flush counter as a slot counter.
3357	// We loop in this state until all slots have been visited.
3358	// A cleanup request is generated for each valid line
3359	// and we are blocked until the previous cleanup is completed
3360	// Finally, both the itlb and dtlb are reset, because
3361	// all TLB entries (including global entries) must be invalidated.
3362	{
3363	if ( not r_dcache_cleanup_req )
3364	{
3365	paddr_t nline;
3366	size_t way = r_dcache_flush_count.read()/m_icache_sets;
3367	size_t set = r_dcache_flush_count.read()%m_icache_sets;
3368
3369	bool cleanup_req = r_dcache.inval( way,
3370	set,
3371	&nline );
3372	if ( cleanup_req )
3373	{
3374	r_dcache_cleanup_req = true;
3375	r_dcache_cleanup_line = nline;
3376	}
3377
3378	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3379
3380	if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last slot
3381	{
3382	r_dtlb.reset(); // global entries are invalidated
3383	r_itlb.reset(); // global entries are invalidated
3384	for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++)
3385	{
3386	r_dcache_in_itlb[line] = false;
3387	r_dcache_in_dtlb[line] = false;
3388	}
3389	r_dcache_fsm = DCACHE_IDLE;
3390	drsp.valid = true;
3391	}
3392	}
3393	break;
3394	}
3395	/////////////////////////
3396	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3397	{
3398	r_dtlb.inval(r_dcache_p0_wdata.read());
3399	r_dcache_fsm = DCACHE_IDLE;
3400	drsp.valid = true;
3401	break;
3402	}
3403	////////////////////////////
3404	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3405	// requires 3 cycles: access tlb, read cache, inval cache
3406	// we compute the physical address in this state
3407	{
3408	paddr_t paddr;
3409	bool hit;
3410
3411	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3412	{
3413	#ifdef INSTRUMENTATION
3414	m_cpt_dtlb_read++;
3415	#endif
3416	hit = r_dtlb.translate( r_dcache_p0_wdata.read(),
3417	&paddr );
3418	}
3419	else // dtlb not activated
3420	{
3421	paddr = (paddr_t)r_dcache_p0_wdata.read();
3422	hit = true;
3423	}
3424
3425	if ( hit ) // tlb hit
3426	{
3427	r_dcache_p0_paddr = paddr;
3428	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3429	}
3430	else // tlb miss
3431	{
3432	#ifdef INSTRUMENTATION
3433	m_cpt_dtlb_miss++;
3434	#endif
3435	r_dcache_tlb_ins = false; // dtlb
3436	r_dcache_tlb_vaddr = r_dcache_p0_wdata.read();
3437	r_dcache_fsm = DCACHE_TLB_MISS;
3438	}
3439	break;
3440	}
3441	////////////////////////////
3442	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3443	// requires 2 cycles: read cache / inval cache
3444	// In this state we read dcache.
3445	{
3446	uint32_t data;
3447	size_t way;
3448	size_t set;
3449	size_t word;
3450	bool hit = r_dcache.read( r_dcache_p0_paddr.read(),
3451	&data,
3452	&way,
3453	&set,
3454	&word );
3455	#ifdef INSTRUMENTATION
3456	m_cpt_dcache_data_read++;
3457	m_cpt_dcache_dir_read++;
3458	#endif
3459	if ( hit ) // inval to be done
3460	{
3461	r_dcache_xtn_way = way;
3462	r_dcache_xtn_set = set;
3463	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3464	}
3465	else // miss : nothing to do
3466	{
3467	r_dcache_fsm = DCACHE_IDLE;
3468	drsp.valid = true;
3469	}
3470	break;
3471	}
3472	////////////////////////////
3473	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line & cleanup
3474	// Blocked if previous cleanup not completed
3475
3476	{
3477	if ( not r_dcache_cleanup_req.read() )
3478	{
3479	paddr_t nline;
3480	size_t way = r_dcache_xtn_way.read();
3481	size_t set = r_dcache_xtn_set.read();
3482	bool inval_tlb = false;
3483
3484	r_icache.inval( way,
3485	set,
3486	&nline );
3487
3488	// request cleanup
3489	r_dcache_cleanup_req = true;
3490	r_dcache_cleanup_line = nline;
3491
3492	// possible itlb & dtlb invalidate requests
3493	r_dcache_tlb_inval_line = nline;
3494
3495	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and
3496	r_dcache_in_dtlb[way*m_dcache_sets+set] )
3497	{
3498	r_dcache_dtlb_inval_req = true;
3499	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
3500	inval_tlb = true;
3501	}
3502	if ( (r_mmu_mode.read() & INS_TLB_MASK) and
3503	r_dcache_in_itlb[m_dcache_sets*way+set] )
3504	{
3505	r_dcache_itlb_inval_req = true;
3506	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
3507	inval_tlb = true;
3508	}
3509
3510	// no valid response until itlb & dtlb invalidated
3511	if (inval_tlb )
3512	{
3513	r_dcache_fsm = DCACHE_XTN_DC_INVAL_WAIT;
3514	}
3515	else
3516	{
3517	r_dcache_fsm = DCACHE_IDLE;
3518	drsp.valid = true;
3519	}
3520	}
3521	break;
3522	}
3523	//////////////////////////////
3524	case DCACHE_XTN_DC_INVAL_WAIT: // waiting completion of itlb and dtlb invalidate
3525	{
3526	if ( not (r_dcache_itlb_inval_req.read() or r_dcache_dtlb_inval_req.read()) )
3527	{
3528	r_dcache_fsm = DCACHE_IDLE;
3529	drsp.valid = true;
3530	}
3531	break;
3532	}
3533	////////////////////////
3534	case DCACHE_MISS_VICTIM: // Selects a victim line
3535	// Set the r_dcache_cleanup_req flip-flop
3536	// when the selected slot is not empty
3537	{
3538	bool valid;
3539	size_t way;
3540	size_t set;
3541	paddr_t victim;
3542
3543	valid = r_dcache.victim_select( r_dcache_vci_paddr.read(),
3544	&victim,
3545	&way,
3546	&set );
3547	r_dcache_miss_way = way;
3548	r_dcache_miss_set = set;
3549
3550	if ( valid )
3551	{
3552	r_dcache_cleanup_req = true;
3553	r_dcache_cleanup_line = victim;
3554	r_dcache_fsm = DCACHE_MISS_INVAL;
3555	}
3556	else
3557	{
3558	r_dcache_fsm = DCACHE_MISS_WAIT;
3559	}
3560
3561	#if DEBUG_DCACHE
3562	if ( m_debug_dcache_fsm )
3563	{
3564	std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:"
3565	<< " / way = " << way
3566	<< " / set = " << set
3567	<< " / valid = " << valid
3568	<< " / line = " << std::hex << victim << std::endl;
3569	}
3570	#endif
3571	break;
3572	}
3573	///////////////////////
3574	case DCACHE_MISS_INVAL: // invalidate the victim line
3575	// and possibly request itlb or dtlb invalidate
3576	{
3577	paddr_t nline;
3578	size_t way = r_dcache_miss_way.read();
3579	size_t set = r_dcache_miss_set.read();
3580
3581	r_dcache.inval( way,
3582	set,
3583	&nline );
3584
3585	// if itlb & dtlb invalidate are required
3586	// the miss response is not handled before invalidate completed
3587	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and
3588	( r_dcache_in_itlb[way*m_dcache_sets+set] or
3589	r_dcache_in_dtlb[m_dcache_sets*way+set] ) )
3590	{
3591	r_dcache_tlb_inval_line = r_dcache_vci_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3592	r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
3593	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
3594	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
3595	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
3596	r_dcache_fsm = DCACHE_MISS_INVAL_WAIT;
3597	}
3598	else
3599	{
3600	r_dcache_fsm = DCACHE_MISS_WAIT;
3601	}
3602	break;
3603	}
3604	////////////////////////////
3605	case DCACHE_MISS_INVAL_WAIT: // waiting completion of itlb / dtlb invalidate
3606	{
3607	if ( (not r_dcache_itlb_inval_req.read()) or (not r_dcache_dtlb_inval_req.read()) )
3608	{
3609	r_dcache_fsm = DCACHE_MISS_WAIT;
3610	}
3611	break;
3612	}
3613	//////////////////////
3614	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3615	// This state is in charge of error signaling
3616	// There is 5 types of error depending on the requester
3617	{
3618	// external coherence request
3619	if ( r_tgt_dcache_req )
3620	{
3621	r_dcache_fsm = DCACHE_CC_CHECK;
3622	r_dcache_fsm_save = r_dcache_fsm;
3623	break;
3624	}
3625
3626	if ( r_vci_rsp_data_error.read() ) // bus error
3627	{
3628	switch ( r_dcache_miss_type.read() )
3629	{
3630	case PROC_MISS:
3631	{
3632	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3633	r_mmu_dbvar = r_dcache_p0_vaddr.read();
3634	drsp.valid = true;
3635	drsp.error = true;
3636	r_dcache_fsm = DCACHE_IDLE;
3637	break;
3638	}
3639	case PTE1_MISS:
3640	{
3641	if ( r_dcache_tlb_ins.read() )
3642	{
3643	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3644	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3645	r_icache_tlb_miss_req = false;
3646	r_icache_tlb_rsp_error = true;
3647	}
3648	else
3649	{
3650	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3651	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3652	drsp.valid = true;
3653	drsp.error = true;
3654	}
3655	r_dcache_fsm = DCACHE_IDLE;
3656	break;
3657	}
3658	case PTE2_MISS:
3659	{
3660	if ( r_dcache_tlb_ins.read() )
3661	{
3662	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3663	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3664	r_icache_tlb_miss_req = false;
3665	r_icache_tlb_rsp_error = true;
3666	}
3667	else
3668	{
3669	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3670	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3671	drsp.valid = true;
3672	drsp.error = true;
3673	}
3674	r_dcache_fsm = DCACHE_IDLE;
3675	break;
3676	}
3677	} // end switch type
3678	r_vci_rsp_data_error = false;
3679	}
3680	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3681	{
3682	r_dcache_miss_word = 0;
3683	r_dcache_fsm = DCACHE_MISS_UPDT;
3684	}
3685	break;
3686	}
3687	//////////////////////
3688	case DCACHE_MISS_UPDT: // update the dcache (one word per cycle)
3689	// returns the response depending on the miss type
3690	{
3691	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3692	{
3693	if ( r_dcache_miss_inval.read() ) // Matching coherence request
3694	// pop the FIFO, without cache update
3695	// send a cleanup for the missing line
3696	// if the previous cleanup is completed
3697	{
3698	if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last
3699	{
3700	vci_rsp_fifo_dcache_get = true;
3701	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3702	}
3703	else // last word
3704	{
3705	if ( not r_dcache_cleanup_req.read() ) // no pending cleanup
3706	{
3707	vci_rsp_fifo_dcache_get = true;
3708	r_dcache_cleanup_req = true;
3709	r_dcache_cleanup_line = r_dcache_vci_paddr.read() >>
3710	(uint32_log2(m_dcache_words)+2);
3711	r_dcache_miss_inval = false;
3712	r_dcache_fsm = DCACHE_IDLE;
3713	}
3714	}
3715	}
3716	else // No matching coherence request
3717	// pop the FIFO and update the cache
3718	// update the directory at the last word
3719	// send a response to ICACHE FSM
3720	// in case of itlb miss
3721	{
3722
3723	#ifdef INSTRUMENTATION
3724	m_cpt_dcache_data_write++;
3725	#endif
3726	r_dcache.write( r_dcache_miss_way.read(),
3727	r_dcache_miss_set.read(),
3728	r_dcache_miss_word.read(),
3729	r_vci_rsp_fifo_dcache.read());
3730
3731	vci_rsp_fifo_dcache_get = true;
3732	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3733
3734	// if last word, update directory, set in_itlb & in_dtlb bits
3735	if ( r_dcache_miss_word.read() == (m_dcache_words - 1) )
3736	{
3737
3738	#ifdef INSTRUMENTATION
3739	m_cpt_dcache_dir_write++;
3740	#endif
3741	r_dcache.victim_update_tag( r_dcache_vci_paddr.read(),
3742	r_dcache_miss_way.read(),
3743	r_dcache_miss_set.read() );
3744
3745	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3746	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3747	else r_dcache_fsm = DCACHE_IDLE;
3748	}
3749	}
3750
3751	#if DEBUG_DCACHE
3752	if ( m_debug_dcache_fsm )
3753	{
3754	if ( r_dcache_miss_inval.read() )
3755	{
3756	if ( r_dcache_miss_word.read() < m_dcache_words-1 )
3757	{
3758	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3759	<< " pop the FIFO, don't update the cache" << std::endl;
3760	}
3761	else
3762	{
3763	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3764	<< " last word : send a cleanup request " << std::endl;
3765	}
3766	}
3767	else
3768	{
3769	std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:"
3770	<< " address = " << r_dcache_vci_paddr.read()
3771	<< " / data = " << r_vci_rsp_fifo_dcache.read()
3772	<< " / way = " << r_dcache_miss_way.read()
3773	<< " / set = " << r_dcache_miss_set.read()
3774	<< " / word = " << r_dcache_miss_word.read() << std::endl;
3775	}
3776	}
3777	#endif
3778
3779	} // end if rok
3780	break;
3781	}
3782	/////////////////////
3783	case DCACHE_UNC_WAIT:
3784	{
3785	// external coherence request
3786	if ( r_tgt_dcache_req.read() )
3787	{
3788	r_dcache_fsm = DCACHE_CC_CHECK;
3789	r_dcache_fsm_save = r_dcache_fsm;
3790	break;
3791	}
3792
3793	if ( r_vci_rsp_data_error.read() ) // bus error
3794	{
3795	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3796	r_mmu_dbvar = dreq.addr;
3797	r_vci_rsp_data_error = false;
3798	drsp.error = true;
3799	drsp.valid = true;
3800	r_dcache_fsm = DCACHE_IDLE;
3801	break;
3802	}
3803	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
3804	{
3805	vci_rsp_fifo_dcache_get = true;
3806	r_dcache_fsm = DCACHE_IDLE;
3807	// we acknowledge the processor request if it has not been modified
3808	if ( dreq.valid and (dreq.addr == r_dcache_p0_vaddr.read()) )
3809	{
3810	drsp.valid = true;
3811	drsp.rdata = r_vci_rsp_fifo_dcache.read();
3812	}
3813	}
3814	break;
3815	}
3816	////////////////////////////
3817	case DCACHE_WRITE_TLB_DIRTY: // set PTE dirty bit in dtlb
3818	{
3819	// set dirty bit in dtlb
3820	r_dtlb.set_dirty( r_dcache_p2_tlb_way.read(),
3821	r_dcache_p2_tlb_set.read() );
3822
3823	// get PTE in dcache
3824	uint32_t pte_flags = 0;
3825	size_t way;
3826	size_t set;
3827	size_t word;
3828	bool hit = r_dcache.read( r_dcache_p2_pte_paddr.read(),
3829	&pte_flags,
3830	&way,
3831	&set,
3832	&word );
3833	#ifdef INSTRUMENTATION
3834	m_cpt_dcache_data_read++;
3835	m_cpt_dcache_dir_read++;
3836	#endif;
3837
3838	#if DEBUG_DCACHE
3839	if ( m_debug_dcache_fsm )
3840	{
3841	std::cout << " <PROC.DCACHE_WRITE_TLB_DIRTY> Set PTE dirty bit in dtlb:"
3842	<< " paddr = " << r_dcache_p2_pte_paddr.read()
3843	<< " / tlb_way = " << r_dcache_p2_tlb_way.read()
3844	<< " / tlb_set = " << r_dcache_p2_tlb_set.read() << std::endl;
3845	}
3846	#endif
3847	assert( hit and "error in DCACHE_WRITE_TLB_DIRTY: the PTE should be in dcache" );
3848
3849	r_dcache_p2_pte_way = way; // register pte way in dcache
3850	r_dcache_p2_pte_set = set; // register pte set in dcache;
3851	r_dcache_p2_pte_word = word; // register pte word in dcache;
3852	r_dcache_p2_pte_flags = pte_flags; // register pte value
3853	r_dcache_fsm = DCACHE_WRITE_CACHE_DIRTY;
3854	break;
3855	}
3856	//////////////////////////////
3857	case DCACHE_WRITE_CACHE_DIRTY: // set PTE dirty bit in dcache
3858	// request SC tranansaction to CMD FSM
3859	{
3860	// set PTE dirty bit in dcache
3861	r_dcache.write( r_dcache_p2_pte_way.read(),
3862	r_dcache_p2_pte_set.read(),
3863	r_dcache_p2_pte_word.read(),
3864	r_dcache_p2_pte_flags.read() \| PTE_D_MASK,
3865	0xF );
3866
3867	#ifdef INSTRUMENTATION
3868	m_cpt_dcache_data_write++;
3869	#endif
3870
3871	#if DEBUG_DCACHE
3872	if ( m_debug_dcache_fsm )
3873	{
3874	std::cout << " <PROC.DCACHE_WRITE_CACHE_DIRTY> Set PTE dirty bit in dcache:"
3875	<< " / way = " << r_dcache_p2_pte_way.read()
3876	<< " / set = " << r_dcache_p2_pte_set.read()
3877	<< " / word = " << r_dcache_p2_pte_word.read() << std::endl;
3878	}
3879	#endif
3880	// request sc transaction to CMD_FSM
3881	r_dcache_vci_sc_req = true;
3882	r_dcache_vci_sc_old = r_dcache_p2_pte_flags.read();
3883	r_dcache_vci_sc_new = r_dcache_p2_pte_flags.read() \| PTE_D_MASK;
3884	r_dcache_fsm = DCACHE_WRITE_SC_WAIT;
3885	break;
3886	}
3887	//////////////////////////
3888	case DCACHE_WRITE_SC_WAIT: // wait completion of SC
3889	// if atomic, write completed : return to IDLE state
3890	// else, makes an uncacheable read to retry the SC
3891	{
3892	// external coherence request
3893	if ( r_tgt_dcache_req )
3894	{
3895	r_dcache_fsm = DCACHE_CC_CHECK;
3896	r_dcache_fsm_save = r_dcache_fsm;
3897	break;
3898	}
3899
3900	if ( r_vci_rsp_data_error.read() ) // bus error
3901	{
3902	r_mmu_detr = MMU_WRITE_PT2_ILLEGAL_ACCESS;
3903	r_mmu_dbvar = r_dcache_p2_vaddr;
3904	drsp.valid = true;
3905	drsp.error = true;
3906	r_dcache_fsm = DCACHE_IDLE;
3907	break;
3908	}
3909	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3910	{
3911	if ( r_vci_rsp_fifo_dcache.read() == 0 ) // atomic
3912	{
3913	drsp.valid = true; // acknowledge the initial write
3914	r_dcache_fsm = DCACHE_IDLE;
3915	}
3916	else
3917	{
3918	r_dcache_vci_paddr = r_dcache_p2_pte_paddr;
3919	r_dcache_vci_unc_req = true;
3920	r_dcache_vci_unc_be = 0xF;
3921	r_dcache_fsm = DCACHE_WRITE_UNC_WAIT;
3922	}
3923	}
3924	break;
3925	}
3926	///////////////////////////
3927	case DCACHE_WRITE_UNC_WAIT: // wait completion of uncacheable read
3928	// in case of success we retry a SC request to
3929	// set the dirty bit in the PTE
3930	{
3931	// external coherence request
3932	if ( r_tgt_dcache_req )
3933	{
3934	r_dcache_fsm = DCACHE_CC_CHECK;
3935	r_dcache_fsm_save = r_dcache_fsm;
3936	break;
3937	}
3938
3939	if ( r_vci_rsp_data_error.read() ) // bus error
3940	{
3941	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3942	r_mmu_dbvar = r_dcache_p2_vaddr;
3943	drsp.valid = true;
3944	drsp.error = true;
3945	r_dcache_fsm = DCACHE_IDLE;
3946	break;
3947	}
3948	if ( r_vci_rsp_fifo_dcache.rok() ) // PTE available
3949	{
3950	r_dcache_vci_sc_req = true;
3951	r_dcache_vci_sc_old = r_vci_rsp_fifo_dcache.read();
3952	r_dcache_vci_sc_new = r_vci_rsp_fifo_dcache.read() \| PTE_D_MASK;
3953	r_dcache_fsm = DCACHE_WRITE_SC_WAIT;
3954	}
3955	break;
3956	}
3957	/////////////////////
3958	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
3959	// handling coherence requests.
3960	// If there is a matching pending miss on the modified cache
3961	// line this is signaled in the r_dcache_miss inval flip-flop.
3962	// If the updated (or invalidated) cache line has copies in TLBs
3963	// these TLB copies are invalidated.
3964	// The return state is defined in r_dcache_fsm_save
3965	{
3966	paddr_t paddr = r_tgt_paddr.read();
3967	paddr_t mask = ~((m_dcache_words<<2)-1);
3968
3969
3970	if( (r_dcache_fsm_save == DCACHE_MISS_WAIT) and
3971	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss
3972	{
3973	r_dcache_miss_inval = true; // signaling the match
3974	r_tgt_dcache_req = false; // coherence request completed
3975	r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update
3976	r_dcache_fsm = r_dcache_fsm_save;
3977
3978	#if DEBUG_DCACHE
3979	if ( m_debug_dcache_fsm )
3980	{
3981	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:"
3982	<< " address = " << std::hex << paddr << std::endl;
3983	}
3984	#endif
3985
3986	}
3987	else // no match
3988	{
3989	uint32_t rdata;
3990	size_t way;
3991	size_t set;
3992	size_t word;
3993
3994	bool hit = r_dcache.read(paddr,
3995	&rdata, // unused
3996	&way,
3997	&set,
3998	&word); // unused
3999	#ifdef INSTRUMENTATION
4000	m_cpt_dcache_data_read++;
4001	m_cpt_dcache_dir_read++;
4002	#endif
4003	r_dcache_cc_way = way;
4004	r_dcache_cc_set = set;
4005
4006	if ( hit and r_tgt_update.read() ) // hit update
4007	{
4008	r_dcache_fsm = DCACHE_CC_UPDT;
4009	r_dcache_cc_word = r_tgt_word_min.read();
4010	}
4011	else if ( hit and not r_tgt_update.read() ) // hit inval
4012	{
4013	r_dcache_fsm = DCACHE_CC_INVAL;
4014	}
4015	else // miss can happen
4016	{
4017	r_tgt_dcache_req = false;
4018	r_tgt_dcache_rsp = r_tgt_update.read();
4019	r_dcache_fsm = r_dcache_fsm_save.read();
4020	}
4021
4022	#if DEBUG_DCACHE
4023	if ( m_debug_dcache_fsm )
4024	{
4025
4026	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request received :"
4027	<< " address = " << std::hex << paddr << std::dec;
4028	if ( hit )
4029	{
4030	std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl;
4031	}
4032	else
4033	{
4034	std::cout << " / MISS" << std::endl;
4035	}
4036	}
4037	#endif
4038
4039	}
4040	break;
4041	}
4042	/////////////////////
4043	case DCACHE_CC_INVAL: // invalidate one cache line
4044	// and test possible copies in TLBs
4045	{
4046	paddr_t nline;
4047	size_t way = r_dcache_cc_way.read();
4048	size_t set = r_dcache_cc_set.read();
4049	bool inval_tlb = false;
4050
4051	r_dcache.inval( way,
4052	set,
4053	&nline );
4054
4055	// possible itlb & dtlb invalidate requests
4056	r_dcache_tlb_inval_line = nline;
4057
4058	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and
4059	r_dcache_in_dtlb[way*m_dcache_sets+set] )
4060	{
4061	r_dcache_dtlb_inval_req = true;
4062	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4063	inval_tlb = true;
4064	}
4065	if ( (r_mmu_mode.read() & INS_TLB_MASK) and
4066	r_dcache_in_itlb[m_dcache_sets*way+set] )
4067	{
4068	r_dcache_itlb_inval_req = true;
4069	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4070	inval_tlb = true;
4071	}
4072
4073	// no valid response until itlb & dtlb invalidated
4074	if (inval_tlb )
4075	{
4076	r_dcache_fsm = DCACHE_CC_WAIT;
4077	}
4078	else
4079	{
4080	r_tgt_dcache_rsp = true;
4081	r_tgt_dcache_req = false;
4082	r_dcache_fsm = r_dcache_fsm_save.read();
4083	}
4084
4085	#if DEBUG_DCACHE
4086	if ( m_debug_dcache_fsm )
4087	{
4088	std::cout << " <PROC.DCACHE_CC_INVAL> Invalidate cache line :" << std::dec
4089	<< " way = " << way
4090	<< " / set = " << set << std::endl;
4091	}
4092	#endif
4093
4094	break;
4095	}
4096	///////////////////
4097	case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
4098	// and test possible copies in TLBs
4099	{
4100	size_t word = r_dcache_cc_word.read();
4101	size_t way = r_dcache_cc_way.read();
4102	size_t set = r_dcache_cc_set.read();
4103
4104	r_dcache.write( way,
4105	set,
4106	word,
4107	r_tgt_buf[word],
4108	r_tgt_be[word] );
4109	#ifdef INSTRUMENTATION
4110	m_cpt_dcache_data_write++;
4111	#endif
4112	r_dcache_cc_word = word + 1;
4113
4114	if ( word == r_tgt_word_max.read() ) // last word
4115	{
4116	// invalidate copies in TLBs
4117	if ( (r_mmu_mode.read() & DATA_TLB_MASK) and
4118	( r_dcache_in_itlb[way*m_dcache_sets+set] or
4119	r_dcache_in_dtlb[m_dcache_sets*way+set] ) )
4120	{
4121	r_dcache_tlb_inval_line = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
4122	r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
4123	r_dcache_in_itlb[way*m_dcache_sets+set] = false;
4124	r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set];
4125	r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
4126	r_dcache_fsm = DCACHE_CC_WAIT;
4127	}
4128	else
4129	{
4130	r_tgt_dcache_rsp = true;
4131	r_tgt_dcache_req = false;
4132	r_dcache_fsm = r_dcache_fsm_save.read();
4133	}
4134	}
4135
4136	#if DEBUG_DCACHE
4137	if ( m_debug_dcache_fsm )
4138	{
4139	std::cout << " <PROC.DCACHE_CC_UPDT> Update one word :" << std::dec
4140	<< " way = " << way
4141	<< " / set = " << set
4142	<< " / word = " << word
4143	<< " / value = " << std::hex << r_tgt_buf[word] << std::endl;
4144	}
4145	#endif
4146
4147	break;
4148	}
4149	////////////////////
4150	case DCACHE_CC_WAIT: // wait completion of TLB invalidate
4151	{
4152	if ( not r_dcache_itlb_inval_req.read() and not r_dcache_dtlb_inval_req.read() )
4153	{
4154	r_tgt_dcache_rsp = true;
4155	r_tgt_dcache_req = false;
4156	r_dcache_fsm = r_dcache_fsm_save.read();
4157	}
4158	}
4159	} // end switch r_dcache_fsm
4160
4161
4162	//////////////////// save DREQ and DRSP fields for print_trace() ////////////////
4163	m_dreq_valid = dreq.valid;
4164	m_dreq_addr = dreq.addr;
4165	m_dreq_mode = dreq.mode;
4166	m_dreq_type = dreq.type;
4167	m_dreq_wdata = dreq.wdata;
4168	m_dreq_be = dreq.be;
4169
4170	m_drsp_valid = drsp.valid;
4171	m_drsp_rdata = drsp.rdata;
4172	m_drsp_error = drsp.error;
4173
4174	///////////////// wbuf update //////////////////////////////////////////////////////
4175	r_wbuf.update();
4176
4177	////////////////////////////////////////////////////////////////////////////////////
4178	// INVAL DTLB FSM
4179	// This FSM works in parallel with the DCACHE FSM.
4180	// When the r_dcache_dtlb_inval_req flip-flop is activated by the DCACHE FSM
4181	// it scans sequencially all entries in the DTLB, and invalidates the
4182	// entries matching the evicted line.
4183	// It signals the completion of invalidation by reseting r_dcache_itlb_inval_req.
4184	////////////////////////////////////////////////////////////////////////////////////
4185
4186	switch(r_inval_dtlb_fsm)
4187	{
4188	/////////////////////
4189	case INVAL_DTLB_IDLE:
4190	{
4191	if ( r_dcache_dtlb_inval_req.read() )
4192	{
4193	r_dtlb.reset_bypass(r_dcache_tlb_inval_line.read());
4194	r_inval_dtlb_count = 0;
4195	r_inval_dtlb_fsm = INVAL_DTLB_SCAN;
4196
4197	#if DEBUG_INVAL_DTLB
4198	if ( m_debug_inval_dtlb_fsm )
4199	{
4200	std::cout << " <PROC.INVAL_DTLB_IDLE> Invalidate request for line "
4201	<< std::hex << r_dcache_tlb_inval_line.read() << std::endl;
4202	r_dtlb.print();
4203	}
4204	#endif
4205	}
4206	break;
4207	}
4208	/////////////////////
4209	case INVAL_DTLB_SCAN:
4210	{
4211	paddr_t line = r_dcache_tlb_inval_line.read(); // nline
4212	size_t way = r_inval_dtlb_count.read()/m_itlb_sets; // way
4213	size_t set = r_inval_dtlb_count.read()%m_itlb_sets; // set
4214
4215	bool ok = r_dtlb.inval( line,
4216	way,
4217	set );
4218
4219	#if DEBUG_INVAL_DTLB
4220	if ( m_debug_inval_dtlb_fsm )
4221	{
4222	std::cout << " <PROC.INVAL_DTLB_SCAN>" << std::hex
4223	<< " line = " << line << std::dec
4224	<< " / set = " << set
4225	<< " / way = " << way;
4226	if ( ok ) std::cout << " / HIT" << std::endl;
4227	else std::cout << " / MISS" << std::endl;
4228	}
4229	#endif
4230
4231	r_inval_dtlb_count = r_inval_dtlb_count.read() + 1;
4232	if ( r_inval_dtlb_count.read() == (m_dtlb_sets*m_dtlb_ways - 1) )
4233	{
4234	r_inval_dtlb_fsm = INVAL_DTLB_IDLE;
4235	r_dcache_dtlb_inval_req = false;
4236	}
4237	break;
4238	}
4239	} // end switch r_inval_dtlb_fsm
4240
4241	/////////// test processor frozen /////////////////////////////////////////////
4242	// The simulation exit if the number of consecutive frozen cycles
4243	// is larger than the m_max_frozen_cycles (constructor parameter)
4244	if ( (ireq.valid and not irsp.valid) or (dreq.valid and not drsp.valid) )
4245	{
4246	m_cpt_frz_cycles++; // used for instrumentation
4247	m_cpt_stop_simulation++; // used for debug
4248	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4249	{
4250	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4251	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4252	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4253	<< std::endl;
4254	exit(1);
4255	}
4256	}
4257	else
4258	{
4259	m_cpt_stop_simulation = 0;
4260	}
4261
4262	/////////// execute one iss cycle /////////////////////////////////
4263	{
4264	uint32_t it = 0;
4265	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4266	r_iss.executeNCycles(1, irsp, drsp, it);
4267	}
4268
4269	////////////////////////////////////////////////////////////////////////////
4270	// The VCI_CMD FSM controls the following ressources:
4271	// - r_vci_cmd_fsm
4272	// - r_vci_cmd_min
4273	// - r_vci_cmd_max
4274	// - r_vci_cmd_cpt
4275	// - r_vci_cmd_imiss_prio
4276	// - wbuf (reset)
4277	// - r_icache_miss_req (reset)
4278	// - r_icache_unc_req (reset)
4279	// - r_dcache_vci_miss_req (reset)
4280	// - r_dcache_vci_unc_req (reset)
4281	// - r_dcache_vci_sc_req (reset)
4282	//
4283	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4284	// There is 6 request types, with the following priorities :
4285	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4286	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4287	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4288	// 4 - Instruction Uncachable : r_icache_unc_req
4289	// 5 - Data Write : r_wbuf.rok()
4290	// 6 - Data Store Conditionnal: r_dcache_vci_sc_req
4291	//
4292	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4293	// and the VCI_RSP_FSM are fully desynchronized.
4294	//
4295	// VCI formats:
4296	// According to the VCI advanced specification, all read requests packets
4297	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4298	// are one word packets.
4299	// For write burst packets, all words are in the same cache line,
4300	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4301	// The sc command packet implements actually a compare-and-swap mechanism
4302	// and the packet contains two flits.
4303	////////////////////////////////////////////////////////////////////////////////////
4304
4305	switch ( r_vci_cmd_fsm.read() )
4306	{
4307	//////////////
4308	case CMD_IDLE:
4309	{
4310	// r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access
4311	// to check a possible pending write on the same cache line.
4312	// As there is only one possible access per cycle to write buffer, we implement
4313	// a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop.
4314
4315	size_t wbuf_min;
4316	size_t wbuf_max;
4317
4318	bool dcache_miss_req = r_dcache_vci_miss_req.read()
4319	and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4320	bool icache_miss_req = r_icache_miss_req.read()
4321	and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );
4322
4323	// 1 - Data Read Miss
4324	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4325	{
4326	r_vci_cmd_fsm = CMD_DATA_MISS;
4327	r_dcache_vci_miss_req = false;
4328	r_vci_cmd_imiss_prio = true;
4329	// m_cpt_dmiss_transaction++;
4330	}
4331	// 2 - Data Read Uncachable
4332	else if ( r_dcache_vci_unc_req.read() )
4333	{
4334	r_vci_cmd_fsm = CMD_DATA_UNC;
4335	r_dcache_vci_unc_req = false;
4336	// m_cpt_dunc_transaction++;
4337	}
4338	// 3 - Instruction Miss
4339	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4340	{
4341	r_vci_cmd_fsm = CMD_INS_MISS;
4342	r_icache_miss_req = false;
4343	r_vci_cmd_imiss_prio = false;
4344	// m_cpt_imiss_transaction++;
4345	}
4346	// 4 - Instruction Uncachable
4347	else if ( r_icache_unc_req.read() )
4348	{
4349	r_vci_cmd_fsm = CMD_INS_UNC;
4350	r_icache_unc_req = false;
4351	// m_cpt_iunc_transaction++;
4352	}
4353	// 5 - Data Write
4354	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4355	{
4356	r_vci_cmd_fsm = CMD_DATA_WRITE;
4357	r_vci_cmd_cpt = wbuf_min;
4358	r_vci_cmd_min = wbuf_min;
4359	r_vci_cmd_max = wbuf_max;
4360	// m_cpt_write_transaction++;
4361	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4362	}
4363	// 6 - Data Store Conditionnal
4364	else if ( r_dcache_vci_sc_req.read() )
4365	{
4366	r_vci_cmd_fsm = CMD_DATA_SC;
4367	r_dcache_vci_sc_req = false;
4368	r_vci_cmd_cpt = 0;
4369	// m_cpt_sc_transaction++;
4370	}
4371	break;
4372	}
4373	////////////////////
4374	case CMD_DATA_WRITE:
4375	{
4376	if ( p_vci_ini_d.cmdack.read() )
4377	{
4378	// m_conso_wbuf_read++;
4379	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4380	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4381	{
4382	r_vci_cmd_fsm = CMD_IDLE ;
4383	r_wbuf.sent() ;
4384	}
4385	}
4386	break;
4387	}
4388	/////////////////
4389	case CMD_DATA_SC:
4390	{
4391	// The SC VCI command contains two flits
4392	if ( p_vci_ini_d.cmdack.read() )
4393	{
4394	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4395	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4396	}
4397	break;
4398	}
4399	//////////////////
4400	case CMD_INS_MISS:
4401	case CMD_INS_UNC:
4402	case CMD_DATA_MISS:
4403	case CMD_DATA_UNC:
4404	{
4405	// all read VCI commands contain one single flit
4406	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4407	break;
4408	}
4409
4410	} // end switch r_vci_cmd_fsm
4411
4412	//////////////////////////////////////////////////////////////////////////
4413	// The VCI_RSP FSM controls the following ressources:
4414	// - r_vci_rsp_fsm:
4415	// - r_vci_rsp_fifo_icache (push)
4416	// - r_vci_rsp_fifo_dcache (push)
4417	// - r_vci_rsp_data_error (set)
4418	// - r_vci_rsp_ins_error (set)
4419	// - r_vci_rsp_cpt
4420	//
4421	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4422	// simultaneous VCI transactions, this FSM uses the VCI TRDID field
4423	// to identify the transactions.
4424	//
4425	// VCI vormat:
4426	// This component checks the response packet length and accepts only
4427	// single word packets for write response packets.
4428	//
4429	// Error handling:
4430	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
4431	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
4432	// flip_flop and the error is signaled by the DCACHE FSM.
4433	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
4434	// flip_flop and the error is signaled by the ICACHE FSM.
4435	// In case of Cleanup Error, the simulation stops with an error message...
4436	//////////////////////////////////////////////////////////////////////////
4437
4438	switch ( r_vci_rsp_fsm.read() )
4439	{
4440	//////////////
4441	case RSP_IDLE:
4442	{
4443	if ( p_vci_ini_d.rspval.read() )
4444	{
4445	r_vci_rsp_cpt = 0;
4446
4447	if ( (p_vci_ini_d.rtrdid.read() >> (vci_param::T-1)) != 0 ) // Write transaction
4448	{
4449	r_vci_rsp_fsm = RSP_DATA_WRITE;
4450	}
4451	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS )
4452	{
4453	r_vci_rsp_fsm = RSP_INS_MISS;
4454	}
4455	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC )
4456	{
4457	r_vci_rsp_fsm = RSP_INS_UNC;
4458	}
4459	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS )
4460	{
4461	r_vci_rsp_fsm = RSP_DATA_MISS;
4462	}
4463	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC )
4464	{
4465	r_vci_rsp_fsm = RSP_DATA_UNC;
4466	}
4467	else
4468	{
4469	assert(false and "Unexpected VCI response");
4470	}
4471	}
4472	break;
4473	}
4474	//////////////////
4475	case RSP_INS_MISS:
4476	{
4477	if ( p_vci_ini_d.rspval.read() )
4478	{
4479	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4480	{
4481	r_vci_rsp_ins_error = true;
4482	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4483	}
4484	else // no error reported
4485	{
4486	if ( r_vci_rsp_fifo_icache.wok() )
4487	{
4488	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
4489	"The VCI response packet for instruction miss is too long" );
4490
4491	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4492	vci_rsp_fifo_icache_put = true,
4493	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4494	if ( p_vci_ini_d.reop.read() )
4495	{
4496	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
4497	"The VCI response packet for instruction miss is too short");
4498
4499	r_vci_rsp_fsm = RSP_IDLE;
4500	}
4501	}
4502	}
4503	}
4504	break;
4505	}
4506	/////////////////
4507	case RSP_INS_UNC:
4508	{
4509	if (p_vci_ini_d.rspval.read() )
4510	{
4511	assert( p_vci_ini_d.reop.read() and
4512	"illegal VCI response packet for uncachable instruction");
4513
4514	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4515	{
4516	r_vci_rsp_ins_error = true;
4517	r_vci_rsp_fsm = RSP_IDLE;
4518	}
4519	else // no error reported
4520	{
4521	if ( r_vci_rsp_fifo_icache.wok())
4522	{
4523	vci_rsp_fifo_icache_put = true;
4524	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4525	r_vci_rsp_fsm = RSP_IDLE;
4526	}
4527	}
4528	}
4529	break;
4530	}
4531	///////////////////
4532	case RSP_DATA_MISS:
4533	{
4534	if ( p_vci_ini_d.rspval.read() )
4535	{
4536	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4537	{
4538	r_vci_rsp_data_error = true;
4539	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4540	}
4541	else // no error reported
4542	{
4543	if ( r_vci_rsp_fifo_dcache.wok() )
4544	{
4545	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
4546	"The VCI response packet for data miss is too long");
4547
4548	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4549	vci_rsp_fifo_dcache_put = true,
4550	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4551	if ( p_vci_ini_d.reop.read() )
4552	{
4553	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
4554	"The VCI response packet for data miss is too short");
4555
4556	r_vci_rsp_fsm = RSP_IDLE;
4557	}
4558	}
4559	}
4560	}
4561	break;
4562	}
4563	//////////////////
4564	case RSP_DATA_UNC:
4565	{
4566	if (p_vci_ini_d.rspval.read() )
4567	{
4568	assert( p_vci_ini_d.reop.read() and
4569	"illegal VCI response packet for uncachable read data");
4570
4571	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4572	{
4573	r_vci_rsp_data_error = true;
4574	r_vci_rsp_fsm = RSP_IDLE;
4575	}
4576	else // no error reported
4577	{
4578	if ( r_vci_rsp_fifo_dcache.wok())
4579	{
4580	vci_rsp_fifo_dcache_put = true;
4581	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4582	r_vci_rsp_fsm = RSP_IDLE;
4583	}
4584	}
4585	}
4586	break;
4587	}
4588	////////////////////
4589	case RSP_DATA_WRITE:
4590	{
4591	if (p_vci_ini_d.rspval.read())
4592	{
4593	assert( p_vci_ini_d.reop.read() and
4594	"a VCI response packet must contain one flit for a write transaction");
4595
4596	r_vci_rsp_fsm = RSP_IDLE;
4597	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1));
4598	bool cacheable = r_wbuf.completed(wbuf_index);
4599	if ( not cacheable ) r_dcache_pending_unc_write = false;
4600	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
4601	}
4602	break;
4603	}
4604	} // end switch r_vci_rsp_fsm
4605
4606	////////////////////////////////////////////////////////////////////////////////
4607	// The CLEANUP FSM send the cleanup commands on the coherence network,
4608	// and supports simultaneous cleanup transactions, but two simultaneous
4609	// transactions mut address different cache lines.
4610	// Therefore, the line number is registered in an associative
4611	// registration buffer (Content Adressable Memory) by the CLEANUP FSM,
4612	// and the corresponding slot (identified by the VCI TRDID field) is cleared
4613	// when the cleanup transaction response is received.
4614	// It handles cleanup requests from both the DCACHE FSM & ICACHE FSM
4615	// with a round robin priority, and can support up to 4 simultaneous
4616	// cleanup transactions (4 slots in the registration buffer).
4617	// The r_dcache_cleanup_req (or r_icache_cleanup_req) flip-flops are reset
4618	// when the command has been sent.
4619	// The VCI TRDID field is used to distinguish data/instruction cleanups:
4620	// - if data cleanup : TRDID = 2*index + 0
4621	// - if instruction cleanup : TRDID = 2*index + 1
4622	////////////////////////////////////////////////////////////////////////////
4623
4624	switch ( r_cleanup_fsm.read() )
4625	{
4626	///////////////////////
4627	case CLEANUP_DATA_IDLE: // dcache has highest priority
4628	{
4629	size_t index = 0;
4630	bool ok;
4631	if ( r_dcache_cleanup_req.read() ) // dcache request
4632	{
4633	ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(),
4634	&index );
4635	if ( ok ) // successful registration
4636	{
4637	r_cleanup_fsm = CLEANUP_DATA_GO;
4638	r_cleanup_trdid = index<<1;
4639	}
4640	}
4641	else if ( r_icache_cleanup_req.read() ) // icache request
4642	{
4643	ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(),
4644	&index );
4645	if ( ok ) // successful registration
4646	{
4647	r_cleanup_fsm = CLEANUP_INS_GO;
4648	r_cleanup_trdid = (index<<1) + 1;
4649	}
4650	}
4651	break;
4652	}
4653	//////////////////////
4654	case CLEANUP_INS_IDLE: // icache has highest priority
4655	{
4656	size_t index = 0;
4657	bool ok;
4658	if ( r_icache_cleanup_req.read() ) // icache request
4659	{
4660	ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(),
4661	&index );
4662	if ( ok ) // successful registration
4663	{
4664	r_cleanup_fsm = CLEANUP_INS_GO;
4665	r_cleanup_trdid = (index<<1) + 1;
4666	}
4667	}
4668	else if ( r_dcache_cleanup_req.read() ) // dcache request
4669	{
4670	ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(),
4671	&index );
4672	if ( ok ) // successful registration
4673	{
4674	r_cleanup_fsm = CLEANUP_DATA_GO;
4675	r_cleanup_trdid = index<<1;
4676	}
4677	}
4678	break;
4679	}
4680	/////////////////////
4681	case CLEANUP_DATA_GO:
4682	{
4683	if ( p_vci_ini_c.cmdack.read() )
4684	{
4685	r_dcache_cleanup_req = false;
4686	r_cleanup_fsm = CLEANUP_INS_IDLE;
4687
4688	#if DEBUG_CLEANUP
4689	if ( m_debug_cleanup_fsm )
4690	{
4691	std::cout << " <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
4692	<< " address = " << (r_dcache_cleanup_line.read()m_dcache_words4)
4693	<< " / trdid = " << r_cleanup_trdid.read() << std::endl;
4694	}
4695	#endif
4696	}
4697	}
4698	////////////////////////
4699	case CLEANUP_INS_GO:
4700	{
4701	if ( p_vci_ini_c.cmdack.read() )
4702	{
4703	r_icache_cleanup_req = false;
4704	r_cleanup_fsm = CLEANUP_DATA_IDLE;
4705
4706	#if DEBUG_CLEANUP
4707	if ( m_debug_cleanup_fsm )
4708	{
4709	std::cout << " <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
4710	<< " address = " << (r_icache_cleanup_line.read()m_icache_words4)
4711	<< " / trdid = " << r_cleanup_trdid.read() << std::endl;
4712	}
4713	#endif
4714	}
4715	}
4716	} // end switch CLEANUP FSM
4717
4718	//////////////// Handling cleanup responses //////////////////
4719	if ( p_vci_ini_c.rspval.read() ) // valid response
4720	{
4721	r_cleanup_buffer.cancel_index( p_vci_ini_c.rtrdid.read() >> 1);
4722	}
4723
4724	///////////////// Response FIFOs update //////////////////////
4725	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
4726	vci_rsp_fifo_icache_put,
4727	vci_rsp_fifo_icache_data);
4728
4729	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
4730	vci_rsp_fifo_dcache_put,
4731	vci_rsp_fifo_dcache_data);
4732	} // end transition()
4733
4734	///////////////////////
4735	tmpl(void)::genMoore()
4736	///////////////////////
4737	{
4738	////////////////////////////////////////////////////////////////
4739	// VCI initiator command on the coherence network (cleanup)
4740	// it depends on the CLEANUP FSM state
4741
4742	paddr_t address;
4743
4744	if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
4745	address = r_dcache_cleanup_line.read()m_dcache_words4;
4746	else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
4747	address = r_icache_cleanup_line.read()m_icache_words4;
4748	else
4749	address = 0;
4750
4751	p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
4752	(r_cleanup_fsm.read() == CLEANUP_INS_GO) );
4753	p_vci_ini_c.address = address;
4754	p_vci_ini_c.wdata = 0;
4755	p_vci_ini_c.be = 0xF;
4756	p_vci_ini_c.plen = 4;
4757	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
4758	p_vci_ini_c.trdid = r_cleanup_trdid.read();
4759	p_vci_ini_c.pktid = 0;
4760	p_vci_ini_c.srcid = m_srcid_c;
4761	p_vci_ini_c.cons = false;
4762	p_vci_ini_c.wrap = false;
4763	p_vci_ini_c.contig = false;
4764	p_vci_ini_c.clen = 0;
4765	p_vci_ini_c.cfixed = false;
4766	p_vci_ini_c.eop = true;
4767
4768	/////////////////////////////////////////////////////////////////
4769	// VCI initiator response on the coherence network (cleanup)
4770	// We always consume the response, and we don't use it.
4771
4772	p_vci_ini_c.rspack = true;
4773
4774	/////////////////////////////////////////////////////////////////
4775	// VCI initiator command on the direct network
4776	// it depends on the CMD FSM state
4777
4778	p_vci_ini_d.pktid = 0;
4779	p_vci_ini_d.srcid = m_srcid_d;
4780	p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4781	p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4782	p_vci_ini_d.wrap = false;
4783	p_vci_ini_d.clen = 0;
4784	p_vci_ini_d.cfixed = false;
4785
4786	switch ( r_vci_cmd_fsm.read() ) {
4787
4788	case CMD_IDLE:
4789	p_vci_ini_d.cmdval = false;
4790	p_vci_ini_d.address = 0;
4791	p_vci_ini_d.wdata = 0;
4792	p_vci_ini_d.be = 0;
4793	p_vci_ini_d.trdid = 0;
4794	p_vci_ini_d.plen = 0;
4795	p_vci_ini_d.cmd = vci_param::CMD_NOP;
4796	p_vci_ini_d.eop = false;
4797	break;
4798
4799	case CMD_INS_MISS:
4800	p_vci_ini_d.cmdval = true;
4801	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
4802	p_vci_ini_d.wdata = 0;
4803	p_vci_ini_d.be = 0xF;
4804	p_vci_ini_d.trdid = TYPE_INS_MISS;
4805	p_vci_ini_d.plen = m_icache_words<<2;
4806	p_vci_ini_d.cmd = vci_param::CMD_READ;
4807	p_vci_ini_d.eop = true;
4808	break;
4809
4810	case CMD_INS_UNC:
4811	p_vci_ini_d.cmdval = true;
4812	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
4813	p_vci_ini_d.wdata = 0;
4814	p_vci_ini_d.be = 0xF;
4815	p_vci_ini_d.trdid = TYPE_INS_UNC;
4816	p_vci_ini_d.plen = 4;
4817	p_vci_ini_d.cmd = vci_param::CMD_READ;
4818	p_vci_ini_d.eop = true;
4819	break;
4820
4821	case CMD_DATA_MISS:
4822	p_vci_ini_d.cmdval = true;
4823	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
4824	p_vci_ini_d.wdata = 0;
4825	p_vci_ini_d.be = 0xF;
4826	p_vci_ini_d.trdid = TYPE_DATA_MISS;
4827	p_vci_ini_d.plen = m_dcache_words << 2;
4828	p_vci_ini_d.cmd = vci_param::CMD_READ;
4829	p_vci_ini_d.eop = true;
4830	break;
4831
4832	case CMD_DATA_UNC:
4833	p_vci_ini_d.cmdval = true;
4834	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4835	p_vci_ini_d.wdata = 0;
4836	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
4837	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4838	p_vci_ini_d.plen = 4;
4839	p_vci_ini_d.cmd = vci_param::CMD_READ;
4840	p_vci_ini_d.eop = true;
4841	break;
4842
4843	case CMD_DATA_WRITE:
4844	p_vci_ini_d.cmdval = true;
4845	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
4846	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
4847	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
4848	p_vci_ini_d.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1));
4849	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
4850	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
4851	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
4852	break;
4853
4854	case CMD_DATA_SC:
4855	p_vci_ini_d.cmdval = true;
4856	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4857	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_sc_old.read();
4858	else p_vci_ini_d.wdata = r_dcache_vci_sc_new.read();
4859	p_vci_ini_d.be = 0xF;
4860	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4861	p_vci_ini_d.plen = 8;
4862	p_vci_ini_d.cmd = vci_param::CMD_STORE_COND;
4863	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
4864	break;
4865	} // end switch r_vci_cmd_fsm
4866
4867	//////////////////////////////////////////////////////////
4868	// VCI initiator response on the direct network
4869	// it depends on the VCI RSP state
4870
4871	switch (r_vci_rsp_fsm.read() )
4872	{
4873	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
4874	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4875	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4876	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4877	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4878	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
4879	} // end switch r_vci_rsp_fsm
4880
4881	////////////////////////////////////////////////////////////////
4882	// VCI target command and response on the coherence network
4883	switch ( r_tgt_fsm.read() )
4884	{
4885	case TGT_IDLE:
4886	case TGT_UPDT_WORD:
4887	case TGT_UPDT_DATA:
4888	p_vci_tgt_c.cmdack = true;
4889	p_vci_tgt_c.rspval = false;
4890	break;
4891
4892	case TGT_RSP_BROADCAST:
4893	p_vci_tgt_c.cmdack = false;
4894	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()
4895	and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() );
4896	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4897	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4898	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4899	p_vci_tgt_c.rdata = 0;
4900	p_vci_tgt_c.rerror = 0;
4901	p_vci_tgt_c.reop = true;
4902	break;
4903
4904	case TGT_RSP_ICACHE:
4905	p_vci_tgt_c.cmdack = false;
4906	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
4907	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4908	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4909	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4910	p_vci_tgt_c.rdata = 0;
4911	p_vci_tgt_c.rerror = 0;
4912	p_vci_tgt_c.reop = true;
4913	break;
4914
4915	case TGT_RSP_DCACHE:
4916	p_vci_tgt_c.cmdack = false;
4917	p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
4918	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4919	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4920	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4921	p_vci_tgt_c.rdata = 0;
4922	p_vci_tgt_c.rerror = 0;
4923	p_vci_tgt_c.reop = true;
4924	break;
4925
4926	case TGT_REQ_BROADCAST:
4927	case TGT_REQ_ICACHE:
4928	case TGT_REQ_DCACHE:
4929	p_vci_tgt_c.cmdack = false;
4930	p_vci_tgt_c.rspval = false;
4931	break;
4932
4933	} // end switch TGT_FSM
4934	} // end genMoore
4935
4936	}}
4937
4938	// Local Variables:
4939	// tab-width: 4
4940	// c-basic-offset: 4
4941	// c-file-offsets:((innamespace . 0)(inline-open . 0))
4942	// indent-tabs-mode: nil
4943	// End:
4944
4945	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
4946
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