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source: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp @ 210

Last change on this file since 210 was 210, checked in by bouyer, 12 years ago

cache_monitor(): use read_neutral(), this should not change the cache state
If paddr_t is not larger than 32bits do not try to shift by 32bits,

and assert that the high bits are 0.

ICACHE_MISS_INVAL, DCACHE_MISS_INVAL: assert that inval() did something.
Add some more debug messages

File size: 185.9 KB

Line
1	/* -- c++ --C
2	* File : vci_cc_vcache_wrapper_v4.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#include <cassert>
28	#include "arithmetics.h"
29	#include "../include/vci_cc_vcache_wrapper_v4.h"
30
31	#define DEBUG_DCACHE 1
32	#define DEBUG_ICACHE 1
33	#define DEBUG_CLEANUP 0
34
35	namespace soclib {
36	namespace caba {
37
38	namespace {
39	const char *icache_fsm_state_str[] = {
40	"ICACHE_IDLE",
41
42	"ICACHE_XTN_TLB_FLUSH",
43	"ICACHE_XTN_CACHE_FLUSH",
44	"ICACHE_XTN_TLB_INVAL",
45	"ICACHE_XTN_CACHE_INVAL_VA",
46	"ICACHE_XTN_CACHE_INVAL_PA",
47	"ICACHE_XTN_CACHE_INVAL_GO",
48
49	"ICACHE_TLB_WAIT",
50
51	"ICACHE_MISS_VICTIM",
52	"ICACHE_MISS_INVAL",
53	"ICACHE_MISS_WAIT",
54	"ICACHE_MISS_UPDT",
55
56	"ICACHE_UNC_WAIT",
57
58	"ICACHE_CC_CHECK",
59	"ICACHE_CC_INVAL",
60	"ICACHE_CC_UPDT",
61
62	};
63	const char *dcache_fsm_state_str[] = {
64	"DCACHE_IDLE",
65
66	"DCACHE_TLB_MISS",
67	"DCACHE_TLB_PTE1_GET",
68	"DCACHE_TLB_PTE1_SELECT",
69	"DCACHE_TLB_PTE1_UPDT",
70	"DCACHE_TLB_PTE2_GET",
71	"DCACHE_TLB_PTE2_SELECT",
72	"DCACHE_TLB_PTE2_UPDT",
73	"DCACHE_TLB_LR_UPDT",
74	"DCACHE_TLB_LR_WAIT",
75	"DCACHE_TLB_RETURN",
76
77	"DCACHE_XTN_SWITCH",
78	"DCACHE_XTN_SYNC",
79	"DCACHE_XTN_IC_INVAL_VA",
80	"DCACHE_XTN_IC_FLUSH",
81	"DCACHE_XTN_IC_INVAL_PA",
82	"DCACHE_XTN_IT_INVAL",
83	"DCACHE_XTN_DC_FLUSH",
84	"DCACHE_XTN_DC_INVAL_VA",
85	"DCACHE_XTN_DC_INVAL_PA",
86	"DCACHE_XTN_DC_INVAL_END",
87	"DCACHE_XTN_DC_INVAL_GO",
88	"DCACHE_XTN_DT_INVAL",
89
90	"DCACHE_DIRTY_PTE_GET",
91	"DCACHE_DIRTY_SC_WAIT",
92
93	"DCACHE_MISS_VICTIM",
94	"DCACHE_MISS_INVAL",
95	"DCACHE_MISS_WAIT",
96	"DCACHE_MISS_UPDT",
97
98	"DCACHE_UNC_WAIT",
99	"DCACHE_SC_WAIT",
100
101	"DCACHE_CC_CHECK",
102	"DCACHE_CC_INVAL",
103	"DCACHE_CC_UPDT",
104
105	"DCACHE_INVAL_TLB_SCAN",
106	};
107	const char *cmd_fsm_state_str[] = {
108	"CMD_IDLE",
109	"CMD_INS_MISS",
110	"CMD_INS_UNC",
111	"CMD_DATA_MISS",
112	"CMD_DATA_UNC",
113	"CMD_DATA_WRITE",
114	"CMD_DATA_SC",
115	};
116	const char *rsp_fsm_state_str[] = {
117	"RSP_IDLE",
118	"RSP_INS_MISS",
119	"RSP_INS_UNC",
120	"RSP_DATA_MISS",
121	"RSP_DATA_UNC",
122	"RSP_DATA_WRITE",
123	};
124	const char *cleanup_fsm_state_str[] = {
125	"CLEANUP_DATA_IDLE",
126	"CLEANUP_DATA_GO",
127	"CLEANUP_INS_IDLE",
128	"CLEANUP_INS_GO",
129	};
130	const char *tgt_fsm_state_str[] = {
131	"TGT_IDLE",
132	"TGT_UPDT_WORD",
133	"TGT_UPDT_DATA",
134	"TGT_REQ_BROADCAST",
135	"TGT_REQ_ICACHE",
136	"TGT_REQ_DCACHE",
137	"TGT_RSP_BROADCAST",
138	"TGT_RSP_ICACHE",
139	"TGT_RSP_DCACHE",
140	};
141	}
142
143	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t>
144
145	using soclib::common::uint32_log2;
146
147	/////////////////////////////////
148	tmpl(/**/)::VciCcVCacheWrapperV4(
149	sc_module_name name,
150	int proc_id,
151	const soclib::common::MappingTable &mtp,
152	const soclib::common::MappingTable &mtc,
153	const soclib::common::IntTab &initiator_index_d,
154	const soclib::common::IntTab &initiator_index_c,
155	const soclib::common::IntTab &target_index_d,
156	size_t itlb_ways,
157	size_t itlb_sets,
158	size_t dtlb_ways,
159	size_t dtlb_sets,
160	size_t icache_ways,
161	size_t icache_sets,
162	size_t icache_words,
163	size_t dcache_ways,
164	size_t dcache_sets,
165	size_t dcache_words,
166	size_t wbuf_nlines,
167	size_t wbuf_nwords,
168	uint32_t max_frozen_cycles,
169	uint32_t debug_start_cycle,
170	bool debug_ok)
171	: soclib::caba::BaseModule(name),
172
173	p_clk("clk"),
174	p_resetn("resetn"),
175	p_vci_ini_d("vci_ini_d"),
176	p_vci_ini_c("vci_ini_c"),
177	p_vci_tgt_c("vci_tgt_d"),
178
179	m_cacheability_table(mtp.getCacheabilityTable()),
180	m_segment(mtc.getSegment(target_index_d)),
181	m_srcid_d(mtp.indexForId(initiator_index_d)),
182	m_srcid_c(mtp.indexForId(initiator_index_c)),
183
184	m_itlb_ways(itlb_ways),
185	m_itlb_sets(itlb_sets),
186
187	m_dtlb_ways(dtlb_ways),
188	m_dtlb_sets(dtlb_sets),
189
190	m_icache_ways(icache_ways),
191	m_icache_sets(icache_sets),
192	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
193	m_icache_words(icache_words),
194
195	m_dcache_ways(dcache_ways),
196	m_dcache_sets(dcache_sets),
197	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
198	m_dcache_words(dcache_words),
199
200	m_proc_id(proc_id),
201
202	m_max_frozen_cycles(max_frozen_cycles),
203
204	m_paddr_nbits(vci_param::N),
205
206	m_debug_start_cycle(debug_start_cycle),
207	m_debug_ok(debug_ok),
208
209	r_mmu_ptpr("r_mmu_ptpr"),
210	r_mmu_mode("r_mmu_mode"),
211	r_mmu_word_lo("r_mmu_word_lo"),
212	r_mmu_word_hi("r_mmu_word_hi"),
213	r_mmu_ibvar("r_mmu_ibvar"),
214	r_mmu_dbvar("r_mmu_dbvar"),
215	r_mmu_ietr("r_mmu_ietr"),
216	r_mmu_detr("r_mmu_detr"),
217
218	r_icache_fsm("r_icache_fsm"),
219	r_icache_fsm_save("r_icache_fsm_save"),
220	r_icache_vci_paddr("r_icache_vci_paddr"),
221	r_icache_vaddr_save("r_icache_vaddr_save"),
222
223	r_icache_miss_way("r_icache_miss_way"),
224	r_icache_miss_set("r_icache_miss_set"),
225	r_icache_miss_word("r_icache_miss_word"),
226	r_icache_miss_inval("r_icache_miss_inval"),
227
228	r_icache_cc_way("r_icache_cc_way"),
229	r_icache_cc_set("r_icache_cc_set"),
230	r_icache_cc_word("r_icache_cc_word"),
231
232	r_icache_flush_count("r_icache_flush_count"),
233
234	r_icache_miss_req("r_icache_miss_req"),
235	r_icache_unc_req("r_icache_unc_req"),
236
237	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
238	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
239
240	r_icache_cleanup_req("r_icache_cleanup_req"),
241	r_icache_cleanup_line("r_icache_cleanup_line"),
242
243	r_dcache_fsm("r_dcache_fsm"),
244	r_dcache_fsm_save("r_dcache_fsm_save"),
245
246	r_dcache_p0_valid("r_dcache_p0_valid"),
247	r_dcache_p0_vaddr("r_dcache_p0_vaddr"),
248	r_dcache_p0_wdata("r_dcache_p0_wdata"),
249	r_dcache_p0_be("r_dcache_p0_be"),
250	r_dcache_p0_paddr("r_dcache_p0_paddr"),
251	r_dcache_p0_cacheable("r_dcache_p0_cacheable"),
252
253	r_dcache_p1_valid("r_dcache_p1_valid"),
254	r_dcache_p1_wdata("r_dcache_p1_wdata"),
255	r_dcache_p1_be("r_dcache_p1_be"),
256	r_dcache_p1_paddr("r_dcache_p1_paddr"),
257	r_dcache_p1_cache_way("r_dcache_p1_cache_way"),
258	r_dcache_p1_cache_set("r_dcache_p1_cache_set"),
259	r_dcache_p1_cache_word("r_dcache_p1_word_save"),
260
261	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
262	r_dcache_dirty_way("r_dcache_dirty_way"),
263	r_dcache_dirty_set("r_dcache_dirty_set"),
264
265	r_dcache_vci_paddr("r_dcache_vci_paddr"),
266	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
267	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
268	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
269	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
270	r_dcache_vci_sc_old("r_dcache_vci_sc_old"),
271	r_dcache_vci_sc_new("r_dcache_vci_sc_new"),
272
273	r_dcache_xtn_way("r_dcache_xtn_way"),
274	r_dcache_xtn_set("r_dcache_xtn_set"),
275
276	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
277
278	r_dcache_miss_type("r_dcache_miss_type"),
279	r_dcache_miss_word("r_dcache_miss_word"),
280	r_dcache_miss_way("r_dcache_miss_way"),
281	r_dcache_miss_set("r_dcache_miss_set"),
282	r_dcache_miss_inval("r_dcache_miss_inval"),
283
284	r_dcache_cc_way("r_dcache_cc_way"),
285	r_dcache_cc_set("r_dcache_cc_set"),
286	r_dcache_cc_word("r_dcache_cc_word"),
287
288	r_dcache_flush_count("r_dcache_flush_count"),
289
290	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
291	r_dcache_tlb_ins("r_dcache_tlb_ins"),
292	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
293	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
294	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
295	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
296	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
297	r_dcache_tlb_way("r_dcache_tlb_way"),
298	r_dcache_tlb_set("r_dcache_tlb_set"),
299
300	r_dcache_ll_valid("r_dcache_ll_valid"),
301	r_dcache_ll_data("r_dcache_ll_data"),
302	r_dcache_ll_vaddr("r_dcache_ll_vaddr"),
303
304	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
305	r_dcache_tlb_inval_count("r_dcache_tlb_inval_count"),
306
307	r_dcache_xtn_req("r_dcache_xtn_req"),
308	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
309
310	r_dcache_cleanup_req("r_dcache_cleanup_req"),
311	r_dcache_cleanup_line("r_dcache_cleanup_line"),
312
313	r_vci_cmd_fsm("r_vci_cmd_fsm"),
314	r_vci_cmd_min("r_vci_cmd_min"),
315	r_vci_cmd_max("r_vci_cmd_max"),
316	r_vci_cmd_cpt("r_vci_cmd_cpt"),
317	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
318
319	r_vci_rsp_fsm("r_vci_rsp_fsm"),
320	r_vci_rsp_cpt("r_vci_rsp_cpt"),
321	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
322	r_vci_rsp_data_error("r_vci_rsp_data_error"),
323	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
324	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
325
326	r_cleanup_fsm("r_cleanup_fsm"),
327	r_cleanup_trdid("r_cleanup_trdid"),
328	r_cleanup_buffer(4), // up to 4 simultaneous cleanups
329
330	r_tgt_fsm("r_tgt_fsm"),
331	r_tgt_paddr("r_tgt_paddr"),
332	r_tgt_word_count("r_tgt_word_count"),
333	r_tgt_word_min("r_tgt_word_min"),
334	r_tgt_word_max("r_tgt_word_max"),
335	r_tgt_update("r_tgt_update"),
336	r_tgt_update_data("r_tgt_update_data"),
337	r_tgt_srcid("r_tgt_srcid"),
338	r_tgt_pktid("r_tgt_pktid"),
339	r_tgt_trdid("r_tgt_trdid"),
340
341	r_tgt_icache_req("r_tgt_icache_req"),
342	r_tgt_dcache_req("r_tgt_dcache_req"),
343	r_tgt_icache_rsp("r_tgt_icache_rsp"),
344	r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
345
346	r_iss(this->name(), proc_id),
347	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
348	r_icache("icache", icache_ways, icache_sets, icache_words),
349	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
350	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
351	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
352	{
353	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
354	"Need more PLEN bits.");
355
356	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
357	"Need more TRDID bits.");
358
359	assert( (icache_words == dcache_words) and
360	"icache_words and dcache_words parameters must be equal");
361
362	assert( (itlb_sets == dtlb_sets) and
363	"itlb_sets and dtlb_sets parameters must be etqual");
364
365	assert( (itlb_ways == dtlb_ways) and
366	"itlb_ways and dtlb_ways parameters must be etqual");
367
368	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
369	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
370	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
371	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
372	(uint32_log2(m_icache_words<<2));
373
374	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
375
376	r_tgt_buf = new uint32_t[dcache_words];
377	r_tgt_be = new vci_be_t[dcache_words];
378	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
379	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
380
381	SC_METHOD(transition);
382	dont_initialize();
383	sensitive << p_clk.pos();
384
385	SC_METHOD(genMoore);
386	dont_initialize();
387	sensitive << p_clk.neg();
388
389	typename iss_t::CacheInfo cache_info;
390	cache_info.has_mmu = true;
391	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
392	cache_info.icache_assoc = icache_ways;
393	cache_info.icache_n_lines = icache_sets;
394	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
395	cache_info.dcache_assoc = dcache_ways;
396	cache_info.dcache_n_lines = dcache_sets;
397	r_iss.setCacheInfo(cache_info);
398	}
399
400	/////////////////////////////////////
401	tmpl(/**/)::~VciCcVCacheWrapperV4()
402	/////////////////////////////////////
403	{
404	delete [] r_tgt_be;
405	delete [] r_tgt_buf;
406	delete [] r_dcache_in_tlb;
407	delete [] r_dcache_contains_ptd;
408	}
409
410	////////////////////////
411	tmpl(void)::print_cpi()
412	////////////////////////
413	{
414	std::cout << name() << " CPI = "
415	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
416	}
417
418	////////////////////////////////////
419	tmpl(void)::print_trace(size_t mode)
420	////////////////////////////////////
421	{
422	// b0 : write buffer trace
423	// b1 : write buffer verbose
424	// b2 : dcache trace
425	// b3 : icache trace
426	// b4 : dtlb trace
427	// b5 : itlb trace
428
429	std::cout << std::dec << "PROC " << name() << std::endl;
430
431	std::cout << " " << m_ireq << std::endl;
432	std::cout << " " << m_irsp << std::endl;
433	std::cout << " " << m_dreq << std::endl;
434	std::cout << " " << m_drsp << std::endl;
435
436	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
437	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
438	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
439	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
440	<< " \| " << tgt_fsm_state_str[r_tgt_fsm.read()]
441	<< " \| " << cleanup_fsm_state_str[r_cleanup_fsm.read()];
442	if (r_dcache_p0_valid.read() ) std::cout << " \| P1_WRITE";
443	if (r_dcache_p1_valid.read() ) std::cout << " \| P2_WRITE";
444	std::cout << std::endl;
445
446	if(mode & 0x01)
447	{
448	r_wbuf.printTrace((mode>>1)&1);
449	}
450	if(mode & 0x04)
451	{
452	std::cout << " Data Cache" << std::endl;
453	r_dcache.printTrace();
454	}
455	if(mode & 0x08)
456	{
457	std::cout << " Instruction Cache" << std::endl;
458	r_icache.printTrace();
459	}
460	if(mode & 0x10)
461	{
462	std::cout << " Data TLB" << std::endl;
463	r_dtlb.printTrace();
464	}
465	if(mode & 0x20)
466	{
467	std::cout << " Instruction TLB" << std::endl;
468	r_itlb.printTrace();
469	}
470	}
471
472	//////////////////////////////////////////
473	tmpl(void)::cache_monitor( paddr_t addr )
474	//////////////////////////////////////////
475	{
476	size_t cache_way;
477	size_t cache_set;
478	size_t cache_word;
479	uint32_t cache_rdata;
480	bool cache_hit = r_dcache.read_neutral( addr,
481	&cache_rdata,
482	&cache_way,
483	&cache_set,
484	&cache_word );
485	if ( cache_hit != m_debug_previous_hit )
486	{
487	std::cout << "PROC " << name()
488	<< " cache change at cycle " << std::dec << m_cpt_total_cycles
489	<< " for adresse " << std::hex << addr
490	<< " / HIT = " << cache_hit << std::endl;
491	}
492	m_debug_previous_hit = cache_hit;
493	}
494
495
496
497	/*
498	////////////////////////
499	tmpl(void)::print_stats()
500	////////////////////////
501	{
502	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
503	std::cout << name() << std::endl
504	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
505	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
506	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
507	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
508	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
509	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
510	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
511	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
512	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
513	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
514	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
515	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
516	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
517	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
518	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
519	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
520	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
521	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
522	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
523	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
524	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
525	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
526	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
527	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
528	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
529	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
530	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
531	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
532	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
533	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
534	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
535	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
536	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
537	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
538	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
539	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
540	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
541	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
542	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
543	}
544
545	////////////////////////
546	tmpl(void)::clear_stats()
547	////////////////////////
548	{
549	m_cpt_dcache_data_read = 0;
550	m_cpt_dcache_data_write = 0;
551	m_cpt_dcache_dir_read = 0;
552	m_cpt_dcache_dir_write = 0;
553	m_cpt_icache_data_read = 0;
554	m_cpt_icache_data_write = 0;
555	m_cpt_icache_dir_read = 0;
556	m_cpt_icache_dir_write = 0;
557
558	m_cpt_frz_cycles = 0;
559	m_cpt_dcache_frz_cycles = 0;
560	m_cpt_total_cycles = 0;
561
562	m_cpt_read = 0;
563	m_cpt_write = 0;
564	m_cpt_data_miss = 0;
565	m_cpt_ins_miss = 0;
566	m_cpt_unc_read = 0;
567	m_cpt_write_cached = 0;
568	m_cpt_ins_read = 0;
569
570	m_cost_write_frz = 0;
571	m_cost_data_miss_frz = 0;
572	m_cost_unc_read_frz = 0;
573	m_cost_ins_miss_frz = 0;
574
575	m_cpt_imiss_transaction = 0;
576	m_cpt_dmiss_transaction = 0;
577	m_cpt_unc_transaction = 0;
578	m_cpt_write_transaction = 0;
579	m_cpt_icache_unc_transaction = 0;
580
581	m_cost_imiss_transaction = 0;
582	m_cost_dmiss_transaction = 0;
583	m_cost_unc_transaction = 0;
584	m_cost_write_transaction = 0;
585	m_cost_icache_unc_transaction = 0;
586	m_length_write_transaction = 0;
587
588	m_cpt_ins_tlb_read = 0;
589	m_cpt_ins_tlb_miss = 0;
590	m_cpt_ins_tlb_update_acc = 0;
591
592	m_cpt_data_tlb_read = 0;
593	m_cpt_data_tlb_miss = 0;
594	m_cpt_data_tlb_update_acc = 0;
595	m_cpt_data_tlb_update_dirty = 0;
596	m_cpt_ins_tlb_hit_dcache = 0;
597	m_cpt_data_tlb_hit_dcache = 0;
598	m_cpt_ins_tlb_occup_cache = 0;
599	m_cpt_data_tlb_occup_cache = 0;
600
601	m_cost_ins_tlb_miss_frz = 0;
602	m_cost_data_tlb_miss_frz = 0;
603	m_cost_ins_tlb_update_acc_frz = 0;
604	m_cost_data_tlb_update_acc_frz = 0;
605	m_cost_data_tlb_update_dirty_frz = 0;
606	m_cost_ins_tlb_occup_cache_frz = 0;
607	m_cost_data_tlb_occup_cache_frz = 0;
608
609	m_cpt_itlbmiss_transaction = 0;
610	m_cpt_itlb_ll_transaction = 0;
611	m_cpt_itlb_sc_transaction = 0;
612	m_cpt_dtlbmiss_transaction = 0;
613	m_cpt_dtlb_ll_transaction = 0;
614	m_cpt_dtlb_sc_transaction = 0;
615	m_cpt_dtlb_ll_dirty_transaction = 0;
616	m_cpt_dtlb_sc_dirty_transaction = 0;
617
618	m_cost_itlbmiss_transaction = 0;
619	m_cost_itlb_ll_transaction = 0;
620	m_cost_itlb_sc_transaction = 0;
621	m_cost_dtlbmiss_transaction = 0;
622	m_cost_dtlb_ll_transaction = 0;
623	m_cost_dtlb_sc_transaction = 0;
624	m_cost_dtlb_ll_dirty_transaction = 0;
625	m_cost_dtlb_sc_dirty_transaction = 0;
626
627	m_cpt_cc_update_data = 0;
628	m_cpt_cc_inval_ins = 0;
629	m_cpt_cc_inval_data = 0;
630	m_cpt_cc_broadcast = 0;
631
632	m_cost_updt_data_frz = 0;
633	m_cost_inval_ins_frz = 0;
634	m_cost_inval_data_frz = 0;
635	m_cost_broadcast_frz = 0;
636
637	m_cpt_cc_cleanup_data = 0;
638	m_cpt_cc_cleanup_ins = 0;
639	}
640
641	*/
642
643	/////////////////////////
644	tmpl(void)::transition()
645	/////////////////////////
646	{
647	if ( not p_resetn.read() )
648	{
649	r_iss.reset();
650	r_wbuf.reset();
651	r_icache.reset();
652	r_dcache.reset();
653	r_itlb.reset();
654	r_dtlb.reset();
655
656	r_dcache_fsm = DCACHE_IDLE;
657	r_icache_fsm = ICACHE_IDLE;
658	r_vci_cmd_fsm = CMD_IDLE;
659	r_vci_rsp_fsm = RSP_IDLE;
660	r_tgt_fsm = TGT_IDLE;
661	r_cleanup_fsm = CLEANUP_DATA_IDLE;
662
663	// reset dcache directory extension
664	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
665	{
666	r_dcache_in_tlb[i] = false;
667	r_dcache_contains_ptd[i] = false;
668	}
669
670	// Response FIFOs and cleanup buffer
671	r_vci_rsp_fifo_icache.init();
672	r_vci_rsp_fifo_dcache.init();
673	r_cleanup_buffer.reset();
674
675	// ICACHE & DCACHE activated
676	r_mmu_mode = 0x3;
677
678	// No request from ICACHE FSM to CMD FSM
679	r_icache_miss_req = false;
680	r_icache_unc_req = false;
681
682	// No request from ICACHE_FSM to DCACHE FSM
683	r_icache_tlb_miss_req = false;
684
685	// No request from ICACHE_FSM to CLEANUP FSMs
686	r_icache_cleanup_req = false;
687
688	// No pending write in pipeline
689	r_dcache_p0_valid = false;
690	r_dcache_p1_valid = false;
691
692	// No request from DCACHE_FSM to CMD_FSM
693	r_dcache_vci_miss_req = false;
694	r_dcache_vci_unc_req = false;
695	r_dcache_vci_sc_req = false;
696
697	// No uncacheable write pending
698	r_dcache_pending_unc_write = false;
699
700	// No LL reservation
701	r_dcache_ll_valid = false;
702
703	// No processor XTN request pending
704	r_dcache_xtn_req = false;
705
706	// No request from DCACHE FSM to CLEANUP FSMs
707	r_dcache_cleanup_req = false;
708
709	// No request from TGT FSM to ICACHE/DCACHE FSMs
710	r_tgt_icache_req = false;
711	r_tgt_dcache_req = false;
712
713	// No signalisation of a coherence request matching a pending miss
714	r_icache_miss_inval = false;
715	r_dcache_miss_inval = false;
716
717	// No signalisation of errors
718	r_vci_rsp_ins_error = false;
719	r_vci_rsp_data_error = false;
720
721	// Debug variables
722	m_debug_previous_hit = false;
723	m_debug_dcache_fsm = false;
724	m_debug_icache_fsm = false;
725	m_debug_cleanup_fsm = false;
726
727	// activity counters
728	m_cpt_dcache_data_read = 0;
729	m_cpt_dcache_data_write = 0;
730	m_cpt_dcache_dir_read = 0;
731	m_cpt_dcache_dir_write = 0;
732	m_cpt_icache_data_read = 0;
733	m_cpt_icache_data_write = 0;
734	m_cpt_icache_dir_read = 0;
735	m_cpt_icache_dir_write = 0;
736
737	m_cpt_frz_cycles = 0;
738	m_cpt_total_cycles = 0;
739	m_cpt_stop_simulation = 0;
740
741	m_cpt_data_miss = 0;
742	m_cpt_ins_miss = 0;
743	m_cpt_unc_read = 0;
744	m_cpt_write_cached = 0;
745	m_cpt_ins_read = 0;
746
747	m_cost_write_frz = 0;
748	m_cost_data_miss_frz = 0;
749	m_cost_unc_read_frz = 0;
750	m_cost_ins_miss_frz = 0;
751
752	m_cpt_imiss_transaction = 0;
753	m_cpt_dmiss_transaction = 0;
754	m_cpt_unc_transaction = 0;
755	m_cpt_write_transaction = 0;
756	m_cpt_icache_unc_transaction = 0;
757
758	m_cost_imiss_transaction = 0;
759	m_cost_dmiss_transaction = 0;
760	m_cost_unc_transaction = 0;
761	m_cost_write_transaction = 0;
762	m_cost_icache_unc_transaction = 0;
763	m_length_write_transaction = 0;
764
765	m_cpt_ins_tlb_read = 0;
766	m_cpt_ins_tlb_miss = 0;
767	m_cpt_ins_tlb_update_acc = 0;
768
769	m_cpt_data_tlb_read = 0;
770	m_cpt_data_tlb_miss = 0;
771	m_cpt_data_tlb_update_acc = 0;
772	m_cpt_data_tlb_update_dirty = 0;
773	m_cpt_ins_tlb_hit_dcache = 0;
774	m_cpt_data_tlb_hit_dcache = 0;
775	m_cpt_ins_tlb_occup_cache = 0;
776	m_cpt_data_tlb_occup_cache = 0;
777
778	m_cost_ins_tlb_miss_frz = 0;
779	m_cost_data_tlb_miss_frz = 0;
780	m_cost_ins_tlb_update_acc_frz = 0;
781	m_cost_data_tlb_update_acc_frz = 0;
782	m_cost_data_tlb_update_dirty_frz = 0;
783	m_cost_ins_tlb_occup_cache_frz = 0;
784	m_cost_data_tlb_occup_cache_frz = 0;
785
786	m_cpt_ins_tlb_inval = 0;
787	m_cpt_data_tlb_inval = 0;
788	m_cost_ins_tlb_inval_frz = 0;
789	m_cost_data_tlb_inval_frz = 0;
790
791	m_cpt_cc_broadcast = 0;
792
793	m_cost_updt_data_frz = 0;
794	m_cost_inval_ins_frz = 0;
795	m_cost_inval_data_frz = 0;
796	m_cost_broadcast_frz = 0;
797
798	m_cpt_cc_cleanup_data = 0;
799	m_cpt_cc_cleanup_ins = 0;
800
801	m_cpt_itlbmiss_transaction = 0;
802	m_cpt_itlb_ll_transaction = 0;
803	m_cpt_itlb_sc_transaction = 0;
804	m_cpt_dtlbmiss_transaction = 0;
805	m_cpt_dtlb_ll_transaction = 0;
806	m_cpt_dtlb_sc_transaction = 0;
807	m_cpt_dtlb_ll_dirty_transaction = 0;
808	m_cpt_dtlb_sc_dirty_transaction = 0;
809
810	m_cost_itlbmiss_transaction = 0;
811	m_cost_itlb_ll_transaction = 0;
812	m_cost_itlb_sc_transaction = 0;
813	m_cost_dtlbmiss_transaction = 0;
814	m_cost_dtlb_ll_transaction = 0;
815	m_cost_dtlb_sc_transaction = 0;
816	m_cost_dtlb_ll_dirty_transaction = 0;
817	m_cost_dtlb_sc_dirty_transaction = 0;
818	/*
819	m_cpt_dcache_frz_cycles = 0;
820	m_cpt_read = 0;
821	m_cpt_write = 0;
822	m_cpt_cc_update_data = 0;
823	m_cpt_cc_inval_ins = 0;
824	m_cpt_cc_inval_data = 0;
825	*/
826
827	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
828	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
829	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
830	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
831	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0;
832	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0;
833	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0;
834
835	return;
836	}
837
838	// Response FIFOs default values
839	bool vci_rsp_fifo_icache_get = false;
840	bool vci_rsp_fifo_icache_put = false;
841	uint32_t vci_rsp_fifo_icache_data = 0;
842
843	bool vci_rsp_fifo_dcache_get = false;
844	bool vci_rsp_fifo_dcache_put = false;
845	uint32_t vci_rsp_fifo_dcache_data = 0;
846
847	#ifdef INSTRUMENTATION
848	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
849	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
850	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
851	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
852	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
853	m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++;
854	#endif
855
856	m_cpt_total_cycles++;
857
858	m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
859	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
860	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
861
862	/////////////////////////////////////////////////////////////////////
863	// The TGT_FSM controls the following ressources:
864	// - r_tgt_fsm
865	// - r_tgt_buf[nwords]
866	// - r_tgt_be[nwords]
867	// - r_tgt_update
868	// - r_tgt_word_min
869	// - r_tgt_word_max
870	// - r_tgt_word_count
871	// - r_tgt_paddr
872	// - r_tgt_srcid
873	// - r_tgt_trdid
874	// - r_tgt_pktid
875	// - r_tgt_icache_req (set)
876	// - r_tgt_dcache_req (set)
877	//
878	// All VCI commands must be CMD_WRITE.
879	// - If the 2 LSB bits of the VCI address are 11, it is a broadcast request.
880	// It is a multicast request otherwise.
881	// - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS
882	// (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes
883	// INVAL/UPDATE (0 for invalidate / 1 for UPDATE).
884	//
885	// For all types of coherence request, the line index (i.e. the Z & Y fields)
886	// is coded on 34 bits, and is contained in the WDATA and BE fields
887	// of the first VCI flit.
888	// - for a multicast invalidate or for a broadcast invalidate request
889	// the VCI packet length is 1 word.
890	// - for an update request the VCI packet length is (n+2) words.
891	// The WDATA field of the second VCI word contains the word index.
892	// The WDATA field of the n following words contains the values.
893	// - for all transaction types, the VCI response is one single word.
894	// In case of errors in the VCI command packet, the simulation
895	// is stopped with an error message.
896	//
897	// This FSM is NOT pipelined : It consumes a new coherence request
898	// on the VCI port only when the previous request is completed.
899	//
900	// The VCI_TGT FSM stores the external request arguments in the
901	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
902	// and/or the r_tgt_dcache_req flip-flops to signal the coherence request
903	// to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST
904	// states. It waits the completion of the coherence request by polling the
905	// r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST
906	// states. These flip-flops are reset by the ICACHE and DCACHE FSMs.
907	// These two FSMs signal if a VCI answer must be send by setting
908	// the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops.
909	///////////////////////////////////////////////////////////////////////////////
910
911	switch( r_tgt_fsm.read() )
912	{
913	//////////////
914	case TGT_IDLE:
915	{
916	if ( p_vci_tgt_c.cmdval.read() )
917	{
918	paddr_t address = p_vci_tgt_c.address.read();
919
920	// command checking
921	if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE)
922	{
923	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
924	std::cout << "the received VCI coherence command is not a write" << std::endl;
925	exit(0);
926	}
927
928	// address checking
929	if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) )
930	{
931	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
932	std::cout << "out of segment VCI coherence command received" << std::endl;
933	exit(0);
934	}
935
936	r_tgt_srcid = p_vci_tgt_c.srcid.read();
937	r_tgt_trdid = p_vci_tgt_c.trdid.read();
938	r_tgt_pktid = p_vci_tgt_c.pktid.read();
939
940	if (sizeof(paddr_t) <= 32) {
941	assert(p_vci_tgt_c.be.read() == 0 && "byte enable should be 0 for 32bits paddr");
942	r_tgt_paddr =
943	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
944	} else {
945	r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 \|
946	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
947	}
948
949	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
950	{
951	if ( not p_vci_tgt_c.eop.read() )
952	{
953	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
954	std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl;
955	exit(0);
956	}
957	r_tgt_update = false;
958	r_tgt_fsm = TGT_REQ_BROADCAST;
959
960	#ifdef INSTRUMENTATION
961	m_cpt_cc_broadcast++;
962	#endif
963	}
964	else // multi-update or multi-invalidate for data type
965	{
966	paddr_t cell = address - m_segment.baseAddress();
967
968	if (cell == 0) // invalidate data
969	{
970	if ( not p_vci_tgt_c.eop.read() )
971	{
972	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
973	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
974	exit(0);
975	}
976	r_tgt_update = false;
977	r_tgt_fsm = TGT_REQ_DCACHE;
978
979	#ifdef INSTRUMENTATION
980	m_cpt_cc_inval_dcache++;
981	#endif
982	}
983	else if (cell == 4) // invalidate instruction
984	{
985	if ( not p_vci_tgt_c.eop.read() )
986	{
987	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
988	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
989	exit(0);
990	}
991	r_tgt_update = false;
992	r_tgt_fsm = TGT_REQ_ICACHE;
993
994	#ifdef INSTRUMENTATION
995	m_cpt_cc_inval_icache++;
996	#endif
997	}
998	else if (cell == 8) // update data
999	{
1000	if ( p_vci_tgt_c.eop.read() )
1001	{
1002	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1003	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1004	exit(0);
1005	}
1006	r_tgt_update = true;
1007	r_tgt_update_data = true;
1008	r_tgt_fsm = TGT_UPDT_WORD;
1009
1010	#ifdef INSTRUMENTATION
1011	m_cpt_cc_update_dcache++;
1012	#endif
1013	}
1014	else // update instruction
1015	{
1016	if ( p_vci_tgt_c.eop.read() )
1017	{
1018	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1019	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1020	exit(0);
1021	}
1022	r_tgt_update = true;
1023	r_tgt_update_data = false;
1024	r_tgt_fsm = TGT_UPDT_WORD;
1025
1026	#ifdef INSTRUMENTATION
1027	m_cpt_cc_update_icache++;
1028	#endif
1029	}
1030	} // end if multi
1031	} // end if cmdval
1032	break;
1033	}
1034	///////////////////
1035	case TGT_UPDT_WORD: // first word index acquisition
1036	{
1037	if (p_vci_tgt_c.cmdval.read())
1038	{
1039	if ( p_vci_tgt_c.eop.read() )
1040	{
1041	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1042	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1043	exit(0);
1044	}
1045	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false;
1046
1047	r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index
1048	r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index
1049	r_tgt_fsm = TGT_UPDT_DATA;
1050	}
1051	break;
1052	}
1053	///////////////////
1054	case TGT_UPDT_DATA:
1055	{
1056	if (p_vci_tgt_c.cmdval.read())
1057	{
1058	size_t word = r_tgt_word_count.read();
1059	if (word >= m_dcache_words)
1060	{
1061	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1062	std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl;
1063	exit(0);
1064	}
1065	r_tgt_buf[word] = p_vci_tgt_c.wdata.read();
1066	r_tgt_be[word] = p_vci_tgt_c.be.read();
1067	r_tgt_word_count = word + 1;
1068
1069	if (p_vci_tgt_c.eop.read()) // last word
1070	{
1071	r_tgt_word_max = word;
1072	if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE;
1073	else r_tgt_fsm = TGT_REQ_ICACHE;
1074	}
1075	}
1076	break;
1077	}
1078	///////////////////////
1079	case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs
1080	{
1081	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() )
1082	{
1083	r_tgt_fsm = TGT_RSP_BROADCAST;
1084	r_tgt_icache_req = true;
1085	r_tgt_dcache_req = true;
1086	}
1087	break;
1088	}
1089	/////////////////////
1090	case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending)
1091	{
1092	if ( not r_tgt_icache_req.read() )
1093	{
1094	r_tgt_fsm = TGT_RSP_ICACHE;
1095	r_tgt_icache_req = true;
1096	}
1097	break;
1098	}
1099	////////////////////
1100	case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending)
1101	{
1102	if ( not r_tgt_dcache_req.read() )
1103	{
1104	r_tgt_fsm = TGT_RSP_DCACHE;
1105	r_tgt_dcache_req = true;
1106	}
1107	break;
1108	}
1109	///////////////////////
1110	case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs
1111	// no response when r_tgt_*cache_rsp is false
1112	{
1113	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed
1114	{
1115	if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response
1116	{
1117	if ( p_vci_tgt_c.rspack.read() )
1118	{
1119	// reset dcache first if activated
1120	if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false;
1121	else r_tgt_icache_rsp = false;
1122	}
1123	}
1124	else
1125	{
1126	r_tgt_fsm = TGT_IDLE;
1127	}
1128	}
1129	break;
1130	}
1131	////////////////////
1132	case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM
1133	{
1134	// no response when r_tgt_icache_rsp is false
1135	if ( not r_tgt_icache_req.read() and p_vci_tgt_c.rspack.read() )
1136	{
1137	r_tgt_fsm = TGT_IDLE;
1138	r_tgt_icache_rsp = false;
1139	}
1140	break;
1141	}
1142	////////////////////
1143	case TGT_RSP_DCACHE:
1144	{
1145	// no response when r_tgt_dcache_rsp is false
1146	if ( not r_tgt_dcache_req.read() and p_vci_tgt_c.rspack.read() )
1147	{
1148	r_tgt_fsm = TGT_IDLE;
1149	r_tgt_dcache_rsp = false;
1150	}
1151	break;
1152	}
1153	} // end switch TGT_FSM
1154
1155	/////////////////////////////////////////////////////////////////////
1156	// Get data and instruction requests from processor
1157	///////////////////////////////////////////////////////////////////////
1158
1159	r_iss.getRequests(m_ireq, m_dreq);
1160
1161	////////////////////////////////////////////////////////////////////////////////////
1162	// ICACHE_FSM
1163	//
1164	// There is 9 conditions to exit the IDLE state:
1165	// One condition is a coherence request from TGT FSM :
1166	// - Coherence operation => ICACHE_CC_CHEK
1167	// Five configurations corresponding to XTN processor requests sent by DCACHE FSM :
1168	// - Flush TLB => ICACHE_XTN_TLB_FLUSH
1169	// - Flush cache => ICACHE_XTN_CACHE_FLUSH
1170	// - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL
1171	// - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@
1172	// - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA
1173	// three configurations corresponding to instruction processor requests :
1174	// - tlb miss => ICACHE_TLB_WAIT
1175	// - cacheable read miss => ICACHE_MISS_VICTIM
1176	// - uncacheable read miss => ICACHE_UNC_REQ
1177	//
1178	// In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM
1179	// using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the
1180	// transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM
1181	// state to select a slot and request a VCI transaction to the CLEANUP FSM.
1182	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM.
1183	// The availability of the missing cache line is signaled by the response fifo,
1184	// and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state.
1185	//
1186	// In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
1187	// to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop
1188	// when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
1189	// the response from the RSP FSM, through the response fifo. The missing instruction
1190	// is directly returned to processor in this state.
1191	//
1192	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb
1193	// using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register,
1194	// and goes to the ICACHE_TLB_WAIT state.
1195	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until
1196	// the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
1197	//
1198	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1199	// using the r_dcache_xtn_req flip-flop.
1200	// The request opcode and the address to be invalidated are transmitted
1201	// in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
1202	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1203	// is completed.
1204	//
1205	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1206	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1207	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1208	////////////////////////////////////////////////////////////////////////////////////////
1209
1210	// default value for m_irsp
1211	m_irsp.valid = false;
1212	m_irsp.error = false;
1213	m_irsp.instruction = 0;
1214
1215	switch( r_icache_fsm.read() )
1216	{
1217	/////////////////
1218	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent
1219	// by DCACHE FSM, and coherence requests with a fixed priority:
1220	// coherence > XTN > instruction
1221	// We access the itlb and dcache in parallel with the virtual address
1222	// for itlb, and with a speculative physical address for icache,
1223	// computed during the previous cycle.
1224	{
1225	// coherence request from the target FSM
1226	if ( r_tgt_icache_req.read() )
1227	{
1228	r_icache_fsm = ICACHE_CC_CHECK;
1229	r_icache_fsm_save = r_icache_fsm.read();
1230	break;
1231	}
1232
1233	// Decoding processor XTN requests sent by DCACHE FSM
1234	// These request are not executed in this IDLE state, because
1235	// they require access to icache or itlb, that are already accessed
1236	if ( r_dcache_xtn_req.read() )
1237	{
1238	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1239	{
1240	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1241	break;
1242	}
1243	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1244	{
1245	r_icache_flush_count = 0;
1246	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1247	break;
1248	}
1249	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1250	{
1251	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1252	break;
1253	}
1254	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1255	{
1256	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1257	break;
1258	}
1259	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1260	{
1261	if (sizeof(paddr_t) <= 32) {
1262	assert(r_mmu_word_hi.read() == 0 &&
1263	"high bits should be 0 for 32bit paddr");
1264	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1265	} else {
1266	r_icache_vci_paddr =
1267	(paddr_t)r_mmu_word_hi.read() << 32 \|
1268	(paddr_t)r_mmu_word_lo.read();
1269	}
1270	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1271	break;
1272	}
1273	} // end if xtn_req
1274
1275	// processor request
1276	if ( m_ireq.valid )
1277	{
1278	bool cacheable;
1279	paddr_t paddr;
1280
1281	// We register processor request
1282	r_icache_vaddr_save = m_ireq.addr;
1283
1284	// speculative icache access (if cache activated)
1285	// we use the speculative PPN computed during the previous cycle
1286
1287	uint32_t cache_inst = 0;
1288	bool cache_hit = false;
1289
1290	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1291	{
1292	paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) \|
1293	((paddr_t)m_ireq.addr & PAGE_K_MASK);
1294
1295	#ifdef INSTRUMENTATION
1296	m_cpt_icache_data_read++;
1297	m_cpt_icache_dir_read++;
1298	#endif
1299	cache_hit = r_icache.read( spc_paddr,
1300	&cache_inst );
1301	}
1302
1303	// systematic itlb access (if tlb activated)
1304	// we use the virtual address
1305
1306	paddr_t tlb_paddr;
1307	pte_info_t tlb_flags;
1308	size_t tlb_way;
1309	size_t tlb_set;
1310	paddr_t tlb_nline;
1311	bool tlb_hit = false;;
1312
1313	if ( r_mmu_mode.read() & INS_TLB_MASK )
1314	{
1315
1316	#ifdef INSTRUMENTATION
1317	m_cpt_itlb_read++;
1318	#endif
1319	tlb_hit = r_itlb.translate( m_ireq.addr,
1320	&tlb_paddr,
1321	&tlb_flags,
1322	&tlb_nline, // unused
1323	&tlb_way, // unused
1324	&tlb_set ); // unused
1325	}
1326
1327	// We compute cacheability, physical address and check access rights:
1328	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1329	// the physical address is obtained from the TLB, and the access rights are
1330	// defined by the U and X bits in the PTE.
1331	// - If MMU not activated : cacheability is defined by the segment table,
1332	// the physical address is equal to the virtual address (identity mapping)
1333	// and there is no access rights checking
1334
1335	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1336	{
1337	// cacheability
1338	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1339	else cacheable = m_cacheability_table[m_ireq.addr];
1340
1341	// physical address
1342	paddr = (paddr_t)m_ireq.addr;
1343	}
1344	else // itlb activated
1345	{
1346	if ( tlb_hit ) // tlb hit
1347	{
1348	// cacheability
1349	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1350	else cacheable = tlb_flags.c;
1351
1352	// physical address
1353	paddr = tlb_paddr;
1354
1355	// access rights checking
1356	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1357	{
1358	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1359	r_mmu_ibvar = m_ireq.addr;
1360	m_irsp.valid = true;
1361	m_irsp.error = true;
1362	m_irsp.instruction = 0;
1363	break;
1364	}
1365	else if ( not tlb_flags.x )
1366	{
1367	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1368	r_mmu_ibvar = m_ireq.addr;
1369	m_irsp.valid = true;
1370	m_irsp.error = true;
1371	m_irsp.instruction = 0;
1372	break;
1373	}
1374	}
1375	// in case of TLB miss we send an itlb miss request to DCACHE FSM and break
1376	else
1377	{
1378
1379	#ifdef INSTRUMENTATION
1380	m_cpt_itlb_miss++;
1381	#endif
1382	r_icache_fsm = ICACHE_TLB_WAIT;
1383	r_icache_tlb_miss_req = true;
1384	break;
1385	}
1386	} // end if itlb activated
1387
1388	// physical address registration (for next cycle)
1389	r_icache_vci_paddr = paddr;
1390
1391	// We enter this section only in case of TLB hit:
1392	// Finally, we get the instruction depending on cacheability,
1393	// we send the response to processor, and compute next state
1394	if ( cacheable ) // cacheable read
1395	{
1396	if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK)
1397	!= (paddr & ~PAGE_K_MASK) ) // speculative access KO
1398	{
1399
1400	#ifdef INSTRUMENTATION
1401	m_cpt_icache_spc_miss++;
1402	#endif
1403	// we return an invalid response and stay in IDLE state
1404	// the cache access will cost one extra cycle.
1405	break;
1406	}
1407
1408	if ( not cache_hit ) // cache miss
1409	{
1410	// in case of icache miss we send a request to CMD FSM, but we are
1411	// blocked in IDLE state if the previous cleanup is not completed
1412	if ( not r_icache_cleanup_req.read() )
1413	{
1414
1415	#ifdef INSTRUMENTATION
1416	m_cpt_icache_miss++;
1417	#endif
1418	r_icache_fsm = ICACHE_MISS_VICTIM;
1419	r_icache_miss_req = true;
1420	}
1421	break;
1422	}
1423	else // cache hit
1424	{
1425
1426	#ifdef INSTRUMENTATION
1427	m_cpt_ins_read++;
1428	#endif
1429	m_irsp.valid = true;
1430	m_irsp.instruction = cache_inst;
1431	}
1432	}
1433	else // non cacheable read
1434	{
1435	r_icache_unc_req = true;
1436	r_icache_fsm = ICACHE_UNC_WAIT;
1437	}
1438	} // end if m_ireq.valid
1439	break;
1440	}
1441	/////////////////////
1442	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1443	// the itlb is udated by the DCACHE FSM, as well as the
1444	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1445	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1446	// reset the r_icache_tlb_miss_req flip-flop
1447	// external coherence request are accepted in this state.
1448	{
1449	// external coherence request
1450	if ( r_tgt_icache_req.read() )
1451	{
1452	r_icache_fsm = ICACHE_CC_CHECK;
1453	r_icache_fsm_save = r_icache_fsm.read();
1454	break;
1455	}
1456
1457	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1458
1459	// DCACHE FSM signals response by reseting the request flip-flop
1460	if ( not r_icache_tlb_miss_req.read() )
1461	{
1462	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1463	{
1464	r_icache_tlb_rsp_error = false;
1465	m_irsp.error = true;
1466	m_irsp.valid = true;
1467	r_icache_fsm = ICACHE_IDLE;
1468	}
1469	else // tlb updated : return to IDLE state
1470	{
1471	r_icache_fsm = ICACHE_IDLE;
1472	}
1473	}
1474	break;
1475	}
1476	//////////////////////////
1477	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1478	{
1479	r_itlb.flush();
1480	r_dcache_xtn_req = false;
1481	r_icache_fsm = ICACHE_IDLE;
1482	break;
1483	}
1484	////////////////////////////
1485	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using
1486	// the r_icache_flush_count register as a slot counter.
1487	// We loop in this state until all slots have been visited.
1488	// A cleanup request is generated for each valid line
1489	// and we are blocked until the previous cleanup is completed
1490	{
1491	if ( not r_icache_cleanup_req.read() )
1492	{
1493	size_t way = r_icache_flush_count.read()/m_icache_sets;
1494	size_t set = r_icache_flush_count.read()%m_icache_sets;
1495	paddr_t nline;
1496	bool cleanup_req = r_icache.inval( way,
1497	set,
1498	&nline );
1499	if ( cleanup_req )
1500	{
1501	r_icache_cleanup_req = true;
1502	r_icache_cleanup_line = nline;
1503	}
1504	r_icache_flush_count = r_icache_flush_count.read() + 1;
1505	}
1506
1507	if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) )
1508	{
1509	r_dcache_xtn_req = false;
1510	r_icache_fsm = ICACHE_IDLE;
1511	}
1512	break;
1513	}
1514	//////////////////////////
1515	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1516	// stored in the r_dcache_p0_wdata register
1517	{
1518	r_itlb.inval(r_dcache_p0_wdata.read());
1519	r_dcache_xtn_req = false;
1520	r_icache_fsm = ICACHE_IDLE;
1521	break;
1522	}
1523	///////////////////////////////
1524	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1525	// requires 3 cycles (in case of hit on itlb and icache).
1526	// In this state, we access TLB to translate virtual address
1527	// stored in the r_dcache_p0_wdata register.
1528	{
1529	paddr_t paddr;
1530	bool hit;
1531
1532	// read physical address in TLB when MMU activated
1533	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1534	{
1535
1536	#ifdef INSTRUMENTATION
1537	m_cpt_itlb_read++;
1538	#endif
1539	hit = r_itlb.translate(r_dcache_p0_wdata.read(),
1540	&paddr);
1541	}
1542	else // itlb not activated
1543	{
1544	paddr = (paddr_t)r_dcache_p0_wdata.read();
1545	hit = true;
1546	}
1547
1548	if ( hit ) // continue the selective inval process
1549	{
1550	r_icache_vci_paddr = paddr;
1551	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1552	}
1553	else // miss : send a request to DCACHE FSM
1554	{
1555
1556	#ifdef INSTRUMENTATION
1557	m_cpt_itlb_miss++;
1558	#endif
1559	r_icache_tlb_miss_req = true;
1560	r_icache_fsm = ICACHE_TLB_WAIT;
1561	}
1562	break;
1563	}
1564	///////////////////////////////
1565	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1566	// require 2 cycles. In this state, we read dcache,
1567	// with address stored in r_icache_vci_paddr register.
1568	{
1569	uint32_t data;
1570	size_t way;
1571	size_t set;
1572	size_t word;
1573	bool hit = r_icache.read(r_icache_vci_paddr.read(),
1574	&data,
1575	&way,
1576	&set,
1577	&word);
1578	if ( hit ) // inval to be done
1579	{
1580	r_icache_miss_way = way;
1581	r_icache_miss_set = set;
1582	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1583	}
1584	else // miss : acknowlege the XTN request and return
1585	{
1586	r_dcache_xtn_req = false;
1587	r_icache_fsm = ICACHE_IDLE;
1588	}
1589	break;
1590	}
1591	///////////////////////////////
1592	case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup.
1593	// We are blocked if the previous cleanup is not completed
1594	{
1595	paddr_t nline;
1596
1597	if ( not r_icache_cleanup_req.read() )
1598	{
1599	r_icache.inval( r_icache_miss_way.read(),
1600	r_icache_miss_set.read(),
1601	&nline );
1602
1603	// request cleanup
1604	r_icache_cleanup_req = true;
1605	r_icache_cleanup_line = nline;
1606	// acknowledge the XTN request and return
1607	r_dcache_xtn_req = false;
1608	r_icache_fsm = ICACHE_IDLE;
1609	}
1610	break;
1611	}
1612
1613	////////////////////////
1614	case ICACHE_MISS_VICTIM: // Selects a victim line
1615	// Set the r_icache_cleanup_req flip-flop
1616	// when the selected slot is not empty
1617	{
1618	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1619
1620	bool valid;
1621	size_t way;
1622	size_t set;
1623	paddr_t victim;
1624
1625	valid = r_icache.victim_select(r_icache_vci_paddr.read(),
1626	&victim,
1627	&way,
1628	&set);
1629	r_icache_miss_way = way;
1630	r_icache_miss_set = set;
1631
1632	if ( valid )
1633	{
1634	r_icache_cleanup_req = true;
1635	r_icache_cleanup_line = victim;
1636	r_icache_fsm = ICACHE_MISS_INVAL;
1637	}
1638	else
1639	{
1640	r_icache_fsm = ICACHE_MISS_WAIT;
1641	}
1642	break;
1643	}
1644	///////////////////////
1645	case ICACHE_MISS_INVAL: // invalidate the victim line
1646	{
1647	paddr_t nline;
1648	bool hit;
1649
1650	hit = r_icache.inval( r_icache_miss_way.read(),
1651	r_icache_miss_set.read(),
1652	&nline ); // unused
1653	assert(hit && "selected way/set line should be in icache");
1654
1655	r_icache_fsm = ICACHE_MISS_WAIT;
1656	break;
1657	}
1658	//////////////////////
1659	case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM
1660	{
1661	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1662
1663	// external coherence request
1664	if ( r_tgt_icache_req.read() )
1665	{
1666	r_icache_fsm = ICACHE_CC_CHECK;
1667	r_icache_fsm_save = r_icache_fsm.read();
1668	break;
1669	}
1670
1671	if ( r_vci_rsp_ins_error.read() ) // bus error
1672	{
1673	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1674	r_mmu_ibvar = r_icache_vaddr_save.read();
1675	m_irsp.valid = true;
1676	m_irsp.error = true;
1677	r_vci_rsp_ins_error = false;
1678	r_icache_fsm = ICACHE_IDLE;
1679	}
1680	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1681	{
1682	r_icache_miss_word = 0;
1683	r_icache_fsm = ICACHE_MISS_UPDT;
1684	}
1685	break;
1686	}
1687	//////////////////////
1688	case ICACHE_MISS_UPDT: // update the cache (one word per cycle)
1689	{
1690	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1691
1692	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1693	{
1694	if ( r_icache_miss_inval ) // Matching coherence request
1695	// We pop the response FIFO, without updating the cache
1696	// We send a cleanup for the missing line at the last word
1697	// Blocked if the previous cleanup is not completed
1698	{
1699	if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word
1700	{
1701	vci_rsp_fifo_icache_get = true;
1702	r_icache_miss_word = r_icache_miss_word.read() + 1;
1703	}
1704	else // last word
1705	{
1706	if ( not r_icache_cleanup_req.read() ) // no pending cleanup
1707	{
1708	vci_rsp_fifo_icache_get = true;
1709	r_icache_cleanup_req = true;
1710	r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2));
1711	r_icache_miss_inval = false;
1712	r_icache_fsm = ICACHE_IDLE;
1713	}
1714	}
1715	}
1716	else // No matching coherence request
1717	// We pop the FIFO and update the cache
1718	// We update the directory at the last word
1719	{
1720
1721	#ifdef INSTRUMENTATION
1722	m_cpt_icache_data_write++;
1723	#endif
1724	r_icache.write( r_icache_miss_way.read(),
1725	r_icache_miss_set.read(),
1726	r_icache_miss_word.read(),
1727	r_vci_rsp_fifo_icache.read() );
1728	vci_rsp_fifo_icache_get = true;
1729	r_icache_miss_word = r_icache_miss_word.read() + 1;
1730	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1731	{
1732
1733	#ifdef INSTRUMENTATION
1734	m_cpt_icache_dir_write++;
1735	#endif
1736	r_icache.victim_update_tag( r_icache_vci_paddr.read(),
1737	r_icache_miss_way.read(),
1738	r_icache_miss_set.read() );
1739	r_icache_fsm = ICACHE_IDLE;
1740	}
1741	}
1742	}
1743	break;
1744	}
1745	////////////////////
1746	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1747	//
1748	{
1749	// external coherence request
1750	if ( r_tgt_icache_req.read() )
1751	{
1752	r_icache_fsm = ICACHE_CC_CHECK;
1753	r_icache_fsm_save = r_icache_fsm.read();
1754	break;
1755	}
1756
1757	if ( r_vci_rsp_ins_error.read() ) // bus error
1758	{
1759	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1760	r_mmu_ibvar = m_ireq.addr;
1761	r_vci_rsp_ins_error = false;
1762	m_irsp.valid = true;
1763	m_irsp.error = true;
1764	r_icache_fsm = ICACHE_IDLE;
1765	}
1766	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1767	{
1768	vci_rsp_fifo_icache_get = true;
1769	r_icache_fsm = ICACHE_IDLE;
1770	if ( m_ireq.valid and (m_ireq.addr == r_icache_vaddr_save.read()) ) // request not modified
1771	{
1772	m_irsp.valid = true;
1773	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1774	}
1775	}
1776	break;
1777	}
1778	/////////////////////
1779	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1780	// handling coherence requests.
1781	// the return state is defined in r_icache_fsm_save.
1782	{
1783	paddr_t paddr = r_tgt_paddr.read();
1784	paddr_t mask = ~((m_icache_words<<2)-1);
1785
1786	if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and
1787	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss
1788	{
1789	r_icache_miss_inval = true; // signaling the matching
1790	r_tgt_icache_req = false; // coherence request completed
1791	r_tgt_icache_rsp = r_tgt_update.read(); // response required if update
1792	r_icache_fsm = r_icache_fsm_save.read();
1793	}
1794	else // no match
1795	{
1796
1797	#ifdef INSTRUMENTATION
1798	m_cpt_icache_dir_read++;
1799	#endif
1800	uint32_t inst;
1801	size_t way;
1802	size_t set;
1803	size_t word;
1804	bool hit = r_icache.read(paddr,
1805	&inst,
1806	&way,
1807	&set,
1808	&word);
1809	r_icache_cc_way = way;
1810	r_icache_cc_set = set;
1811
1812	if ( hit and r_tgt_update.read() ) // hit update
1813	{
1814	r_icache_fsm = ICACHE_CC_UPDT;
1815	r_icache_cc_word = r_tgt_word_min.read();
1816	}
1817	else if ( hit and not r_tgt_update.read() ) // hit inval
1818	{
1819	r_icache_fsm = ICACHE_CC_INVAL;
1820	}
1821	else // miss can happen
1822	{
1823	r_tgt_icache_req = false;
1824	r_tgt_icache_rsp = r_tgt_update.read();
1825	r_icache_fsm = r_icache_fsm_save.read();
1826	}
1827	}
1828	break;
1829	}
1830
1831	/////////////////////
1832	case ICACHE_CC_INVAL: // invalidate a cache line
1833	{
1834	paddr_t nline;
1835	r_icache.inval( r_icache_cc_way.read(),
1836	r_icache_cc_set.read(),
1837	&nline );
1838
1839	r_tgt_icache_req = false;
1840	r_tgt_icache_rsp = true;
1841	r_icache_fsm = r_icache_fsm_save.read();
1842	break;
1843	}
1844	////////////////////
1845	case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
1846	{
1847	size_t word = r_icache_cc_word.read();
1848	size_t way = r_icache_cc_way.read();
1849	size_t set = r_icache_cc_set.read();
1850
1851	r_icache.write( way,
1852	set,
1853	word,
1854	r_tgt_buf[word],
1855	r_tgt_be[word] );
1856
1857	r_icache_cc_word = word+1;
1858
1859	if ( word == r_tgt_word_max.read() ) // last word
1860	{
1861	r_tgt_icache_req = false;
1862	r_tgt_icache_rsp = true;
1863	r_icache_fsm = r_icache_fsm_save.read();
1864	}
1865	break;
1866	}
1867
1868	} // end switch r_icache_fsm
1869
1870	////////////////////////////////////////////////////////////////////////////////////
1871	// DCACHE FSM
1872	//
1873	// Both the Cacheability Table, and the MMU cacheable bit are used to define
1874	// the cacheability, depending on the MMU mode.
1875	//
1876	// 1/ Coherence requests :
1877	// There is a coherence request when the tgt_dcache_req flip-flop is set,
1878	// requesting a line invalidation or a line update.
1879	// Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states.
1880	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
1881	// goes to the CC_CHECK state to execute the requested action, and returns to the
1882	// pre-empted state.
1883	//
1884	// 2/ TLB miss
1885	// The page tables can be cacheable.
1886	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1887	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1888	// this sub-fsm implement the table-walk...
1889	//
1890	// 3/ processor requests :
1891	// Processor READ, WRITE, LL or SC requests are taken in IDLE state only.
1892	// The IDLE state implements a three stages pipe-line to handle write bursts:
1893	// - The physical address is computed by dtlb in stage P0.
1894	// - The registration in wbuf and the dcache hit are computed in stage P1.
1895	// - The dcache update is done in stage P2.
1896	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
1897	// that is done (before handling the processor request) by a dedicated sub-fsm
1898	// (DCACHE_DIRTY_TLB_SET state).
1899	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
1900	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
1901	// If there is no write in the pipe, dcache and dtlb are accessed in parallel,
1902	// (virtual address for itlb, and speculative physical address computed during
1903	// previous cycle for dcache) in order to return the data in one cycle for a READ
1904	// request. We just pay an extra cycle when the speculative access is failing.
1905	//
1906	// 4/ Atomic instructions LL/SC
1907	// The LL/SC address can be cacheable or non cacheable.
1908	// The reservation registers (r_dcache_ll_valid, r_dcache_ll_vaddr and
1909	// r_dcache_ll_data are stored in the L1 cache controller, and not in the
1910	// memory controller.
1911	// - LL requests from the processor are transmitted as standard VCI
1912	// READ transactions (one word / one line, depending on the cacheability).
1913	// - SC requests from the processor are systematically transmitted to the
1914	// memory cache as Compare&swap requests (both the data value stored in the
1915	// r_dcache_ll_data register and the new value).
1916	// The cache is not updated, as this is done in case of success by the
1917	// coherence transaction.
1918	//
1919	// 5/ Non cacheable access:
1920	// This component implement a strong order between non cacheable access
1921	// (read or write) : A new non cacheable VCI transaction starts only when
1922	// the previous non cacheable transaction is completed. Both cacheable and
1923	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
1924	// a non cacheable write transaction posted in the write buffer by setting the
1925	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
1926	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
1927	// pending non cacheable write transaction completes).
1928	//
1929	// 6/ Error handling:
1930	// When the MMU is not activated, Read Bus Errors are synchronous events,
1931	// but Write Bus Errors are asynchronous events (processor is not frozen).
1932	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
1933	// r_vci_rsp_data_error flip-flop, without writing any data in the
1934	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
1935	// by the DCACHE FSM.
1936	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
1937	// the asynchronous error using the setWriteBerr() method.
1938	// When the MMU is activated bus error are rare events, as the MMU
1939	// checks the physical address before the VCI transaction starts.
1940	////////////////////////////////////////////////////////////////////////////////////////
1941
1942	// default value for m_drsp
1943	m_drsp.valid = false;
1944	m_drsp.error = false;
1945	m_drsp.rdata = 0;
1946
1947	switch ( r_dcache_fsm.read() )
1948	{
1949	case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state :
1950	// 1) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
1951	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
1952	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
1953	// 4) XTN request (processor) => DCACHE_XTN_*
1954	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
1955	// 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM
1956	// 7) Uncacheable read (processor) => DCACHE_UNC_WAIT
1957	// 8) SC access (processor) => DCACHE_SC_WAIT
1958	//
1959	// The dtlb is unconditionally accessed to translate the
1960	// virtual adress from processor.
1961	//
1962	// There is 4 configurations to access the cache,
1963	// depending on the pipe-line state, defined
1964	// by the r_dcache_p0_valid (V0) flip-flop : P1 stage activated
1965	// and r_dcache_p1_valid (V1) flip-flop : P2 stage activated
1966	// V0 / V1 / Data / Directory / comment
1967	// 0 / 0 / read(A0) / read(A0) / read speculative access
1968	// 0 / 1 / write(A2) / nop / read request delayed
1969	// 1 / 0 / nop / read(A1) / read request delayed
1970	// 1 / 1 / write(A2) / read(A1) / read request delayed
1971	{
1972	////////////////////////////////////////////////////////////////////////////////
1973	// Handling P2 pipe-line stage
1974	// Inputs are r_dcache_p1_* registers.
1975	// If r_dcache_p1_valid is true, we update the local copy in dcache.
1976	// If the modified cache line has copies in TLBs, we launch a TLB invalidate
1977	// operation, going to DCACHE_INVAL_TLB_SCAN state.
1978
1979	bool tlb_inval_required = false;
1980
1981	if ( r_dcache_p1_valid.read() ) // P2 stage activated
1982	{
1983	size_t way = r_dcache_p1_cache_way.read();
1984	size_t set = r_dcache_p1_cache_set.read();
1985	size_t word = r_dcache_p1_cache_word.read();
1986	uint32_t wdata = r_dcache_p1_wdata.read();
1987	vci_be_t be = r_dcache_p1_be.read();
1988
1989	r_dcache.write( way,
1990	set,
1991	word,
1992	wdata,
1993	be );
1994	#ifdef INSTRUMENTATION
1995	m_cpt_dcache_data_write++;
1996	#endif
1997	// cache update after a WRITE hit can require itlb & dtlb inval or flush
1998	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
1999	{
2000	tlb_inval_required = true;
2001	r_dcache_tlb_inval_count = 0;
2002	r_dcache_tlb_inval_line = r_dcache_p1_paddr.read()>>(uint32_log2(m_dcache_words<<2));
2003	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2004	}
2005	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2006	{
2007	r_itlb.reset();
2008	r_dtlb.reset();
2009	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2010	}
2011
2012	#if DEBUG_DCACHE
2013	if ( m_debug_dcache_fsm )
2014	{
2015	std::cout << " <PROC.DCACHE_IDLE> Cache update in P2 stage" << std::dec
2016	<< " / WAY = " << way
2017	<< " / SET = " << set
2018	<< " / WORD = " << word << std::hex
2019	<< " / DATA = " << wdata
2020	<< " / BE = " << be << std::endl;
2021	}
2022	#endif
2023	} // end P2 stage
2024
2025	///////////////////////////////////////////////////////////////////////////
2026	// Handling P1 pipe-line stage
2027	// Inputs are r_dcache_p0_* registers.
2028	// We must write into wbuf and test the hit in dcache.
2029	// If the write request is non cacheable, and there is a pending
2030	// non cacheable write, or if the write buffer is full, we break,
2031	// because the P0 and P1 pipe-line stages are frozen until the write
2032	// request registration is possible, but he P2 stage is not frozen.
2033	// The r_dcache_p1_valid bit must be computed at all cycles, and
2034	// the P2 stage must be activated if there is local copy in dcache.
2035
2036	if ( r_dcache_p0_valid.read() ) // P1 stage activated
2037	{
2038	// write not cacheable, and previous non cacheable write registered
2039	if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() )
2040	{
2041	r_dcache_p1_valid = false;
2042	break;
2043	}
2044
2045	// try a registration into write buffer
2046	bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
2047	r_dcache_p0_be.read(),
2048	r_dcache_p0_wdata.read(),
2049	r_dcache_p0_cacheable.read() );
2050	#ifdef INSTRUMENTATION
2051	m_cpt_wbuf_write++;
2052	#endif
2053	// write buffer full
2054	if ( not wok )
2055	{
2056	r_dcache_p1_valid = false;
2057	break;
2058	}
2059	// update the write_buffer state extension
2060	r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
2061
2062	// read directory to check local copy
2063	size_t cache_way;
2064	size_t cache_set;
2065	size_t cache_word;
2066	bool local_copy;
2067	if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated
2068	{
2069	local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
2070	&cache_way,
2071	&cache_set,
2072	&cache_word );
2073	#ifdef INSTRUMENTATION
2074	m_cpt_dcache_dir_read++;
2075	#endif
2076	}
2077	else
2078	{
2079	local_copy = false;
2080	}
2081
2082	// store values for P2 pipe stage
2083	if ( local_copy )
2084	{
2085	r_dcache_p1_valid = true;
2086	r_dcache_p1_wdata = r_dcache_p0_wdata.read();
2087	r_dcache_p1_be = r_dcache_p0_be.read();
2088	r_dcache_p1_paddr = r_dcache_p0_paddr.read();
2089	r_dcache_p1_cache_way = cache_way;
2090	r_dcache_p1_cache_set = cache_set;
2091	r_dcache_p1_cache_word = cache_word;
2092	}
2093	else
2094	{
2095	r_dcache_p1_valid = false;
2096	}
2097	}
2098	else // P1 stage not activated
2099	{
2100	r_dcache_p1_valid = false;
2101	} // end P1 stage
2102
2103	/////////////////////////////////////////////////////////////////////////////////
2104	// handling P0 pipe-line stage
2105	// This stage is controlling r_dcache_fsm and r_dcache_p0_* registers.
2106	// The r_dcache_p0_valid flip-flop is only set in case of a WRITE request.
2107	// - the TLB invalidate requests have the highest priority,
2108	// - then the external coherence requests,
2109	// - then the itlb miss requests,
2110	// - and finally the processor requests.
2111	// If dtlb is activated, there is an unconditionnal access to dtlb,
2112	// for address translation.
2113	// 1) A processor WRITE request is blocked if the Dirty bit mus be set, or if
2114	// dtlb miss. If dtlb is OK, It enters the three stage pipe-line (fully
2115	// handled by the IDLE state), and the processor request is acknowledged.
2116	// 2) A processor READ or LL request generate a simultaneouss access to
2117	// both dcache data and dcache directoty, using speculative PPN, but
2118	// is delayed if the write pipe-line is not empty.
2119	// In case of miss, we wait the VCI response in DCACHE_UNC_WAIT or
2120	// DCACHE_MISS_WAIT states.
2121	// 3) A processor SC request is delayed until the write pipe-line is empty.
2122	// A VCI SC transaction is launched, and we wait the VCI response in
2123	// DCACHE_SC_WAIT state. It can be completed by a "long write" if the
2124	// PTE dirty bit must be updated in dtlb, dcache, and RAM.
2125	// The data is not modified in dcache, as it will be done by the
2126	// coherence transaction.
2127
2128	// TLB inval required
2129	if ( tlb_inval_required )
2130	{
2131	r_dcache_fsm_save = DCACHE_IDLE;
2132	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2133	r_dcache_p0_valid = false;
2134	}
2135	// external coherence request
2136	else if ( r_tgt_dcache_req.read() )
2137	{
2138	r_dcache_fsm_save = DCACHE_IDLE;
2139	r_dcache_fsm = DCACHE_CC_CHECK;
2140	r_dcache_p0_valid = false;
2141	}
2142
2143	// itlb miss request
2144	else if ( r_icache_tlb_miss_req.read() )
2145	{
2146	r_dcache_tlb_ins = true;
2147	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2148	r_dcache_fsm = DCACHE_TLB_MISS;
2149	r_dcache_p0_valid = false;
2150	}
2151
2152	// processor request
2153	else if ( m_dreq.valid )
2154	{
2155	// dcache access using speculative PPN only if pipe-line empty
2156	paddr_t cache_paddr;
2157	size_t cache_way;
2158	size_t cache_set;
2159	size_t cache_word;
2160	uint32_t cache_rdata;
2161	bool cache_hit;
2162
2163	if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated
2164	not r_dcache_p0_valid.read() and
2165	not r_dcache_p1_valid.read() ) // pipe-line empty
2166	{
2167	cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) \|
2168	((paddr_t)m_dreq.addr & PAGE_K_MASK);
2169
2170	cache_hit = r_dcache.read( cache_paddr,
2171	&cache_rdata,
2172	&cache_way,
2173	&cache_set,
2174	&cache_word );
2175	#ifdef INSTRUMENTATION
2176	m_cpt_dcache_dir_read++;
2177	m_cpt_dcache_data_read++;
2178	#endif
2179	}
2180	else
2181	{
2182	cache_hit = false;
2183	} // end dcache access
2184
2185	// systematic dtlb access using virtual address
2186	paddr_t tlb_paddr;
2187	pte_info_t tlb_flags;
2188	size_t tlb_way;
2189	size_t tlb_set;
2190	paddr_t tlb_nline;
2191	bool tlb_hit;
2192
2193	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2194	{
2195	tlb_hit = r_dtlb.translate( m_dreq.addr,
2196	&tlb_paddr,
2197	&tlb_flags,
2198	&tlb_nline,
2199	&tlb_way,
2200	&tlb_set );
2201	#ifdef INSTRUMENTATION
2202	m_cpt_dtlb_read++;
2203	#endif
2204	}
2205	else
2206	{
2207	tlb_hit = false;
2208	} // end dtlb access
2209
2210	// register the processor request
2211	r_dcache_p0_vaddr = m_dreq.addr;
2212	r_dcache_p0_be = m_dreq.be;
2213	r_dcache_p0_wdata = m_dreq.wdata;
2214
2215	// Handling READ XTN requests from processor
2216	// They are executed in this DCACHE_IDLE state.
2217	// The processor must not be in user mode
2218	if (m_dreq.type == iss_t::XTN_READ)
2219	{
2220	int xtn_opcode = (int)m_dreq.addr/4;
2221
2222	// checking processor mode:
2223	if (m_dreq.mode == iss_t::MODE_USER)
2224	{
2225	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2226	r_mmu_dbvar = m_dreq.addr;
2227	m_drsp.valid = true;
2228	m_drsp.error = true;
2229	r_dcache_fsm = DCACHE_IDLE;
2230	}
2231	else
2232	{
2233	switch( xtn_opcode )
2234	{
2235	case iss_t::XTN_INS_ERROR_TYPE:
2236	m_drsp.rdata = r_mmu_ietr.read();
2237	m_drsp.valid = true;
2238	break;
2239
2240	case iss_t::XTN_DATA_ERROR_TYPE:
2241	m_drsp.rdata = r_mmu_detr.read();
2242	m_drsp.valid = true;
2243	break;
2244
2245	case iss_t::XTN_INS_BAD_VADDR:
2246	m_drsp.rdata = r_mmu_ibvar.read();
2247	m_drsp.valid = true;
2248	break;
2249
2250	case iss_t::XTN_DATA_BAD_VADDR:
2251	m_drsp.rdata = r_mmu_dbvar.read();
2252	m_drsp.valid = true;
2253	break;
2254
2255	case iss_t::XTN_PTPR:
2256	m_drsp.rdata = r_mmu_ptpr.read();
2257	m_drsp.valid = true;
2258	break;
2259
2260	case iss_t::XTN_TLB_MODE:
2261	m_drsp.rdata = r_mmu_mode.read();
2262	m_drsp.valid = true;
2263	break;
2264
2265	case iss_t::XTN_MMU_PARAMS:
2266	m_drsp.rdata = r_mmu_params;
2267	m_drsp.valid = true;
2268	break;
2269
2270	case iss_t::XTN_MMU_RELEASE:
2271	m_drsp.rdata = r_mmu_release;
2272	m_drsp.valid = true;
2273	break;
2274
2275	case iss_t::XTN_MMU_WORD_LO:
2276	m_drsp.rdata = r_mmu_word_lo.read();
2277	m_drsp.valid = true;
2278	break;
2279
2280	case iss_t::XTN_MMU_WORD_HI:
2281	m_drsp.rdata = r_mmu_word_hi.read();
2282	m_drsp.valid = true;
2283	break;
2284
2285	default:
2286	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2287	r_mmu_dbvar = m_dreq.addr;
2288	m_drsp.valid = true;
2289	m_drsp.error = true;
2290	break;
2291	} // end switch xtn_opcode
2292	} // end else
2293	r_dcache_p0_valid = false;
2294	} // end if XTN_READ
2295
2296	// Handling WRITE XTN requests from processor.
2297	// They are not executed in this DCACHE_IDLE state,
2298	// if they require access to the caches or the TLBs
2299	// that are already accessed for speculative read.
2300	// Caches can be invalidated or flushed in user mode,
2301	// and the sync instruction can be executed in user mode
2302	else if (m_dreq.type == iss_t::XTN_WRITE)
2303	{
2304	int xtn_opcode = (int)m_dreq.addr/4;
2305	r_dcache_xtn_opcode = xtn_opcode;
2306
2307	// checking processor mode:
2308	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2309	(xtn_opcode != iss_t:: XTN_SYNC) &&
2310	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2311	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2312	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2313	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2314	{
2315	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2316	r_mmu_dbvar = m_dreq.addr;
2317	m_drsp.valid = true;
2318	m_drsp.error = true;
2319	r_dcache_fsm = DCACHE_IDLE;
2320	}
2321	else
2322	{
2323	switch( xtn_opcode )
2324	{
2325	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2326	r_mmu_ptpr = m_dreq.wdata;
2327	r_dcache_xtn_req = true;
2328	r_dcache_fsm = DCACHE_XTN_SWITCH;
2329	break;
2330
2331	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2332	r_mmu_mode = m_dreq.wdata;
2333	m_drsp.valid = true;
2334	r_dcache_fsm = DCACHE_IDLE;
2335	break;
2336
2337	case iss_t::XTN_DTLB_INVAL: // dtlb access
2338	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2339	break;
2340
2341	case iss_t::XTN_ITLB_INVAL: // itlb access
2342	r_dcache_xtn_req = true;
2343	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2344	break;
2345
2346	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2347	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2348	break;
2349
2350	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2351	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2352	if (sizeof(paddr_t) <= 32) {
2353	assert(r_mmu_word_hi.read() == 0 &&
2354	"high bits should be 0 for 32bit paddr");
2355	r_dcache_p0_paddr =
2356	(paddr_t)r_mmu_word_lo.read();
2357	} else {
2358	r_dcache_p0_paddr =
2359	(paddr_t)r_mmu_word_hi.read() << 32 \|
2360	(paddr_t)r_mmu_word_lo.read();
2361	}
2362	break;
2363
2364	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2365	r_dcache_flush_count = 0;
2366	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2367	break;
2368
2369	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2370	r_dcache_xtn_req = true;
2371	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2372	break;
2373
2374	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2375	r_dcache_xtn_req = true;
2376	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2377	break;
2378
2379	case iss_t::XTN_ICACHE_FLUSH: // icache access
2380	r_dcache_xtn_req = true;
2381	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2382	break;
2383
2384	case iss_t::XTN_SYNC: // wait until write buffer empty
2385	r_dcache_fsm = DCACHE_XTN_SYNC;
2386	break;
2387
2388	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2389	r_mmu_word_lo = m_dreq.wdata;
2390	m_drsp.valid = true;
2391	r_dcache_fsm = DCACHE_IDLE;
2392	break;
2393
2394	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2395	r_mmu_word_hi = m_dreq.wdata;
2396	m_drsp.valid = true;
2397	r_dcache_fsm = DCACHE_IDLE;
2398	break;
2399
2400	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2401	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2402	m_drsp.valid = true;
2403	r_dcache_fsm = DCACHE_IDLE;
2404	break;
2405
2406	default:
2407	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2408	r_mmu_dbvar = m_dreq.addr;
2409	m_drsp.valid = true;
2410	m_drsp.error = true;
2411	r_dcache_fsm = DCACHE_IDLE;
2412	break;
2413	} // end switch xtn_opcode
2414	} // end else
2415	r_dcache_p0_valid = false;
2416	} // end if XTN_WRITE
2417
2418	// Handling read/write/ll/sc processor requests.
2419	// The dtlb and dcache can be activated or not.
2420	// We compute the physical address, the cacheability, and check processor request.
2421	// - If DTLB not activated : cacheability is defined by the segment table,
2422	// the physical address is equal to the virtual address (identity mapping)
2423	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2424	// the physical address is obtained from the TLB, and the U & W bits
2425	// of the PTE are checked.
2426	// The processor request is decoded only if the TLB is not activated or if
2427	// the virtual address hits in tLB and access rights are OK.
2428	// We call the TLB_MISS sub-fsm in case of dtlb miss.
2429	else
2430	{
2431	bool valid_req = false;
2432	bool cacheable = false;
2433	paddr_t paddr = 0;
2434
2435	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2436	{
2437	valid_req = true;
2438
2439	// cacheability
2440	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2441	else cacheable = m_cacheability_table[m_dreq.addr];
2442
2443	// physical address
2444	paddr = (paddr_t)m_dreq.addr;
2445	}
2446	else // dtlb activated
2447	{
2448	if ( tlb_hit ) // tlb hit
2449	{
2450	// cacheability
2451	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2452	else cacheable = tlb_flags.c;
2453
2454	// access rights checking
2455	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2456	{
2457	if ( (m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL) )
2458	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2459	else
2460	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2461
2462	r_mmu_dbvar = m_dreq.addr;
2463	m_drsp.valid = true;
2464	m_drsp.error = true;
2465	m_drsp.rdata = 0;
2466	#if DEBUG_DCACHE
2467	if ( m_debug_dcache_fsm )
2468	{
2469	std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2470	}
2471	#endif
2472	}
2473	else if ( not tlb_flags.w and
2474	((m_dreq.type == iss_t::DATA_WRITE) or
2475	(m_dreq.type == iss_t::DATA_SC)) )
2476	{
2477	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2478	r_mmu_dbvar = m_dreq.addr;
2479	m_drsp.valid = true;
2480	m_drsp.error = true;
2481	m_drsp.rdata = 0;
2482	#if DEBUG_DCACHE
2483	if ( m_debug_dcache_fsm )
2484	{
2485	std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2486	}
2487	#endif
2488	}
2489	else
2490	{
2491	valid_req = true;
2492	}
2493
2494	// physical address
2495	paddr = tlb_paddr;
2496	}
2497	else // tlb miss
2498	{
2499	r_dcache_tlb_vaddr = m_dreq.addr;
2500	r_dcache_tlb_ins = false;
2501	r_dcache_fsm = DCACHE_TLB_MISS;
2502	}
2503	} // end DTLB activated
2504
2505	if ( valid_req ) // processor request is valid after TLB check
2506	{
2507	// physical address and cacheability registration
2508	r_dcache_p0_paddr = paddr;
2509	r_dcache_p0_cacheable = cacheable;
2510
2511	// READ or LL request
2512	// The read requests are taken only if the write pipe-line is empty.
2513	// If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle.
2514	// If speculative access is KO we just pay one extra cycle.
2515	// If dcache miss, we go to DCACHE_MISS_VICTIM state.
2516	// If uncacheable, we go to DCACHE_UNC_WAIT state.
2517	if ( ((m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL))
2518	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2519	{
2520	if ( cacheable ) // cacheable read
2521	{
2522	// if the speculative access is illegal, we pay an extra cycle
2523	if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK)
2524	!= (paddr & ~PAGE_K_MASK))
2525	{
2526	#ifdef INSTRUMENTATION
2527	m_cpt_dcache_spec_miss++;
2528	#endif
2529	}
2530	// if cache miss, try to get the missing line
2531	else if ( not cache_hit )
2532	{
2533	#ifdef INSTRUMENTATION
2534	m_cpt_dcache_miss++;
2535	#endif
2536	// blocked in IDLE state if previous cleanup not completed
2537	if ( not r_dcache_cleanup_req.read() )
2538	{
2539	r_dcache_vci_paddr = paddr;
2540	r_dcache_vci_miss_req = true;
2541	r_dcache_miss_type = PROC_MISS;
2542	r_dcache_fsm = DCACHE_MISS_VICTIM;
2543	}
2544	}
2545	// if cache hit return the data
2546	else
2547	{
2548	#ifdef INSTRUMENTATION
2549	m_cpt_data_read++;
2550	#endif
2551	m_drsp.valid = true;
2552	m_drsp.rdata = cache_rdata;
2553	#if DEBUG_DCACHE
2554	if ( m_debug_dcache_fsm )
2555	{
2556	std::cout << " <PROC.DCACHE_IDLE> HIT in dcache" << std::endl;
2557	}
2558	#endif
2559	}
2560	}
2561	else // uncacheable read
2562	{
2563	r_dcache_vci_paddr = paddr;
2564	r_dcache_vci_unc_be = m_dreq.be;
2565	r_dcache_vci_unc_req = true;
2566	r_dcache_fsm = DCACHE_UNC_WAIT;
2567	}
2568
2569	// makes reservation in case of LL
2570	if ( m_dreq.type == iss_t::DATA_LL )
2571	{
2572	r_dcache_ll_valid = true;
2573	r_dcache_ll_data = cache_rdata;
2574	r_dcache_ll_vaddr = m_dreq.addr;
2575	}
2576	r_dcache_p0_valid = false;
2577	} // end READ or LL
2578
2579	// WRITE request:
2580	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2581	// the processor and set the Dirty bit before handling the write request.
2582	// If we don't need to set the Dirty bit, we can acknowledge
2583	// the processor request, as the write arguments (including the
2584	// physical address) are registered in r_dcache_p0 registers:
2585	// We simply activate the P1 pipeline stage.
2586	else if ( m_dreq.type == iss_t::DATA_WRITE )
2587	{
2588	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2589	and not tlb_flags.d ) // Dirty bit must be set
2590	{
2591	// The PTE physical address is obtained from the nline value (dtlb),
2592	// and the word index (proper bits of the virtual address)
2593	if ( tlb_flags.b ) // PTE1
2594	{
2595	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2596	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2597	}
2598	else // PTE2
2599	{
2600	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2601	(paddr_t)((m_dreq.addr>>9) & 0x38);
2602	}
2603	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2604	r_dcache_p0_valid = false;
2605	}
2606	else // Write request accepted
2607	{
2608	#ifdef INSTRUMENTATION
2609	m_cpt_data_write++;
2610	#endif
2611	m_drsp.valid = true;
2612	m_drsp.rdata = 0;
2613	r_dcache_p0_valid = true;
2614	}
2615	} // end WRITE
2616
2617	// SC request:
2618	// The SC requests are taken only if the write pipe-line is empty.
2619	// - if there is no valid registered LL, we just return rdata = 1
2620	// (atomic access failed) and the SC transaction is completed.
2621	// - if a valid LL reservation (with the same address) is registered,
2622	// we test if a DIRTY bit update is required.
2623	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2624	// the processor and set the Dirty bit before handling the write request.
2625	// If we don't need to set the Dirty bit, we request a SC transaction
2626	// to CMD FSM and go to DCACHE_SC_WAIT state, that will return
2627	// the response to the processor.
2628	// We don't check a possible write hit in dcache, as the cache update
2629	// is done by the coherence transaction induced by the SC...
2630	else if ( ( m_dreq.type == iss_t::DATA_SC )
2631	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2632	{
2633	if ( (r_dcache_ll_vaddr.read() != m_dreq.addr)
2634	or not r_dcache_ll_valid.read() ) // no valid registered LL
2635	{
2636	#ifdef INSTRUMENTATION
2637	m_cpt_data_sc++;
2638	#endif
2639	m_drsp.valid = true;
2640	m_drsp.rdata = 1;
2641	r_dcache_ll_valid = false;
2642	}
2643	else // valid registered LL
2644	{
2645	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2646	and not tlb_flags.d ) // Dirty bit must be set
2647	{
2648	// The PTE physical address is obtained from the nline value (dtlb),
2649	// and the word index (proper bits of the virtual address)
2650	if ( tlb_flags.b ) // PTE1
2651	{
2652	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2653	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2654	}
2655	else // PTE2
2656	{
2657	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2658	(paddr_t)((m_dreq.addr>>9) & 0x38);
2659	}
2660	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2661	}
2662	else // SC request accepted
2663	{
2664	#ifdef INSTRUMENTATION
2665	m_cpt_data_sc++;
2666	#endif
2667
2668	r_dcache_vci_paddr = paddr;
2669	r_dcache_vci_sc_req = true;
2670	r_dcache_vci_sc_old = r_dcache_ll_data.read();
2671	r_dcache_vci_sc_new = m_dreq.wdata;
2672	r_dcache_ll_valid = false;
2673	r_dcache_fsm = DCACHE_SC_WAIT;
2674	}
2675	}
2676	r_dcache_p0_valid = false;
2677	} // end SC
2678	else
2679	{
2680	r_dcache_p0_valid = false;
2681	}
2682	} // end valid_req
2683	else
2684	{
2685	r_dcache_p0_valid = false;
2686	}
2687	} // end if read/write/ll/sc request
2688	} // end dreq.valid
2689	else
2690	{
2691	r_dcache_p0_valid = false;
2692	} // end P0 pipe stage
2693	break;
2694	}
2695	/////////////////////
2696	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2697	// Input arguments are:
2698	// - r_dcache_tlb_vaddr
2699	// - r_dcache_tlb_ins (true when itlb miss)
2700	// The sub-fsm access the dcache to find the missing TLB entry,
2701	// and activates the cache miss procedure in case of miss.
2702	// It bypass the first level page table access if possible.
2703	// It uses atomic access to update the R/L access bits
2704	// in the page table if required.
2705	// It directly updates the itlb or dtlb, and writes into the
2706	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2707	{
2708	uint32_t ptba = 0;
2709	bool bypass;
2710	paddr_t pte_paddr;
2711
2712	// evaluate bypass in order to skip first level page table access
2713	if ( r_dcache_tlb_ins.read() ) // itlb miss
2714	{
2715	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2716	}
2717	else // dtlb miss
2718	{
2719	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2720	}
2721
2722	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2723	{
2724	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2725	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2726	r_dcache_tlb_paddr = pte_paddr;
2727	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2728	}
2729	else // Try to read PTE2 in dcache
2730	{
2731	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2732	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2733	r_dcache_tlb_paddr = pte_paddr;
2734	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2735	}
2736
2737	#if DEBUG_DCACHE
2738	if ( m_debug_dcache_fsm )
2739	{
2740	if ( r_dcache_tlb_ins.read() )
2741	{
2742	std::cout << " <PROC.DCACHE_TLB_MISS> ITLB miss";
2743	}
2744	else
2745	{
2746	std::cout << " <PROC.DCACHE_TLB_MISS> DTLB miss";
2747	}
2748	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2749	<< " / BYPASS = " << bypass
2750	<< " / PTE_ADR = " << pte_paddr << std::endl;
2751	}
2752	#endif
2753
2754	break;
2755	}
2756	/////////////////////////
2757	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2758	{
2759	uint32_t entry;
2760	size_t way;
2761	size_t set;
2762	size_t word;
2763
2764	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2765	&entry,
2766	&way,
2767	&set,
2768	&word );
2769	#ifdef INSTRUMENTATION
2770	m_cpt_dcache_data_read++;
2771	m_cpt_dcache_dir_read++;
2772	#endif
2773	if ( hit ) // hit in dcache
2774	{
2775	if ( not (entry & PTE_V_MASK) ) // unmapped
2776	{
2777	if ( r_dcache_tlb_ins.read() )
2778	{
2779	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2780	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2781	r_icache_tlb_miss_req = false;
2782	r_icache_tlb_rsp_error = true;
2783	}
2784	else
2785	{
2786	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2787	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2788	m_drsp.valid = true;
2789	m_drsp.error = true;
2790	}
2791	r_dcache_fsm = DCACHE_IDLE;
2792
2793	#if DEBUG_DCACHE
2794	if ( m_debug_dcache_fsm )
2795	{
2796	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2797	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2798	<< std::dec << " / way = " << way
2799	<< std::dec << " / set = " << set
2800	<< std::dec << " / word = " << word
2801	<< std::hex << " / PTE1 = " << entry << std::endl;
2802	}
2803	#endif
2804
2805	}
2806	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2807	{
2808	// mark the cache line ac containing a PTD
2809	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2810
2811	// register bypass
2812	if ( r_dcache_tlb_ins.read() ) // itlb
2813	{
2814	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2815	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2816	r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2)));
2817	}
2818	else // dtlb
2819	{
2820	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2821	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2822	r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2));
2823	}
2824	r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2825	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2826	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2827
2828	#if DEBUG_DCACHE
2829	if ( m_debug_dcache_fsm )
2830	{
2831	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2832	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2833	<< std::dec << " / way = " << way
2834	<< std::dec << " / set = " << set
2835	<< std::dec << " / word = " << word
2836	<< std::hex << " / PTD = " << entry << std::endl;
2837	}
2838	#endif
2839	}
2840	else // PTE1 : we must update the TLB
2841	{
2842	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2843	r_dcache_tlb_pte_flags = entry;
2844	r_dcache_tlb_cache_way = way;
2845	r_dcache_tlb_cache_set = set;
2846	r_dcache_tlb_cache_word = word;
2847	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2848
2849	#if DEBUG_DCACHE
2850	if ( m_debug_dcache_fsm )
2851	{
2852	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2853	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2854	<< std::dec << " / way = " << way
2855	<< std::dec << " / set = " << set
2856	<< std::dec << " / word = " << word
2857	<< std::hex << " / PTE1 = " << entry << std::endl;
2858	}
2859	#endif
2860	}
2861	}
2862	else // we must load the missing cache line in dcache
2863	{
2864	r_dcache_vci_miss_req = true;
2865	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2866	r_dcache_miss_type = PTE1_MISS;
2867	r_dcache_fsm = DCACHE_MISS_VICTIM;
2868
2869	#if DEBUG_DCACHE
2870	if ( m_debug_dcache_fsm )
2871	{
2872	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:"
2873	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2874	}
2875	#endif
2876	}
2877	break;
2878	}
2879	////////////////////////////
2880	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2881	{
2882	size_t way;
2883	size_t set;
2884
2885	if ( r_dcache_tlb_ins.read() )
2886	{
2887	r_itlb.select( r_dcache_tlb_vaddr.read(),
2888	true, // PTE1
2889	&way,
2890	&set );
2891	#ifdef INSTRUMENTATION
2892	m_cpt_itlb_read++;
2893	#endif
2894	}
2895	else
2896	{
2897	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2898	true, // PTE1
2899	&way,
2900	&set );
2901	#ifdef INSTRUMENTATION
2902	m_cpt_dtlb_read++;
2903	#endif
2904	}
2905	r_dcache_tlb_way = way;
2906	r_dcache_tlb_set = set;
2907	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
2908
2909	#if DEBUG_DCACHE
2910	if ( m_debug_dcache_fsm )
2911	{
2912	if ( r_dcache_tlb_ins.read() )
2913	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
2914	else
2915	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
2916	std::cout << " way = " << std::dec << way
2917	<< " / set = " << set << std::endl;
2918	}
2919	#endif
2920	break;
2921	}
2922	//////////////////////////
2923	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
2924	// if L/R bit already set, exit the sub-fsm
2925	// if not, the page table must be updated
2926	{
2927	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
2928	uint32_t pte = r_dcache_tlb_pte_flags.read();
2929	bool updt = false;
2930	bool local = true;
2931
2932	// We should compute the access locality:
2933	// The PPN MSB bits define the destination cluster index.
2934	// The m_srcid_d MSB bits define the source cluster index.
2935	// The number of bits to compare depends on the number of clusters,
2936	// and can be obtained in the mapping table.
2937	// As long as this computation is not done, all access are local.
2938
2939	if ( local ) // local access
2940	{
2941	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
2942	{
2943	updt = true;
2944	r_dcache_vci_sc_old = pte;
2945	r_dcache_vci_sc_new = pte \| PTE_L_MASK;
2946	pte = pte \| PTE_L_MASK;
2947	}
2948	}
2949	else // remote access
2950	{
2951	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
2952	{
2953	updt = true;
2954	r_dcache_vci_sc_old = pte;
2955	r_dcache_vci_sc_new = pte \| PTE_R_MASK;
2956	pte = pte \| PTE_R_MASK;
2957	}
2958	}
2959
2960	// update TLB
2961	if ( r_dcache_tlb_ins.read() )
2962	{
2963	r_itlb.write( true, // 2M page
2964	pte,
2965	0, // argument unused for a PTE1
2966	r_dcache_tlb_vaddr.read(),
2967	r_dcache_tlb_way.read(),
2968	r_dcache_tlb_set.read(),
2969	nline );
2970	#ifdef INSTRUMENTATION
2971	m_cpt_itlb_write++;
2972	#endif
2973	}
2974	else
2975	{
2976	r_dtlb.write( true, // 2M page
2977	pte,
2978	0, // argument unused for a PTE1
2979	r_dcache_tlb_vaddr.read(),
2980	r_dcache_tlb_way.read(),
2981	r_dcache_tlb_set.read(),
2982	nline );
2983	#ifdef INSTRUMENTATION
2984	m_cpt_dtlb_write++;
2985	#endif
2986	}
2987	// next state
2988	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
2989	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
2990
2991	#if DEBUG_DCACHE
2992	if ( m_debug_dcache_fsm )
2993	{
2994	if ( r_dcache_tlb_ins.read() )
2995	{
2996	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
2997	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
2998	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
2999	r_itlb.printTrace();
3000	}
3001	else
3002	{
3003	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3004	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3005	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3006	r_dtlb.printTrace();
3007	}
3008
3009	}
3010	#endif
3011	break;
3012	}
3013	/////////////////////////
3014	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3015	{
3016	uint32_t pte_flags;
3017	uint32_t pte_ppn;
3018	size_t way;
3019	size_t set;
3020	size_t word;
3021
3022	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
3023	&pte_flags,
3024	&pte_ppn,
3025	&way,
3026	&set,
3027	&word );
3028	#ifdef INSTRUMENTATION
3029	m_cpt_dcache_data_read++;
3030	m_cpt_dcache_dir_read++;
3031	#endif
3032	if ( hit ) // request hits in dcache
3033	{
3034	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3035	{
3036	if ( r_dcache_tlb_ins.read() )
3037	{
3038	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3039	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3040	r_icache_tlb_miss_req = false;
3041	r_icache_tlb_rsp_error = true;
3042	}
3043	else
3044	{
3045	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3046	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3047	m_drsp.valid = true;
3048	m_drsp.error = true;
3049	}
3050	r_dcache_fsm = DCACHE_IDLE;
3051
3052	#if DEBUG_DCACHE
3053	if ( m_debug_dcache_fsm )
3054	{
3055	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3056	<< " PTE_FLAGS = " << std::hex << pte_flags
3057	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3058	}
3059	#endif
3060	}
3061	else // mapped : we must update the TLB
3062	{
3063	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3064	r_dcache_tlb_pte_flags = pte_flags;
3065	r_dcache_tlb_pte_ppn = pte_ppn;
3066	r_dcache_tlb_cache_way = way;
3067	r_dcache_tlb_cache_set = set;
3068	r_dcache_tlb_cache_word = word;
3069	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3070
3071	#if DEBUG_DCACHE
3072	if ( m_debug_dcache_fsm )
3073	{
3074	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:"
3075	<< " PTE_FLAGS = " << std::hex << pte_flags
3076	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3077	}
3078	#endif
3079	}
3080	}
3081	else // we must load the missing cache line in dcache
3082	{
3083	r_dcache_fsm = DCACHE_MISS_VICTIM;
3084	r_dcache_vci_miss_req = true;
3085	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3086	r_dcache_miss_type = PTE2_MISS;
3087
3088	#if DEBUG_DCACHE
3089	if ( m_debug_dcache_fsm )
3090	{
3091	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:"
3092	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3093	}
3094	#endif
3095	}
3096	break;
3097	}
3098	////////////////////////////
3099	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3100	{
3101	size_t way;
3102	size_t set;
3103
3104	if ( r_dcache_tlb_ins.read() )
3105	{
3106	r_itlb.select( r_dcache_tlb_vaddr.read(),
3107	false, // PTE2
3108	&way,
3109	&set );
3110	#ifdef INSTRUMENTATION
3111	m_cpt_itlb_read++;
3112	#endif
3113	}
3114	else
3115	{
3116	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3117	false, // PTE2
3118	&way,
3119	&set );
3120	#ifdef INSTRUMENTATION
3121	m_cpt_dtlb_read++;
3122	#endif
3123	}
3124
3125	#if DEBUG_DCACHE
3126	if ( m_debug_dcache_fsm )
3127	{
3128	if ( r_dcache_tlb_ins.read() )
3129	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3130	else
3131	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3132	std::cout << " way = " << std::dec << way
3133	<< " / set = " << set << std::endl;
3134	}
3135	#endif
3136	r_dcache_tlb_way = way;
3137	r_dcache_tlb_set = set;
3138	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3139	break;
3140	}
3141	//////////////////////////
3142	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3143	// if L/R bit already set, exit the sub-fsm
3144	// if not, the page table must be updated by an atomic access
3145	{
3146	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3147	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3148	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3149	bool updt = false;
3150	bool local = true;
3151
3152	// We should compute the access locality:
3153	// The PPN MSB bits define the destination cluster index.
3154	// The m_srcid_d MSB bits define the source cluster index.
3155	// The number of bits to compare depends on the number of clusters,
3156	// and can be obtained in the mapping table.
3157	// As long as this computation is not done, all access are local.
3158
3159	if ( local ) // local access
3160	{
3161	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3162	{
3163	updt = true;
3164	r_dcache_vci_sc_old = pte_flags;
3165	r_dcache_vci_sc_new = pte_flags \| PTE_L_MASK;
3166	pte_flags = pte_flags \| PTE_L_MASK;
3167	}
3168	}
3169	else // remote access
3170	{
3171	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3172	{
3173	updt = true;
3174	r_dcache_vci_sc_old = pte_flags;
3175	r_dcache_vci_sc_new = pte_flags \| PTE_R_MASK;
3176	pte_flags = pte_flags \| PTE_R_MASK;
3177	}
3178	}
3179
3180	// update TLB for a PTE2
3181	if ( r_dcache_tlb_ins.read() )
3182	{
3183	r_itlb.write( false, // 4K page
3184	pte_flags,
3185	pte_ppn,
3186	r_dcache_tlb_vaddr.read(),
3187	r_dcache_tlb_way.read(),
3188	r_dcache_tlb_set.read(),
3189	nline );
3190	#ifdef INSTRUMENTATION
3191	m_cpt_itlb_write++;
3192	#endif
3193	}
3194	else
3195	{
3196	r_dtlb.write( false, // 4K page
3197	pte_flags,
3198	pte_ppn,
3199	r_dcache_tlb_vaddr.read(),
3200	r_dcache_tlb_way.read(),
3201	r_dcache_tlb_set.read(),
3202	nline );
3203	#ifdef INSTRUMENTATION
3204	m_cpt_dtlb_write++;
3205	#endif
3206	}
3207
3208	#if DEBUG_DCACHE
3209	if ( m_debug_dcache_fsm )
3210	{
3211	if ( r_dcache_tlb_ins.read() )
3212	{
3213	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";
3214	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3215	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3216	r_itlb.printTrace();
3217	}
3218	else
3219	{
3220	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";
3221	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3222	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3223	r_dtlb.printTrace();
3224	}
3225	}
3226	#endif
3227	// next state
3228	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3229	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3230	break;
3231	}
3232	////////////////////////
3233	case DCACHE_TLB_LR_UPDT: // update the dcache after a tlb miss (L/R bit),
3234	// request a SC transaction to CMD FSM
3235	{
3236	#if DEBUG_DCACHE
3237	if ( m_debug_dcache_fsm )
3238	{
3239	std::cout << " <PROC.DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3240	}
3241	#endif
3242	r_dcache.write(r_dcache_tlb_cache_way.read(),
3243	r_dcache_tlb_cache_set.read(),
3244	r_dcache_tlb_cache_word.read(),
3245	r_dcache_tlb_pte_flags.read());
3246	#ifdef INSTRUMENTATION
3247	m_cpt_dcache_data_write++;
3248	#endif
3249	// r_dcache_vci_sc_old & r_dcache_vci_sc_new registers are already set
3250	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3251	r_dcache_vci_sc_req = true;
3252	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3253	break;
3254	}
3255	////////////////////////
3256	case DCACHE_TLB_LR_WAIT: // Waiting a response to SC transaction.
3257	// We consume the response in rsp FIFO,
3258	// and exit the sub-fsm, but we don't
3259	// analyse the response, because we don't
3260	// care if the L/R bit update is not done.
3261	// We must take the coherence requests because
3262	// there is a risk of dead-lock
3263
3264	{
3265	// external coherence request
3266	if ( r_tgt_dcache_req )
3267	{
3268	r_dcache_fsm = DCACHE_CC_CHECK;
3269	r_dcache_fsm_save = r_dcache_fsm;
3270	break;
3271	}
3272
3273	if ( r_vci_rsp_data_error.read() ) // bus error
3274	{
3275	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3276	std::cout << "This should not happen in this state" << std::endl;
3277	exit(0);
3278	}
3279	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3280	{
3281	#if DEBUG_DCACHE
3282	if ( m_debug_dcache_fsm )
3283	{
3284	std::cout << " <PROC.DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3285	}
3286	#endif
3287	vci_rsp_fifo_dcache_get = true;
3288	r_dcache_fsm = DCACHE_TLB_RETURN;
3289	}
3290	break;
3291	}
3292	///////////////////////
3293	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3294	{
3295	#if DEBUG_DCACHE
3296	if ( m_debug_dcache_fsm )
3297	{
3298	std::cout << " <PROC.DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3299	}
3300	#endif
3301	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3302	r_dcache_fsm = DCACHE_IDLE;
3303	break;
3304	}
3305	///////////////////////
3306	case DCACHE_XTN_SWITCH: // Both itlb and dtlb must be flushed
3307	{
3308	if ( not r_dcache_xtn_req.read() )
3309	{
3310	r_dtlb.flush();
3311	r_dcache_fsm = DCACHE_IDLE;
3312	m_drsp.valid = true;
3313	}
3314	break;
3315	}
3316	/////////////////////
3317	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3318	// The coherence request must be taken
3319	// as there is a risk of dead-lock
3320	{
3321	// external coherence request
3322	if ( r_tgt_dcache_req.read() )
3323	{
3324	r_dcache_fsm = DCACHE_CC_CHECK;
3325	r_dcache_fsm_save = DCACHE_XTN_SYNC;
3326	}
3327
3328	if ( r_wbuf.empty() )
3329	{
3330	m_drsp.valid = true;
3331	r_dcache_fsm = DCACHE_IDLE;
3332	}
3333	break;
3334	}
3335	////////////////////////
3336	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3337	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3338	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3339	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss...
3340	{
3341	// external coherence request
3342	if ( r_tgt_dcache_req )
3343	{
3344	r_dcache_fsm = DCACHE_CC_CHECK;
3345	r_dcache_fsm_save = r_dcache_fsm;
3346	break;
3347	}
3348
3349	// itlb miss request
3350	if ( r_icache_tlb_miss_req.read() )
3351	{
3352	r_dcache_tlb_ins = true;
3353	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3354	r_dcache_fsm = DCACHE_TLB_MISS;
3355	break;
3356	}
3357
3358	// test if XTN request to icache completed
3359	if ( not r_dcache_xtn_req.read() )
3360	{
3361	r_dcache_fsm = DCACHE_IDLE;
3362	m_drsp.valid = true;
3363	}
3364	break;
3365	}
3366	/////////////////////////
3367	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3368	// the r_dcache_flush counter as a slot counter.
3369	// We loop in this state until all slots have been visited.
3370	// A cleanup request is generated for each valid line
3371	// and we are blocked until the previous cleanup is completed
3372	// Finally, both the itlb and dtlb are reset, because
3373	// all TLB entries (including global entries) must be invalidated.
3374	{
3375	if ( not r_dcache_cleanup_req )
3376	{
3377	paddr_t nline;
3378	size_t way = r_dcache_flush_count.read()/m_icache_sets;
3379	size_t set = r_dcache_flush_count.read()%m_icache_sets;
3380
3381	bool cleanup_req = r_dcache.inval( way,
3382	set,
3383	&nline );
3384	if ( cleanup_req )
3385	{
3386	r_dcache_cleanup_req = true;
3387	r_dcache_cleanup_line = nline;
3388	}
3389
3390	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3391
3392	if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last slot
3393	{
3394	r_dtlb.reset();
3395	r_itlb.reset();
3396	for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++)
3397	{
3398	r_dcache_in_tlb[line] = false;
3399	r_dcache_contains_ptd[line] = false;
3400	}
3401	r_dcache_fsm = DCACHE_IDLE;
3402	m_drsp.valid = true;
3403	}
3404	}
3405	break;
3406	}
3407	/////////////////////////
3408	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3409	{
3410	r_dtlb.inval(r_dcache_p0_wdata.read());
3411	r_dcache_fsm = DCACHE_IDLE;
3412	m_drsp.valid = true;
3413	break;
3414	}
3415	////////////////////////////
3416	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3417	// requires 3 cycles: access tlb, read cache, inval cache
3418	// we compute the physical address in this state
3419	{
3420	paddr_t paddr;
3421	bool hit;
3422
3423	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3424	{
3425	#ifdef INSTRUMENTATION
3426	m_cpt_dtlb_read++;
3427	#endif
3428	hit = r_dtlb.translate( r_dcache_p0_wdata.read(),
3429	&paddr );
3430	}
3431	else // dtlb not activated
3432	{
3433	paddr = (paddr_t)r_dcache_p0_wdata.read();
3434	hit = true;
3435	}
3436
3437	if ( hit ) // tlb hit
3438	{
3439	r_dcache_p0_paddr = paddr;
3440	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3441	}
3442	else // tlb miss
3443	{
3444	#ifdef INSTRUMENTATION
3445	m_cpt_dtlb_miss++;
3446	#endif
3447	r_dcache_tlb_ins = false; // dtlb
3448	r_dcache_tlb_vaddr = r_dcache_p0_wdata.read();
3449	r_dcache_fsm = DCACHE_TLB_MISS;
3450	}
3451
3452	#if DEBUG_DCACHE
3453	if ( m_debug_dcache_fsm )
3454	{
3455	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3456	<< " / VADDR = " << r_dcache_p0_wdata.read()
3457	<< " / PADDR = " << paddr << std::endl;
3458	}
3459	#endif
3460
3461	break;
3462	}
3463	////////////////////////////
3464	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3465	// requires 2 cycles: read cache / inval cache
3466	// In this state we read dcache.
3467	{
3468	uint32_t data;
3469	size_t way;
3470	size_t set;
3471	size_t word;
3472	bool hit = r_dcache.read( r_dcache_p0_paddr.read(),
3473	&data,
3474	&way,
3475	&set,
3476	&word );
3477	#ifdef INSTRUMENTATION
3478	m_cpt_dcache_data_read++;
3479	m_cpt_dcache_dir_read++;
3480	#endif
3481	if ( hit ) // inval to be done
3482	{
3483	r_dcache_xtn_way = way;
3484	r_dcache_xtn_set = set;
3485	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3486	}
3487	else // miss : nothing to do
3488	{
3489	r_dcache_fsm = DCACHE_IDLE;
3490	m_drsp.valid = true;
3491	}
3492
3493	#if DEBUG_DCACHE
3494	if ( m_debug_dcache_fsm )
3495	{
3496	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3497	<< " / PADDR = " << r_dcache_p0_paddr.read() << std::dec
3498	<< " / HIT = " << hit
3499	<< " / SET = " << set
3500	<< " / WAY = " << way << std::endl;
3501	}
3502	#endif
3503	break;
3504	}
3505	////////////////////////////
3506	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3507	// Blocked if previous cleanup not completed
3508	// Test if itlb or dtlb inval is required
3509	{
3510	if ( not r_dcache_cleanup_req.read() )
3511	{
3512	paddr_t nline;
3513	size_t way = r_dcache_xtn_way.read();
3514	size_t set = r_dcache_xtn_set.read();
3515
3516	r_dcache.inval( way,
3517	set,
3518	&nline );
3519
3520	// request cleanup
3521	r_dcache_cleanup_req = true;
3522	r_dcache_cleanup_line = nline;
3523
3524	// possible itlb & dtlb invalidate
3525	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3526	{
3527	r_dcache_tlb_inval_line = nline;
3528	r_dcache_tlb_inval_count = 0;
3529	r_dcache_fsm_save = DCACHE_XTN_DC_INVAL_END;
3530	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3531	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3532	}
3533	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3534	{
3535	r_itlb.reset();
3536	r_dtlb.reset();
3537	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3538	r_dcache_fsm = DCACHE_IDLE;
3539	m_drsp.valid = true;
3540	}
3541	else
3542	{
3543	r_dcache_fsm = DCACHE_IDLE;
3544	m_drsp.valid = true;
3545	}
3546
3547	#if DEBUG_DCACHE
3548	if ( m_debug_dcache_fsm )
3549	{
3550	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3551	<< " / NLINE = " << nline << std::endl;
3552	}
3553	#endif
3554	}
3555	break;
3556	}
3557	//////////////////////////////
3558	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3559	{
3560	r_dcache_fsm = DCACHE_IDLE;
3561	m_drsp.valid = true;
3562	break;
3563	}
3564	////////////////////////
3565	case DCACHE_MISS_VICTIM: // Selects a victim line
3566	// Set the r_dcache_cleanup_req flip-flop
3567	// when the selected slot is not empty
3568	{
3569	bool valid;
3570	size_t way;
3571	size_t set;
3572	paddr_t victim;
3573
3574	valid = r_dcache.victim_select( r_dcache_vci_paddr.read(),
3575	&victim,
3576	&way,
3577	&set );
3578	r_dcache_miss_way = way;
3579	r_dcache_miss_set = set;
3580
3581	if ( valid )
3582	{
3583	r_dcache_cleanup_req = true;
3584	r_dcache_cleanup_line = victim;
3585	r_dcache_fsm = DCACHE_MISS_INVAL;
3586	}
3587	else
3588	{
3589	r_dcache_fsm = DCACHE_MISS_WAIT;
3590	}
3591
3592	#if DEBUG_DCACHE
3593	if ( m_debug_dcache_fsm )
3594	{
3595	std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:"
3596	<< " / way = " << way
3597	<< " / set = " << set
3598	<< " / valid = " << valid
3599	<< " / line = " << std::hex << victim << std::endl;
3600	}
3601	#endif
3602	break;
3603	}
3604	///////////////////////
3605	case DCACHE_MISS_INVAL: // invalidate the victim line
3606	// and possibly request itlb or dtlb invalidate
3607	{
3608	paddr_t nline;
3609	size_t way = r_dcache_miss_way.read();
3610	size_t set = r_dcache_miss_set.read();
3611	bool hit;
3612
3613	hit = r_dcache.inval( way,
3614	set,
3615	&nline );
3616	assert(hit && "selected way/set line should be in dcache");
3617
3618	#if DEBUG_DCACHE
3619	if ( m_debug_dcache_fsm )
3620	{
3621	std::cout << " <PROC.DCACHE_MISS_INVAL> inval line:"
3622	<< " / way = " << way
3623	<< " / set = " << set
3624	<< " / nline = " << std::hex << nline << std::endl;
3625	}
3626	#endif
3627	// if selective itlb & dtlb invalidate are required
3628	// the miss response is not handled before invalidate completed
3629	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3630	{
3631	r_dcache_tlb_inval_line = nline;
3632	r_dcache_tlb_inval_count = 0;
3633	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3634	r_dcache_fsm_save = DCACHE_MISS_WAIT;
3635	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3636	}
3637	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3638	{
3639	r_itlb.reset();
3640	r_dtlb.reset();
3641	r_dcache_fsm = DCACHE_MISS_WAIT;
3642	}
3643	else
3644	{
3645	r_dcache_fsm = DCACHE_MISS_WAIT;
3646	}
3647	break;
3648	}
3649	//////////////////////
3650	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3651	// This state is in charge of error signaling
3652	// There is 5 types of error depending on the requester
3653	{
3654	// external coherence request
3655	if ( r_tgt_dcache_req )
3656	{
3657	r_dcache_fsm = DCACHE_CC_CHECK;
3658	r_dcache_fsm_save = r_dcache_fsm;
3659	break;
3660	}
3661
3662	if ( r_vci_rsp_data_error.read() ) // bus error
3663	{
3664	switch ( r_dcache_miss_type.read() )
3665	{
3666	case PROC_MISS:
3667	{
3668	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3669	r_mmu_dbvar = r_dcache_p0_vaddr.read();
3670	m_drsp.valid = true;
3671	m_drsp.error = true;
3672	r_dcache_fsm = DCACHE_IDLE;
3673	break;
3674	}
3675	case PTE1_MISS:
3676	{
3677	if ( r_dcache_tlb_ins.read() )
3678	{
3679	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3680	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3681	r_icache_tlb_miss_req = false;
3682	r_icache_tlb_rsp_error = true;
3683	}
3684	else
3685	{
3686	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3687	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3688	m_drsp.valid = true;
3689	m_drsp.error = true;
3690	}
3691	r_dcache_fsm = DCACHE_IDLE;
3692	break;
3693	}
3694	case PTE2_MISS:
3695	{
3696	if ( r_dcache_tlb_ins.read() )
3697	{
3698	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3699	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3700	r_icache_tlb_miss_req = false;
3701	r_icache_tlb_rsp_error = true;
3702	}
3703	else
3704	{
3705	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3706	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3707	m_drsp.valid = true;
3708	m_drsp.error = true;
3709	}
3710	r_dcache_fsm = DCACHE_IDLE;
3711	break;
3712	}
3713	} // end switch type
3714	r_vci_rsp_data_error = false;
3715	}
3716	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3717	{
3718	r_dcache_miss_word = 0;
3719	r_dcache_fsm = DCACHE_MISS_UPDT;
3720	}
3721	break;
3722	}
3723	//////////////////////
3724	case DCACHE_MISS_UPDT: // update the dcache (one word per cycle)
3725	// returns the response depending on the miss type
3726	{
3727	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3728	{
3729	if ( r_dcache_miss_inval.read() ) // Matching coherence request
3730	// pop the FIFO, without cache update
3731	// send a cleanup for the missing line
3732	// if the previous cleanup is completed
3733	{
3734	if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last
3735	{
3736	vci_rsp_fifo_dcache_get = true;
3737	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3738	}
3739	else // last word
3740	{
3741	if ( not r_dcache_cleanup_req.read() ) // no pending cleanup
3742	{
3743	vci_rsp_fifo_dcache_get = true;
3744	r_dcache_cleanup_req = true;
3745	r_dcache_cleanup_line = r_dcache_vci_paddr.read() >>
3746	(uint32_log2(m_dcache_words)+2);
3747	r_dcache_miss_inval = false;
3748	r_dcache_fsm = DCACHE_IDLE;
3749	}
3750	}
3751	}
3752	else // No matching coherence request
3753	// pop the FIFO and update the cache
3754	// update the directory at the last word
3755	{
3756	size_t way = r_dcache_miss_way.read();
3757	size_t set = r_dcache_miss_set.read();
3758	size_t word = r_dcache_miss_word.read();
3759
3760	#ifdef INSTRUMENTATION
3761	m_cpt_dcache_data_write++;
3762	#endif
3763	r_dcache.write( way,
3764	set,
3765	word,
3766	r_vci_rsp_fifo_dcache.read());
3767
3768	vci_rsp_fifo_dcache_get = true;
3769	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3770
3771	// if last word, update directory, set in_tlb & contains_ptd bits
3772	if ( r_dcache_miss_word.read() == (m_dcache_words - 1) )
3773	{
3774
3775	#ifdef INSTRUMENTATION
3776	m_cpt_dcache_dir_write++;
3777	#endif
3778	r_dcache.victim_update_tag( r_dcache_vci_paddr.read(),
3779	r_dcache_miss_way.read(),
3780	r_dcache_miss_set.read() );
3781
3782	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3783	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3784
3785	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3786	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3787	else r_dcache_fsm = DCACHE_IDLE;
3788	}
3789	}
3790
3791	#if DEBUG_DCACHE
3792	if ( m_debug_dcache_fsm )
3793	{
3794	if ( r_dcache_miss_inval.read() )
3795	{
3796	if ( r_dcache_miss_word.read() < m_dcache_words-1 )
3797	{
3798	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3799	<< " pop the FIFO, don't update the cache" << std::endl;
3800	}
3801	else
3802	{
3803	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3804	<< " last word : send a cleanup request " << std::endl;
3805	}
3806	}
3807	else
3808	{
3809	std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:"
3810	<< " address = " << r_dcache_vci_paddr.read()
3811	<< " / data = " << r_vci_rsp_fifo_dcache.read()
3812	<< " / way = " << r_dcache_miss_way.read()
3813	<< " / set = " << r_dcache_miss_set.read()
3814	<< " / word = " << r_dcache_miss_word.read() << std::endl;
3815	}
3816	}
3817	#endif
3818
3819	} // end if rok
3820	break;
3821	}
3822	/////////////////////
3823	case DCACHE_UNC_WAIT:
3824	{
3825	// external coherence request
3826	if ( r_tgt_dcache_req.read() )
3827	{
3828	r_dcache_fsm = DCACHE_CC_CHECK;
3829	r_dcache_fsm_save = r_dcache_fsm;
3830	break;
3831	}
3832
3833	if ( r_vci_rsp_data_error.read() ) // bus error
3834	{
3835	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3836	r_mmu_dbvar = m_dreq.addr;
3837	r_vci_rsp_data_error = false;
3838	m_drsp.error = true;
3839	m_drsp.valid = true;
3840	r_dcache_fsm = DCACHE_IDLE;
3841	break;
3842	}
3843	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
3844	{
3845	vci_rsp_fifo_dcache_get = true;
3846	r_dcache_fsm = DCACHE_IDLE;
3847	// we acknowledge the processor request if it has not been modified
3848	if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) )
3849	{
3850	m_drsp.valid = true;
3851	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3852	}
3853	}
3854	break;
3855	}
3856	////////////////////
3857	case DCACHE_SC_WAIT: // waiting VCI response after a processor SC request
3858	{
3859	// external coherence request
3860	if ( r_tgt_dcache_req.read() )
3861	{
3862	r_dcache_fsm = DCACHE_CC_CHECK;
3863	r_dcache_fsm_save = r_dcache_fsm;
3864	break;
3865	}
3866
3867	if ( r_vci_rsp_data_error.read() ) // bus error
3868	{
3869	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3870	r_mmu_dbvar = m_dreq.addr;
3871	r_vci_rsp_data_error = false;
3872	m_drsp.error = true;
3873	m_drsp.valid = true;
3874	r_dcache_fsm = DCACHE_IDLE;
3875	break;
3876	}
3877	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3878	{
3879	vci_rsp_fifo_dcache_get = true;
3880	m_drsp.valid = true;
3881	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3882	r_dcache_fsm = DCACHE_IDLE;
3883	}
3884	break;
3885	}
3886	//////////////////////////
3887	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
3888	// before handling a processor WRITE or SC request
3889	// Input argument is r_dcache_dirty_paddr
3890	// In this first state, we get PTE value in dcache
3891	// and post a SC request to CMD FSM
3892	{
3893	// get PTE in dcache
3894	uint32_t pte;
3895	size_t way;
3896	size_t set;
3897	size_t word; // unused
3898	bool hit = r_dcache.read( r_dcache_dirty_paddr.read(),
3899	&pte,
3900	&way,
3901	&set,
3902	&word );
3903	#ifdef INSTRUMENTATION
3904	m_cpt_dcache_data_read++;
3905	m_cpt_dcache_dir_read++;
3906	#endif
3907	assert( hit and "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
3908
3909	// request sc transaction to CMD_FSM
3910	r_dcache_dirty_way = way;
3911	r_dcache_dirty_set = set;
3912	r_dcache_vci_sc_req = true;
3913	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
3914	r_dcache_vci_sc_old = pte;
3915	r_dcache_vci_sc_new = pte \| PTE_D_MASK;
3916	r_dcache_fsm = DCACHE_DIRTY_SC_WAIT;
3917
3918	#if DEBUG_DCACHE
3919	if ( m_debug_dcache_fsm )
3920	{
3921	std::cout << " <PROC.DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex
3922	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
3923	<< " / PTE_VALUE = " << pte << std::dec
3924	<< " / CACHE_SET = " << set
3925	<< " / CACHE_WAY = " << way << std::endl;
3926	}
3927	#endif
3928	break;
3929	}
3930	//////////////////////////
3931	case DCACHE_DIRTY_SC_WAIT: // wait completion of SC for PTE Dirty bit
3932	// If the PTE update is a success, return to IDLE state.
3933	// If the PTE update is a failure, invalidate the cache line
3934	// in DCACHE and invalidate the matching TLB entries.
3935	{
3936	// external coherence request
3937	if ( r_tgt_dcache_req )
3938	{
3939	r_dcache_fsm = DCACHE_CC_CHECK;
3940	r_dcache_fsm_save = r_dcache_fsm;
3941	break;
3942	}
3943
3944	if ( r_vci_rsp_data_error.read() ) // bus error
3945	{
3946	std::cout << "BUS ERROR in DCACHE_DIRTY_SC_WAIT state" << std::endl;
3947	std::cout << "This should not happen in this state" << std::endl;
3948	exit(0);
3949	}
3950	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3951	{
3952	vci_rsp_fifo_dcache_get = true;
3953	if ( r_vci_rsp_fifo_dcache.read() == 0 ) // exit if dirty bit update atomic
3954	{
3955	r_dcache_fsm = DCACHE_IDLE;
3956
3957	#if DEBUG_DCACHE
3958	if ( m_debug_dcache_fsm )
3959	{
3960	std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set"
3961	<< std::endl;
3962	}
3963	#endif
3964	}
3965	else // invalidate the cache line and TLBs
3966	{
3967	paddr_t nline;
3968	size_t way = r_dcache_dirty_way.read();
3969	size_t set = r_dcache_dirty_set.read();
3970
3971	r_dcache.inval( r_dcache_dirty_way.read(),
3972	r_dcache_dirty_set.read(),
3973	&nline );
3974
3975	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // contains PTE
3976	{
3977	r_dcache_tlb_inval_line = nline;
3978	r_dcache_tlb_inval_count = 0;
3979	r_dcache_fsm_save = DCACHE_IDLE;
3980	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3981	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3982	}
3983	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // contains PTD
3984	{
3985	r_itlb.reset();
3986	r_dtlb.reset();
3987	r_dcache_fsm = DCACHE_IDLE;
3988	}
3989	#if DEBUG_DCACHE
3990	if ( m_debug_dcache_fsm )
3991	{
3992	std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs"
3993	<< std::endl;
3994	}
3995	#endif
3996	}
3997	}
3998	break;
3999	}
4000	/////////////////////
4001	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4002	// handling coherence requests.
4003	// If there is a matching pending miss on the modified cache
4004	// line this is signaled in the r_dcache_miss inval flip-flop.
4005	// If the updated (or invalidated) cache line has copies in TLBs
4006	// these TLB copies are invalidated.
4007	// The return state is defined in r_dcache_fsm_save
4008	{
4009	paddr_t paddr = r_tgt_paddr.read();
4010	paddr_t mask = ~((m_dcache_words<<2)-1);
4011
4012
4013	if( (r_dcache_fsm_save == DCACHE_MISS_WAIT) and
4014	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss
4015	{
4016	r_dcache_miss_inval = true; // signaling the match
4017	r_tgt_dcache_req = false; // coherence request completed
4018	r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update
4019	r_dcache_fsm = r_dcache_fsm_save;
4020
4021	#if DEBUG_DCACHE
4022	if ( m_debug_dcache_fsm )
4023	{
4024	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4025	<< " address = " << std::hex << paddr << std::endl;
4026	}
4027	#endif
4028
4029	}
4030	else // no match
4031	{
4032	uint32_t rdata;
4033	size_t way;
4034	size_t set;
4035	size_t word;
4036
4037	bool hit = r_dcache.read(paddr,
4038	&rdata, // unused
4039	&way,
4040	&set,
4041	&word); // unused
4042	#ifdef INSTRUMENTATION
4043	m_cpt_dcache_data_read++;
4044	m_cpt_dcache_dir_read++;
4045	#endif
4046	r_dcache_cc_way = way;
4047	r_dcache_cc_set = set;
4048
4049	if ( hit and r_tgt_update.read() ) // hit update
4050	{
4051	r_dcache_fsm = DCACHE_CC_UPDT;
4052	r_dcache_cc_word = r_tgt_word_min.read();
4053	}
4054	else if ( hit and not r_tgt_update.read() ) // hit inval
4055	{
4056	r_dcache_fsm = DCACHE_CC_INVAL;
4057	}
4058	else // miss can happen
4059	{
4060	r_tgt_dcache_req = false;
4061	r_tgt_dcache_rsp = r_tgt_update.read();
4062	r_dcache_fsm = r_dcache_fsm_save.read();
4063	}
4064
4065	#if DEBUG_DCACHE
4066	if ( m_debug_dcache_fsm )
4067	{
4068
4069	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request received :"
4070	<< " address = " << std::hex << paddr << std::dec;
4071	if ( hit )
4072	{
4073	std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl;
4074	}
4075	else
4076	{
4077	std::cout << " / MISS" << std::endl;
4078	}
4079	}
4080	#endif
4081
4082	}
4083	break;
4084	}
4085	/////////////////////
4086	case DCACHE_CC_INVAL: // invalidate one cache line
4087	// and test possible copies in TLBs
4088	{
4089	paddr_t nline;
4090	size_t way = r_dcache_cc_way.read();
4091	size_t set = r_dcache_cc_set.read();
4092
4093	r_dcache.inval( way,
4094	set,
4095	&nline );
4096
4097	// possible itlb & dtlb invalidate
4098	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective inval
4099	{
4100	r_dcache_tlb_inval_line = nline;
4101	r_dcache_tlb_inval_count = 0;
4102	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4103	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4104	}
4105	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // flush
4106	{
4107	r_itlb.reset();
4108	r_dtlb.reset();
4109	r_tgt_dcache_rsp = true;
4110	r_tgt_dcache_req = false;
4111	r_dcache_fsm = r_dcache_fsm_save.read();
4112	}
4113	else // no inval
4114	{
4115	r_tgt_dcache_rsp = true;
4116	r_tgt_dcache_req = false;
4117	r_dcache_fsm = r_dcache_fsm_save.read();
4118	}
4119
4120	#if DEBUG_DCACHE
4121	if ( m_debug_dcache_fsm )
4122	{
4123	std::cout << " <PROC.DCACHE_CC_INVAL> Invalidate cache line" << std::dec
4124	<< " / WAY = " << way
4125	<< " / SET = " << set << std::endl;
4126	}
4127	#endif
4128
4129	break;
4130	}
4131	///////////////////
4132	case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
4133	// and test possible copies in TLBs
4134	{
4135	size_t word = r_dcache_cc_word.read();
4136	size_t way = r_dcache_cc_way.read();
4137	size_t set = r_dcache_cc_set.read();
4138	paddr_t nline = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
4139
4140	r_dcache.write( way,
4141	set,
4142	word,
4143	r_tgt_buf[word],
4144	r_tgt_be[word] );
4145	#ifdef INSTRUMENTATION
4146	m_cpt_dcache_data_write++;
4147	#endif
4148	r_dcache_cc_word = word + 1;
4149
4150	if ( word == r_tgt_word_max.read() ) // last word
4151	{
4152	// possible itlb & dtlb invalidate
4153	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective inval
4154	{
4155	r_dcache_tlb_inval_line = nline;
4156	r_dcache_tlb_inval_count = 0;
4157	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4158	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4159	}
4160	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // flush
4161	{
4162	r_itlb.reset();
4163	r_dtlb.reset();
4164	r_tgt_dcache_rsp = true;
4165	r_tgt_dcache_req = false;
4166	r_dcache_fsm = r_dcache_fsm_save.read();
4167	}
4168	else // no inval
4169	{
4170	r_tgt_dcache_rsp = true;
4171	r_tgt_dcache_req = false;
4172	r_dcache_fsm = r_dcache_fsm_save.read();
4173	}
4174	}
4175
4176	#if DEBUG_DCACHE
4177	if ( m_debug_dcache_fsm )
4178	{
4179	std::cout << " <PROC.DCACHE_CC_UPDT> Update one word" << std::dec
4180	<< " / WAY = " << way
4181	<< " / SET = " << set
4182	<< " / WORD = " << word
4183	<< " / VALUE = " << std::hex << r_tgt_buf[word] << std::endl;
4184	}
4185	#endif
4186
4187	break;
4188	}
4189	///////////////////////////
4190	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all TLB entries for both ITLB & DTLB
4191	// It makes the assumption that (m_itlb_sets == m_dtlb_sets)
4192	// and (m_itlb_ways == m_dtlb_ways)
4193	// We enter this state when a DCACHE line is modified,
4194	// and there is a copy in itlb or dtlb.
4195	// It can be caused by:
4196	// - a coherence inval or updt transaction,
4197	// - a line inval caused by a cache miss
4198	// - a processor XTN inval request,
4199	// - a WRITE hit,
4200	// - a Dirty bit update failure
4201	// Input arguments are:
4202	// - r_dcache_tlb_inval_line
4203	// - r_dcache_tlb_inval_count
4204	// - r_dcache_fsm_save
4205	{
4206	paddr_t line = r_dcache_tlb_inval_line.read(); // nline
4207	size_t way = r_dcache_tlb_inval_count.read()/m_itlb_sets; // way
4208	size_t set = r_dcache_tlb_inval_count.read()%m_itlb_sets; // set
4209	bool ok;
4210
4211	ok = r_itlb.inval( line,
4212	way,
4213	set );
4214	#if DEBUG_DCACHE
4215	if ( m_debug_dcache_fsm and ok )
4216	{
4217	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4218	<< " line = " << line << std::dec
4219	<< " / set = " << set
4220	<< " / way = " << way << std::endl;
4221	r_itlb.printTrace();
4222	}
4223	#endif
4224	ok = r_dtlb.inval( line,
4225	way,
4226	set );
4227	#if DEBUG_DCACHE
4228	if ( m_debug_dcache_fsm and ok )
4229	{
4230	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4231	<< " line = " << line << std::dec
4232	<< " / set = " << set
4233	<< " / way = " << way << std::endl;
4234	r_dtlb.printTrace();
4235	}
4236	#endif
4237
4238	// return to the calling state when TLB inval completed
4239	if ( r_dcache_tlb_inval_count.read() == (m_dtlb_sets*m_dtlb_ways-1) )
4240	{
4241	if ( r_tgt_dcache_req.read() ) // It's a coherence request
4242	{
4243	r_tgt_dcache_rsp = true;
4244	r_tgt_dcache_req = false;
4245	}
4246	r_dcache_fsm = r_dcache_fsm_save.read();
4247	}
4248	r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1;
4249	}
4250	} // end switch r_dcache_fsm
4251
4252	///////////////// wbuf update //////////////////////////////////////////////////////
4253	r_wbuf.update();
4254
4255	//////////////// test processor frozen /////////////////////////////////////////////
4256	// The simulation exit if the number of consecutive frozen cycles
4257	// is larger than the m_max_frozen_cycles (constructor parameter)
4258	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4259	{
4260	m_cpt_frz_cycles++; // used for instrumentation
4261	m_cpt_stop_simulation++; // used for debug
4262	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4263	{
4264	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4265	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4266	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4267	<< std::endl;
4268	exit(1);
4269	}
4270	}
4271	else
4272	{
4273	m_cpt_stop_simulation = 0;
4274	}
4275
4276	/////////// execute one iss cycle /////////////////////////////////
4277	{
4278	uint32_t it = 0;
4279	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4280	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4281	}
4282
4283	////////////////////////////////////////////////////////////////////////////
4284	// The VCI_CMD FSM controls the following ressources:
4285	// - r_vci_cmd_fsm
4286	// - r_vci_cmd_min
4287	// - r_vci_cmd_max
4288	// - r_vci_cmd_cpt
4289	// - r_vci_cmd_imiss_prio
4290	// - wbuf (reset)
4291	// - r_icache_miss_req (reset)
4292	// - r_icache_unc_req (reset)
4293	// - r_dcache_vci_miss_req (reset)
4294	// - r_dcache_vci_unc_req (reset)
4295	// - r_dcache_vci_sc_req (reset)
4296	//
4297	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4298	// There is 6 request types, with the following priorities :
4299	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4300	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4301	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4302	// 4 - Instruction Uncachable : r_icache_unc_req
4303	// 5 - Data Write : r_wbuf.rok()
4304	// 6 - Data Store Conditionnal: r_dcache_vci_sc_req
4305	//
4306	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4307	// and the VCI_RSP_FSM are fully desynchronized.
4308	//
4309	// VCI formats:
4310	// According to the VCI advanced specification, all read requests packets
4311	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4312	// are one word packets.
4313	// For write burst packets, all words are in the same cache line,
4314	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4315	// The sc command packet implements actually a compare-and-swap mechanism
4316	// and the packet contains two flits.
4317	////////////////////////////////////////////////////////////////////////////////////
4318
4319	switch ( r_vci_cmd_fsm.read() )
4320	{
4321	//////////////
4322	case CMD_IDLE:
4323	{
4324	// r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access
4325	// to check a possible pending write on the same cache line.
4326	// As there is only one possible access per cycle to write buffer, we implement
4327	// a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop.
4328
4329	size_t wbuf_min;
4330	size_t wbuf_max;
4331
4332	bool dcache_miss_req = r_dcache_vci_miss_req.read()
4333	and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4334	bool icache_miss_req = r_icache_miss_req.read()
4335	and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );
4336
4337	// 1 - Data Read Miss
4338	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4339	{
4340	r_vci_cmd_fsm = CMD_DATA_MISS;
4341	r_dcache_vci_miss_req = false;
4342	r_vci_cmd_imiss_prio = true;
4343	// m_cpt_dmiss_transaction++;
4344	}
4345	// 2 - Data Read Uncachable
4346	else if ( r_dcache_vci_unc_req.read() )
4347	{
4348	r_vci_cmd_fsm = CMD_DATA_UNC;
4349	r_dcache_vci_unc_req = false;
4350	// m_cpt_dunc_transaction++;
4351	}
4352	// 3 - Instruction Miss
4353	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4354	{
4355	r_vci_cmd_fsm = CMD_INS_MISS;
4356	r_icache_miss_req = false;
4357	r_vci_cmd_imiss_prio = false;
4358	// m_cpt_imiss_transaction++;
4359	}
4360	// 4 - Instruction Uncachable
4361	else if ( r_icache_unc_req.read() )
4362	{
4363	r_vci_cmd_fsm = CMD_INS_UNC;
4364	r_icache_unc_req = false;
4365	// m_cpt_iunc_transaction++;
4366	}
4367	// 5 - Data Write
4368	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4369	{
4370	r_vci_cmd_fsm = CMD_DATA_WRITE;
4371	r_vci_cmd_cpt = wbuf_min;
4372	r_vci_cmd_min = wbuf_min;
4373	r_vci_cmd_max = wbuf_max;
4374	// m_cpt_write_transaction++;
4375	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4376	}
4377	// 6 - Data Store Conditionnal
4378	else if ( r_dcache_vci_sc_req.read() )
4379	{
4380	r_vci_cmd_fsm = CMD_DATA_SC;
4381	r_dcache_vci_sc_req = false;
4382	r_vci_cmd_cpt = 0;
4383	// m_cpt_sc_transaction++;
4384	}
4385	break;
4386	}
4387	////////////////////
4388	case CMD_DATA_WRITE:
4389	{
4390	if ( p_vci_ini_d.cmdack.read() )
4391	{
4392	// m_conso_wbuf_read++;
4393	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4394	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4395	{
4396	r_vci_cmd_fsm = CMD_IDLE ;
4397	r_wbuf.sent() ;
4398	}
4399	}
4400	break;
4401	}
4402	/////////////////
4403	case CMD_DATA_SC:
4404	{
4405	// The SC VCI command contains two flits
4406	if ( p_vci_ini_d.cmdack.read() )
4407	{
4408	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4409	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4410	}
4411	break;
4412	}
4413	//////////////////
4414	case CMD_INS_MISS:
4415	case CMD_INS_UNC:
4416	case CMD_DATA_MISS:
4417	case CMD_DATA_UNC:
4418	{
4419	// all read VCI commands contain one single flit
4420	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4421	break;
4422	}
4423
4424	} // end switch r_vci_cmd_fsm
4425
4426	//////////////////////////////////////////////////////////////////////////
4427	// The VCI_RSP FSM controls the following ressources:
4428	// - r_vci_rsp_fsm:
4429	// - r_vci_rsp_fifo_icache (push)
4430	// - r_vci_rsp_fifo_dcache (push)
4431	// - r_vci_rsp_data_error (set)
4432	// - r_vci_rsp_ins_error (set)
4433	// - r_vci_rsp_cpt
4434	//
4435	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4436	// simultaneous VCI transactions, this FSM uses the VCI TRDID field
4437	// to identify the transactions.
4438	//
4439	// VCI vormat:
4440	// This component checks the response packet length and accepts only
4441	// single word packets for write response packets.
4442	//
4443	// Error handling:
4444	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
4445	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
4446	// flip_flop and the error is signaled by the DCACHE FSM.
4447	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
4448	// flip_flop and the error is signaled by the ICACHE FSM.
4449	// In case of Cleanup Error, the simulation stops with an error message...
4450	//////////////////////////////////////////////////////////////////////////
4451
4452	switch ( r_vci_rsp_fsm.read() )
4453	{
4454	//////////////
4455	case RSP_IDLE:
4456	{
4457	if ( p_vci_ini_d.rspval.read() )
4458	{
4459	r_vci_rsp_cpt = 0;
4460
4461	if ( (p_vci_ini_d.rtrdid.read() >> (vci_param::T-1)) != 0 ) // Write transaction
4462	{
4463	r_vci_rsp_fsm = RSP_DATA_WRITE;
4464	}
4465	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS )
4466	{
4467	r_vci_rsp_fsm = RSP_INS_MISS;
4468	}
4469	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC )
4470	{
4471	r_vci_rsp_fsm = RSP_INS_UNC;
4472	}
4473	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS )
4474	{
4475	r_vci_rsp_fsm = RSP_DATA_MISS;
4476	}
4477	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC )
4478	{
4479	r_vci_rsp_fsm = RSP_DATA_UNC;
4480	}
4481	else
4482	{
4483	assert(false and "Unexpected VCI response");
4484	}
4485	}
4486	break;
4487	}
4488	//////////////////
4489	case RSP_INS_MISS:
4490	{
4491	if ( p_vci_ini_d.rspval.read() )
4492	{
4493	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4494	{
4495	r_vci_rsp_ins_error = true;
4496	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4497	}
4498	else // no error reported
4499	{
4500	if ( r_vci_rsp_fifo_icache.wok() )
4501	{
4502	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
4503	"The VCI response packet for instruction miss is too long" );
4504
4505	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4506	vci_rsp_fifo_icache_put = true,
4507	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4508	if ( p_vci_ini_d.reop.read() )
4509	{
4510	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
4511	"The VCI response packet for instruction miss is too short");
4512
4513	r_vci_rsp_fsm = RSP_IDLE;
4514	}
4515	}
4516	}
4517	}
4518	break;
4519	}
4520	/////////////////
4521	case RSP_INS_UNC:
4522	{
4523	if (p_vci_ini_d.rspval.read() )
4524	{
4525	assert( p_vci_ini_d.reop.read() and
4526	"illegal VCI response packet for uncachable instruction");
4527
4528	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4529	{
4530	r_vci_rsp_ins_error = true;
4531	r_vci_rsp_fsm = RSP_IDLE;
4532	}
4533	else // no error reported
4534	{
4535	if ( r_vci_rsp_fifo_icache.wok())
4536	{
4537	vci_rsp_fifo_icache_put = true;
4538	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4539	r_vci_rsp_fsm = RSP_IDLE;
4540	}
4541	}
4542	}
4543	break;
4544	}
4545	///////////////////
4546	case RSP_DATA_MISS:
4547	{
4548	if ( p_vci_ini_d.rspval.read() )
4549	{
4550	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4551	{
4552	r_vci_rsp_data_error = true;
4553	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4554	}
4555	else // no error reported
4556	{
4557	if ( r_vci_rsp_fifo_dcache.wok() )
4558	{
4559	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
4560	"The VCI response packet for data miss is too long");
4561
4562	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4563	vci_rsp_fifo_dcache_put = true,
4564	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4565	if ( p_vci_ini_d.reop.read() )
4566	{
4567	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
4568	"The VCI response packet for data miss is too short");
4569
4570	r_vci_rsp_fsm = RSP_IDLE;
4571	}
4572	}
4573	}
4574	}
4575	break;
4576	}
4577	//////////////////
4578	case RSP_DATA_UNC:
4579	{
4580	if (p_vci_ini_d.rspval.read() )
4581	{
4582	assert( p_vci_ini_d.reop.read() and
4583	"illegal VCI response packet for uncachable read data");
4584
4585	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4586	{
4587	r_vci_rsp_data_error = true;
4588	r_vci_rsp_fsm = RSP_IDLE;
4589	}
4590	else // no error reported
4591	{
4592	if ( r_vci_rsp_fifo_dcache.wok())
4593	{
4594	vci_rsp_fifo_dcache_put = true;
4595	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4596	r_vci_rsp_fsm = RSP_IDLE;
4597	}
4598	}
4599	}
4600	break;
4601	}
4602	////////////////////
4603	case RSP_DATA_WRITE:
4604	{
4605	if (p_vci_ini_d.rspval.read())
4606	{
4607	assert( p_vci_ini_d.reop.read() and
4608	"a VCI response packet must contain one flit for a write transaction");
4609
4610	r_vci_rsp_fsm = RSP_IDLE;
4611	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1));
4612	bool cacheable = r_wbuf.completed(wbuf_index);
4613	if ( not cacheable ) r_dcache_pending_unc_write = false;
4614	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
4615	}
4616	break;
4617	}
4618	} // end switch r_vci_rsp_fsm
4619
4620	////////////////////////////////////////////////////////////////////////////////
4621	// The CLEANUP FSM send the cleanup commands on the coherence network,
4622	// and supports simultaneous cleanup transactions, but two simultaneous
4623	// transactions mut address different cache lines.
4624	// Therefore, the line number is registered in an associative
4625	// registration buffer (Content Adressable Memory) by the CLEANUP FSM,
4626	// and the corresponding slot (identified by the VCI TRDID field) is cleared
4627	// when the cleanup transaction response is received.
4628	// It handles cleanup requests from both the DCACHE FSM & ICACHE FSM
4629	// with a round robin priority, and can support up to 4 simultaneous
4630	// cleanup transactions (4 slots in the registration buffer).
4631	// The r_dcache_cleanup_req (or r_icache_cleanup_req) flip-flops are reset
4632	// when the command has been sent.
4633	// The VCI TRDID field is used to distinguish data/instruction cleanups:
4634	// - if data cleanup : TRDID = 2*index + 0
4635	// - if instruction cleanup : TRDID = 2*index + 1
4636	////////////////////////////////////////////////////////////////////////////
4637
4638	switch ( r_cleanup_fsm.read() )
4639	{
4640	///////////////////////
4641	case CLEANUP_DATA_IDLE: // dcache has highest priority
4642	{
4643	size_t index = 0;
4644	bool ok;
4645	if ( r_dcache_cleanup_req.read() ) // dcache request
4646	{
4647	ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(),
4648	&index );
4649	if ( ok ) // successful registration
4650	{
4651	r_cleanup_fsm = CLEANUP_DATA_GO;
4652	r_cleanup_trdid = index<<1;
4653	}
4654	}
4655	else if ( r_icache_cleanup_req.read() ) // icache request
4656	{
4657	ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(),
4658	&index );
4659	if ( ok ) // successful registration
4660	{
4661	r_cleanup_fsm = CLEANUP_INS_GO;
4662	r_cleanup_trdid = (index<<1) + 1;
4663	}
4664	}
4665	break;
4666	}
4667	//////////////////////
4668	case CLEANUP_INS_IDLE: // icache has highest priority
4669	{
4670	size_t index = 0;
4671	bool ok;
4672	if ( r_icache_cleanup_req.read() ) // icache request
4673	{
4674	ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(),
4675	&index );
4676	if ( ok ) // successful registration
4677	{
4678	r_cleanup_fsm = CLEANUP_INS_GO;
4679	r_cleanup_trdid = (index<<1) + 1;
4680	}
4681	}
4682	else if ( r_dcache_cleanup_req.read() ) // dcache request
4683	{
4684	ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(),
4685	&index );
4686	if ( ok ) // successful registration
4687	{
4688	r_cleanup_fsm = CLEANUP_DATA_GO;
4689	r_cleanup_trdid = index<<1;
4690	}
4691	}
4692	break;
4693	}
4694	/////////////////////
4695	case CLEANUP_DATA_GO:
4696	{
4697	if ( p_vci_ini_c.cmdack.read() )
4698	{
4699	r_dcache_cleanup_req = false;
4700	r_cleanup_fsm = CLEANUP_INS_IDLE;
4701
4702	#if DEBUG_CLEANUP
4703	if ( m_debug_cleanup_fsm )
4704	{
4705	std::cout << " <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
4706	<< " address = " << (r_dcache_cleanup_line.read()m_dcache_words4)
4707	<< " / trdid = " << r_cleanup_trdid.read() << std::endl;
4708	}
4709	#endif
4710	}
4711	}
4712	////////////////////////
4713	case CLEANUP_INS_GO:
4714	{
4715	if ( p_vci_ini_c.cmdack.read() )
4716	{
4717	r_icache_cleanup_req = false;
4718	r_cleanup_fsm = CLEANUP_DATA_IDLE;
4719
4720	#if DEBUG_CLEANUP
4721	if ( m_debug_cleanup_fsm )
4722	{
4723	std::cout << " <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
4724	<< " address = " << (r_icache_cleanup_line.read()m_icache_words4)
4725	<< " / trdid = " << r_cleanup_trdid.read() << std::endl;
4726	}
4727	#endif
4728	}
4729	}
4730	} // end switch CLEANUP FSM
4731
4732	//////////////// Handling cleanup responses //////////////////
4733	if ( p_vci_ini_c.rspval.read() ) // valid response
4734	{
4735	r_cleanup_buffer.cancel_index( p_vci_ini_c.rtrdid.read() >> 1);
4736	}
4737
4738	///////////////// Response FIFOs update //////////////////////
4739	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
4740	vci_rsp_fifo_icache_put,
4741	vci_rsp_fifo_icache_data);
4742
4743	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
4744	vci_rsp_fifo_dcache_put,
4745	vci_rsp_fifo_dcache_data);
4746	} // end transition()
4747
4748	///////////////////////
4749	tmpl(void)::genMoore()
4750	///////////////////////
4751	{
4752	////////////////////////////////////////////////////////////////
4753	// VCI initiator command on the coherence network (cleanup)
4754	// it depends on the CLEANUP FSM state
4755
4756	paddr_t address;
4757
4758	if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
4759	address = r_dcache_cleanup_line.read()m_dcache_words4;
4760	else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
4761	address = r_icache_cleanup_line.read()m_icache_words4;
4762	else
4763	address = 0;
4764
4765	p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
4766	(r_cleanup_fsm.read() == CLEANUP_INS_GO) );
4767	p_vci_ini_c.address = address;
4768	p_vci_ini_c.wdata = 0;
4769	p_vci_ini_c.be = 0xF;
4770	p_vci_ini_c.plen = 4;
4771	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
4772	p_vci_ini_c.trdid = r_cleanup_trdid.read();
4773	p_vci_ini_c.pktid = 0;
4774	p_vci_ini_c.srcid = m_srcid_c;
4775	p_vci_ini_c.cons = false;
4776	p_vci_ini_c.wrap = false;
4777	p_vci_ini_c.contig = false;
4778	p_vci_ini_c.clen = 0;
4779	p_vci_ini_c.cfixed = false;
4780	p_vci_ini_c.eop = true;
4781
4782	/////////////////////////////////////////////////////////////////
4783	// VCI initiator response on the coherence network (cleanup)
4784	// We always consume the response, and we don't use it.
4785
4786	p_vci_ini_c.rspack = true;
4787
4788	/////////////////////////////////////////////////////////////////
4789	// VCI initiator command on the direct network
4790	// it depends on the CMD FSM state
4791
4792	p_vci_ini_d.pktid = 0;
4793	p_vci_ini_d.srcid = m_srcid_d;
4794	p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4795	p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4796	p_vci_ini_d.wrap = false;
4797	p_vci_ini_d.clen = 0;
4798	p_vci_ini_d.cfixed = false;
4799
4800	switch ( r_vci_cmd_fsm.read() ) {
4801
4802	case CMD_IDLE:
4803	p_vci_ini_d.cmdval = false;
4804	p_vci_ini_d.address = 0;
4805	p_vci_ini_d.wdata = 0;
4806	p_vci_ini_d.be = 0;
4807	p_vci_ini_d.trdid = 0;
4808	p_vci_ini_d.plen = 0;
4809	p_vci_ini_d.cmd = vci_param::CMD_NOP;
4810	p_vci_ini_d.eop = false;
4811	break;
4812
4813	case CMD_INS_MISS:
4814	p_vci_ini_d.cmdval = true;
4815	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
4816	p_vci_ini_d.wdata = 0;
4817	p_vci_ini_d.be = 0xF;
4818	p_vci_ini_d.trdid = TYPE_INS_MISS;
4819	p_vci_ini_d.plen = m_icache_words<<2;
4820	p_vci_ini_d.cmd = vci_param::CMD_READ;
4821	p_vci_ini_d.eop = true;
4822	break;
4823
4824	case CMD_INS_UNC:
4825	p_vci_ini_d.cmdval = true;
4826	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
4827	p_vci_ini_d.wdata = 0;
4828	p_vci_ini_d.be = 0xF;
4829	p_vci_ini_d.trdid = TYPE_INS_UNC;
4830	p_vci_ini_d.plen = 4;
4831	p_vci_ini_d.cmd = vci_param::CMD_READ;
4832	p_vci_ini_d.eop = true;
4833	break;
4834
4835	case CMD_DATA_MISS:
4836	p_vci_ini_d.cmdval = true;
4837	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
4838	p_vci_ini_d.wdata = 0;
4839	p_vci_ini_d.be = 0xF;
4840	p_vci_ini_d.trdid = TYPE_DATA_MISS;
4841	p_vci_ini_d.plen = m_dcache_words << 2;
4842	p_vci_ini_d.cmd = vci_param::CMD_READ;
4843	p_vci_ini_d.eop = true;
4844	break;
4845
4846	case CMD_DATA_UNC:
4847	p_vci_ini_d.cmdval = true;
4848	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4849	p_vci_ini_d.wdata = 0;
4850	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
4851	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4852	p_vci_ini_d.plen = 4;
4853	p_vci_ini_d.cmd = vci_param::CMD_READ;
4854	p_vci_ini_d.eop = true;
4855	break;
4856
4857	case CMD_DATA_WRITE:
4858	p_vci_ini_d.cmdval = true;
4859	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
4860	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
4861	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
4862	p_vci_ini_d.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1));
4863	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
4864	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
4865	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
4866	break;
4867
4868	case CMD_DATA_SC:
4869	p_vci_ini_d.cmdval = true;
4870	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4871	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_sc_old.read();
4872	else p_vci_ini_d.wdata = r_dcache_vci_sc_new.read();
4873	p_vci_ini_d.be = 0xF;
4874	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4875	p_vci_ini_d.plen = 8;
4876	p_vci_ini_d.cmd = vci_param::CMD_STORE_COND;
4877	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
4878	break;
4879	} // end switch r_vci_cmd_fsm
4880
4881	//////////////////////////////////////////////////////////
4882	// VCI initiator response on the direct network
4883	// it depends on the VCI RSP state
4884
4885	switch (r_vci_rsp_fsm.read() )
4886	{
4887	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
4888	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4889	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4890	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4891	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4892	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
4893	} // end switch r_vci_rsp_fsm
4894
4895	////////////////////////////////////////////////////////////////
4896	// VCI target command and response on the coherence network
4897	switch ( r_tgt_fsm.read() )
4898	{
4899	case TGT_IDLE:
4900	case TGT_UPDT_WORD:
4901	case TGT_UPDT_DATA:
4902	p_vci_tgt_c.cmdack = true;
4903	p_vci_tgt_c.rspval = false;
4904	break;
4905
4906	case TGT_RSP_BROADCAST:
4907	p_vci_tgt_c.cmdack = false;
4908	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()
4909	and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() );
4910	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4911	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4912	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4913	p_vci_tgt_c.rdata = 0;
4914	p_vci_tgt_c.rerror = 0;
4915	p_vci_tgt_c.reop = true;
4916	break;
4917
4918	case TGT_RSP_ICACHE:
4919	p_vci_tgt_c.cmdack = false;
4920	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
4921	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4922	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4923	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4924	p_vci_tgt_c.rdata = 0;
4925	p_vci_tgt_c.rerror = 0;
4926	p_vci_tgt_c.reop = true;
4927	break;
4928
4929	case TGT_RSP_DCACHE:
4930	p_vci_tgt_c.cmdack = false;
4931	p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
4932	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4933	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4934	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4935	p_vci_tgt_c.rdata = 0;
4936	p_vci_tgt_c.rerror = 0;
4937	p_vci_tgt_c.reop = true;
4938	break;
4939
4940	case TGT_REQ_BROADCAST:
4941	case TGT_REQ_ICACHE:
4942	case TGT_REQ_DCACHE:
4943	p_vci_tgt_c.cmdack = false;
4944	p_vci_tgt_c.rspval = false;
4945	break;
4946
4947	} // end switch TGT_FSM
4948	} // end genMoore
4949
4950	}}
4951
4952	// Local Variables:
4953	// tab-width: 4
4954	// c-basic-offset: 4
4955	// c-file-offsets:((innamespace . 0)(inline-open . 0))
4956	// indent-tabs-mode: nil
4957	// End:
4958
4959	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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