source: trunk/modules/vci_cc_xcache_wrapper_v1/caba/source/include/vci_cc_xcache_wrapper_v1.h @ 191

Last change on this file since 191 was 191, checked in by cfuguet, 12 years ago

Cleanup transaction modification
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1/* -*- c++ -*-
2 *
3 * SOCLIB_LGPL_HEADER_BEGIN
4 *
5 * This file is part of SoCLib, GNU LGPLv2.1.
6 *
7 * SoCLib is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU Lesser General Public License as published
9 * by the Free Software Foundation; version 2.1 of the License.
10 *
11 * SoCLib is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with SoCLib; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * SOCLIB_LGPL_HEADER_END
22 *
23 * Copyright (c) UPMC, Lip6, SoC
24 *         Alain Greiner <alain.greiner@lip6.fr>, 2008
25 *
26 * Maintainers: alain
27 */
28 
29#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V1_H
30#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V1_H
31
32#include <inttypes.h>
33#include <systemc>
34#include "caba_base_module.h"
35#include "write_buffer.h"
36#include "generic_cache.h"
37#include "vci_initiator.h"
38#include "vci_target.h"
39#include "mapping_table.h"
40#include "static_assert.h"
41
42
43namespace soclib {
44namespace caba {
45
46using namespace sc_core;
47
48////////////////////////////////////////////
49template<typename vci_param, typename iss_t>
50class VciCcXCacheWrapperV1
51///////////////////////////////////////////
52    : public soclib::caba::BaseModule
53{
54    typedef sc_dt::sc_uint<40> addr_40;
55    typedef uint32_t    data_t;
56    typedef uint32_t    tag_t;
57    typedef uint32_t    be_t;
58    typedef typename vci_param::fast_addr_t vci_addr_t;
59    enum dcache_fsm_state_e {
60        DCACHE_IDLE,
61        DCACHE_WRITE_UPDT,
62        DCACHE_WRITE_REQ,
63        DCACHE_MISS_WAIT,
64        DCACHE_MISS_UPDT,
65        DCACHE_UNC_WAIT,
66        DCACHE_INVAL,
67        DCACHE_ERROR,
68        DCACHE_CC_CHECK,
69        DCACHE_CC_INVAL,
70        DCACHE_CC_UPDT,
71        DCACHE_CC_CLEANUP,
72    };
73
74    enum icache_fsm_state_e {
75        ICACHE_IDLE,
76        ICACHE_MISS_WAIT,
77        ICACHE_MISS_UPDT,
78        ICACHE_UNC_WAIT,
79        ICACHE_ERROR,
80        ICACHE_CC_CHECK,
81        ICACHE_CC_INVAL,
82        ICACHE_CC_UPDT,
83        ICACHE_CC_CLEANUP
84    };
85
86    enum cmd_fsm_state_e {
87        CMD_IDLE,
88        CMD_INS_MISS,
89        CMD_INS_UNC,
90        CMD_DATA_MISS,
91        CMD_DATA_UNC,
92        CMD_DATA_WRITE,
93        CMD_INS_CLEANUP,
94        CMD_DATA_CLEANUP,
95    };
96
97    enum rsp_fsm_state_e {
98        RSP_IDLE,
99        RSP_INS_MISS,
100        RSP_INS_UNC,
101        RSP_DATA_MISS,
102        RSP_DATA_UNC,
103        RSP_DATA_WRITE,
104        RSP_INS_CLEANUP,
105        RSP_DATA_CLEANUP,
106    };
107
108    enum tgt_fsm_state_e {
109        TGT_IDLE,
110        TGT_UPDT_WORD,
111        TGT_UPDT_DATA,
112        TGT_REQ_BROADCAST,
113        TGT_REQ_ICACHE,
114        TGT_REQ_DCACHE,
115        TGT_RSP_BROADCAST,
116        TGT_RSP_ICACHE,
117        TGT_RSP_DCACHE,
118    };
119
120public:
121
122    // PORTS
123    sc_in<bool>                             p_clk;
124    sc_in<bool>                             p_resetn;
125    sc_in<bool>                             p_irq[iss_t::n_irq];
126    soclib::caba::VciInitiator<vci_param>   p_vci_ini_rw;
127    soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
128    soclib::caba::VciTarget<vci_param>      p_vci_tgt;
129
130private:
131
132    // STRUCTURAL PARAMETERS
133    const soclib::common::AddressDecodingTable<vci_addr_t, bool>    m_cacheability_table;
134    const soclib::common::Segment                                   m_segment;
135    iss_t               m_iss;
136    const uint32_t      m_srcid_rw;   
137    const uint32_t      m_srcid_c;   
138   
139    const size_t        m_dcache_ways;
140    const size_t        m_dcache_words;
141    const size_t        m_dcache_yzmask;
142    const size_t        m_icache_ways;
143    const size_t        m_icache_words;
144    const size_t        m_icache_yzmask;
145
146    const size_t        m_x_width;   
147    const size_t        m_y_width;   
148    const size_t        m_memc_id;   
149    addr_40             m_srcid_mask;
150
151    // REGISTERS
152    sc_signal<int>          r_dcache_fsm;
153    sc_signal<int>          r_dcache_fsm_save;
154    sc_signal<addr_40>      r_dcache_addr_save;
155    sc_signal<data_t>       r_dcache_wdata_save;
156    sc_signal<data_t>       r_dcache_rdata_save;
157    sc_signal<int>          r_dcache_type_save;
158    sc_signal<be_t>         r_dcache_be_save;
159    sc_signal<bool>         r_dcache_cached_save;
160    sc_signal<bool>         r_dcache_cleanup_req;
161    sc_signal<addr_40>      r_dcache_cleanup_line;
162    sc_signal<bool>         r_dcache_miss_req;
163    sc_signal<bool>         r_dcache_unc_req;
164    sc_signal<bool>         r_dcache_write_req;
165    sc_signal<bool>         r_dcache_inval_rsp;
166
167    sc_signal<int>          r_icache_fsm;
168    sc_signal<int>          r_icache_fsm_save;
169    sc_signal<addr_40>      r_icache_addr_save;
170    sc_signal<bool>         r_icache_miss_req;
171    sc_signal<bool>         r_icache_unc_req;
172    sc_signal<bool>         r_icache_cleanup_req;
173    sc_signal<addr_40>      r_icache_cleanup_line;
174    sc_signal<bool>         r_icache_inval_rsp;
175
176    sc_signal<int>          r_vci_cmd_fsm;
177    sc_signal<size_t>       r_vci_cmd_min;       
178    sc_signal<size_t>       r_vci_cmd_max;       
179    sc_signal<size_t>       r_vci_cmd_cpt;       
180     
181    sc_signal<int>          r_vci_rsp_fsm;
182    sc_signal<bool>         r_vci_rsp_ins_error;   
183    sc_signal<bool>         r_vci_rsp_data_error;   
184    sc_signal<size_t>       r_vci_rsp_cpt; 
185
186    data_t                  *r_icache_miss_buf;   
187    data_t                  *r_dcache_miss_buf;   
188    sc_signal<bool>         r_icache_buf_unc_valid;
189    sc_signal<bool>         r_dcache_buf_unc_valid;
190
191    data_t                  *r_tgt_buf;
192    be_t                    *r_tgt_be;
193
194    sc_signal<int>          r_vci_tgt_fsm;
195    sc_signal<addr_40>       r_tgt_addr;
196    sc_signal<size_t>       r_tgt_word;
197    sc_signal<bool>         r_tgt_update;
198    sc_signal<bool>         r_data_update; // 0 : update ins; 1 : update data
199    sc_signal<bool>         r_tgt_brdcast;
200    sc_signal<size_t>       r_tgt_srcid;
201    sc_signal<size_t>       r_tgt_pktid;
202    sc_signal<size_t>       r_tgt_trdid;
203    sc_signal<size_t>       r_tgt_plen;
204    sc_signal<bool>         r_tgt_icache_req;
205    sc_signal<bool>         r_tgt_dcache_req;
206    sc_signal<bool>         r_tgt_icache_rsp;
207    sc_signal<bool>         r_tgt_dcache_rsp;
208
209    WriteBuffer<addr_40>        r_wbuf;
210    GenericCache<vci_addr_t>    r_icache;
211    GenericCache<vci_addr_t>    r_dcache;
212
213    // Activity counters
214    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
215    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
216    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
217    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
218
219    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
220    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
221    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
222    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
223
224    uint32_t m_cpt_cc_update;               // number of coherence update packets
225    uint32_t m_cpt_cc_inval;                // number of coherence inval packets
226
227    uint32_t m_cpt_frz_cycles;              // number of cycles where the cpu is frozen
228    uint32_t m_cpt_total_cycles;                // total number of cycles
229
230    uint32_t m_cpt_read;                    // total number of read instructions
231    uint32_t m_cpt_write;                   // total number of write instructions
232    uint32_t m_cpt_data_miss;               // number of read miss
233    uint32_t m_cpt_ins_miss;                // number of instruction miss
234    uint32_t m_cpt_unc_read;                // number of read uncached
235    uint32_t m_cpt_write_cached;            // number of cached write
236
237    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer         
238    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
239    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
240    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
241
242    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
243    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
244    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
245    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
246
247    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
248    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
249    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
250    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
251    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
252
253protected:
254    SC_HAS_PROCESS(VciCcXCacheWrapperV1);
255
256public:
257
258    VciCcXCacheWrapperV1(
259                       sc_module_name insname,
260                       int proc_id,
261                       const soclib::common::MappingTable &mtp,
262                       const soclib::common::MappingTable &mtc,
263                       const soclib::common::IntTab &initiator_index_rw,
264                       const soclib::common::IntTab &initiator_index_c,
265                       const soclib::common::IntTab &target_index,
266                       size_t icache_ways,
267                       size_t icache_sets,
268                       size_t icache_words,
269                       size_t dcache_ways,
270                       size_t dcache_sets,
271                       size_t dcache_words,
272                       size_t x_width,
273                       size_t y_width,
274                       size_t memc_id );
275
276    ~VciCcXCacheWrapperV1();
277
278    void print_cpi();
279    void print_stats();
280
281private:
282
283    void transition();
284    void genMoore();
285
286    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
287    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
288};
289
290}}
291
292#endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V1_H */
293
294// Local Variables:
295// tab-width: 4
296// c-basic-offset: 4
297// c-file-offsets:((innamespace . 0)(inline-open . 0))
298// indent-tabs-mode: nil
299// End:
300
301// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
302
303
304
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