[2] | 1 | /* -*- c++ -*- |
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| 2 | * |
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| 3 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 4 | * |
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| 5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 6 | * |
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| 7 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 8 | * under the terms of the GNU Lesser General Public License as published |
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| 9 | * by the Free Software Foundation; version 2.1 of the License. |
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| 10 | * |
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| 11 | * SoCLib is distributed in the hope that it will be useful, but |
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| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | * Lesser General Public License for more details. |
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| 15 | * |
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| 16 | * You should have received a copy of the GNU Lesser General Public |
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| 17 | * License along with SoCLib; if not, write to the Free Software |
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| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 19 | * 02110-1301 USA |
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| 20 | * |
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| 21 | * SOCLIB_LGPL_HEADER_END |
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| 22 | * |
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| 23 | * Copyright (c) UPMC, Lip6, SoC |
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| 24 | * Alain Greiner <alain.greiner@lip6.fr>, 2008 |
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| 25 | * |
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| 26 | * Maintainers: alain |
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| 27 | */ |
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| 28 | |
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| 29 | #ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H |
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| 30 | #define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H |
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| 31 | |
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| 32 | #include <inttypes.h> |
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[140] | 33 | #include <fstream> |
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[2] | 34 | #include <systemc> |
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[134] | 35 | #include <queue> |
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[2] | 36 | #include "caba_base_module.h" |
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[134] | 37 | #include "multi_write_buffer.h" |
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[2] | 38 | #include "generic_cache.h" |
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| 39 | #include "vci_initiator.h" |
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| 40 | #include "vci_target.h" |
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| 41 | #include "mapping_table.h" |
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| 42 | #include "static_assert.h" |
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| 43 | |
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[134] | 44 | /* |
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| 45 | * CC_XCACHE_WRAPPER_SELECT_VICTIM : |
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| 46 | * The selection and the update of cache (after a read miss) |
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| 47 | * are separated in two step |
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| 48 | * Also, the cleanup can be send in parallel at the read miss. |
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| 49 | * |
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| 50 | * CC_XCACHE_WRAPPER_FIFO_RSP |
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| 51 | * Two simple fifo (each 2x32 depth) receive the cache line from |
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| 52 | * RAM. Instead of two buffers (m_icache_words and m_dcache_words) |
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| 53 | * |
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| 54 | * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE |
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| 55 | * Update cache in "2*cache_words" cycles (read+mask, write) |
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| 56 | * |
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| 57 | * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT |
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| 58 | * Update cache with only modified data (be != 0) |
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| 59 | * |
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| 60 | * CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME |
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| 61 | * Write buffer scheme for update step : |
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| 62 | * 1 - multi_scan |
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| 63 | * 2 - round_robin_scan |
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| 64 | * 3 - one_scan |
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| 65 | * else - default scheme |
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| 66 | * |
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| 67 | * CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY |
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| 68 | * Write buffer access is conditionnal with dcache_miss_req and icache_miss_req |
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| 69 | * 1 - two access authorized |
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| 70 | * 2 - one access with static priority (dcache prior) |
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| 71 | * 3 - one access with static priority (icache prior) |
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| 72 | * 4 - one access with round robin priority |
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| 73 | * |
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[140] | 74 | * CC_XCACHE_WRAPPER_MULTI_CACHE : |
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| 75 | * 1 - icache static partitionnement |
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| 76 | * 2 - icache dedicated |
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| 77 | * |
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[134] | 78 | * CC_XCACHE_WRAPPER_STOP_SIMULATION : |
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| 79 | * stop simulation if processor is stall after a long time |
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| 80 | * (configurable with "stop_simulation" function) |
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| 81 | * |
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| 82 | * CC_XCACHE_WRAPPER_DEBUG : |
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| 83 | * Add log to help the debugging |
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| 84 | * |
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| 85 | * CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN : |
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| 86 | * Number of cycle before to prinf debug message |
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| 87 | * |
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[140] | 88 | * CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION |
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| 89 | * Print transaction between : |
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| 90 | * - the cpu and the cache (icache and dcache) |
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| 91 | * - vci |
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| 92 | * - cleanup |
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| 93 | * - coherency |
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[134] | 94 | */ |
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[2] | 95 | |
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[134] | 96 | // implementation |
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| 97 | #ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM |
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[140] | 98 | #define CC_XCACHE_WRAPPER_SELECT_VICTIM 1 |
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[134] | 99 | #endif |
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| 100 | #ifndef CC_XCACHE_WRAPPER_FIFO_RSP |
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[140] | 101 | #define CC_XCACHE_WRAPPER_FIFO_RSP 1 |
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[134] | 102 | #endif |
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| 103 | #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE |
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[140] | 104 | #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1 |
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[134] | 105 | #endif |
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| 106 | #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT |
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[140] | 107 | #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1 |
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[134] | 108 | #endif |
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| 109 | #ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME |
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[140] | 110 | #define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 2 |
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[134] | 111 | #endif |
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| 112 | #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY |
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[140] | 113 | #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 4 |
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[134] | 114 | #endif |
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[140] | 115 | #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE |
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| 116 | #define CC_XCACHE_WRAPPER_MULTI_CACHE 2 |
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| 117 | #endif |
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[134] | 118 | // debugging |
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| 119 | #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION |
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[140] | 120 | #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 |
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[134] | 121 | #endif |
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| 122 | #ifndef CC_XCACHE_WRAPPER_DEBUG |
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[140] | 123 | #define CC_XCACHE_WRAPPER_DEBUG 0 |
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[134] | 124 | #endif |
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| 125 | #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN |
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[140] | 126 | #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 949900 |
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[134] | 127 | #endif |
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[140] | 128 | #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION |
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| 129 | #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 0 |
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| 130 | #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log" |
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[134] | 131 | #endif |
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| 132 | |
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[140] | 133 | // don't change |
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| 134 | #if not CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE |
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| 135 | #undef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT |
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| 136 | #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 0 |
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| 137 | #endif |
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| 138 | |
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[2] | 139 | namespace soclib { |
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| 140 | namespace caba { |
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| 141 | |
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| 142 | using namespace sc_core; |
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| 143 | |
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| 144 | //////////////////////////////////////////// |
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| 145 | template<typename vci_param, typename iss_t> |
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| 146 | class VciCcXCacheWrapperV4 |
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| 147 | /////////////////////////////////////////// |
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| 148 | : public soclib::caba::BaseModule |
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| 149 | { |
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[90] | 150 | typedef sc_dt::sc_uint<40> addr_40; |
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[110] | 151 | typedef sc_dt::sc_uint<64> data_64; |
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[90] | 152 | typedef uint32_t data_t; |
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| 153 | typedef uint32_t tag_t; |
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| 154 | typedef uint32_t be_t; |
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[2] | 155 | typedef typename vci_param::fast_addr_t vci_addr_t; |
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[134] | 156 | |
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[2] | 157 | enum dcache_fsm_state_e { |
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| 158 | DCACHE_IDLE, |
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| 159 | DCACHE_WRITE_UPDT, |
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[134] | 160 | #if CC_XCACHE_WRAPPER_SELECT_VICTIM |
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| 161 | DCACHE_MISS_VICTIM, |
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| 162 | #endif |
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[2] | 163 | DCACHE_MISS_WAIT, |
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| 164 | DCACHE_MISS_UPDT, |
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| 165 | DCACHE_UNC_WAIT, |
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| 166 | DCACHE_SC_WAIT, |
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| 167 | DCACHE_INVAL, |
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[134] | 168 | DCACHE_SYNC, |
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[2] | 169 | DCACHE_ERROR, |
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| 170 | DCACHE_CC_CHECK, |
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| 171 | DCACHE_CC_INVAL, |
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| 172 | DCACHE_CC_UPDT, |
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| 173 | DCACHE_CC_CLEANUP, |
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| 174 | }; |
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| 175 | |
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| 176 | enum icache_fsm_state_e { |
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| 177 | ICACHE_IDLE, |
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[134] | 178 | #if CC_XCACHE_WRAPPER_SELECT_VICTIM |
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| 179 | ICACHE_MISS_VICTIM, |
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| 180 | #endif |
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[2] | 181 | ICACHE_MISS_WAIT, |
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| 182 | ICACHE_MISS_UPDT, |
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| 183 | ICACHE_UNC_WAIT, |
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| 184 | ICACHE_ERROR, |
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| 185 | ICACHE_CC_CLEANUP, |
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| 186 | ICACHE_CC_CHECK, |
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| 187 | ICACHE_CC_INVAL, |
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| 188 | ICACHE_CC_UPDT, |
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| 189 | }; |
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| 190 | |
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| 191 | enum cmd_fsm_state_e { |
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| 192 | CMD_IDLE, |
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| 193 | CMD_INS_MISS, |
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| 194 | CMD_INS_UNC, |
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| 195 | CMD_DATA_MISS, |
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| 196 | CMD_DATA_UNC, |
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| 197 | CMD_DATA_WRITE, |
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| 198 | CMD_DATA_SC, |
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| 199 | }; |
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| 200 | |
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| 201 | enum rsp_fsm_state_e { |
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| 202 | RSP_IDLE, |
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| 203 | RSP_INS_MISS, |
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| 204 | RSP_INS_UNC, |
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| 205 | RSP_DATA_MISS, |
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| 206 | RSP_DATA_UNC, |
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| 207 | RSP_DATA_WRITE, |
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| 208 | RSP_DATA_SC, |
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| 209 | }; |
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| 210 | |
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| 211 | enum tgt_fsm_state_e { |
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| 212 | TGT_IDLE, |
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| 213 | TGT_UPDT_WORD, |
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| 214 | TGT_UPDT_DATA, |
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| 215 | TGT_REQ_BROADCAST, |
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| 216 | TGT_REQ_ICACHE, |
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| 217 | TGT_REQ_DCACHE, |
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| 218 | TGT_RSP_BROADCAST, |
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| 219 | TGT_RSP_ICACHE, |
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| 220 | TGT_RSP_DCACHE, |
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| 221 | }; |
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| 222 | |
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[134] | 223 | enum cleanup_fsm_state_e { |
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| 224 | CLEANUP_IDLE, |
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[140] | 225 | CLEANUP_REQ, |
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| 226 | CLEANUP_RSP_DCACHE, |
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| 227 | CLEANUP_RSP_ICACHE, |
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[134] | 228 | }; |
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| 229 | |
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| 230 | enum transaction_type_c_e { |
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| 231 | // convention with memcache |
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| 232 | TYPE_DATA_CLEANUP = 0x0, |
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| 233 | TYPE_INS_CLEANUP = 0x1 |
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| 234 | }; |
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| 235 | |
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| 236 | enum transaction_type_rw_e { |
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| 237 | // convention with memcache |
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| 238 | // b0 : 1 if cached |
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| 239 | // b1 : 1 if instruction |
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| 240 | // b2 : 1 if sc |
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| 241 | TYPE_DATA_UNC = 0x0, |
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| 242 | TYPE_DATA_MISS = 0x1, |
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| 243 | TYPE_INS_UNC = 0x2, |
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| 244 | TYPE_INS_MISS = 0x3, |
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| 245 | TYPE_DATA_SC = 0x4, // sc is data and no cached |
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| 246 | }; |
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| 247 | |
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[2] | 248 | public: |
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| 249 | |
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| 250 | // PORTS |
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| 251 | sc_in<bool> p_clk; |
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| 252 | sc_in<bool> p_resetn; |
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[140] | 253 | sc_in<bool> ** p_irq;//[m_nb_cpu][iss_t::n_irq]; |
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[2] | 254 | soclib::caba::VciInitiator<vci_param> p_vci_ini_rw; |
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| 255 | soclib::caba::VciInitiator<vci_param> p_vci_ini_c; |
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| 256 | soclib::caba::VciTarget<vci_param> p_vci_tgt; |
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| 257 | |
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| 258 | private: |
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| 259 | |
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| 260 | // STRUCTURAL PARAMETERS |
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| 261 | const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table; |
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| 262 | const soclib::common::Segment m_segment; |
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[140] | 263 | iss_t ** m_iss; //[m_nb_cpu] |
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[2] | 264 | const uint32_t m_srcid_rw; |
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| 265 | const uint32_t m_srcid_c; |
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| 266 | |
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[140] | 267 | const size_t m_nb_cpu; |
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| 268 | const size_t m_nb_icache; |
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| 269 | const size_t m_nb_dcache; |
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| 270 | const size_t m_nb_cache; |
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[2] | 271 | const size_t m_dcache_ways; |
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| 272 | const size_t m_dcache_words; |
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[134] | 273 | const uint32_t m_dcache_words_shift; |
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[2] | 274 | const size_t m_dcache_yzmask; |
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| 275 | const size_t m_icache_ways; |
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| 276 | const size_t m_icache_words; |
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[134] | 277 | const uint32_t m_icache_words_shift; |
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[2] | 278 | const size_t m_icache_yzmask; |
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[134] | 279 | const size_t m_cache_words; // max between m_dcache_words and m_icache_words |
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[2] | 280 | |
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[134] | 281 | #if CC_XCACHE_WRAPPER_STOP_SIMULATION |
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| 282 | bool m_stop_simulation; |
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| 283 | uint32_t m_stop_simulation_nb_frz_cycles_max; |
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[140] | 284 | uint32_t * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu] |
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[134] | 285 | #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION |
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| 286 | |
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[2] | 287 | // REGISTERS |
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[140] | 288 | sc_signal<uint32_t> r_cpu_prior; |
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| 289 | sc_signal<uint32_t> * r_icache_lock;//[m_nb_icache] |
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| 290 | sc_signal<uint32_t> * r_dcache_lock;//[m_nb_dcache] |
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| 291 | sc_signal<bool> * r_dcache_sync;//[m_nb_dcache] |
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[2] | 292 | |
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[140] | 293 | sc_signal<int> * r_dcache_fsm; //[m_nb_dcache] |
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| 294 | sc_signal<int> * r_dcache_fsm_save; //[m_nb_dcache] |
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| 295 | sc_signal<addr_40> * r_dcache_addr_save; //[m_nb_dcache] |
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| 296 | sc_signal<data_t> * r_dcache_wdata_save; //[m_nb_dcache] |
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| 297 | sc_signal<data_t> * r_dcache_rdata_save; //[m_nb_dcache] |
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| 298 | sc_signal<int> * r_dcache_type_save; //[m_nb_dcache] |
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| 299 | sc_signal<be_t> * r_dcache_be_save; //[m_nb_dcache] |
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| 300 | sc_signal<bool> * r_dcache_cached_save; //[m_nb_dcache] |
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| 301 | sc_signal<bool> * r_dcache_cleanup_req; //[m_nb_dcache] |
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| 302 | sc_signal<addr_40> * r_dcache_cleanup_line; //[m_nb_dcache] |
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| 303 | sc_signal<bool> * r_dcache_miss_req; //[m_nb_dcache] |
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| 304 | sc_signal<size_t> * r_dcache_miss_way; //[m_nb_dcache] |
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| 305 | sc_signal<size_t> * r_dcache_miss_set; //[m_nb_dcache] |
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| 306 | sc_signal<bool> * r_dcache_unc_req; //[m_nb_dcache] |
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| 307 | sc_signal<bool> * r_dcache_sc_req; //[m_nb_dcache] |
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| 308 | sc_signal<bool> * r_dcache_inval_rsp; //[m_nb_dcache] |
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| 309 | sc_signal<size_t> * r_dcache_update_addr; //[m_nb_dcache] |
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| 310 | sc_signal<data_64> ** r_dcache_ll_data; //[m_nb_dcache][m_nb_cpu] |
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| 311 | sc_signal<addr_40> ** r_dcache_ll_addr; //[m_nb_dcache][m_nb_cpu] |
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| 312 | sc_signal<bool> ** r_dcache_ll_valid; //[m_nb_dcache][m_nb_cpu] |
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| 313 | sc_signal<uint32_t> * r_dcache_num_cpu_save; //[m_nb_dcache] |
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| 314 | sc_signal<bool> * r_dcache_previous_unc; //[m_nb_dcache] |
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| 315 | |
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| 316 | sc_signal<int> * r_icache_fsm; //[m_nb_icache] |
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| 317 | sc_signal<int> * r_icache_fsm_save; //[m_nb_icache] |
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| 318 | sc_signal<addr_40> * r_icache_addr_save; //[m_nb_icache] |
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| 319 | sc_signal<bool> * r_icache_miss_req; //[m_nb_icache] |
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| 320 | sc_signal<size_t> * r_icache_miss_way; //[m_nb_icache] |
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| 321 | sc_signal<size_t> * r_icache_miss_set; //[m_nb_icache] |
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| 322 | sc_signal<bool> * r_icache_unc_req; //[m_nb_icache] |
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| 323 | sc_signal<bool> * r_icache_cleanup_req; //[m_nb_icache] |
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| 324 | sc_signal<addr_40> * r_icache_cleanup_line; //[m_nb_icache] |
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| 325 | sc_signal<bool> * r_icache_inval_rsp; //[m_nb_icache] |
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| 326 | sc_signal<size_t> * r_icache_update_addr; //[m_nb_icache] |
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| 327 | sc_signal<bool> * r_icache_buf_unc_valid;//[m_nb_icache] |
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[2] | 328 | |
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| 329 | sc_signal<int> r_vci_cmd_fsm; |
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| 330 | sc_signal<size_t> r_vci_cmd_min; |
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| 331 | sc_signal<size_t> r_vci_cmd_max; |
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| 332 | sc_signal<size_t> r_vci_cmd_cpt; |
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[134] | 333 | sc_signal<bool> r_vci_cmd_dcache_prior; |
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[140] | 334 | sc_signal<uint32_t> r_vci_cmd_num_cache; |
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| 335 | |
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[2] | 336 | sc_signal<int> r_vci_rsp_fsm; |
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| 337 | sc_signal<size_t> r_vci_rsp_cpt; |
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[140] | 338 | bool s_vci_rsp_ack; |
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| 339 | sc_signal<uint32_t> r_vci_rsp_num_cache; |
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| 340 | sc_signal<bool> * r_vci_rsp_ins_error; //[m_nb_icache] |
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| 341 | sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache] |
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[2] | 342 | |
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[134] | 343 | #if CC_XCACHE_WRAPPER_FIFO_RSP |
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[140] | 344 | std::queue<data_t> * r_icache_miss_buf; //[m_nb_icache] |
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| 345 | std::queue<data_t> * r_dcache_miss_buf; //[m_nb_dcache] |
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[134] | 346 | #else |
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[140] | 347 | bool ** r_icache_miss_val; //[m_nb_icache][m_icache_words] |
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| 348 | data_t ** r_icache_miss_buf; //[m_nb_icache][m_icache_words] |
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| 349 | bool ** r_dcache_miss_val; //[m_nb_dcache][m_dcache_words] |
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| 350 | data_t ** r_dcache_miss_buf; //[m_nb_dcache][m_dcache_words] |
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[134] | 351 | #endif |
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[140] | 352 | data_t * r_tgt_buf; //[m_cache_words] |
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| 353 | be_t * r_tgt_be; //[m_cache_words] |
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[134] | 354 | #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE |
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| 355 | sc_signal<uint32_t> r_cache_word; |
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| 356 | #endif |
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[2] | 357 | |
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| 358 | sc_signal<int> r_vci_tgt_fsm; |
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[140] | 359 | sc_signal<addr_40> r_tgt_iaddr; |
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| 360 | sc_signal<addr_40> r_tgt_daddr; |
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[2] | 361 | sc_signal<size_t> r_tgt_word; |
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| 362 | sc_signal<bool> r_tgt_update; |
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| 363 | sc_signal<bool> r_tgt_update_data; |
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[134] | 364 | //sc_signal<bool> r_tgt_brdcast; |
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[2] | 365 | sc_signal<size_t> r_tgt_srcid; |
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| 366 | sc_signal<size_t> r_tgt_pktid; |
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| 367 | sc_signal<size_t> r_tgt_trdid; |
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[134] | 368 | //sc_signal<size_t> r_tgt_plen; |
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[140] | 369 | sc_signal<uint32_t> r_tgt_num_cache; |
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| 370 | sc_signal<bool> * r_tgt_icache_req; //[m_nb_icache] |
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| 371 | sc_signal<bool> * r_tgt_icache_rsp; //[m_nb_icache] |
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| 372 | sc_signal<bool> * r_tgt_dcache_req; //[m_nb_dcache] |
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| 373 | sc_signal<bool> * r_tgt_dcache_rsp; //[m_nb_dcache] |
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[2] | 374 | |
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[134] | 375 | sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network |
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[140] | 376 | sc_signal<uint32_t> r_cleanup_num_cache; |
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| 377 | sc_signal<bool> r_cleanup_icache; |
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[134] | 378 | |
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[140] | 379 | MultiWriteBuffer<addr_40>** r_wbuf; |
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| 380 | GenericCache<vci_addr_t> ** r_icache; |
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| 381 | GenericCache<vci_addr_t> ** r_dcache; |
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[2] | 382 | |
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[140] | 383 | #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION |
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| 384 | std::ofstream * log_transaction_file_icache; //[m_nb_cpu] |
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| 385 | std::ofstream * log_transaction_file_dcache; //[m_nb_cpu] |
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| 386 | std::ofstream log_transaction_file_cmd; |
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| 387 | std::ofstream log_transaction_file_tgt; |
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| 388 | std::ofstream log_transaction_file_cleanup; |
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[134] | 389 | #endif |
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| 390 | |
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[2] | 391 | // Activity counters |
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[140] | 392 | uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ |
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| 393 | uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE |
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| 394 | uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ |
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| 395 | uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE |
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| 396 | |
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| 397 | uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ |
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| 398 | uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE |
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| 399 | uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ |
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| 400 | uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE |
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| 401 | |
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| 402 | uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) |
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| 403 | uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) |
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| 404 | uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets |
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| 405 | uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets |
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| 406 | uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets |
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| 407 | uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets |
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| 408 | uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets |
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| 409 | |
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| 410 | uint32_t * m_cpt_frz_cycles; // * number of cycles where the cpu is frozen |
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| 411 | uint32_t m_cpt_total_cycles; // total number of cycles |
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| 412 | |
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| 413 | uint32_t m_cpt_data_read; // number of data read |
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| 414 | uint32_t m_cpt_data_read_miss; // number of data read miss |
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| 415 | uint32_t m_cpt_data_read_uncached; // number of data read uncached |
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| 416 | uint32_t m_cpt_data_write; // number of data write |
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| 417 | uint32_t m_cpt_data_write_miss; // number of data write miss |
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| 418 | uint32_t m_cpt_data_write_uncached; // number of data write uncached |
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| 419 | uint32_t m_cpt_ins_miss; // * number of instruction miss |
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| 420 | |
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| 421 | uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer |
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| 422 | uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss |
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| 423 | uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read |
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| 424 | uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss |
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| 425 | |
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| 426 | uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions |
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| 427 | uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions |
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| 428 | uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions |
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| 429 | uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions |
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| 430 | |
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| 431 | uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions |
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| 432 | uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions |
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| 433 | uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions |
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| 434 | uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions |
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| 435 | uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions |
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[2] | 436 | |
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[140] | 437 | uint32_t * m_cpt_icache_access; //[m_nb_icache] |
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| 438 | uint32_t * m_cpt_dcache_access; //[m_nb_dcache] |
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[2] | 439 | |
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[140] | 440 | uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache] |
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| 441 | uint32_t ** m_cpt_fsm_icache; //[m_nb_icache] |
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| 442 | uint32_t * m_cpt_fsm_cmd; |
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| 443 | uint32_t * m_cpt_fsm_rsp; |
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| 444 | uint32_t * m_cpt_fsm_tgt; |
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| 445 | uint32_t * m_cpt_fsm_cleanup; |
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[2] | 446 | |
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[140] | 447 | // Non blocking multi-cache |
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| 448 | typename iss_t::InstructionRequest * ireq ; //[m_nb_icache] |
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| 449 | typename iss_t::InstructionResponse * irsp ; //[m_nb_icache] |
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| 450 | bool * ireq_cached ; //[m_nb_icache] |
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| 451 | uint32_t * ireq_num_cpu; //[m_nb_dcache] |
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| 452 | typename iss_t::DataRequest * dreq ; //[m_nb_dcache] |
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| 453 | typename iss_t::DataResponse * drsp ; //[m_nb_dcache] |
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| 454 | bool * dreq_cached ; //[m_nb_dcache] |
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| 455 | uint32_t * dreq_num_cpu; //[m_nb_dcache] |
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[2] | 456 | |
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[140] | 457 | const uint32_t m_num_cache_LSB; |
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| 458 | const uint32_t m_num_cache_MSB; |
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| 459 | addr_40 m_num_cache_LSB_mask; |
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| 460 | addr_40 m_num_cache_mask; |
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[2] | 461 | |
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| 462 | protected: |
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| 463 | SC_HAS_PROCESS(VciCcXCacheWrapperV4); |
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| 464 | |
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| 465 | public: |
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| 466 | |
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| 467 | VciCcXCacheWrapperV4( |
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| 468 | sc_module_name insname, |
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| 469 | int proc_id, |
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| 470 | const soclib::common::MappingTable &mtp, |
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| 471 | const soclib::common::MappingTable &mtc, |
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| 472 | const soclib::common::IntTab &initiator_index_rw, |
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| 473 | const soclib::common::IntTab &initiator_index_c, |
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| 474 | const soclib::common::IntTab &target_index, |
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[140] | 475 | size_t nb_cpu, |
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| 476 | size_t nb_cache, |
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[2] | 477 | size_t icache_ways, |
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| 478 | size_t icache_sets, |
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| 479 | size_t icache_words, |
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| 480 | size_t dcache_ways, |
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| 481 | size_t dcache_sets, |
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[134] | 482 | size_t dcache_words, |
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| 483 | size_t wbuf_nwords, |
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| 484 | size_t wbuf_nlines, |
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| 485 | size_t wbuf_timeout |
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| 486 | ); |
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[2] | 487 | |
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| 488 | ~VciCcXCacheWrapperV4(); |
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| 489 | |
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[118] | 490 | void print_trace(size_t mode = 0); |
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[2] | 491 | void print_cpi(); |
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| 492 | void print_stats(); |
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| 493 | |
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[134] | 494 | // #if CC_XCACHE_WRAPPER_STOP_SIMULATION |
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| 495 | void stop_simulation (uint32_t); |
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| 496 | // #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION |
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| 497 | |
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[2] | 498 | private: |
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| 499 | |
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| 500 | void transition(); |
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| 501 | void genMoore(); |
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| 502 | |
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[140] | 503 | uint32_t get_num_cache (addr_40 & addr); |
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| 504 | uint32_t get_num_cache_only(addr_40 addr); |
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| 505 | void set_num_cache (addr_40 & addr, uint32_t num_cache); |
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| 506 | addr_40 set_num_cache_only(addr_40 addr, uint32_t num_cache); |
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| 507 | |
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| 508 | soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
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[2] | 509 | soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
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| 510 | }; |
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| 511 | |
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| 512 | }} |
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| 513 | |
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| 514 | #endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H */ |
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| 515 | |
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| 516 | // Local Variables: |
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| 517 | // tab-width: 4 |
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| 518 | // c-basic-offset: 4 |
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| 519 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 520 | // indent-tabs-mode: nil |
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| 521 | // End: |
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| 522 | |
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| 523 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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