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vci_cc_xcache_wrapper_v4.h @ 147

Last change on this file since 147 was 147, checked in by alain, 13 years ago
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1	/* -- c++ --
2	*
3	* SOCLIB_LGPL_HEADER_BEGIN
4	*
5	* This file is part of SoCLib, GNU LGPLv2.1.
6	*
7	* SoCLib is free software; you can redistribute it and/or modify it
8	* under the terms of the GNU Lesser General Public License as published
9	* by the Free Software Foundation; version 2.1 of the License.
10	*
11	* SoCLib is distributed in the hope that it will be useful, but
12	* WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with SoCLib; if not, write to the Free Software
18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19	* 02110-1301 USA
20	*
21	* SOCLIB_LGPL_HEADER_END
22	*
23	* Copyright (c) UPMC, Lip6, SoC
24	* Alain Greiner <alain.greiner@lip6.fr>, 2008
25	*
26	* Maintainers: alain
27	*/
28
29	#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
30	#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
31
32	#include <inttypes.h>
33	#include <systemc>
34	#include <queue>
35	#include "caba_base_module.h"
36	#include "multi_write_buffer.h"
37	#include "generic_cache.h"
38	#include "vci_initiator.h"
39	#include "vci_target.h"
40	#include "mapping_table.h"
41	#include "static_assert.h"
42
43	/*
44	* CC_XCACHE_WRAPPER_SELECT_VICTIM :
45	* The selection and the update of cache (after a read miss)
46	* are separated in two step
47	* Also, the cleanup can be send in parallel at the read miss.
48	*
49	* CC_XCACHE_WRAPPER_FIFO_RSP
50	* Two simple fifo (each 2x32 depth) receive the cache line from
51	* RAM. Instead of two buffers (m_icache_words and m_dcache_words)
52	*
53	* CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
54	* Update cache in "2*cache_words" cycles (read+mask, write)
55	*
56	* CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
57	* Update cache with only modified data (be != 0)
58	*
59	* CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME
60	* Write buffer scheme for update step :
61	* 1 - multi_scan
62	* 2 - round_robin_scan
63	* 3 - one_scan
64	* else - default scheme
65	*
66	* CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY
67	* Write buffer access is conditionnal with dcache_miss_req and icache_miss_req
68	* 1 - two access authorized
69	* 2 - one access with static priority (dcache prior)
70	* 3 - one access with static priority (icache prior)
71	* 4 - one access with round robin priority
72	*
73	* CC_XCACHE_WRAPPER_STOP_SIMULATION :
74	* stop simulation if processor is stall after a long time
75	* (configurable with "stop_simulation" function)
76	*
77	* CC_XCACHE_WRAPPER_DEBUG :
78	* Add log to help the debugging
79	*
80	* CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN :
81	* Number of cycle before to prinf debug message
82	*
83	* CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
84	* Print transaction between the cpu and the cache
85	*/
86
87	// implementation
88	#ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM
89	#define CC_XCACHE_WRAPPER_SELECT_VICTIM 0
90	#endif
91	#ifndef CC_XCACHE_WRAPPER_FIFO_RSP
92	#define CC_XCACHE_WRAPPER_FIFO_RSP 0
93	#endif
94	#ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
95	#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1
96	#endif
97	#ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
98	#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1
99	#endif
100	#ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME
101	#define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 0
102	#endif
103	#ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY
104	#define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 2
105	#endif
106	// debugging
107	#ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION
108	#define CC_XCACHE_WRAPPER_STOP_SIMULATION 1
109	#endif
110	#ifndef CC_XCACHE_WRAPPER_DEBUG
111	#define CC_XCACHE_WRAPPER_DEBUG 0
112	#endif
113	#ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN
114	#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 200000
115	#endif
116	#ifndef CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
117	#define CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 0
118	#endif
119
120	namespace soclib {
121	namespace caba {
122
123	using namespace sc_core;
124
125	////////////////////////////////////////////
126	template<typename vci_param, typename iss_t>
127	class VciCcXCacheWrapperV4
128	///////////////////////////////////////////
129	: public soclib::caba::BaseModule
130	{
131	typedef sc_dt::sc_uint<40> addr_40;
132	typedef sc_dt::sc_uint<64> data_64;
133	typedef uint32_t data_t;
134	typedef uint32_t tag_t;
135	typedef uint32_t be_t;
136	typedef typename vci_param::fast_addr_t vci_addr_t;
137
138	enum dcache_fsm_state_e {
139	DCACHE_IDLE,
140	DCACHE_WRITE_UPDT,
141	#if CC_XCACHE_WRAPPER_SELECT_VICTIM
142	DCACHE_MISS_VICTIM,
143	#endif
144	DCACHE_MISS_WAIT,
145	DCACHE_MISS_UPDT,
146	DCACHE_UNC_WAIT,
147	DCACHE_SC_WAIT,
148	DCACHE_INVAL,
149	DCACHE_SYNC,
150	DCACHE_ERROR,
151	DCACHE_CC_CHECK,
152	DCACHE_CC_INVAL,
153	DCACHE_CC_UPDT,
154	DCACHE_CC_CLEANUP,
155	};
156
157	enum icache_fsm_state_e {
158	ICACHE_IDLE,
159	#if CC_XCACHE_WRAPPER_SELECT_VICTIM
160	ICACHE_MISS_VICTIM,
161	#endif
162	ICACHE_MISS_WAIT,
163	ICACHE_MISS_UPDT,
164	ICACHE_UNC_WAIT,
165	ICACHE_ERROR,
166	ICACHE_CC_CLEANUP,
167	ICACHE_CC_CHECK,
168	ICACHE_CC_INVAL,
169	ICACHE_CC_UPDT,
170	};
171
172	enum cmd_fsm_state_e {
173	CMD_IDLE,
174	CMD_INS_MISS,
175	CMD_INS_UNC,
176	CMD_DATA_MISS,
177	CMD_DATA_UNC,
178	CMD_DATA_WRITE,
179	CMD_DATA_SC,
180	};
181
182	enum rsp_fsm_state_e {
183	RSP_IDLE,
184	RSP_INS_MISS,
185	RSP_INS_UNC,
186	RSP_DATA_MISS,
187	RSP_DATA_UNC,
188	RSP_DATA_WRITE,
189	RSP_DATA_SC,
190	};
191
192	enum tgt_fsm_state_e {
193	TGT_IDLE,
194	TGT_UPDT_WORD,
195	TGT_UPDT_DATA,
196	TGT_REQ_BROADCAST,
197	TGT_REQ_ICACHE,
198	TGT_REQ_DCACHE,
199	TGT_RSP_BROADCAST,
200	TGT_RSP_ICACHE,
201	TGT_RSP_DCACHE,
202	};
203
204	enum cleanup_fsm_state_e {
205	CLEANUP_IDLE,
206	CLEANUP_DCACHE,
207	CLEANUP_ICACHE,
208	};
209
210	enum transaction_type_c_e {
211	// convention with memcache
212	TYPE_DATA_CLEANUP = 0x0,
213	TYPE_INS_CLEANUP = 0x1
214	};
215
216	enum transaction_type_rw_e {
217	// convention with memcache
218	// b0 : 1 if cached
219	// b1 : 1 if instruction
220	// b2 : 1 if sc
221	TYPE_DATA_UNC = 0x0,
222	TYPE_DATA_MISS = 0x1,
223	TYPE_INS_UNC = 0x2,
224	TYPE_INS_MISS = 0x3,
225	TYPE_DATA_SC = 0x4, // sc is data and no cached
226	};
227
228	public:
229
230	// PORTS
231	sc_in<bool> p_clk;
232	sc_in<bool> p_resetn;
233	sc_in<bool> p_irq[iss_t::n_irq];
234	soclib::caba::VciInitiator<vci_param> p_vci_ini_rw;
235	soclib::caba::VciInitiator<vci_param> p_vci_ini_c;
236	soclib::caba::VciTarget<vci_param> p_vci_tgt;
237
238	private:
239
240	// STRUCTURAL PARAMETERS
241	const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table;
242	const soclib::common::Segment m_segment;
243	iss_t m_iss;
244	const uint32_t m_srcid_rw;
245	const uint32_t m_srcid_c;
246
247	const size_t m_dcache_ways;
248	const size_t m_dcache_words;
249	const uint32_t m_dcache_words_shift;
250	const size_t m_dcache_yzmask;
251	const size_t m_icache_ways;
252	const size_t m_icache_words;
253	const uint32_t m_icache_words_shift;
254	const size_t m_icache_yzmask;
255	const size_t m_cache_words; // max between m_dcache_words and m_icache_words
256
257	#if CC_XCACHE_WRAPPER_STOP_SIMULATION
258	bool m_stop_simulation;
259	uint32_t m_stop_simulation_nb_frz_cycles_max;
260	uint32_t m_stop_simulation_nb_frz_cycles;
261	#endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
262
263	// REGISTERS
264	sc_signal<int> r_dcache_fsm;
265	sc_signal<int> r_dcache_fsm_save;
266	sc_signal<addr_40> r_dcache_addr_save;
267	sc_signal<data_t> r_dcache_wdata_save;
268	sc_signal<data_t> r_dcache_rdata_save;
269	sc_signal<int> r_dcache_type_save;
270	sc_signal<be_t> r_dcache_be_save;
271	sc_signal<bool> r_dcache_cached_save;
272	sc_signal<bool> r_dcache_cleanup_req;
273	sc_signal<addr_40> r_dcache_cleanup_line;
274	sc_signal<bool> r_dcache_miss_req;
275	sc_signal<size_t> r_dcache_miss_way;
276	sc_signal<size_t> r_dcache_miss_set;
277	sc_signal<bool> r_dcache_unc_req;
278	sc_signal<bool> r_dcache_sc_req;
279	sc_signal<bool> r_dcache_inval_rsp;
280	sc_signal<size_t> r_dcache_update_addr;
281	sc_signal<data_64> r_dcache_ll_data;
282	sc_signal<addr_40> r_dcache_ll_addr;
283	sc_signal<bool> r_dcache_ll_valid;
284	sc_signal<bool> r_dcache_previous_unc;
285
286	sc_signal<int> r_icache_fsm;
287	sc_signal<int> r_icache_fsm_save;
288	sc_signal<addr_40> r_icache_addr_save;
289	sc_signal<bool> r_icache_miss_req;
290	sc_signal<size_t> r_icache_miss_way;
291	sc_signal<size_t> r_icache_miss_set;
292	sc_signal<bool> r_icache_unc_req;
293	sc_signal<bool> r_icache_cleanup_req;
294	sc_signal<addr_40> r_icache_cleanup_line;
295	sc_signal<bool> r_icache_inval_rsp;
296	sc_signal<size_t> r_icache_update_addr;
297
298	sc_signal<int> r_vci_cmd_fsm;
299	sc_signal<size_t> r_vci_cmd_min;
300	sc_signal<size_t> r_vci_cmd_max;
301	sc_signal<size_t> r_vci_cmd_cpt;
302	sc_signal<bool> r_vci_cmd_dcache_prior;
303
304	sc_signal<int> r_vci_rsp_fsm;
305	sc_signal<bool> r_vci_rsp_ins_error;
306	sc_signal<bool> r_vci_rsp_data_error;
307	sc_signal<size_t> r_vci_rsp_cpt;
308	sc_signal<bool> r_vci_rsp_ack;
309
310	#if CC_XCACHE_WRAPPER_FIFO_RSP
311	std::queue<data_t> r_icache_miss_buf;
312	std::queue<data_t> r_dcache_miss_buf;
313	#else
314	bool *r_icache_miss_val; //[m_icache_words]
315	data_t *r_icache_miss_buf; //[m_icache_words]
316	bool *r_dcache_miss_val; //[m_dcache_words]
317	data_t *r_dcache_miss_buf; //[m_dcache_words]
318	#endif
319	sc_signal<bool> r_icache_buf_unc_valid;
320
321	data_t *r_tgt_buf; //[m_cache_words]
322	be_t *r_tgt_be; //[m_cache_words]
323	#if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
324	sc_signal<uint32_t> r_cache_word;
325	#endif
326
327	sc_signal<int> r_vci_tgt_fsm;
328	sc_signal<addr_40> r_tgt_addr;
329	sc_signal<size_t> r_tgt_word;
330	sc_signal<bool> r_tgt_update;
331	sc_signal<bool> r_tgt_update_data;
332	//sc_signal<bool> r_tgt_brdcast;
333	sc_signal<size_t> r_tgt_srcid;
334	sc_signal<size_t> r_tgt_pktid;
335	sc_signal<size_t> r_tgt_trdid;
336	//sc_signal<size_t> r_tgt_plen;
337	sc_signal<bool> r_tgt_icache_req;
338	sc_signal<bool> r_tgt_dcache_req;
339	sc_signal<bool> r_tgt_icache_rsp;
340	sc_signal<bool> r_tgt_dcache_rsp;
341
342	sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network
343
344	MultiWriteBuffer<addr_40> r_wbuf;
345	GenericCache<vci_addr_t> r_icache;
346	GenericCache<vci_addr_t> r_dcache;
347
348	#if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
349	std::ofstream log_dcache_transaction_file;
350	#endif
351
352	// Activity counters
353	uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ
354	uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE
355	uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ
356	uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE
357
358	uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ
359	uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE
360	uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ
361	uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE
362
363	uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache)
364	uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache)
365	uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets
366	uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets
367	uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets
368	uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets
369	uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets
370
371	uint32_t m_cpt_frz_cycles; // * number of cycles where the cpu is frozen
372	uint32_t m_cpt_total_cycles; // total number of cycles
373
374	uint32_t m_cpt_data_read; // number of data read
375	uint32_t m_cpt_data_read_miss; // number of data read miss
376	uint32_t m_cpt_data_read_uncached; // number of data read uncached
377	uint32_t m_cpt_data_write; // number of data write
378	uint32_t m_cpt_data_write_miss; // number of data write miss
379	uint32_t m_cpt_data_write_uncached; // number of data write uncached
380	uint32_t m_cpt_ins_miss; // * number of instruction miss
381
382	uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer
383	uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss
384	uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read
385	uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss
386
387	uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions
388	uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions
389	uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions
390	uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions
391
392	uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions
393	uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions
394	uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions
395	uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions
396	uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions
397
398	protected:
399	SC_HAS_PROCESS(VciCcXCacheWrapperV4);
400
401	public:
402
403	VciCcXCacheWrapperV4(
404	sc_module_name insname,
405	int proc_id,
406	const soclib::common::MappingTable &mtp,
407	const soclib::common::MappingTable &mtc,
408	const soclib::common::IntTab &initiator_index_rw,
409	const soclib::common::IntTab &initiator_index_c,
410	const soclib::common::IntTab &target_index,
411	size_t icache_ways,
412	size_t icache_sets,
413	size_t icache_words,
414	size_t dcache_ways,
415	size_t dcache_sets,
416	size_t dcache_words,
417	size_t wbuf_nwords,
418	size_t wbuf_nlines,
419	size_t wbuf_timeout
420	);
421
422	~VciCcXCacheWrapperV4();
423
424	void print_trace(size_t mode = 0);
425	void print_cpi();
426	void print_stats();
427
428	// #if CC_XCACHE_WRAPPER_STOP_SIMULATION
429	void stop_simulation (uint32_t);
430	// #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
431
432	private:
433
434	void transition();
435	void genMoore();
436
437	soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
438	soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
439	};
440
441	}}
442
443	#endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H */
444
445	// Local Variables:
446	// tab-width: 4
447	// c-basic-offset: 4
448	// c-file-offsets:((innamespace . 0)(inline-open . 0))
449	// indent-tabs-mode: nil
450	// End:
451
452	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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