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vci_cc_xcache_wrapper_v4.cpp @ 90

Last change on this file since 90 was 90, checked in by alain, 14 years ago
Introducing a print_trace() method for debug.
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1	/* -- c++ --
2	*
3	* SOCLIB_LGPL_HEADER_BEGIN
4	*
5	* This file is part of SoCLib, GNU LGPLv2.1.
6	*
7	* SoCLib is free software; you can redistribute it and/or modify it
8	* under the terms of the GNU Lesser General Public License as published
9	* by the Free Software Foundation; version 2.1 of the License.
10	*
11	* SoCLib is distributed in the hope that it will be useful, but
12	* WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with SoCLib; if not, write to the Free Software
18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19	* 02110-1301 USA
20	*
21	* SOCLIB_LGPL_HEADER_END
22	*
23	* Copyright (c) UPMC, Lip6, SoC
24	* Alain Greiner <alain.greiner@lip6.fr>, 2008
25	*
26	* Maintainers: alain eric.guthmuller@polytechnique.edu nipo
27	*/
28
29	/////////////////////////////////////////////////////////////////////////////
30	// History
31	// - 25/04/2008
32	// The existing vci_xcache component has been extended to include
33	// a VCI target port to support a directory based coherence protocol.
34	// Two types of packets can be send by the L2 cache to the L1 cache
35	// * INVALIDATE packets : length = 1
36	// * UPDATE packets : length = n + 2
37	// The CLEANUP packets are sent by the L1 cache to the L2 cache,
38	// to signal a replaced cache line.
39	// - 12/08/2008
40	// The vci_cc_xcache_wrapper component instanciates directly the processsor
41	// iss, in order to supress the processor/cache interface.
42	// According to the VCI advanced specification, this component uses one
43	// word VCI CMD packets for MISS transactions, and accept one word VCI RSP
44	// packets for Write burst transactions.
45	// The write buffer has been modified to use the WriteBuffer object.
46	// A VCI write burst is constructed when two conditions are satisfied :
47	// The processor make strictly successive write requests, and they are
48	// in the same cache line. The write buffer performs re-ordering, to
49	// respect the contiguous addresses VCI constraint. In case of several
50	// WRITE_WORD requests in the same word, only the last request is conserved.
51	// In case of several WRITE_HALF or WRITE_WORD requests in the same word,
52	// the requests are merged in the same word. In case of uncached write
53	// requests, each request is transmited as a single VCI transaction.
54	// Both the data & instruction caches can be flushed in one single cycle.
55	///////////////////////////////////////////////////////////////////////////////
56
57	#include <cassert>
58	#include "arithmetics.h"
59	#include "../include/vci_cc_xcache_wrapper_v4.h"
60
61	//#define DEBUG_CC_XCACHE_WRAPPER 1
62
63	namespace soclib {
64	namespace caba {
65
66	namespace {
67	const char *dcache_fsm_state_str[] = {
68	"DCACHE_IDLE",
69	"DCACHE_WRITE_UPDT",
70	"DCACHE_WRITE_REQ",
71	"DCACHE_MISS_WAIT",
72	"DCACHE_MISS_UPDT",
73	"DCACHE_UNC_WAIT",
74	"DCACHE_SC_WAIT",
75	"DCACHE_INVAL",
76	"DCACHE_ERROR",
77	"DCACHE_CC_CHECK",
78	"DCACHE_CC_INVAL",
79	"DCACHE_CC_UPDT",
80	"DCACHE_CC_CLEANUP",
81	};
82	const char *icache_fsm_state_str[] = {
83	"ICACHE_IDLE",
84	"ICACHE_MISS_WAIT",
85	"ICACHE_MISS_UPDT",
86	"ICACHE_UNC_WAIT",
87	"ICACHE_ERROR",
88	"ICACHE_CC_CLEANUP",
89	"ICACHE_CC_CHECK",
90	"ICACHE_CC_INVAL",
91	"ICACHE_CC_UPDT",
92	};
93	const char *cmd_fsm_state_str[] = {
94	"CMD_IDLE",
95	"CMD_INS_MISS",
96	"CMD_INS_UNC",
97	"CMD_DATA_MISS",
98	"CMD_DATA_UNC",
99	"CMD_DATA_WRITE",
100	"CMD_DATA_SC",
101	"CMD_INS_CLEANUP",
102	"CMD_DATA_CLEANUP",
103	};
104	const char *rsp_fsm_state_str[] = {
105	"RSP_IDLE",
106	"RSP_INS_MISS",
107	"RSP_INS_UNC",
108	"RSP_DATA_MISS",
109	"RSP_DATA_UNC",
110	"RSP_DATA_WRITE",
111	"RSP_DATA_SC",
112	"RSP_INS_CLEANUP",
113	"RSP_DATA_CLEANUP",
114	};
115	const char *tgt_fsm_state_str[] = {
116	"TGT_IDLE",
117	"TGT_UPDT_WORD",
118	"TGT_UPDT_DATA",
119	"TGT_REQ_BROADCAST",
120	"TGT_REQ_ICACHE",
121	"TGT_REQ_DCACHE",
122	"TGT_RSP_BROADCAST",
123	"TGT_RSP_ICACHE",
124	"TGT_RSP_DCACHE",
125	};
126	}
127
128	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcXCacheWrapperV4<vci_param, iss_t>
129
130	using soclib::common::uint32_log2;
131
132	/////////////////////////////////
133	tmpl(/**/)::VciCcXCacheWrapperV4(
134	/////////////////////////////////
135	sc_module_name name,
136	int proc_id,
137	const soclib::common::MappingTable &mtp,
138	const soclib::common::MappingTable &mtc,
139	const soclib::common::IntTab &initiator_index_rw,
140	const soclib::common::IntTab &initiator_index_c,
141	const soclib::common::IntTab &target_index,
142	size_t icache_ways,
143	size_t icache_sets,
144	size_t icache_words,
145	size_t dcache_ways,
146	size_t dcache_sets,
147	size_t dcache_words )
148	:
149	soclib::caba::BaseModule(name),
150
151	p_clk("clk"),
152	p_resetn("resetn"),
153	p_vci_ini_rw("vci_ini_rw"),
154	p_vci_ini_c("vci_ini_c"),
155	p_vci_tgt("vci_tgt"),
156
157	m_cacheability_table(mtp.getCacheabilityTable<vci_addr_t>()),
158	m_segment(mtc.getSegment(target_index)),
159	m_iss(this->name(), proc_id),
160	m_srcid_rw(mtp.indexForId(initiator_index_rw)),
161	m_srcid_c(mtc.indexForId(initiator_index_c)),
162
163	m_dcache_ways(dcache_ways),
164	m_dcache_words(dcache_words),
165	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
166	m_icache_ways(icache_ways),
167	m_icache_words(icache_words),
168	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
169
170	r_dcache_fsm("r_dcache_fsm"),
171	r_dcache_fsm_save("r_dcache_fsm_save"),
172	r_dcache_addr_save("r_dcache_addr_save"),
173	r_dcache_wdata_save("r_dcache_wdata_save"),
174	r_dcache_rdata_save("r_dcache_rdata_save"),
175	r_dcache_ll_data("r_dcache_ll_data"),
176	r_dcache_ll_addr("r_dcache_ll_addr"),
177	r_dcache_ll_valid("r_dcache_ll_valid"),
178	r_dcache_type_save("r_dcache_type_save"),
179	r_dcache_be_save("r_dcache_be_save"),
180	r_dcache_cached_save("r_dcache_cached_save"),
181	r_dcache_cleanup_req("r_dcache_cleanup_req"),
182	r_dcache_cleanup_line("r_dcache_cleanup_line"),
183	r_dcache_miss_req("r_dcache_miss_req"),
184	r_dcache_unc_req("r_dcache_unc_req"),
185	r_dcache_write_req("r_dcache_write_req"),
186
187	r_icache_fsm("r_icache_fsm"),
188	r_icache_fsm_save("r_icache_fsm_save"),
189	r_icache_addr_save("r_icache_addr_save"),
190	r_icache_miss_req("r_icache_miss_req"),
191	r_icache_cleanup_req("r_icache_cleanup_req"),
192	r_icache_cleanup_line("r_icache_cleanup_line"),
193
194	r_vci_cmd_fsm("r_vci_cmd_fsm"),
195	r_vci_cmd_min("r_vci_cmd_min"),
196	r_vci_cmd_max("r_vci_cmd_max"),
197	r_vci_cmd_cpt("r_vci_cmd_cpt"),
198
199	r_vci_rsp_fsm("r_vci_rsp_fsm"),
200	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
201	r_vci_rsp_data_error("r_vci_rsp_data_error"),
202	r_vci_rsp_cpt("r_vci_rsp_cpt"),
203
204	r_icache_buf_unc_valid("r_icache_buf_unc_valid"),
205
206	r_vci_tgt_fsm("r_vci_tgt_fsm"),
207	r_tgt_addr("r_tgt_addr"),
208	r_tgt_word("r_tgt_word"),
209	r_tgt_update("r_tgt_update"),
210	r_tgt_srcid("r_tgt_srcid"),
211	r_tgt_pktid("r_tgt_pktid"),
212	r_tgt_trdid("r_tgt_trdid"),
213	r_tgt_icache_req("r_tgt_icache_req"),
214	r_tgt_dcache_req("r_tgt_dcache_req"),
215
216	r_wbuf("r_wbuf", dcache_words ),
217	r_icache("icache", icache_ways, icache_sets, icache_words),
218	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
219
220	{
221	r_icache_miss_buf = new data_t[icache_words];
222	r_dcache_miss_buf = new data_t[dcache_words];
223	r_tgt_buf = new data_t[dcache_words];
224	r_tgt_be = new be_t[dcache_words];
225
226	SC_METHOD(transition);
227	dont_initialize();
228	sensitive << p_clk.pos();
229
230	SC_METHOD(genMoore);
231	dont_initialize();
232	sensitive << p_clk.neg();
233
234
235	typename iss_t::CacheInfo cache_info;
236	cache_info.has_mmu = false;
237	cache_info.icache_line_size = icache_words*sizeof(data_t);
238	cache_info.icache_assoc = icache_ways;
239	cache_info.icache_n_lines = icache_sets;
240	cache_info.dcache_line_size = dcache_words*sizeof(data_t);
241	cache_info.dcache_assoc = dcache_ways;
242	cache_info.dcache_n_lines = dcache_sets;
243	m_iss.setCacheInfo(cache_info);
244	} // end constructor
245
246	///////////////////////////////////
247	tmpl(/**/)::~VciCcXCacheWrapperV4()
248	///////////////////////////////////
249	{
250	delete [] r_icache_miss_buf;
251	delete [] r_dcache_miss_buf;
252	delete [] r_tgt_be;
253	delete [] r_tgt_buf;
254	}
255
256	////////////////////////
257	tmpl(void)::print_cpi()
258	////////////////////////
259	{
260	std::cout << "CPU " << m_srcid_rw << " : CPI = "
261	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
262	}
263	////////////////////////
264	tmpl(void)::print_stats()
265	////////////////////////
266	{
267	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
268	std::cout << "------------------------------------" << std:: dec << std::endl;
269	std::cout << "CPU " << m_srcid_rw << " / Time = " << m_cpt_total_cycles << std::endl;
270	std::cout << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl ;
271	std::cout << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl ;
272	std::cout << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl;
273	std::cout << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl ;
274	std::cout << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl ;
275	std::cout << "- IMISS_RATE = " << (float)m_cpt_ins_miss/run_cycles << std::endl;
276	std::cout << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl ;
277	std::cout << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl;
278	std::cout << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl;
279	std::cout << "- DMISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl;
280	std::cout << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl;
281	std::cout << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl;
282	std::cout << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl;
283	std::cout << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl;
284	std::cout << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl;
285	std::cout << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl;
286	}
287	/////////////////////////
288	tmpl(void)::print_trace()
289	/////////////////////////
290	{
291	typename iss_t::InstructionRequest ireq;
292	typename iss_t::DataRequest dreq;
293	m_iss.getRequests( ireq, dreq );
294
295	std::cout << std::dec << "CC_XCACHE_WRAPPER " << m_srcid_rw << std::endl;
296	std::cout << " cache state : " << icache_fsm_state_str[r_icache_fsm] << " / "
297	<< dcache_fsm_state_str[r_dcache_fsm] << " / "
298	<< cmd_fsm_state_str[r_vci_cmd_fsm] << " / "
299	<< rsp_fsm_state_str[r_vci_rsp_fsm] << " / "
300	<< tgt_fsm_state_str[r_vci_tgt_fsm] << std::endl;
301	std::cout << " proc state : PC = " << ireq.addr << " / AD = " << dreq.addr
302	<< " / V = " << dreq.valid << " TYPE = " << dreq.type << std::endl;
303	}
304	//////////////////////////
305	tmpl(void)::transition()
306	//////////////////////////
307	{
308	if ( ! p_resetn.read() ) {
309
310	m_iss.reset();
311
312	// FSM states
313	r_dcache_fsm = DCACHE_IDLE;
314	r_icache_fsm = ICACHE_IDLE;
315	r_vci_cmd_fsm = CMD_IDLE;
316	r_vci_rsp_fsm = RSP_IDLE;
317	r_vci_tgt_fsm = TGT_IDLE;
318
319	// write buffer & caches
320	r_wbuf.reset();
321	r_icache.reset();
322	r_dcache.reset();
323
324	// synchronisation flip-flops from ICACHE & DCACHE FSMs to VCI FSMs
325	r_icache_miss_req = false;
326	r_icache_unc_req = false;
327	r_icache_cleanup_req = false;
328	r_dcache_miss_req = false;
329	r_dcache_unc_req = false;
330	r_dcache_sc_req = false;
331	r_dcache_write_req = false;
332	r_dcache_cleanup_req = false;
333
334	// synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs
335	r_tgt_icache_req = false;
336	r_tgt_dcache_req = false;
337
338	// internal messages in DCACHE et ICACHE FSMs
339	r_icache_inval_rsp = false;
340	r_dcache_inval_rsp = false;
341
342	// error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs
343	r_dcache_ll_valid = false;
344	r_icache_buf_unc_valid = false;
345	r_vci_rsp_data_error = false;
346	r_vci_rsp_ins_error = false;
347
348	// activity counters
349	m_cpt_dcache_data_read = 0;
350	m_cpt_dcache_data_write = 0;
351	m_cpt_dcache_dir_read = 0;
352	m_cpt_dcache_dir_write = 0;
353	m_cpt_icache_data_read = 0;
354	m_cpt_icache_data_write = 0;
355	m_cpt_icache_dir_read = 0;
356	m_cpt_icache_dir_write = 0;
357
358	m_cpt_cc_update = 0;
359	m_cpt_cc_inval = 0;
360
361	m_cpt_frz_cycles = 0;
362	m_cpt_total_cycles = 0;
363
364	m_cpt_read = 0;
365	m_cpt_write = 0;
366	m_cpt_data_miss = 0;
367	m_cpt_ins_miss = 0;
368	m_cpt_unc_read = 0;
369	m_cpt_write_cached = 0;
370
371	m_cost_write_frz = 0;
372	m_cost_data_miss_frz = 0;
373	m_cost_unc_read_frz = 0;
374	m_cost_ins_miss_frz = 0;
375
376	m_cpt_imiss_transaction = 0;
377	m_cpt_dmiss_transaction = 0;
378	m_cpt_unc_transaction = 0;
379	m_cpt_write_transaction = 0;
380
381	m_cost_imiss_transaction = 0;
382	m_cost_dmiss_transaction = 0;
383	m_cost_unc_transaction = 0;
384	m_cost_write_transaction = 0;
385	m_length_write_transaction = 0;
386
387	return;
388	}
389
390	#if DEBUG_CC_XCACHE_WRAPPER
391	std::cout << "--------------------------------------------" << std::endl;
392	std::cout << std::dec << "CC_XCACHE_WRAPPER " << m_srcid_rw << " / Time = " << m_cpt_total_cycles << std::endl;
393	std::cout << " tgt fsm = " << tgt_fsm_state_str[r_vci_tgt_fsm] << std::endl
394	<< " dcache fsm = " << dcache_fsm_state_str[r_dcache_fsm] << std::endl
395	<< " icache fsm = " << icache_fsm_state_str[r_icache_fsm] << std::endl
396	<< " cmd fsm = " << cmd_fsm_state_str[r_vci_cmd_fsm] << std::endl
397	<< " rsp fsm = " << rsp_fsm_state_str[r_vci_rsp_fsm] << std::endl;
398	#endif
399
400	m_cpt_total_cycles++;
401
402	/////////////////////////////////////////////////////////////////////
403	// The TGT_FSM controls the following ressources:
404	// - r_vci_tgt_fsm
405	// - r_tgt_buf[nwords]
406	// - r_tgt_be[nwords]
407	// - r_tgt_update
408	// - r_tgt_word
409	// - r_tgt_addr
410	// - r_tgt_srcid
411	// - r_tgt_trdid
412	// - r_tgt_pktid
413	// All VCI commands must be CMD_WRITE.
414	// If the VCI address offset is null, the command is an invalidate
415	// request. It is an update request otherwise.
416	// The VCI_TGT FSM stores the external request arguments in the
417	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
418	// & r_tgt_dcache_req flip-flops to signal the external request to
419	// the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
420	// of the update or invalidate request in the RSP state.
421	// - for an invalidate request the VCI packet length is 1 word.
422	// The WDATA field contains the line index (i.e. the Z & Y fields).
423	// - for an update request the VCI packet length is (n+2) words.
424	// The WDATA field of the first VCI word contains the line number.
425	// The WDATA field of the second VCI word contains the word index.
426	// The WDATA field of the n following words contains the values.
427	// - for both invalidate & update requests, the VCI response
428	// is one single word.
429	// In case of errors in the VCI command packet, the simulation
430	// is stopped with an error message.
431	/////////////////////////////////////////////////////////////////////
432
433	switch(r_vci_tgt_fsm) {
434
435	case TGT_IDLE:
436	if ( p_vci_tgt.cmdval.read() )
437	{
438	addr_40 address = p_vci_tgt.address.read();
439
440	if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE)
441	{
442	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
443	std::cout << "the received VCI command from " << std::dec << p_vci_tgt.srcid.read() << " is not a write" << std::endl;
444	exit(0);
445	}
446
447	// multi-update or multi-invalidate for data type
448	if ( ((address&0x3) != 0x3) && (! m_segment.contains(address)) )
449	{
450	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
451	std::cout << "out of segment VCI command received for a multi-updt or multi-inval request" << std::endl;
452	exit(0);
453	}
454
455	r_tgt_addr = (((addr_40) ((p_vci_tgt.be.read() & 0x3) << 32)) \|
456	((addr_40) (p_vci_tgt.wdata.read()))) * m_dcache_words * 4;
457	r_tgt_srcid = p_vci_tgt.srcid.read();
458	r_tgt_trdid = p_vci_tgt.trdid.read();
459	r_tgt_pktid = p_vci_tgt.pktid.read();
460	r_tgt_plen = p_vci_tgt.plen.read();
461
462	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
463	{
464	if ( ! p_vci_tgt.eop.read() )
465	{
466	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
467	std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
468	exit(0);
469	}
470	r_tgt_update = false;
471	r_tgt_brdcast= true;
472	r_vci_tgt_fsm = TGT_REQ_BROADCAST;
473	m_cpt_cc_inval++ ;
474	}
475	else // multi-update or multi-invalidate for data type
476	{
477	uint32_t cell = address - m_segment.baseAddress(); // addr_40
478	r_tgt_brdcast = false;
479	if (cell == 0)
480	{ // invalidate data
481	if ( ! p_vci_tgt.eop.read() )
482	{
483	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
484	std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
485	exit(0);
486	}
487	r_tgt_update = false;
488	r_vci_tgt_fsm = TGT_REQ_DCACHE;
489	m_cpt_cc_inval++ ;
490	}
491	else if (cell == 4) // invalidate instruction
492	{
493	if ( ! p_vci_tgt.eop.read() )
494	{
495	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
496	std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
497	exit(0);
498	}
499	r_tgt_update = false;
500	r_vci_tgt_fsm = TGT_REQ_ICACHE;
501	m_cpt_cc_inval++ ;
502	}
503	else if ( (cell == 8) \|\| (cell==12) ) // update data or instruction
504	{
505	if ( p_vci_tgt.eop.read() )
506	{
507	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
508	std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
509	exit(0);
510	}
511	if(cell == 8)
512	r_tgt_update_data = true;
513	else
514	r_tgt_update_data = false;
515	r_tgt_update = true;
516	r_vci_tgt_fsm = TGT_UPDT_WORD;
517	m_cpt_cc_update++ ;
518	}
519
520	} // end if address
521	} // end if cmdval
522	break;
523
524	case TGT_UPDT_WORD:
525	if (p_vci_tgt.cmdval.read())
526	{
527	if ( p_vci_tgt.eop.read() )
528	{
529	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
530	std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
531	exit(0);
532	}
533	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = 0;
534	r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
535	#ifdef COHERENCE_DEBUG
536	std::cout << "PROC " << m_srcid_rw << " update, line : " << std::hex << r_tgt_addr.read() << " word : " << p_vci_tgt.wdata.read() << std::dec << std::endl;
537	#endif
538	r_vci_tgt_fsm = TGT_UPDT_DATA;
539	}
540	break;
541
542	case TGT_UPDT_DATA:
543	if (p_vci_tgt.cmdval.read())
544	{
545	size_t word = r_tgt_word.read();
546	if ( word >= m_dcache_words )
547	{
548	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
549	std::cout << "the reveived MULTI-UPDATE command length is wrong" << std::endl;
550	exit(0);
551	}
552	#ifdef COHERENCE_DEBUG
553	std::cout << "PROC " << m_srcid_rw << " update, data : " << p_vci_tgt.wdata.read() << " be : " << std::hex << p_vci_tgt.be.read() << std::dec << std::endl;
554	#endif
555	r_tgt_buf[word] = p_vci_tgt.wdata.read();
556	r_tgt_be[word] = p_vci_tgt.be.read();
557	r_tgt_word = word + 1;
558	if (p_vci_tgt.eop.read()){
559	if(r_tgt_update_data.read()){
560	r_vci_tgt_fsm = TGT_REQ_DCACHE;
561	} else {
562	r_vci_tgt_fsm = TGT_REQ_ICACHE;
563	}
564	}
565	}
566	break;
567
568	case TGT_REQ_BROADCAST:
569	if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
570	{
571	r_vci_tgt_fsm = TGT_RSP_BROADCAST;
572	r_tgt_icache_req = true;
573	r_tgt_dcache_req = true;
574	}
575	break;
576	////////////////////
577	case TGT_REQ_ICACHE:
578	{
579	if ( !r_tgt_icache_req.read() )
580	{
581	r_vci_tgt_fsm = TGT_RSP_ICACHE;
582	r_tgt_icache_req = true;
583	}
584	break;
585	}
586
587	case TGT_REQ_DCACHE:
588	if ( !r_tgt_dcache_req.read() )
589	{
590	r_vci_tgt_fsm = TGT_RSP_DCACHE;
591	r_tgt_dcache_req = true;
592	}
593	break;
594
595	case TGT_RSP_BROADCAST:
596	if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
597	{
598	// one response
599	if ( !r_tgt_icache_rsp \|\| !r_tgt_dcache_rsp )
600	{
601	if ( p_vci_tgt.rspack.read() )
602	{
603	r_vci_tgt_fsm = TGT_IDLE;
604	r_tgt_icache_rsp = false;
605	r_tgt_dcache_rsp = false;
606	}
607	}
608
609	// if data and instruction have the inval line, need two responses
610	if ( r_tgt_icache_rsp && r_tgt_dcache_rsp )
611	{
612	if ( p_vci_tgt.rspack.read() )
613	{
614	r_tgt_icache_rsp = false; // only reset one for respond the second time
615	}
616	}
617
618	// if there is no need for a response
619	if ( !r_tgt_icache_rsp && !r_tgt_dcache_rsp )
620	{
621	r_vci_tgt_fsm = TGT_IDLE;
622	}
623
624	}
625	break;
626	////////////////////
627	case TGT_RSP_ICACHE:
628	{
629	if ( (p_vci_tgt.rspack.read() \|\| !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() )
630	{
631	r_vci_tgt_fsm = TGT_IDLE;
632	r_tgt_icache_rsp = false;
633	}
634	break;
635	}
636
637	case TGT_RSP_DCACHE:
638	{
639	if ( (p_vci_tgt.rspack.read() \|\| !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() )
640	{
641	r_vci_tgt_fsm = TGT_IDLE;
642	r_tgt_dcache_rsp = false;
643	}
644	break;
645	}
646	} // end switch TGT_FSM
647
648	/////////////////////////////////////////////////////////////////////
649	// The ICACHE FSM controls the following ressources:
650	// - r_icache_fsm
651	// - r_icache_fsm_save
652	// - r_icache instruction cache access
653	// - r_icache_addr_save
654	// - r_icache_miss_req set
655	// - r_icache_unc_req set
656	// - r_icache_buf_unc_valid set
657	// - r_vci_rsp_ins_error reset
658	// - r_tgt_icache_req reset
659	// - ireq & irsp structures for communication with the processor
660	//
661	// 1/ External requests (update or invalidate) have highest priority.
662	// They are taken into account in the IDLE and WAIT states.
663	// As external hit should be extremly rare on the ICACHE,
664	// all external requests are handled as invalidate...
665	// In case of external request the ICACHE FSM goes to the CC_CHECK
666	// state to test the external hit, and returns in the
667	// pre-empted state after completion.
668	// 2/ Processor requests are taken into account only in the IDLE state.
669	// In case of MISS, or in case of uncached instruction, the FSM
670	// writes the missing address line in the r_icache_addr_save register
671	// and sets the r_icache_miss_req or the r_icache_unc_req flip-flops.
672	// These request flip-flops are reset by the VCI_RSP FSM
673	// when the VCI transaction is completed and the r_icache_buf_unc_valid
674	// is set in case of uncached access.
675	// In case of bus error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
676	// flip-flop. It is reset by the ICACHE FSM.
677	///////////////////////////////////////////////////////////////////////
678
679	typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
680	typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
681
682	typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
683	typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
684
685	m_iss.getRequests( ireq, dreq );
686
687	#if DEBUG_CC_XCACHE_WRAPPER
688	std::cout << " Instruction Request: " << ireq << std::endl;
689	#endif
690
691	switch(r_icache_fsm) {
692	/////////////////
693	case ICACHE_IDLE:
694	{
695	if ( r_tgt_icache_req ) { // external request
696	if ( ireq.valid ) m_cost_ins_miss_frz++;
697	r_icache_fsm = ICACHE_CC_CHECK;
698	r_icache_fsm_save = r_icache_fsm.read();
699	break;
700	}
701	if ( ireq.valid ) {
702	data_t icache_ins = 0;
703	bool icache_hit = false;
704	bool icache_cached = m_cacheability_table[(vci_addr_t)ireq.addr];
705	// icache_hit & icache_ins evaluation
706	if ( icache_cached ) {
707	icache_hit = r_icache.read((vci_addr_t) ireq.addr, &icache_ins);
708	} else {
709	icache_hit = ( r_icache_buf_unc_valid && ((addr_40) ireq.addr == (addr_40)r_icache_addr_save) );
710	icache_ins = r_icache_miss_buf[0];
711	}
712	if ( ! icache_hit ) {
713	m_cpt_ins_miss++;
714	m_cost_ins_miss_frz++;
715	r_icache_addr_save = (addr_40) ireq.addr;
716	if ( icache_cached ) {
717	r_icache_fsm = ICACHE_MISS_WAIT;
718	r_icache_miss_req = true;
719	} else {
720	r_icache_fsm = ICACHE_UNC_WAIT;
721	r_icache_unc_req = true;
722	}
723	} else {
724	r_icache_buf_unc_valid = false;
725	}
726	m_cpt_icache_dir_read += m_icache_ways;
727	m_cpt_icache_data_read += m_icache_ways;
728	irsp.valid = icache_hit;
729	irsp.instruction = icache_ins;
730	}
731	break;
732	}
733	//////////////////////
734	case ICACHE_MISS_WAIT:
735	{
736	m_cost_ins_miss_frz++;
737	if ( r_tgt_icache_req ) { // external request
738	r_icache_fsm = ICACHE_CC_CHECK;
739	r_icache_fsm_save = r_icache_fsm.read();
740	break;
741	}
742	if ( !r_icache_miss_req && !r_icache_inval_rsp ) { // Miss read response and no invalidation
743	if ( r_vci_rsp_ins_error ) {
744	r_icache_fsm = ICACHE_ERROR;
745	} else {
746	r_icache_fsm = ICACHE_MISS_UPDT;
747	}
748	}
749	if ( !r_icache_miss_req && r_icache_inval_rsp ) { // Miss read response and invalidation
750	if ( r_vci_rsp_ins_error ) {
751	r_icache_inval_rsp = false;
752	r_icache_fsm = ICACHE_ERROR;
753	} else {
754	r_icache_inval_rsp = false;
755	r_icache_fsm = ICACHE_CC_CLEANUP;
756	}
757	}
758	break;
759	}
760	/////////////////////
761	case ICACHE_UNC_WAIT:
762	{
763	m_cost_ins_miss_frz++;
764	if ( r_tgt_icache_req ) { // external request
765	r_icache_fsm = ICACHE_CC_CHECK;
766	r_icache_fsm_save = r_icache_fsm.read();
767	break;
768	}
769	if ( !r_icache_unc_req ) {
770	if ( r_vci_rsp_ins_error ) {
771	r_icache_fsm = ICACHE_ERROR;
772	} else {
773	r_icache_fsm = ICACHE_IDLE;
774	r_icache_buf_unc_valid = true;
775	}
776	}
777	break;
778	}
779	//////////////////
780	case ICACHE_ERROR:
781	{
782	r_icache_fsm = ICACHE_IDLE;
783	r_vci_rsp_ins_error = false;
784	irsp.error = true;
785	irsp.valid = true;
786	break;
787	}
788	//////////////////////
789	case ICACHE_MISS_UPDT:
790	{
791	if ( r_tgt_icache_req ) { // external request
792	r_icache_fsm = ICACHE_CC_CHECK;
793	r_icache_fsm_save = r_icache_fsm.read();
794	break;
795	}
796	if(!r_icache_cleanup_req.read() && !r_icache_inval_rsp){
797	vci_addr_t ad = 0;
798	ad = (vci_addr_t) r_icache_addr_save.read();
799	data_t* buf = r_icache_miss_buf;
800	vci_addr_t victim_index = 0;
801	m_cpt_icache_dir_write++;
802	m_cpt_icache_data_write++;
803	if ( ireq.valid ) m_cost_ins_miss_frz++;
804
805	r_icache_cleanup_req = r_icache.update(ad, buf, &victim_index);
806	r_icache_cleanup_line = (addr_40) victim_index;
807
808	r_icache_fsm = ICACHE_IDLE;
809	break;
810	}
811	if(r_icache_inval_rsp){
812	if ( ireq.valid ) m_cost_ins_miss_frz++;
813	r_icache_inval_rsp = false;
814	r_icache_fsm = ICACHE_CC_CLEANUP;
815	break;
816	}
817	if ( ireq.valid ) m_cost_ins_miss_frz++;
818	}
819	////////////////////
820	case ICACHE_CC_CLEANUP:
821	{
822	// external cache invalidate request
823	if ( r_tgt_icache_req )
824	{
825	r_icache_fsm = ICACHE_CC_CHECK;
826	r_icache_fsm_save = r_icache_fsm.read();
827	break;
828	}
829	// cleanup
830	if(!r_icache_cleanup_req){
831	r_icache_cleanup_req = true;
832	r_icache_cleanup_line = r_icache_addr_save.read() >> (uint32_log2(m_icache_words) + 2);
833	r_icache_fsm = ICACHE_IDLE;
834	}
835	break;
836	}
837	/////////////////////
838	case ICACHE_CC_CHECK: // read directory in case of invalidate or update request
839	{
840
841	m_cpt_icache_dir_read += m_icache_ways;
842	m_cpt_icache_data_read += m_icache_ways;
843	addr_40 ad = r_tgt_addr;
844	data_t icache_rdata = 0;
845
846	if(( ( r_icache_fsm_save == ICACHE_MISS_WAIT ) \|\| ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) &&
847	( (r_icache_addr_save.read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1)))) {
848	r_icache_inval_rsp = true;
849	r_tgt_icache_req = false;
850	if(r_tgt_update){ // Also send a cleanup and answer
851	r_tgt_icache_rsp = true;
852	} else { // Also send a cleanup but don't answer
853	r_tgt_icache_rsp = false;
854	}
855	r_icache_fsm = r_icache_fsm_save;
856	} else {
857	bool icache_hit = r_icache.read(ad, &icache_rdata);
858	if ( icache_hit && r_tgt_update ) {
859	r_icache_fsm = ICACHE_CC_UPDT;
860	// complete the line buffer in case of update
861	for(size_t i=0; i<m_icache_words; i++){
862	data_t rdata = 0;
863	r_icache.read(ad + i*4,&rdata);
864	data_t mask = vci_param::be2mask(r_tgt_be[i]);
865	r_tgt_buf[i] = (mask & r_tgt_buf[i]) \| (~mask & rdata);
866	}
867	} else if ( icache_hit && !r_tgt_update ) {
868	r_icache_fsm = ICACHE_CC_INVAL;
869	} else { // instruction not found (can happen)
870	r_tgt_icache_req = false;
871	if(r_tgt_update){
872	r_tgt_icache_rsp = true;
873	} else {
874	r_tgt_icache_rsp = false;
875	}
876	r_icache_fsm = r_icache_fsm_save;
877	}
878	}
879	break;
880	}
881	/////////////////////
882	case ICACHE_CC_INVAL:
883	{
884	addr_40 ad = r_tgt_addr;
885	if ( ireq.valid ) m_cost_ins_miss_frz++;
886	m_cpt_icache_dir_read += m_icache_ways;
887	r_tgt_icache_rsp = true;
888	r_icache.inval(ad);
889	r_tgt_icache_req = false;
890	r_icache_fsm = r_icache_fsm_save;
891	break;
892	}
893	/////////////////////
894	case ICACHE_CC_UPDT:
895	{
896	m_cpt_icache_dir_write++;
897	m_cpt_icache_data_write++;
898	addr_40 ad = r_tgt_addr.read();
899	data_t* buf = r_tgt_buf;
900	for(size_t i=0; i<m_icache_words;i++){
901	if(r_tgt_be[i]) r_icache.write( ad + i*4, buf[i]);
902	}
903	r_tgt_icache_req = false;
904	r_tgt_icache_rsp = true;
905	r_icache_fsm = r_icache_fsm_save.read();
906	break;
907	}
908
909	} // end switch r_icache_fsm
910
911	#if DEBUG_CC_XCACHE_WRAPPER
912	std::cout << " Instruction Response: " << irsp << std::endl;
913	#endif
914
915	//////////////////////////////////////////////////////////////////////://///////////
916	// The DCACHE FSM controls the following ressources:
917	// - r_dcache_fsm
918	// - r_dcache_fsm_save
919	// - r_dcache (data cache access)
920	// - r_dcache_addr_save
921	// - r_dcache_wdata_save
922	// - r_dcache_rdata_save
923	// - r_dcache_type_save
924	// - r_dcache_be_save
925	// - r_dcache_cached_save
926	// - r_dcache_miss_req set
927	// - r_dcache_unc_req set
928	// - r_dcache_write_req set
929	// - r_dcache_cleanup_req set
930	// - r_vci_rsp_data_error reset
931	// - r_tgt_dcache_req reset
932	// - r_wbuf write
933	// - dreq & drsp structures for communication with the processor
934	//
935	// 1/ EXTERNAL REQUEST :
936	// There is an external request when the tgt_dcache req flip-flop is set,
937	// requesting a line invalidation or a line update.
938	// External requests are taken into account in the states IDLE, WRITE_REQ,
939	// UNC_WAIT, MISS_WAIT, and have the highest priority :
940	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
941	// goes to the CC_CHECK state to execute the requested action, and returns to the
942	// pre-empted state.
943	// 2/ PROCESSOR REQUEST :
944	// In order to support VCI write burst, the processor requests are taken into account
945	// in the WRITE_REQ state as well as in the IDLE state.
946	// - In the IDLE state, the processor request cannot be satisfied if
947	// there is a cached read miss, or an uncached read.
948	// - In the WRITE_REQ state, the request cannot be satisfied if
949	// there is a cached read miss, or an uncached read,
950	// or when the write buffer is full.
951	// - In all other states, the processor request is not satisfied.
952	//
953	// The cache access takes into account the cacheability_table.
954	// In case of processor request, there is five conditions to exit the IDLE state:
955	// - CACHED READ MISS => to the MISS_WAIT state (waiting the r_miss_ok signal),
956	// then to the MISS_UPDT state, and finally to the IDLE state.
957	// - UNCACHED READ => to the UNC_WAIT state (waiting the r_miss_ok signal),
958	// and to the IDLE state.
959	// - CACHE INVALIDATE HIT => to the INVAL state for one cycle, then to IDLE state.
960	// - WRITE MISS => directly to the WRITE_REQ state to access the write buffer.
961	// - WRITE HIT => to the WRITE_UPDT state, then to the WRITE_REQ state.
962	//
963	// Error handling : Read Bus Errors are synchronous events, but
964	// Write Bus Errors are asynchronous events (processor is not frozen).
965	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
966	// r_vci_rsp_data_error flip-flop, and the synchronous error is signaled
967	// by the DCACHE FSM.
968	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
969	// the asynchronous error using the setWriteBerr() method.
970	///////////////////////////////////////////////////////////////////////////////////
971
972	#if DEBUG_CC_XCACHE_WRAPPER
973	std::cout << " Data Request: " << dreq << std::endl;
974	#endif
975
976	//if( (m_cpt_total_cycles % 10000) ==0 ) std::cout << std::dec << "Proc " << m_srcid << " Data Request: " << dreq << std::endl;
977
978	switch ( r_dcache_fsm ) {
979
980	/////////////////////
981	case DCACHE_WRITE_REQ:
982	{
983	if ( r_tgt_dcache_req ) { // external request
984	r_dcache_fsm = DCACHE_CC_CHECK;
985	r_dcache_fsm_save = r_dcache_fsm;
986	break;
987	}
988	// try to post the write request in the write buffer
989	if ( !r_dcache_write_req ) { // no previous write transaction
990	if ( r_wbuf.wok(r_dcache_addr_save) ) { // write request in the same cache line
991	r_wbuf.write(r_dcache_addr_save, r_dcache_be_save, r_dcache_wdata_save);
992	// close the write packet if uncached
993	if ( !r_dcache_cached_save ){
994	r_dcache_write_req = true ;
995	}
996	} else {
997	// close the write packet if write request not in the same cache line
998	r_dcache_write_req = true;
999	if(!m_srcid_rw) {
1000	}
1001	m_cost_write_frz++;
1002	break; // posting request not possible : stay in DCACHE_WRITEREQ state
1003	}
1004	} else { // previous write transaction not completed
1005	m_cost_write_frz++;
1006	break; // posting request not possible : stay in DCACHE_WRITEREQ state
1007	}
1008
1009	// close the write packet if the next processor request is not a write
1010	if ( !dreq.valid \|\| (dreq.type != iss_t::DATA_WRITE) ) {
1011	r_dcache_write_req = true ;
1012	}
1013
1014	// The next state and the processor request parameters are computed
1015	// as in the DCACHE_IDLE state (see below ...)
1016	}
1017	/////////////////
1018	case DCACHE_IDLE:
1019	{
1020	if ( r_tgt_dcache_req ) { // external request
1021	r_dcache_fsm = DCACHE_CC_CHECK;
1022	r_dcache_fsm_save = r_dcache_fsm;
1023	break;
1024	}
1025
1026	if ( dreq.valid ) {
1027	bool dcache_hit = false;
1028	data_t dcache_rdata = 0;
1029	bool dcache_cached;
1030	m_cpt_dcache_data_read += m_dcache_ways;
1031	m_cpt_dcache_dir_read += m_dcache_ways;
1032
1033	// dcache_cached evaluation
1034	switch (dreq.type) {
1035	case iss_t::DATA_SC:
1036	case iss_t::XTN_READ:
1037	case iss_t::XTN_WRITE:
1038	dcache_cached = false;
1039	break;
1040	default:
1041	dcache_cached = m_cacheability_table[(vci_addr_t)dreq.addr];
1042	}
1043
1044	// dcache_hit & dcache_rdata evaluation
1045	if ( dcache_cached ) {
1046	dcache_hit = r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata);
1047	} else {
1048	dcache_hit = false;
1049	}
1050
1051	switch( dreq.type ) {
1052	case iss_t::DATA_READ:
1053	case iss_t::DATA_LL:
1054	m_cpt_read++;
1055	if ( dcache_hit ) {
1056	r_dcache_fsm = DCACHE_IDLE;
1057	drsp.valid = true;
1058	drsp.rdata = dcache_rdata;
1059	if(dreq.type == iss_t::DATA_LL){
1060	r_dcache_ll_valid = true;
1061	r_dcache_ll_data = dcache_rdata;
1062	r_dcache_ll_addr = (vci_addr_t) dreq.addr;
1063	#ifdef COHERENCE_DEBUG
1064	std::cout << "Value returned for LL at address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl;
1065	r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata);
1066	std::cout << "Value stored at this address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl;
1067	#endif
1068	}
1069	} else {
1070	if ( dcache_cached ) {
1071	m_cpt_data_miss++;
1072	m_cost_data_miss_frz++;
1073	r_dcache_miss_req = true;
1074	r_dcache_fsm = DCACHE_MISS_WAIT;
1075	} else {
1076	m_cpt_unc_read++;
1077	m_cost_unc_read_frz++;
1078	r_dcache_unc_req = true;
1079	r_dcache_fsm = DCACHE_UNC_WAIT;
1080	}
1081	}
1082	break;
1083	case iss_t::DATA_SC:
1084	{
1085	m_cpt_unc_read++;
1086	m_cost_unc_read_frz++;
1087	if(r_dcache_ll_valid.read() && (r_dcache_ll_addr.read() == (vci_addr_t)dreq.addr)){
1088	r_dcache_sc_req = true;
1089	r_dcache_fsm = DCACHE_SC_WAIT;
1090	} else {
1091	drsp.valid = true;
1092	drsp.rdata = 1; // SC rsp NOK
1093	r_dcache_ll_valid = false;
1094	}
1095	break;
1096	}
1097	case iss_t::XTN_READ:
1098	case iss_t::XTN_WRITE:
1099	// only DCACHE INVALIDATE request are supported
1100	if ( dreq.addr/4 == iss_t::XTN_DCACHE_INVAL ){
1101	r_dcache_fsm = DCACHE_INVAL;
1102	} else {
1103	r_dcache_fsm = DCACHE_IDLE;
1104	}
1105	drsp.valid = true;
1106	drsp.rdata = 0;
1107	break;
1108	case iss_t::DATA_WRITE:
1109	m_cpt_write++;
1110	if ( dcache_hit && dcache_cached ) {
1111	r_dcache_fsm = DCACHE_WRITE_UPDT;
1112	m_cpt_write_cached++;
1113	} else {
1114	r_dcache_fsm = DCACHE_WRITE_REQ;
1115	}
1116	drsp.valid = true;
1117	drsp.rdata = 0;
1118	break;
1119	} // end switch dreq.type
1120
1121	r_dcache_addr_save = (addr_40) dreq.addr;
1122	r_dcache_type_save = dreq.type;
1123	r_dcache_wdata_save = dreq.wdata;
1124	r_dcache_be_save = dreq.be;
1125	r_dcache_rdata_save = dcache_rdata;
1126	r_dcache_cached_save = dcache_cached;
1127
1128	} else { // end if dreq.valid
1129	r_dcache_fsm = DCACHE_IDLE;
1130	}
1131	// processor request are not accepted in the WRITE_REQUEST state
1132	// when the write buffer is not writeable
1133	if ( (r_dcache_fsm == DCACHE_WRITE_REQ) &&
1134	(r_dcache_write_req \|\| !r_wbuf.wok(r_dcache_addr_save)) ) {
1135	drsp.valid = false;
1136	drsp.rdata = 0;
1137	}
1138	break;
1139	}
1140	///////////////////////
1141	case DCACHE_WRITE_UPDT:
1142	{
1143	m_cpt_dcache_data_write++;
1144	data_t mask = vci_param::be2mask(r_dcache_be_save);
1145	data_t wdata = (mask & r_dcache_wdata_save) \| (~mask & r_dcache_rdata_save);
1146	vci_addr_t ad = r_dcache_addr_save.read();
1147	r_dcache.write(ad, wdata);
1148	r_dcache_fsm = DCACHE_WRITE_REQ;
1149	break;
1150	}
1151	//////////////////////
1152	case DCACHE_MISS_WAIT:
1153	{
1154
1155	if ( dreq.valid ) m_cost_data_miss_frz++;
1156	if ( r_tgt_dcache_req.read() ) { // external request
1157	r_dcache_fsm = DCACHE_CC_CHECK;
1158	r_dcache_fsm_save = r_dcache_fsm;
1159	break;
1160	}
1161	if ( !r_dcache_miss_req && !r_dcache_inval_rsp ) { // Miss read response and no invalidation
1162	if ( r_vci_rsp_data_error ) {
1163	r_dcache_fsm = DCACHE_ERROR;
1164	} else {
1165	r_dcache_fsm = DCACHE_MISS_UPDT;
1166	}
1167	break;
1168	}
1169	if ( !r_dcache_miss_req && r_dcache_inval_rsp ) { // Miss read response and invalidation
1170	if ( r_vci_rsp_data_error ) {
1171	r_dcache_inval_rsp = false;
1172	r_dcache_fsm = DCACHE_ERROR;
1173	} else {
1174	r_dcache_inval_rsp = false;
1175	r_dcache_fsm = DCACHE_CC_CLEANUP;
1176	}
1177	break;
1178	}
1179	break;
1180	}
1181	//////////////////////
1182	case DCACHE_MISS_UPDT:
1183
1184	{
1185	if ( r_tgt_dcache_req.read() ) { // external request
1186	r_dcache_fsm = DCACHE_CC_CHECK;
1187	r_dcache_fsm_save = r_dcache_fsm;
1188	break;
1189	}
1190	if( !r_dcache_cleanup_req.read() && !r_dcache_inval_rsp ){
1191	vci_addr_t ad = 0;
1192	ad = (vci_addr_t) r_dcache_addr_save.read();
1193	data_t* buf = new data_t[m_dcache_words];
1194	for(size_t i=0; i<m_dcache_words; i++) {
1195	buf[i] = r_dcache_miss_buf[i];
1196	}
1197	vci_addr_t victim_index = 0;
1198	if ( dreq.valid ) m_cost_data_miss_frz++;
1199	m_cpt_dcache_data_write++;
1200	m_cpt_dcache_dir_write++;
1201
1202	r_dcache_cleanup_req = r_dcache.update(ad, buf, &victim_index);
1203	r_dcache_cleanup_line = (addr_40) victim_index;
1204
1205	r_dcache_fsm = DCACHE_IDLE;
1206	delete [] buf;
1207	break;
1208	}
1209	if( r_dcache_inval_rsp ){
1210	r_dcache_inval_rsp = false;
1211	r_dcache_fsm = DCACHE_CC_CLEANUP;
1212	break;
1213	}
1214	break;
1215	}
1216	////////////////////
1217	case DCACHE_UNC_WAIT:
1218	{
1219	if ( dreq.valid ) m_cost_unc_read_frz++;
1220	if ( r_tgt_dcache_req ) { // external request
1221	r_dcache_fsm = DCACHE_CC_CHECK;
1222	r_dcache_fsm_save = r_dcache_fsm;
1223	break;
1224	}
1225	if ( !r_dcache_unc_req ) {
1226	if ( r_vci_rsp_data_error ) {
1227	r_dcache_fsm = DCACHE_ERROR;
1228	} else {
1229	if(dreq.type == iss_t::DATA_LL){
1230	r_dcache_ll_valid = true;
1231	r_dcache_ll_data = r_dcache_miss_buf[0];
1232	r_dcache_ll_addr = (vci_addr_t) dreq.addr;
1233	}
1234	r_dcache_fsm = DCACHE_IDLE;
1235	drsp.valid = true;
1236	drsp.rdata = r_dcache_miss_buf[0];
1237	}
1238	}
1239	break;
1240	}
1241	////////////////////
1242	case DCACHE_SC_WAIT:
1243	{
1244	if ( dreq.valid ) m_cost_unc_read_frz++;
1245	if ( r_tgt_dcache_req ) { // external request
1246	r_dcache_fsm = DCACHE_CC_CHECK;
1247	r_dcache_fsm_save = r_dcache_fsm;
1248	break;
1249	}
1250	if ( !r_dcache_sc_req ) {
1251	if ( r_vci_rsp_data_error ) {
1252	r_dcache_fsm = DCACHE_ERROR;
1253	} else {
1254	r_dcache_fsm = DCACHE_IDLE;
1255	drsp.valid = true;
1256	drsp.rdata = r_dcache_miss_buf[0];
1257	r_dcache_ll_valid = false;
1258	}
1259	}
1260	break;
1261	}
1262
1263	//////////////////
1264	case DCACHE_ERROR:
1265	{
1266	r_dcache_fsm = DCACHE_IDLE;
1267	r_vci_rsp_data_error = false;
1268	drsp.error = true;
1269	drsp.valid = true;
1270	break;
1271	}
1272	/////////////////
1273	case DCACHE_INVAL:
1274	{
1275	if ( r_tgt_dcache_req.read() ) { // external request
1276	r_dcache_fsm = DCACHE_CC_CHECK;
1277	r_dcache_fsm_save = r_dcache_fsm;
1278	break;
1279	}
1280	if( !r_dcache_cleanup_req.read() ){
1281	m_cpt_dcache_dir_read += m_dcache_ways;
1282	vci_addr_t ad = r_dcache_addr_save.read();
1283	r_dcache_cleanup_req = r_dcache.inval(ad);
1284	r_dcache_cleanup_line = r_dcache_addr_save.read() >> (uint32_log2(m_dcache_words)+2);
1285
1286	r_dcache_fsm = DCACHE_IDLE;
1287	}
1288	break;
1289	}
1290	/////////////////////
1291	case DCACHE_CC_CHECK: // read directory in case of invalidate or update request
1292	{
1293
1294	m_cpt_dcache_dir_read += m_dcache_ways;
1295	m_cpt_dcache_data_read += m_dcache_ways;
1296	addr_40 ad = r_tgt_addr;
1297	data_t dcache_rdata = 0;
1298
1299	if(( ( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) &&
1300	( (r_dcache_addr_save.read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) {
1301	r_dcache_inval_rsp = true;
1302	r_tgt_dcache_req = false;
1303	if(r_tgt_update){ // Also send a cleanup and answer
1304	r_tgt_dcache_rsp = true;
1305	} else { // Also send a cleanup but don't answer
1306	r_tgt_dcache_rsp = false;
1307	}
1308	r_dcache_fsm = r_dcache_fsm_save;
1309	} else {
1310	bool dcache_hit = r_dcache.read(ad, &dcache_rdata);
1311	#ifdef COHERENCE_DEBUG
1312	std::cout << "PROC " << m_srcid_rw << " DCACHE_CC_CHECK, hit ? : " << dcache_hit << std::endl;
1313	#endif
1314	if ( dcache_hit && r_tgt_update ) {
1315	// complete the line buffer in case of update
1316	for(size_t i=0; i<m_dcache_words; i++){
1317	data_t rdata = 0;
1318	r_dcache.read(ad + i*4,&rdata);
1319	data_t mask = vci_param::be2mask(r_tgt_be[i]);
1320	r_tgt_buf[i] = (mask & r_tgt_buf[i]) \| (~mask & rdata);
1321	}
1322	r_dcache_fsm = DCACHE_CC_UPDT;
1323	} else if ( dcache_hit && !r_tgt_update ) {
1324	r_dcache_fsm = DCACHE_CC_INVAL;
1325	} else {
1326	if(r_tgt_update){
1327	r_tgt_dcache_rsp = true;
1328	} else {
1329	r_tgt_dcache_rsp = false;
1330	}
1331	r_tgt_dcache_req = false;
1332	r_dcache_fsm = r_dcache_fsm_save;
1333	}
1334	}
1335	break;
1336	}
1337	///////////////////
1338	case DCACHE_CC_UPDT: // update directory and data cache
1339	{
1340	m_cpt_dcache_dir_write++;
1341	m_cpt_dcache_data_write++;
1342	addr_40 ad = r_tgt_addr;
1343	data_t* buf = r_tgt_buf;
1344	#ifdef COHERENCE_DEBUG
1345	std::cout << "PROC " << m_srcid_rw << " DCACHE_CC_UPDT, update : " << std::endl;
1346	#endif
1347	for(size_t i=0; i<m_dcache_words; i++){
1348	if(r_tgt_be[i]) {
1349	r_dcache.write( ad + i*4, buf[i]);
1350	#ifdef COHERENCE_DEBUG
1351	std::cout << " address " << std::hex << ad+i*4 << " data " << std::dec << buf[i] << std::endl;
1352	data_t rdata = 0xAAAAAAAA;
1353	r_dcache.read(ad + i*4,&rdata);
1354	std::cout << "data written " << rdata << std::endl;
1355	#endif
1356	}
1357	}
1358	r_tgt_dcache_req = false;
1359	r_tgt_dcache_rsp = true;
1360	r_dcache_fsm = r_dcache_fsm_save;
1361	break;
1362	}
1363	/////////////////////
1364	case DCACHE_CC_INVAL: // invalidate a cache line
1365	{
1366	addr_40 ad = r_tgt_addr;
1367	r_tgt_dcache_rsp = true;
1368	r_dcache.inval(ad);
1369	r_tgt_dcache_req = false;
1370	r_dcache_fsm = r_dcache_fsm_save;
1371	break;
1372	}
1373	///////////////////
1374	case DCACHE_CC_CLEANUP:
1375	{
1376	// external cache invalidate request
1377	if ( r_tgt_dcache_req )
1378	{
1379	r_dcache_fsm = DCACHE_CC_CHECK;
1380	r_dcache_fsm_save = r_dcache_fsm;
1381	break;
1382	}
1383	// cleanup
1384	if(!r_dcache_cleanup_req){
1385	r_dcache_cleanup_req = true;
1386	r_dcache_cleanup_line = r_dcache_addr_save.read() >> (uint32_log2(m_dcache_words) + 2);
1387	r_dcache_fsm = DCACHE_IDLE;
1388	}
1389	break;
1390	}
1391
1392	} // end switch r_dcache_fsm
1393
1394	#if DEBUG_CC_XCACHE_WRAPPER
1395	std::cout << " Data Response: " << drsp << std::endl;
1396	#endif
1397
1398	/////////// execute one iss cycle /////////////////////////////////////////////
1399	{
1400	uint32_t it = 0;
1401	for (size_t i=0; i<(size_t)iss_t::n_irq; i++)
1402	if(p_irq[i].read()) it \|= (1<<i);
1403	m_iss.executeNCycles(1, irsp, drsp, it);
1404	}
1405
1406	if ( (ireq.valid && !irsp.valid) \|\| (dreq.valid && !drsp.valid) ) m_cpt_frz_cycles++;
1407
1408
1409	////////////////////////////////////////////////////////////////////////////
1410	// The VCI_CMD FSM controls the following ressources:
1411	// - r_vci_cmd_fsm
1412	// - r_vci_cmd_min
1413	// - r_vci_cmd_max
1414	// - r_vci_cmd_cpt
1415	// - wbuf reset
1416	//
1417	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
1418	// There is 7 request types, with the following priorities :
1419	// 1 - Instruction Miss : r_icache_miss_req
1420	// 2 - Data Write : r_dcache_write_req
1421	// 3 - Data Read Miss : r_dcache_miss_req
1422	// 4 - Data Read Uncached : r_dcache_unc_req
1423	// 5 - Instruction Cleanup : r_icache_cleanup_req
1424	// 6 - Data Cleanup : r_dcache_cleanup_req
1425	// There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM
1426	// and RSP_FSM exit simultaneously the IDLE state.
1427	//
1428	// VCI formats:
1429	// According to the VCI advanced specification, all read requests packets
1430	// (read Uncached, Miss data, Miss instruction) are one word packets.
1431	// For write burst packets, all words must be in the same cache line,
1432	// and addresses must be contiguous (the BE field is 0 in case of "holes").
1433	//////////////////////////////////////////////////////////////////////////////
1434
1435	switch (r_vci_cmd_fsm) {
1436
1437	case CMD_IDLE:
1438	if (r_vci_rsp_fsm != RSP_IDLE) break;
1439
1440	r_vci_cmd_cpt = 0;
1441	if ( r_icache_cleanup_req ) {
1442	r_vci_cmd_fsm = CMD_INS_CLEANUP;
1443	} else if ( r_dcache_cleanup_req ) {
1444	r_vci_cmd_fsm = CMD_DATA_CLEANUP;
1445	} else if ( r_icache_miss_req ) {
1446	r_vci_cmd_fsm = CMD_INS_MISS;
1447	m_cpt_imiss_transaction++;
1448	} else if ( r_icache_unc_req ) {
1449	r_vci_cmd_fsm = CMD_INS_UNC;
1450	m_cpt_imiss_transaction++;
1451	} else if ( r_dcache_write_req ) {
1452	r_vci_cmd_fsm = CMD_DATA_WRITE;
1453	r_vci_cmd_cpt = r_wbuf.getMin();
1454	r_vci_cmd_min = r_wbuf.getMin();
1455	r_vci_cmd_max = r_wbuf.getMax();
1456	m_cpt_write_transaction++;
1457	m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1);
1458	} else if ( r_dcache_miss_req ) {
1459	r_vci_cmd_fsm = CMD_DATA_MISS;
1460	m_cpt_dmiss_transaction++;
1461	} else if ( r_dcache_unc_req ) {
1462	r_vci_cmd_fsm = CMD_DATA_UNC;
1463	m_cpt_unc_transaction++;
1464	} else if ( r_dcache_sc_req ) {
1465	r_vci_cmd_fsm = CMD_DATA_SC;
1466	r_vci_cmd_max = 1;
1467	m_cpt_unc_transaction++;
1468	}
1469	break;
1470
1471	case CMD_DATA_WRITE:
1472	if ( p_vci_ini_rw.cmdack.read() ) {
1473	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
1474	if (r_vci_cmd_cpt == r_vci_cmd_max) {
1475	r_vci_cmd_fsm = CMD_IDLE ;
1476	r_wbuf.reset() ;
1477	}
1478	}
1479	break;
1480
1481	case CMD_DATA_SC:
1482	if ( p_vci_ini_rw.cmdack.read() ) {
1483	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
1484	if (r_vci_cmd_cpt == r_vci_cmd_max) {
1485	r_vci_cmd_fsm = CMD_IDLE ;
1486	}
1487	}
1488	break;
1489	case CMD_INS_MISS:
1490	case CMD_INS_UNC:
1491	case CMD_DATA_MISS:
1492	case CMD_DATA_UNC:
1493	if ( p_vci_ini_rw.cmdack.read() ) {
1494	r_vci_cmd_fsm = CMD_IDLE;
1495	}
1496	break;
1497	case CMD_INS_CLEANUP:
1498	case CMD_DATA_CLEANUP:
1499	if ( p_vci_ini_c.cmdack.read() ) {
1500	r_vci_cmd_fsm = CMD_IDLE;
1501	}
1502	break;
1503
1504	} // end switch r_vci_cmd_fsm
1505
1506	//////////////////////////////////////////////////////////////////////////
1507	// The VCI_RSP FSM controls the following ressources:
1508	// - r_vci_rsp_fsm:
1509	// - r_icache_miss_buf[m_icache_words]
1510	// - r_dcache_miss_buf[m_dcache_words]
1511	// - r_icache_miss_req reset
1512	// - r_icache_unc_req reset
1513	// - r_dcache_miss_req reset
1514	// - r_icache_cleanup_req reset
1515	// - r_dcache_cleanup_req reset
1516	// - r_vci_rsp_data_error set
1517	// - r_vci_rsp_ins_error set
1518	// - r_vci_rsp_cpt
1519	// In order to have only one active VCI transaction, this VCI_RSP_FSM
1520	// is synchronized with the VCI_CMD FSM, and both FSMs exit the
1521	// IDLE state simultaneously.
1522	//
1523	// VCI formats:
1524	// This component accepts single word or multi-word response packets for
1525	// write response packets.
1526	//
1527	// Error handling:
1528	// This FSM analyzes the VCI error code and signals directly the
1529	// Write Bus Error.
1530	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
1531	// flip_flop and the error is signaled by the DCACHE FSM.
1532	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
1533	// flip_flop and the error is signaled by the DCACHE FSM.
1534	// In case of Cleanup Error, the simulation stops with an error message...
1535	//////////////////////////////////////////////////////////////////////////
1536
1537	switch (r_vci_rsp_fsm) {
1538
1539	case RSP_IDLE:
1540	if(p_vci_ini_rw.rspval.read()\|\|
1541	p_vci_ini_c.rspval.read())
1542	{
1543	std::cout << "CC_XCache " << m_srcid_rw << " Unexpected response" << std::endl;
1544	}
1545	assert( ! p_vci_ini_rw.rspval.read() && ! p_vci_ini_c.rspval.read() && "Unexpected response" );
1546	if (r_vci_cmd_fsm != CMD_IDLE) break;
1547
1548	r_vci_rsp_cpt = 0;
1549	if ( r_icache_cleanup_req ) r_vci_rsp_fsm = RSP_INS_CLEANUP;
1550	else if ( r_dcache_cleanup_req ) r_vci_rsp_fsm = RSP_DATA_CLEANUP;
1551	else if ( r_icache_miss_req ) r_vci_rsp_fsm = RSP_INS_MISS;
1552	else if ( r_icache_unc_req ) r_vci_rsp_fsm = RSP_INS_UNC;
1553	else if ( r_dcache_write_req ) r_vci_rsp_fsm = RSP_DATA_WRITE;
1554	else if ( r_dcache_miss_req ) r_vci_rsp_fsm = RSP_DATA_MISS;
1555	else if ( r_dcache_unc_req ) r_vci_rsp_fsm = RSP_DATA_UNC;
1556	else if ( r_dcache_sc_req ) r_vci_rsp_fsm = RSP_DATA_SC;
1557	break;
1558
1559	case RSP_INS_MISS:
1560	m_cost_imiss_transaction++;
1561	if ( ! p_vci_ini_rw.rspval.read() )
1562	break;
1563	assert( (r_vci_rsp_cpt < m_icache_words) &&
1564	"The VCI response packet for instruction miss is too long" );
1565	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
1566	r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
1567
1568	if ( p_vci_ini_rw.reop.read() ) {
1569	assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
1570	"The VCI response packet for instruction miss is too short");
1571	r_icache_miss_req = false;
1572	r_vci_rsp_fsm = RSP_IDLE;
1573	}
1574	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
1575	break;
1576
1577	case RSP_INS_UNC:
1578	m_cost_imiss_transaction++;
1579	if ( ! p_vci_ini_rw.rspval.read() )
1580	break;
1581	assert(p_vci_ini_rw.reop.read() &&
1582	"illegal VCI response packet for uncached instruction");
1583	r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
1584	r_vci_rsp_fsm = RSP_IDLE;
1585	r_icache_unc_req = false;
1586	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
1587	break;
1588
1589	case RSP_DATA_MISS:
1590	m_cost_dmiss_transaction++;
1591	if ( ! p_vci_ini_rw.rspval.read() )
1592	break;
1593	assert(r_vci_rsp_cpt != m_dcache_words &&
1594	"illegal VCI response packet for data read miss");
1595	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
1596	r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
1597	if ( p_vci_ini_rw.reop.read() ) {
1598	assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
1599	"illegal VCI response packet for data read miss");
1600	r_dcache_miss_req = false;
1601	r_vci_rsp_fsm = RSP_IDLE;
1602	}
1603	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
1604	break;
1605
1606	case RSP_DATA_WRITE:
1607	m_cost_write_transaction++;
1608	if ( ! p_vci_ini_rw.rspval.read() )
1609	break;
1610	if ( p_vci_ini_rw.reop.read() ) {
1611	r_vci_rsp_fsm = RSP_IDLE;
1612	r_dcache_write_req = false;
1613	}
1614	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) m_iss.setWriteBerr();
1615	break;
1616
1617	case RSP_DATA_UNC:
1618	m_cost_unc_transaction++;
1619	if ( ! p_vci_ini_rw.rspval.read() )
1620	break;
1621	assert(p_vci_ini_rw.reop.read() &&
1622	"illegal VCI response packet for data read uncached");
1623	r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
1624	r_vci_rsp_fsm = RSP_IDLE;
1625	r_dcache_unc_req = false;
1626	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
1627	break;
1628
1629	case RSP_DATA_SC:
1630	m_cost_unc_transaction++;
1631	if ( ! p_vci_ini_rw.rspval.read() )
1632	break;
1633	assert(p_vci_ini_rw.reop.read() &&
1634	"illegal VCI response packet for data SC");
1635	r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
1636	r_vci_rsp_fsm = RSP_IDLE;
1637	r_dcache_sc_req = false;
1638	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
1639	break;
1640
1641	case RSP_INS_CLEANUP:
1642	case RSP_DATA_CLEANUP:
1643	if ( ! p_vci_ini_c.rspval.read() )
1644	break;
1645	assert( p_vci_ini_c.reop.read() &&
1646	"illegal VCI response packet for icache cleanup");
1647	assert( ((p_vci_ini_c.rerror.read()&0x1) == vci_param::ERR_NORMAL) &&
1648	"error in response packet for icache cleanup");
1649	if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) r_icache_cleanup_req = false;
1650	else r_dcache_cleanup_req = false;
1651	r_vci_rsp_fsm = RSP_IDLE;
1652	break;
1653
1654	} // end switch r_vci_rsp_fsm
1655
1656	} // end transition()
1657
1658	//////////////////////////////////////////////////////////////////////////////////
1659	tmpl(void)::genMoore()
1660	//////////////////////////////////////////////////////////////////////////////////
1661	{
1662	// VCI initiator response
1663
1664	p_vci_ini_rw.rspack = true;
1665	p_vci_ini_c.rspack = true;
1666
1667	// VCI initiator command
1668
1669	switch (r_vci_cmd_fsm.read() ) {
1670
1671	case CMD_IDLE:
1672	p_vci_ini_rw.cmdval = false;
1673	p_vci_ini_rw.address = 0;
1674	p_vci_ini_rw.wdata = 0;
1675	p_vci_ini_rw.be = 0;
1676	p_vci_ini_rw.plen = 0;
1677	p_vci_ini_rw.cmd = vci_param::CMD_NOP;
1678	p_vci_ini_rw.trdid = 0;
1679	p_vci_ini_rw.pktid = 0;
1680	p_vci_ini_rw.srcid = 0;
1681	p_vci_ini_rw.cons = false;
1682	p_vci_ini_rw.wrap = false;
1683	p_vci_ini_rw.contig = false;
1684	p_vci_ini_rw.clen = 0;
1685	p_vci_ini_rw.cfixed = false;
1686	p_vci_ini_rw.eop = false;
1687
1688	p_vci_ini_c.cmdval = false;
1689	p_vci_ini_c.address = 0;
1690	p_vci_ini_c.wdata = 0;
1691	p_vci_ini_c.be = 0;
1692	p_vci_ini_c.plen = 0;
1693	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1694	p_vci_ini_c.trdid = 0;
1695	p_vci_ini_c.pktid = 0;
1696	p_vci_ini_c.srcid = 0;
1697	p_vci_ini_c.cons = false;
1698	p_vci_ini_c.wrap = false;
1699	p_vci_ini_c.contig = false;
1700	p_vci_ini_c.clen = 0;
1701	p_vci_ini_c.cfixed = false;
1702	p_vci_ini_c.eop = false;
1703
1704	break;
1705
1706	case CMD_DATA_UNC:
1707	p_vci_ini_rw.cmdval = true;
1708	p_vci_ini_rw.address = (addr_40) r_dcache_addr_save.read() & ~0x3;
1709	switch( r_dcache_type_save ) {
1710	case iss_t::DATA_READ:
1711	p_vci_ini_rw.wdata = 0;
1712	p_vci_ini_rw.be = r_dcache_be_save.read();
1713	p_vci_ini_rw.cmd = vci_param::CMD_READ;
1714	break;
1715	case iss_t::DATA_LL:
1716	p_vci_ini_rw.wdata = 0;
1717	p_vci_ini_rw.be = 0xF;
1718	p_vci_ini_rw.cmd = vci_param::CMD_LOCKED_READ;
1719	break;
1720	default:
1721	assert("this should not happen");
1722	}
1723	p_vci_ini_rw.plen = 4;
1724	p_vci_ini_rw.trdid = 0; // data cache uncached read
1725	p_vci_ini_rw.pktid = 0;
1726	p_vci_ini_rw.srcid = m_srcid_rw;
1727	p_vci_ini_rw.cons = false;
1728	p_vci_ini_rw.wrap = false;
1729	p_vci_ini_rw.contig = true;
1730	p_vci_ini_rw.clen = 0;
1731	p_vci_ini_rw.cfixed = false;
1732	p_vci_ini_rw.eop = true;
1733
1734	p_vci_ini_c.cmdval = false;
1735	p_vci_ini_c.address = 0;
1736	p_vci_ini_c.wdata = 0;
1737	p_vci_ini_c.be = 0;
1738	p_vci_ini_c.plen = 0;
1739	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1740	p_vci_ini_c.trdid = 0;
1741	p_vci_ini_c.pktid = 0;
1742	p_vci_ini_c.srcid = 0;
1743	p_vci_ini_c.cons = false;
1744	p_vci_ini_c.wrap = false;
1745	p_vci_ini_c.contig = false;
1746	p_vci_ini_c.clen = 0;
1747	p_vci_ini_c.cfixed = false;
1748	p_vci_ini_c.eop = false;
1749
1750	break;
1751
1752	case CMD_DATA_SC:
1753	p_vci_ini_rw.cmdval = true;
1754	p_vci_ini_rw.address = (addr_40) r_dcache_addr_save.read() & ~0x3;
1755	if(r_vci_cmd_max.read() == 3){
1756	assert(false && "Not handled yet");
1757	} else { // r_vci_cmd_cpt == 1
1758	switch(r_vci_cmd_cpt.read()){
1759	case 0:
1760	p_vci_ini_rw.wdata = (uint32_t)(r_dcache_ll_data.read() & 0xFFFFFFFF);
1761	break;
1762	case 1:
1763	p_vci_ini_rw.wdata = r_dcache_wdata_save.read();
1764	break;
1765	}
1766	}
1767	p_vci_ini_rw.be = 0xF;
1768	p_vci_ini_rw.cmd = vci_param::CMD_STORE_COND;
1769	p_vci_ini_rw.plen = 4*(r_vci_cmd_max.read()+1);
1770	p_vci_ini_rw.trdid = 0; // data cache uncached read
1771	p_vci_ini_rw.pktid = 0;
1772	p_vci_ini_rw.srcid = m_srcid_rw;
1773	p_vci_ini_rw.cons = true;
1774	p_vci_ini_rw.wrap = false;
1775	p_vci_ini_rw.contig = false;
1776	p_vci_ini_rw.clen = 0;
1777	p_vci_ini_rw.cfixed = false;
1778	p_vci_ini_rw.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
1779
1780	p_vci_ini_c.cmdval = false;
1781	p_vci_ini_c.address = 0;
1782	p_vci_ini_c.wdata = 0;
1783	p_vci_ini_c.be = 0;
1784	p_vci_ini_c.plen = 0;
1785	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1786	p_vci_ini_c.trdid = 0;
1787	p_vci_ini_c.pktid = 0;
1788	p_vci_ini_c.srcid = 0;
1789	p_vci_ini_c.cons = false;
1790	p_vci_ini_c.wrap = false;
1791	p_vci_ini_c.contig = false;
1792	p_vci_ini_c.clen = 0;
1793	p_vci_ini_c.cfixed = false;
1794	p_vci_ini_c.eop = false;
1795
1796	break;
1797
1798	case CMD_DATA_WRITE:
1799	p_vci_ini_rw.cmdval = true;
1800	p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt)&~0x3;
1801	p_vci_ini_rw.wdata = r_wbuf.getData(r_vci_cmd_cpt);
1802	p_vci_ini_rw.be = r_wbuf.getBe(r_vci_cmd_cpt);
1803	p_vci_ini_rw.plen = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
1804	p_vci_ini_rw.cmd = vci_param::CMD_WRITE;
1805	p_vci_ini_rw.trdid = 0; // data cache write
1806	p_vci_ini_rw.pktid = 0;
1807	p_vci_ini_rw.srcid = m_srcid_rw;
1808	p_vci_ini_rw.cons = false;
1809	p_vci_ini_rw.wrap = false;
1810	p_vci_ini_rw.contig = true;
1811	p_vci_ini_rw.clen = 0;
1812	p_vci_ini_rw.cfixed = false;
1813	p_vci_ini_rw.eop = (r_vci_cmd_cpt == r_vci_cmd_max);
1814
1815	p_vci_ini_c.cmdval = false;
1816	p_vci_ini_c.address = 0;
1817	p_vci_ini_c.wdata = 0;
1818	p_vci_ini_c.be = 0;
1819	p_vci_ini_c.plen = 0;
1820	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1821	p_vci_ini_c.trdid = 0;
1822	p_vci_ini_c.pktid = 0;
1823	p_vci_ini_c.srcid = 0;
1824	p_vci_ini_c.cons = false;
1825	p_vci_ini_c.wrap = false;
1826	p_vci_ini_c.contig = false;
1827	p_vci_ini_c.clen = 0;
1828	p_vci_ini_c.cfixed = false;
1829	p_vci_ini_c.eop = false;
1830
1831	break;
1832
1833	case CMD_DATA_MISS:
1834	p_vci_ini_rw.cmdval = true;
1835	p_vci_ini_rw.address = r_dcache_addr_save.read() & (addr_40) m_dcache_yzmask;
1836	p_vci_ini_rw.be = 0xF;
1837	p_vci_ini_rw.plen = m_dcache_words << 2;
1838	p_vci_ini_rw.cmd = vci_param::CMD_READ;
1839	p_vci_ini_rw.trdid = 1; // data cache cached read
1840	p_vci_ini_rw.pktid = 0;
1841	p_vci_ini_rw.srcid = m_srcid_rw;
1842	p_vci_ini_rw.cons = false;
1843	p_vci_ini_rw.wrap = false;
1844	p_vci_ini_rw.contig = true;
1845	p_vci_ini_rw.clen = 0;
1846	p_vci_ini_rw.cfixed = false;
1847	p_vci_ini_rw.eop = true;
1848
1849	p_vci_ini_c.cmdval = false;
1850	p_vci_ini_c.address = 0;
1851	p_vci_ini_c.wdata = 0;
1852	p_vci_ini_c.be = 0;
1853	p_vci_ini_c.plen = 0;
1854	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1855	p_vci_ini_c.trdid = 0;
1856	p_vci_ini_c.pktid = 0;
1857	p_vci_ini_c.srcid = 0;
1858	p_vci_ini_c.cons = false;
1859	p_vci_ini_c.wrap = false;
1860	p_vci_ini_c.contig = false;
1861	p_vci_ini_c.clen = 0;
1862	p_vci_ini_c.cfixed = false;
1863	p_vci_ini_c.eop = false;
1864
1865	break;
1866
1867	case CMD_INS_MISS:
1868	p_vci_ini_rw.cmdval = true;
1869	p_vci_ini_rw.address = r_icache_addr_save.read() & (addr_40) m_icache_yzmask;
1870	p_vci_ini_rw.be = 0xF;
1871	p_vci_ini_rw.plen = m_icache_words << 2;
1872	p_vci_ini_rw.cmd = vci_param::CMD_READ;
1873	p_vci_ini_rw.trdid = 3; // ins cache cached read
1874	p_vci_ini_rw.pktid = 0;
1875	p_vci_ini_rw.srcid = m_srcid_rw;
1876	p_vci_ini_rw.cons = false;
1877	p_vci_ini_rw.wrap = false;
1878	p_vci_ini_rw.contig = true;
1879	p_vci_ini_rw.clen = 0;
1880	p_vci_ini_rw.cfixed = false;
1881	p_vci_ini_rw.eop = true;
1882
1883	p_vci_ini_c.cmdval = false;
1884	p_vci_ini_c.address = 0;
1885	p_vci_ini_c.wdata = 0;
1886	p_vci_ini_c.be = 0;
1887	p_vci_ini_c.plen = 0;
1888	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1889	p_vci_ini_c.trdid = 0;
1890	p_vci_ini_c.pktid = 0;
1891	p_vci_ini_c.srcid = 0;
1892	p_vci_ini_c.cons = false;
1893	p_vci_ini_c.wrap = false;
1894	p_vci_ini_c.contig = false;
1895	p_vci_ini_c.clen = 0;
1896	p_vci_ini_c.cfixed = false;
1897	p_vci_ini_c.eop = false;
1898
1899	break;
1900
1901	case CMD_INS_UNC:
1902	p_vci_ini_rw.cmdval = true;
1903	p_vci_ini_rw.address = r_icache_addr_save.read() & ~0x3;
1904	p_vci_ini_rw.be = 0xF;
1905	p_vci_ini_rw.plen = 4;
1906	p_vci_ini_rw.cmd = vci_param::CMD_READ;
1907	p_vci_ini_rw.trdid = 2; // ins cache uncached read
1908	p_vci_ini_rw.pktid = 0;
1909	p_vci_ini_rw.srcid = m_srcid_rw;
1910	p_vci_ini_rw.cons = false;
1911	p_vci_ini_rw.wrap = false;
1912	p_vci_ini_rw.contig = true;
1913	p_vci_ini_rw.clen = 0;
1914	p_vci_ini_rw.cfixed = false;
1915	p_vci_ini_rw.eop = true;
1916
1917	p_vci_ini_c.cmdval = false;
1918	p_vci_ini_c.address = 0;
1919	p_vci_ini_c.wdata = 0;
1920	p_vci_ini_c.be = 0;
1921	p_vci_ini_c.plen = 0;
1922	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1923	p_vci_ini_c.trdid = 0;
1924	p_vci_ini_c.pktid = 0;
1925	p_vci_ini_c.srcid = 0;
1926	p_vci_ini_c.cons = false;
1927	p_vci_ini_c.wrap = false;
1928	p_vci_ini_c.contig = false;
1929	p_vci_ini_c.clen = 0;
1930	p_vci_ini_c.cfixed = false;
1931	p_vci_ini_c.eop = false;
1932
1933
1934	break;
1935
1936	case CMD_INS_CLEANUP:
1937	p_vci_ini_rw.cmdval = false;
1938	p_vci_ini_rw.address = 0;
1939	p_vci_ini_rw.wdata = 0;
1940	p_vci_ini_rw.be = 0;
1941	p_vci_ini_rw.plen = 0;
1942	p_vci_ini_rw.cmd = vci_param::CMD_NOP;
1943	p_vci_ini_rw.trdid = 0;
1944	p_vci_ini_rw.pktid = 0;
1945	p_vci_ini_rw.srcid = 0;
1946	p_vci_ini_rw.cons = false;
1947	p_vci_ini_rw.wrap = false;
1948	p_vci_ini_rw.contig = false;
1949	p_vci_ini_rw.clen = 0;
1950	p_vci_ini_rw.cfixed = false;
1951	p_vci_ini_rw.eop = false;
1952
1953	p_vci_ini_c.cmdval = true;
1954	p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2);
1955	p_vci_ini_c.wdata = 0;
1956	p_vci_ini_c.be = 0;
1957	p_vci_ini_c.plen = 4;
1958	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
1959	p_vci_ini_c.trdid = 1; // cleanup instruction
1960	p_vci_ini_c.pktid = 0;
1961	p_vci_ini_c.srcid = m_srcid_c;
1962	p_vci_ini_c.cons = false;
1963	p_vci_ini_c.wrap = false;
1964	p_vci_ini_c.contig = false;
1965	p_vci_ini_c.clen = 0;
1966	p_vci_ini_c.cfixed = false;
1967	p_vci_ini_c.eop = true;
1968
1969	break;
1970
1971
1972	case CMD_DATA_CLEANUP:
1973	p_vci_ini_rw.cmdval = false;
1974	p_vci_ini_rw.address = 0;
1975	p_vci_ini_rw.wdata = 0;
1976	p_vci_ini_rw.be = 0;
1977	p_vci_ini_rw.plen = 0;
1978	p_vci_ini_rw.cmd = vci_param::CMD_NOP;
1979	p_vci_ini_rw.trdid = 0;
1980	p_vci_ini_rw.pktid = 0;
1981	p_vci_ini_rw.srcid = 0;
1982	p_vci_ini_rw.cons = false;
1983	p_vci_ini_rw.wrap = false;
1984	p_vci_ini_rw.contig = false;
1985	p_vci_ini_rw.clen = 0;
1986	p_vci_ini_rw.cfixed = false;
1987	p_vci_ini_rw.eop = false;
1988
1989	p_vci_ini_c.cmdval = true;
1990	p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
1991	p_vci_ini_c.wdata = 0;
1992	p_vci_ini_c.be = 0;
1993	p_vci_ini_c.plen = 4;
1994	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
1995	p_vci_ini_c.trdid = 0; // cleanup data
1996	p_vci_ini_c.pktid = 0;
1997	p_vci_ini_c.srcid = m_srcid_c;
1998	p_vci_ini_c.cons = false;
1999	p_vci_ini_c.wrap = false;
2000	p_vci_ini_c.contig = false;
2001	p_vci_ini_c.clen = 0;
2002	p_vci_ini_c.cfixed = false;
2003	p_vci_ini_c.eop = true;
2004
2005	break;
2006
2007	} // end switch r_vci_cmd_fsm
2008
2009	// VCI_TGT
2010
2011	switch ( r_vci_tgt_fsm.read() ) {
2012
2013	case TGT_IDLE:
2014	case TGT_UPDT_WORD:
2015	case TGT_UPDT_DATA:
2016	p_vci_tgt.cmdack = true;
2017	p_vci_tgt.rspval = false;
2018	break;
2019
2020	case TGT_RSP_BROADCAST:
2021	p_vci_tgt.cmdack = false;
2022	p_vci_tgt.rspval = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && ( r_tgt_icache_rsp \| r_tgt_dcache_rsp );
2023	p_vci_tgt.rsrcid = r_tgt_srcid.read();
2024	p_vci_tgt.rpktid = r_tgt_pktid.read();
2025	p_vci_tgt.rtrdid = r_tgt_trdid.read();
2026	p_vci_tgt.rdata = 0;
2027	p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
2028	p_vci_tgt.reop = true;
2029	break;
2030
2031	case TGT_RSP_ICACHE:
2032	p_vci_tgt.cmdack = false;
2033	p_vci_tgt.rspval = !r_tgt_icache_req.read() && r_tgt_icache_rsp.read();
2034	p_vci_tgt.rsrcid = r_tgt_srcid.read();
2035	p_vci_tgt.rpktid = r_tgt_pktid.read();
2036	p_vci_tgt.rtrdid = r_tgt_trdid.read();
2037	p_vci_tgt.rdata = 0;
2038	p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
2039	p_vci_tgt.reop = true;
2040	break;
2041
2042	case TGT_RSP_DCACHE:
2043	p_vci_tgt.cmdack = false;
2044	p_vci_tgt.rspval = !r_tgt_dcache_req.read() && r_tgt_dcache_rsp.read();
2045	p_vci_tgt.rsrcid = r_tgt_srcid.read();
2046	p_vci_tgt.rpktid = r_tgt_pktid.read();
2047	p_vci_tgt.rtrdid = r_tgt_trdid.read();
2048	p_vci_tgt.rdata = 0;
2049	p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
2050	p_vci_tgt.reop = true;
2051	break;
2052
2053	case TGT_REQ_BROADCAST:
2054	case TGT_REQ_ICACHE:
2055	case TGT_REQ_DCACHE:
2056	p_vci_tgt.cmdack = false;
2057	p_vci_tgt.rspval = false;
2058	break;
2059
2060	} // end switch TGT_FSM
2061	} // end genMoore()
2062
2063	}} // end namespace
2064
2065	// Local Variables:
2066	// tab-width: 4
2067	// c-basic-offset: 4
2068	// c-file-offsets:((innamespace . 0)(inline-open . 0))
2069	// indent-tabs-mode: nil
2070	// End:
2071
2072	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
2073
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2076

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