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vci_mem_cache_v1.h @ 2

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1	/* -- c++ --
2	* File : vci_mem_cache_v1.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu choichillon.christophe@gmail.com
28	*/
29
30	#ifndef SOCLIB_CABA_MEM_CACHE_V1_H
31	#define SOCLIB_CABA_MEM_CACHE_V1_H
32
33	#include <inttypes.h>
34	#include <systemc>
35	#include <list>
36	#include <cassert>
37	#include "arithmetics.h"
38	#include "alloc_elems.h"
39	#include "caba_base_module.h"
40	#include "vci_target.h"
41	#include "vci_initiator.h"
42	#include "generic_fifo.h"
43	#include "mapping_table.h"
44	#include "int_tab.h"
45	#include "mem_cache_directory_v1.h"
46	#include "xram_transaction_v1.h"
47	#include "update_tab_v1.h"
48	#include "atomic_tab_v1.h"
49
50	#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
51	#define UPDATE_TAB_LINES 4 // Number of lines in the update tab
52	#define BROADCAST_ADDR 0x0000000003 // Address to send the broadcast invalidate
53
54	namespace soclib { namespace caba {
55	using namespace sc_core;
56
57	template<typename vci_param>
58	class VciMemCacheV1
59	: public soclib::caba::BaseModule
60	{
61	typedef sc_dt::sc_uint<40> addr_t;
62	typedef typename vci_param::fast_addr_t vci_addr_t;
63	typedef uint32_t data_t;
64	typedef uint32_t tag_t;
65	typedef uint32_t size_t;
66	typedef uint32_t be_t;
67	typedef uint32_t copy_t;
68
69	/* States of the TGT_CMD fsm */
70	enum tgt_cmd_fsm_state_e{
71	TGT_CMD_IDLE,
72	TGT_CMD_READ,
73	TGT_CMD_READ_EOP,
74	TGT_CMD_WRITE,
75	TGT_CMD_ATOMIC,
76	};
77
78	/* States of the TGT_RSP fsm */
79	enum tgt_rsp_fsm_state_e{
80	TGT_RSP_READ_IDLE,
81	TGT_RSP_WRITE_IDLE,
82	TGT_RSP_LLSC_IDLE,
83	TGT_RSP_XRAM_IDLE,
84	TGT_RSP_INIT_IDLE,
85	TGT_RSP_CLEANUP_IDLE,
86	TGT_RSP_READ_TEST,
87	TGT_RSP_READ_WORD,
88	TGT_RSP_READ_LINE,
89	TGT_RSP_WRITE,
90	TGT_RSP_LLSC,
91	TGT_RSP_XRAM_TEST,
92	TGT_RSP_XRAM_WORD,
93	TGT_RSP_XRAM_LINE,
94	TGT_RSP_INIT,
95	TGT_RSP_CLEANUP,
96	};
97
98	/* States of the INIT_CMD fsm */
99	enum init_cmd_fsm_state_e{
100	INIT_CMD_INVAL_IDLE,
101	INIT_CMD_INVAL_SEL,
102	INIT_CMD_INVAL_NLINE,
103	INIT_CMD_UPDT_IDLE,
104	INIT_CMD_UPDT_SEL,
105	INIT_CMD_BRDCAST,
106	INIT_CMD_UPDT_NLINE,
107	INIT_CMD_UPDT_INDEX,
108	INIT_CMD_UPDT_DATA,
109	};
110
111	/* States of the INIT_RSP fsm */
112	enum init_rsp_fsm_state_e{
113	INIT_RSP_IDLE,
114	INIT_RSP_UPT_LOCK,
115	INIT_RSP_UPT_CLEAR,
116	INIT_RSP_END,
117	};
118
119	/* States of the READ fsm */
120	enum read_fsm_state_e{
121	READ_IDLE,
122	READ_DIR_LOCK,
123	READ_DIR_HIT,
124	READ_RSP,
125	READ_TRT_LOCK,
126	READ_TRT_SET,
127	READ_XRAM_REQ,
128	};
129
130	/* States of the WRITE fsm */
131	enum write_fsm_state_e{
132	WRITE_IDLE,
133	WRITE_NEXT,
134	WRITE_DIR_LOCK,
135	WRITE_DIR_HIT_READ,
136	WRITE_DIR_HIT,
137	WRITE_DIR_HIT_RSP,
138	WRITE_UPT_LOCK,
139	WRITE_WAIT_UPT,
140	WRITE_UPDATE,
141	WRITE_RSP,
142	WRITE_TRT_LOCK,
143	WRITE_TRT_DATA,
144	WRITE_TRT_SET,
145	WRITE_WAIT_TRT,
146	WRITE_XRAM_REQ,
147	WRITE_TRT_WRITE_LOCK,
148	WRITE_INVAL_LOCK,
149	WRITE_DIR_INVAL,
150	WRITE_INVAL,
151	WRITE_XRAM_SEND,
152	};
153
154	/* States of the IXR_RSP fsm */
155	enum ixr_rsp_fsm_state_e{
156	IXR_RSP_IDLE,
157	IXR_RSP_ACK,
158	IXR_RSP_TRT_ERASE,
159	IXR_RSP_TRT_READ,
160	};
161
162	/* States of the XRAM_RSP fsm */
163	enum xram_rsp_fsm_state_e{
164	XRAM_RSP_IDLE,
165	XRAM_RSP_TRT_COPY,
166	XRAM_RSP_TRT_DIRTY,
167	XRAM_RSP_DIR_LOCK,
168	XRAM_RSP_DIR_UPDT,
169	XRAM_RSP_DIR_RSP,
170	XRAM_RSP_INVAL_LOCK,
171	XRAM_RSP_INVAL_WAIT,
172	XRAM_RSP_INVAL,
173	XRAM_RSP_WRITE_DIRTY,
174	};
175
176	/* States of the IXR_CMD fsm */
177	enum ixr_cmd_fsm_state_e{
178	IXR_CMD_READ_IDLE,
179	IXR_CMD_WRITE_IDLE,
180	IXR_CMD_LLSC_IDLE,
181	IXR_CMD_XRAM_IDLE,
182	IXR_CMD_READ_NLINE,
183	IXR_CMD_WRITE_NLINE,
184	IXR_CMD_LLSC_NLINE,
185	IXR_CMD_XRAM_DATA,
186	};
187
188	/* States of the LLSC fsm */
189	enum llsc_fsm_state_e{
190	LLSC_IDLE,
191	LL_DIR_LOCK,
192	LL_DIR_HIT,
193	LL_RSP,
194	SC_DIR_LOCK,
195	SC_DIR_HIT,
196	SC_RSP_FALSE,
197	SC_RSP_TRUE,
198	LLSC_TRT_LOCK,
199	LLSC_TRT_SET,
200	LLSC_XRAM_REQ,
201	};
202
203	/* States of the CLEANUP fsm */
204	enum cleanup_fsm_state_e{
205	CLEANUP_IDLE,
206	CLEANUP_DIR_LOCK,
207	CLEANUP_DIR_WRITE,
208	CLEANUP_UPT_LOCK,
209	CLEANUP_UPT_WRITE,
210	CLEANUP_WRITE_RSP,
211	CLEANUP_RSP,
212	};
213
214	/* States of the ALLOC_DIR fsm */
215	enum alloc_dir_fsm_state_e{
216	ALLOC_DIR_READ,
217	ALLOC_DIR_WRITE,
218	ALLOC_DIR_LLSC,
219	ALLOC_DIR_CLEANUP,
220	ALLOC_DIR_XRAM_RSP,
221	};
222
223	/* States of the ALLOC_TRT fsm */
224	enum alloc_trt_fsm_state_e{
225	ALLOC_TRT_READ,
226	ALLOC_TRT_WRITE,
227	ALLOC_TRT_LLSC,
228	ALLOC_TRT_XRAM_RSP,
229	ALLOC_TRT_IXR_RSP,
230	};
231
232	/* States of the ALLOC_UPT fsm */
233	enum alloc_upt_fsm_state_e{
234	ALLOC_UPT_WRITE,
235	ALLOC_UPT_XRAM_RSP,
236	ALLOC_UPT_INIT_RSP,
237	ALLOC_UPT_CLEANUP,
238	};
239
240	uint32_t m_cpt_cycles; // Counter of cycles
241	uint32_t m_cpt_read; // Number of READ transactions
242	uint32_t m_cpt_read_miss; // Number of MISS READ
243	uint32_t m_cpt_write; // Number of WRITE transactions
244	uint32_t m_cpt_write_miss; // Number of MISS WRITE
245	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
246	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
247	uint32_t m_cpt_update; // Number of UPDATE transactions
248	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
249	uint32_t m_cpt_inval; // Number of INVAL transactions
250	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
251	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
252	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
253	uint32_t m_cpt_ll; // Number of LL transactions
254	uint32_t m_cpt_sc; // Number of SC transactions
255
256	protected:
257
258	SC_HAS_PROCESS(VciMemCacheV1);
259
260	public:
261	sc_in<bool> p_clk;
262	sc_in<bool> p_resetn;
263	soclib::caba::VciTarget<vci_param> p_vci_tgt;
264	soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup;
265	soclib::caba::VciInitiator<vci_param> p_vci_ini;
266	soclib::caba::VciInitiator<vci_param> p_vci_ixr;
267
268	VciMemCacheV1(
269	sc_module_name name, // Instance Name
270	const soclib::common::MappingTable &mtp, // Mapping table for primary requets
271	const soclib::common::MappingTable &mtc, // Mapping table for coherence requets
272	const soclib::common::MappingTable &mtx, // Mapping table for XRAM
273	const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator)
274	const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator)
275	const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target)
276	const soclib::common::IntTab &vci_tgt_index_cleanup, // VCI port to PROC (target) for cleanup
277	size_t nways, // Number of ways per set
278	size_t nsets, // Number of sets
279	size_t nwords); // Number of words per line
280
281	~VciMemCacheV1();
282
283	void transition();
284
285	void genMoore();
286
287	void print_stats();
288
289	private:
290
291	// Component attributes
292	const size_t m_initiators; // Number of initiators
293	const size_t m_ways; // Number of ways in a set
294	const size_t m_sets; // Number of cache sets
295	const size_t m_words; // Number of words in a line
296	const size_t m_srcid_ixr; // Srcid for requests to XRAM
297	const size_t m_srcid_ini; // Srcid for requests to processors
298	std::list<soclib::common::Segment> m_seglist; // memory cached into the cache
299	std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
300	vci_addr_t *m_coherence_table; // address(srcid)
301	AtomicTab m_atomic_tab; // atomic access table
302	TransactionTab m_transaction_tab; // xram transaction table
303	UpdateTab m_update_tab; // pending update & invalidate
304	CacheDirectory m_cache_directory; // data cache directory
305
306	data_t ***m_cache_data; // data array[set][way][word]
307
308	// adress masks
309	const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
310	const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
311	const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
312	const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
313
314	//////////////////////////////////////////////////
315	// Others registers
316	//////////////////////////////////////////////////
317	sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
318
319	//////////////////////////////////////////////////
320	// Registers controlled by the TGT_CMD fsm
321	//////////////////////////////////////////////////
322
323	// Fifo between TGT_CMD fsm and READ fsm
324	GenericFifo<uint64_t> m_cmd_read_addr_fifo;
325	GenericFifo<bool> m_cmd_read_word_fifo;
326	GenericFifo<size_t> m_cmd_read_srcid_fifo;
327	GenericFifo<size_t> m_cmd_read_trdid_fifo;
328	GenericFifo<size_t> m_cmd_read_pktid_fifo;
329
330	// Fifo between TGT_CMD fsm and WRITE fsm
331	GenericFifo<uint64_t> m_cmd_write_addr_fifo;
332	GenericFifo<bool> m_cmd_write_eop_fifo;
333	GenericFifo<size_t> m_cmd_write_srcid_fifo;
334	GenericFifo<size_t> m_cmd_write_trdid_fifo;
335	GenericFifo<size_t> m_cmd_write_pktid_fifo;
336	GenericFifo<data_t> m_cmd_write_data_fifo;
337	GenericFifo<be_t> m_cmd_write_be_fifo;
338
339	// Fifo between TGT_CMD fsm and LLSC fsm
340	GenericFifo<uint64_t> m_cmd_llsc_addr_fifo;
341	GenericFifo<bool> m_cmd_llsc_sc_fifo;
342	GenericFifo<size_t> m_cmd_llsc_srcid_fifo;
343	GenericFifo<size_t> m_cmd_llsc_trdid_fifo;
344	GenericFifo<size_t> m_cmd_llsc_pktid_fifo;
345	GenericFifo<data_t> m_cmd_llsc_wdata_fifo;
346
347	sc_signal<int> r_tgt_cmd_fsm;
348
349	sc_signal<size_t> r_index;
350	size_t nseg;
351	size_t ncseg;
352	soclib::common::Segment **m_seg;
353	soclib::common::Segment **m_cseg;
354	///////////////////////////////////////////////////////
355	// Registers controlled by the READ fsm
356	///////////////////////////////////////////////////////
357
358	sc_signal<int> r_read_fsm; // FSM state
359	sc_signal<copy_t> r_read_d_copies; // bit-vector of copies
360	sc_signal<copy_t> r_read_i_copies; // bit-vector of copies
361	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
362	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
363	sc_signal<bool> r_read_lock; // lock bit (in directory)
364	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
365	sc_signal<size_t> r_read_count; // number of copies
366	sc_signal<data_t> *r_read_data; // data (one cache line)
367	sc_signal<bool> r_read_word; // single word read
368	sc_signal<size_t> r_read_way; // associative way (in cache)
369	sc_signal<size_t> r_read_trt_index; // Transaction Table index
370	sc_signal<bool> r_read_pass; // Used to adjust with VHDL model
371
372	// Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
373	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
374	sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index
375	sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table
376
377	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
378	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
379	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
380	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
381	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
382	sc_signal<data_t> *r_read_to_tgt_rsp_data; // data (one cache line)
383	sc_signal<bool> *r_read_to_tgt_rsp_val; // valid bit (for single_word)
384
385	///////////////////////////////////////////////////////////////
386	// Registers controlled by the WRITE fsm
387	///////////////////////////////////////////////////////////////
388
389	sc_signal<int> r_write_fsm; // FSM state
390	sc_signal<addr_t> r_write_address; // first word address
391	sc_signal<size_t> r_write_word_index; // first word index in line
392	sc_signal<size_t> r_write_word_count; // number of words in line
393	sc_signal<size_t> r_write_srcid; // transaction srcid
394	sc_signal<size_t> r_write_trdid; // transaction trdid
395	sc_signal<size_t> r_write_pktid; // transaction pktid
396	sc_signal<data_t> *r_write_data; // data (one cache line)
397	sc_signal<be_t> *r_write_be; // one byte enable per word
398	sc_signal<bool> r_write_byte; // is it a byte write
399	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
400	sc_signal<bool> r_write_lock; // lock bit (in directory)
401	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
402	sc_signal<copy_t> r_write_d_copies; // bit vector of copies
403	sc_signal<copy_t> r_write_i_copies; // bit vector of copies
404	sc_signal<size_t> r_write_count; // number of copies
405	sc_signal<size_t> r_write_way; // way of the line
406	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
407	sc_signal<size_t> r_write_upt_index; // index in Update Table
408	sc_signal<bool> r_write_pass; // Used to adjust with VHDL model
409
410	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
411	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
412	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
413	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
414	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
415
416	// Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
417	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
418	sc_signal<bool> r_write_to_ixr_cmd_write; // write request
419	sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index
420	sc_signal<data_t> *r_write_to_ixr_cmd_data; // cache line data
421	sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table
422
423	// Buffer between WRITE fsm and INIT_CMD fsm (Update L1 caches)
424	sc_signal<bool> r_write_to_init_cmd_req; // valid request
425	sc_signal<bool> r_write_to_init_cmd_brdcast; // brdcast request
426	sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index
427	sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table
428	sc_signal<copy_t> r_write_to_init_cmd_d_copies; // bit_vector of L1 to update
429	sc_signal<copy_t> r_write_to_init_cmd_i_copies; // bit_vector of L1 to update
430	sc_signal<data_t> *r_write_to_init_cmd_data; // data (one cache line)
431	sc_signal<bool> *r_write_to_init_cmd_we; // word enable
432	sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line
433	sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line
434
435	/////////////////////////////////////////////////////////
436	// Registers controlled by INIT_RSP fsm
437	//////////////////////////////////////////////////////////
438
439	sc_signal<int> r_init_rsp_fsm; // FSM state
440	sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table
441	sc_signal<size_t> r_init_rsp_srcid; // pending write srcid
442	sc_signal<size_t> r_init_rsp_trdid; // pending write trdid
443	sc_signal<size_t> r_init_rsp_pktid; // pending write pktid
444	sc_signal<addr_t> r_init_rsp_nline; // pending write nline
445
446	// Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
447	sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request
448	sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid
449	sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid
450	sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid
451
452	///////////////////////////////////////////////////////
453	// Registers controlled by CLEANUP fsm
454	///////////////////////////////////////////////////////
455
456	sc_signal<int> r_cleanup_fsm; // FSM state
457	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
458	sc_signal<size_t> r_cleanup_trdid; // transaction trdid
459	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
460	sc_signal<addr_t> r_cleanup_nline; // cache line index
461
462	sc_signal<copy_t> r_cleanup_d_copies; // bit-vector of copies
463	sc_signal<copy_t> r_cleanup_i_copies; // bit-vector of copies
464	sc_signal<copy_t> r_cleanup_count; // number of copies
465	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
466	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
467	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
468	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
469	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
470	sc_signal<bool> r_cleanup_pass; // Used to adjust with the VHDL model
471
472	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response
473	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
474	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
475	sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp
476
477	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
478
479	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
480	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
481	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
482	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
483	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
484
485	///////////////////////////////////////////////////////
486	// Registers controlled by LLSC fsm
487	///////////////////////////////////////////////////////
488
489	sc_signal<int> r_llsc_fsm; // FSM state
490	sc_signal<data_t> r_llsc_data; // read data word
491	sc_signal<copy_t> r_llsc_i_copies; // bit_vector of copies
492	sc_signal<copy_t> r_llsc_d_copies; // bit_vector of copies
493	sc_signal<copy_t> r_llsc_count; // number of copies
494	sc_signal<bool> r_llsc_is_cnt; // is_cnt bit (in directory)
495	sc_signal<bool> r_llsc_dirty; // dirty bit (in directory)
496	sc_signal<size_t> r_llsc_way; // way in directory
497	sc_signal<size_t> r_llsc_set; // set in directory
498	sc_signal<data_t> r_llsc_tag; // cache line tag (in directory)
499	sc_signal<size_t> r_llsc_trt_index; // Transaction Table index
500	sc_signal<bool> r_llsc_pass; // Used to adjust with the VHDL model
501
502	// Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)
503	sc_signal<bool> r_llsc_to_ixr_cmd_req; // valid request
504	sc_signal<addr_t> r_llsc_to_ixr_cmd_nline; // cache line index
505	sc_signal<size_t> r_llsc_to_ixr_cmd_trdid; // index in Transaction Table
506
507	// Buffer between LLSC fsm and TGT_RSP fsm
508	sc_signal<bool> r_llsc_to_tgt_rsp_req; // valid request
509	sc_signal<data_t> r_llsc_to_tgt_rsp_data; // read data word
510	sc_signal<size_t> r_llsc_to_tgt_rsp_srcid; // Transaction srcid
511	sc_signal<size_t> r_llsc_to_tgt_rsp_trdid; // Transaction trdid
512	sc_signal<size_t> r_llsc_to_tgt_rsp_pktid; // Transaction pktid
513
514	////////////////////////////////////////////////////
515	// Registers controlled by the IXR_RSP fsm
516	////////////////////////////////////////////////////
517
518	sc_signal<int> r_ixr_rsp_fsm; // FSM state
519	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
520	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
521
522	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
523	sc_signal<bool> *r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
524
525	////////////////////////////////////////////////////
526	// Registers controlled by the XRAM_RSP fsm
527	////////////////////////////////////////////////////
528
529	sc_signal<int> r_xram_rsp_fsm; // FSM state
530	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
531	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
532	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
533	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
534	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
535	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
536	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
537	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
538	sc_signal<copy_t> r_xram_rsp_victim_d_copies; // victim line copies
539	sc_signal<copy_t> r_xram_rsp_victim_i_copies; // victim line copies
540	sc_signal<copy_t> r_xram_rsp_victim_count; // victim line number of copies
541	sc_signal<data_t> *r_xram_rsp_victim_data; // victim line data
542	sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index
543	sc_signal<bool> r_xram_rsp_pass; // Used to adjust with VHDL model
544
545	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
546	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
547	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
548	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
549	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
550	sc_signal<data_t> *r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
551	sc_signal<bool> *r_xram_rsp_to_tgt_rsp_val; // valid bit (for single word)
552
553	// Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
554	sc_signal<bool> r_xram_rsp_to_init_cmd_req; // Valid request
555	sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast; // Broadcast request
556	sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index;
557	sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry
558	sc_signal<copy_t> r_xram_rsp_to_init_cmd_d_copies; // bit_vector of copies
559	sc_signal<copy_t> r_xram_rsp_to_init_cmd_i_copies; // bit_vector of copies
560
561	// Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
562	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
563	sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index
564	sc_signal<data_t> *r_xram_rsp_to_ixr_cmd_data; // cache line data
565	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
566
567	////////////////////////////////////////////////////
568	// Registers controlled by the IXR_CMD fsm
569	////////////////////////////////////////////////////
570
571	sc_signal<int> r_ixr_cmd_fsm;
572	sc_signal<size_t> r_ixr_cmd_cpt;
573
574	////////////////////////////////////////////////////
575	// Registers controlled by TGT_RSP fsm
576	////////////////////////////////////////////////////
577
578	sc_signal<int> r_tgt_rsp_fsm;
579	sc_signal<size_t> r_tgt_rsp_cpt;
580
581	////////////////////////////////////////////////////
582	// Registers controlled by INIT_CMD fsm
583	////////////////////////////////////////////////////
584
585	sc_signal<int> r_init_cmd_fsm;
586	sc_signal<size_t> r_init_cmd_cpt;
587	sc_signal<size_t> r_init_cmd_target;
588	sc_signal<bool> r_init_cmd_inst;
589
590	////////////////////////////////////////////////////
591	// Registers controlled by ALLOC_DIR fsm
592	////////////////////////////////////////////////////
593
594	sc_signal<int> r_alloc_dir_fsm;
595
596	////////////////////////////////////////////////////
597	// Registers controlled by ALLOC_TRT fsm
598	////////////////////////////////////////////////////
599
600	sc_signal<int> r_alloc_trt_fsm;
601
602	////////////////////////////////////////////////////
603	// Registers controlled by ALLOC_UPT fsm
604	////////////////////////////////////////////////////
605
606	sc_signal<int> r_alloc_upt_fsm;
607
608	}; // end class VciMemCacheV1
609
610	}}
611
612	#endif
613
614	// Local Variables:
615	// tab-width: 4
616	// c-basic-offset: 4
617	// c-file-offsets:((innamespace . 0)(inline-open . 0))
618	// indent-tabs-mode: nil
619	// End:
620
621	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
622

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