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vci_mem_cache_v4.h @ 138

Last change on this file since 138 was 138, checked in by guthmull, 13 years ago
Handle bad accesses cleanly : transmit all accesses to the xram and handle rerror in responses. The simulation is no more stopped and gdb can be used for debug.
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1	/* -- c++ --
2	* File : vci_mem_cache_v4.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu
28	*/
29	/*
30	*
31	* Modifications done by Christophe Choichillon on the 7/04/2009:
32	* - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
33	* - Adding a new VCI target port for the CLEANUP network
34	* - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
35	*
36	* Modifications to do :
37	* - Adding new variables used by the CLEANUP FSM
38	*
39	*/
40
41	#ifndef SOCLIB_CABA_MEM_CACHE_V4_H
42	#define SOCLIB_CABA_MEM_CACHE_V4_H
43
44	#include <inttypes.h>
45	#include <systemc>
46	#include <list>
47	#include <cassert>
48	#include "arithmetics.h"
49	#include "alloc_elems.h"
50	#include "caba_base_module.h"
51	#include "vci_target.h"
52	#include "vci_initiator.h"
53	#include "generic_fifo.h"
54	#include "mapping_table.h"
55	#include "int_tab.h"
56	#include "mem_cache_directory_v4.h"
57	#include "xram_transaction_v4.h"
58	#include "update_tab_v4.h"
59
60	#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
61	#define UPDATE_TAB_LINES 4 // Number of lines in the update tab
62
63	namespace soclib { namespace caba {
64	using namespace sc_core;
65
66	template<typename vci_param>
67	class VciMemCacheV4
68	: public soclib::caba::BaseModule
69	{
70	typedef sc_dt::sc_uint<40> addr_t;
71	typedef typename vci_param::fast_addr_t vci_addr_t;
72	typedef uint32_t data_t;
73	typedef uint32_t tag_t;
74	typedef uint32_t size_t;
75	typedef uint32_t be_t;
76	typedef uint32_t copy_t;
77
78	/* States of the TGT_CMD fsm */
79	enum tgt_cmd_fsm_state_e{
80	TGT_CMD_IDLE,
81	TGT_CMD_READ,
82	TGT_CMD_READ_EOP,
83	TGT_CMD_WRITE,
84	TGT_CMD_ATOMIC,
85	};
86
87	/* States of the TGT_RSP fsm */
88	enum tgt_rsp_fsm_state_e{
89	TGT_RSP_READ_IDLE,
90	TGT_RSP_WRITE_IDLE,
91	TGT_RSP_LLSC_IDLE,
92	TGT_RSP_XRAM_IDLE,
93	TGT_RSP_INIT_IDLE,
94	TGT_RSP_CLEANUP_IDLE,
95	TGT_RSP_READ,
96	TGT_RSP_WRITE,
97	TGT_RSP_LLSC,
98	TGT_RSP_XRAM,
99	TGT_RSP_INIT,
100	TGT_RSP_CLEANUP,
101	};
102
103	/* States of the INIT_CMD fsm */
104	enum init_cmd_fsm_state_e{
105	INIT_CMD_INVAL_IDLE,
106	INIT_CMD_INVAL_NLINE,
107	INIT_CMD_XRAM_BRDCAST,
108	INIT_CMD_UPDT_IDLE,
109	INIT_CMD_WRITE_BRDCAST,
110	INIT_CMD_UPDT_NLINE,
111	INIT_CMD_UPDT_INDEX,
112	INIT_CMD_UPDT_DATA,
113	INIT_CMD_SC_UPDT_IDLE,
114	INIT_CMD_SC_BRDCAST,
115	INIT_CMD_SC_UPDT_NLINE,
116	INIT_CMD_SC_UPDT_INDEX,
117	INIT_CMD_SC_UPDT_DATA,
118	INIT_CMD_SC_UPDT_DATA_HIGH,
119	};
120
121	/* States of the INIT_RSP fsm */
122	enum init_rsp_fsm_state_e{
123	INIT_RSP_IDLE,
124	INIT_RSP_UPT_LOCK,
125	INIT_RSP_UPT_CLEAR,
126	INIT_RSP_END,
127	};
128
129	/* States of the READ fsm */
130	enum read_fsm_state_e{
131	READ_IDLE,
132	READ_DIR_LOCK,
133	READ_DIR_HIT,
134	READ_HEAP_LOCK,
135	READ_HEAP_WRITE,
136	READ_HEAP_ERASE,
137	READ_HEAP_LAST,
138	READ_RSP,
139	READ_TRT_LOCK,
140	READ_TRT_SET,
141	READ_XRAM_REQ,
142	};
143
144	/* States of the WRITE fsm */
145	enum write_fsm_state_e{
146	WRITE_IDLE,
147	WRITE_NEXT,
148	WRITE_DIR_LOCK,
149	WRITE_DIR_HIT_READ,
150	WRITE_DIR_HIT,
151	WRITE_UPT_LOCK,
152	WRITE_HEAP_LOCK,
153	WRITE_UPT_REQ,
154	WRITE_UPDATE,
155	WRITE_UPT_DEC,
156	WRITE_RSP,
157	WRITE_TRT_LOCK,
158	WRITE_TRT_DATA,
159	WRITE_TRT_SET,
160	WRITE_WAIT,
161	WRITE_XRAM_REQ,
162	WRITE_TRT_WRITE_LOCK,
163	WRITE_INVAL_LOCK,
164	WRITE_DIR_INVAL,
165	WRITE_INVAL,
166	WRITE_XRAM_SEND,
167	};
168
169	/* States of the IXR_RSP fsm */
170	enum ixr_rsp_fsm_state_e{
171	IXR_RSP_IDLE,
172	IXR_RSP_ACK,
173	IXR_RSP_TRT_ERASE,
174	IXR_RSP_TRT_READ,
175	};
176
177	/* States of the XRAM_RSP fsm */
178	enum xram_rsp_fsm_state_e{
179	XRAM_RSP_IDLE,
180	XRAM_RSP_TRT_COPY,
181	XRAM_RSP_TRT_DIRTY,
182	XRAM_RSP_DIR_LOCK,
183	XRAM_RSP_DIR_UPDT,
184	XRAM_RSP_DIR_RSP,
185	XRAM_RSP_INVAL_LOCK,
186	XRAM_RSP_INVAL_WAIT,
187	XRAM_RSP_INVAL,
188	XRAM_RSP_WRITE_DIRTY,
189	XRAM_RSP_HEAP_ERASE,
190	XRAM_RSP_HEAP_LAST,
191	XRAM_RSP_ERROR_ERASE,
192	XRAM_RSP_ERROR_RSP,
193	};
194
195	/* States of the IXR_CMD fsm */
196	enum ixr_cmd_fsm_state_e{
197	IXR_CMD_READ_IDLE,
198	IXR_CMD_WRITE_IDLE,
199	IXR_CMD_LLSC_IDLE,
200	IXR_CMD_XRAM_IDLE,
201	IXR_CMD_READ_NLINE,
202	IXR_CMD_WRITE_NLINE,
203	IXR_CMD_LLSC_NLINE,
204	IXR_CMD_XRAM_DATA,
205	};
206
207	/* States of the LLSC fsm */
208	enum llsc_fsm_state_e{
209	LLSC_IDLE,
210	SC_DIR_LOCK,
211	SC_DIR_HIT_READ,
212	SC_DIR_HIT_WRITE,
213	SC_UPT_LOCK,
214	SC_WAIT,
215	SC_HEAP_LOCK,
216	SC_UPT_REQ,
217	SC_UPDATE,
218	SC_TRT_LOCK,
219	SC_INVAL_LOCK,
220	SC_DIR_INVAL,
221	SC_INVAL,
222	SC_XRAM_SEND,
223	SC_RSP_FALSE,
224	SC_RSP_TRUE,
225	LLSC_TRT_LOCK,
226	LLSC_TRT_SET,
227	LLSC_XRAM_REQ,
228	};
229
230	/* States of the CLEANUP fsm */
231	enum cleanup_fsm_state_e{
232	CLEANUP_IDLE,
233	CLEANUP_DIR_LOCK,
234	CLEANUP_DIR_WRITE,
235	CLEANUP_HEAP_LOCK,
236	CLEANUP_HEAP_SEARCH,
237	CLEANUP_HEAP_CLEAN,
238	CLEANUP_HEAP_FREE,
239	CLEANUP_UPT_LOCK,
240	CLEANUP_UPT_WRITE,
241	CLEANUP_WRITE_RSP,
242	CLEANUP_RSP,
243	};
244
245	/* States of the ALLOC_DIR fsm */
246	enum alloc_dir_fsm_state_e{
247	ALLOC_DIR_READ,
248	ALLOC_DIR_WRITE,
249	ALLOC_DIR_LLSC,
250	ALLOC_DIR_CLEANUP,
251	ALLOC_DIR_XRAM_RSP,
252	};
253
254	/* States of the ALLOC_TRT fsm */
255	enum alloc_trt_fsm_state_e{
256	ALLOC_TRT_READ,
257	ALLOC_TRT_WRITE,
258	ALLOC_TRT_LLSC,
259	ALLOC_TRT_XRAM_RSP,
260	ALLOC_TRT_IXR_RSP,
261	};
262
263	/* States of the ALLOC_UPT fsm */
264	enum alloc_upt_fsm_state_e{
265	ALLOC_UPT_WRITE,
266	ALLOC_UPT_XRAM_RSP,
267	ALLOC_UPT_INIT_RSP,
268	ALLOC_UPT_CLEANUP,
269	ALLOC_UPT_LLSC,
270	};
271
272	/* States of the ALLOC_HEAP fsm */
273	enum alloc_heap_fsm_state_e{
274	ALLOC_HEAP_READ,
275	ALLOC_HEAP_WRITE,
276	ALLOC_HEAP_LLSC,
277	ALLOC_HEAP_CLEANUP,
278	ALLOC_HEAP_XRAM_RSP,
279	};
280
281	uint32_t m_cpt_cycles; // Counter of cycles
282	uint32_t m_cpt_read; // Number of READ transactions
283	uint32_t m_cpt_read_miss; // Number of MISS READ
284	uint32_t m_cpt_write; // Number of WRITE transactions
285	uint32_t m_cpt_write_miss; // Number of MISS WRITE
286	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
287	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
288	uint32_t m_cpt_update; // Number of UPDATE transactions
289	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
290	uint32_t m_cpt_inval; // Number of INVAL transactions
291	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
292	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
293	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
294	uint32_t m_cpt_ll; // Number of LL transactions
295	uint32_t m_cpt_sc; // Number of SC transactions
296
297	protected:
298
299	SC_HAS_PROCESS(VciMemCacheV4);
300
301	public:
302	sc_in<bool> p_clk;
303	sc_in<bool> p_resetn;
304	soclib::caba::VciTarget<vci_param> p_vci_tgt;
305	soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup;
306	soclib::caba::VciInitiator<vci_param> p_vci_ini;
307	soclib::caba::VciInitiator<vci_param> p_vci_ixr;
308
309	VciMemCacheV4(
310	sc_module_name name, // Instance Name
311	const soclib::common::MappingTable &mtp, // Mapping table for primary requets
312	const soclib::common::MappingTable &mtc, // Mapping table for coherence requets
313	const soclib::common::MappingTable &mtx, // Mapping table for XRAM
314	const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator)
315	const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator)
316	const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target)
317	const soclib::common::IntTab &vci_tgt_index_cleanup, // VCI port to PROC (target) for cleanup
318	size_t nways, // Number of ways per set
319	size_t nsets, // Number of sets
320	size_t nwords, // Number of words per line
321	size_t heap_size=1024); // Size of the heap
322
323	~VciMemCacheV4();
324
325	void transition();
326
327	void genMoore();
328
329	void print_stats();
330
331	void print_trace();
332
333	private:
334
335	// Component attributes
336	const size_t m_initiators; // Number of initiators
337	const size_t m_heap_size; // Size of the heap
338	const size_t m_ways; // Number of ways in a set
339	const size_t m_sets; // Number of cache sets
340	const size_t m_words; // Number of words in a line
341	const size_t m_srcid_ixr; // Srcid for requests to XRAM
342	const size_t m_srcid_ini; // Srcid for requests to processors
343	std::list<soclib::common::Segment> m_seglist; // memory cached into the cache
344	std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
345	vci_addr_t *m_coherence_table; // address(srcid)
346	TransactionTab m_transaction_tab; // xram transaction table
347	UpdateTab m_update_tab; // pending update & invalidate
348	CacheDirectory m_cache_directory; // data cache directory
349	HeapDirectory m_heap_directory; // heap directory
350
351	data_t ***m_cache_data; // data array[set][way][word]
352
353	// adress masks
354	const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
355	const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
356	const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
357	const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
358
359	// broadcast address
360	vci_addr_t m_broadcast_address;
361
362	//////////////////////////////////////////////////
363	// Others registers
364	//////////////////////////////////////////////////
365	sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
366
367	//////////////////////////////////////////////////
368	// Registers controlled by the TGT_CMD fsm
369	//////////////////////////////////////////////////
370
371	// Fifo between TGT_CMD fsm and READ fsm
372	GenericFifo<uint64_t> m_cmd_read_addr_fifo;
373	GenericFifo<size_t> m_cmd_read_length_fifo;
374	GenericFifo<size_t> m_cmd_read_srcid_fifo;
375	GenericFifo<size_t> m_cmd_read_trdid_fifo;
376	GenericFifo<size_t> m_cmd_read_pktid_fifo;
377
378	// Fifo between TGT_CMD fsm and WRITE fsm
379	GenericFifo<uint64_t> m_cmd_write_addr_fifo;
380	GenericFifo<bool> m_cmd_write_eop_fifo;
381	GenericFifo<size_t> m_cmd_write_srcid_fifo;
382	GenericFifo<size_t> m_cmd_write_trdid_fifo;
383	GenericFifo<size_t> m_cmd_write_pktid_fifo;
384	GenericFifo<data_t> m_cmd_write_data_fifo;
385	GenericFifo<be_t> m_cmd_write_be_fifo;
386
387	// Fifo between TGT_CMD fsm and LLSC fsm
388	GenericFifo<uint64_t> m_cmd_llsc_addr_fifo;
389	GenericFifo<bool> m_cmd_llsc_eop_fifo;
390	GenericFifo<size_t> m_cmd_llsc_srcid_fifo;
391	GenericFifo<size_t> m_cmd_llsc_trdid_fifo;
392	GenericFifo<size_t> m_cmd_llsc_pktid_fifo;
393	GenericFifo<data_t> m_cmd_llsc_wdata_fifo;
394
395	sc_signal<int> r_tgt_cmd_fsm;
396
397	size_t nseg;
398	size_t ncseg;
399	soclib::common::Segment **m_seg;
400	soclib::common::Segment **m_cseg;
401	///////////////////////////////////////////////////////
402	// Registers controlled by the READ fsm
403	///////////////////////////////////////////////////////
404
405	sc_signal<int> r_read_fsm; // FSM state
406	sc_signal<size_t> r_read_copy; // Srcid of the first copy
407	sc_signal<bool> r_read_copy_inst; // Type of the first copy
408	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
409	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
410	sc_signal<bool> r_read_lock; // lock bit (in directory)
411	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
412	sc_signal<size_t> r_read_count; // number of copies
413	sc_signal<size_t> r_read_ptr; // pointer to the heap
414	sc_signal<data_t> *r_read_data; // data (one cache line)
415	sc_signal<size_t> r_read_way; // associative way (in cache)
416	sc_signal<size_t> r_read_trt_index; // Transaction Table index
417	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
418	sc_signal<bool> r_read_last_free; // Last free entry
419
420	// Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
421	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
422	sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index
423	sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table
424
425	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
426	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
427	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
428	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
429	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
430	sc_signal<data_t> *r_read_to_tgt_rsp_data; // data (one cache line)
431	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
432	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
433
434	///////////////////////////////////////////////////////////////
435	// Registers controlled by the WRITE fsm
436	///////////////////////////////////////////////////////////////
437
438	sc_signal<int> r_write_fsm; // FSM state
439	sc_signal<addr_t> r_write_address; // first word address
440	sc_signal<size_t> r_write_word_index; // first word index in line
441	sc_signal<size_t> r_write_word_count; // number of words in line
442	sc_signal<size_t> r_write_srcid; // transaction srcid
443	sc_signal<size_t> r_write_trdid; // transaction trdid
444	sc_signal<size_t> r_write_pktid; // transaction pktid
445	sc_signal<data_t> *r_write_data; // data (one cache line)
446	sc_signal<be_t> *r_write_be; // one byte enable per word
447	sc_signal<bool> r_write_byte; // is it a byte write
448	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
449	sc_signal<bool> r_write_lock; // lock bit (in directory)
450	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
451	sc_signal<size_t> r_write_copy; // first owner of the line
452	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
453	sc_signal<size_t> r_write_count; // number of copies
454	sc_signal<size_t> r_write_ptr; // pointer to the heap
455	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
456	sc_signal<bool> r_write_to_dec; // need to decrement update counter
457	sc_signal<size_t> r_write_way; // way of the line
458	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
459	sc_signal<size_t> r_write_upt_index; // index in Update Table
460
461	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
462	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
463	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
464	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
465	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
466
467	// Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
468	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
469	sc_signal<bool> r_write_to_ixr_cmd_write; // write request
470	sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index
471	sc_signal<data_t> *r_write_to_ixr_cmd_data; // cache line data
472	sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table
473
474	// Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
475	sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request
476	sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request
477	sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index
478	sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table
479	sc_signal<data_t> *r_write_to_init_cmd_data; // data (one cache line)
480	sc_signal<be_t> *r_write_to_init_cmd_be; // word enable
481	sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line
482	sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line
483	GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type
484	GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids
485
486	// Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
487	sc_signal<bool> r_write_to_init_rsp_req; // valid request
488	sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table
489
490	/////////////////////////////////////////////////////////
491	// Registers controlled by INIT_RSP fsm
492	//////////////////////////////////////////////////////////
493
494	sc_signal<int> r_init_rsp_fsm; // FSM state
495	sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table
496	sc_signal<size_t> r_init_rsp_srcid; // pending write srcid
497	sc_signal<size_t> r_init_rsp_trdid; // pending write trdid
498	sc_signal<size_t> r_init_rsp_pktid; // pending write pktid
499	sc_signal<addr_t> r_init_rsp_nline; // pending write nline
500
501	// Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
502	sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request
503	sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid
504	sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid
505	sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid
506
507	///////////////////////////////////////////////////////
508	// Registers controlled by CLEANUP fsm
509	///////////////////////////////////////////////////////
510
511	sc_signal<int> r_cleanup_fsm; // FSM state
512	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
513	sc_signal<size_t> r_cleanup_trdid; // transaction trdid
514	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
515	sc_signal<addr_t> r_cleanup_nline; // cache line index
516
517	sc_signal<copy_t> r_cleanup_copy; // first copy
518	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
519	sc_signal<copy_t> r_cleanup_count; // number of copies
520	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
521	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
522	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
523	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
524	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
525	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
526	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
527	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
528	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
529	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
530
531	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response
532	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
533	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
534	sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp
535
536	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
537
538	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
539	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
540	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
541	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
542	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
543
544	///////////////////////////////////////////////////////
545	// Registers controlled by LLSC fsm
546	///////////////////////////////////////////////////////
547
548	sc_signal<int> r_llsc_fsm; // FSM state
549	sc_signal<data_t> r_llsc_wdata; // write data word
550	sc_signal<data_t> *r_llsc_rdata; // read data word
551	sc_signal<uint32_t> r_llsc_lfsr; // lfsr for random introducing
552	sc_signal<size_t> r_llsc_cpt; // size of command
553	sc_signal<copy_t> r_llsc_copy; // Srcid of the first copy
554	sc_signal<bool> r_llsc_copy_inst; // Type of the first copy
555	sc_signal<size_t> r_llsc_count; // number of copies
556	sc_signal<size_t> r_llsc_ptr; // pointer to the heap
557	sc_signal<size_t> r_llsc_next_ptr; // next pointer to the heap
558	sc_signal<bool> r_llsc_is_cnt; // is_cnt bit (in directory)
559	sc_signal<bool> r_llsc_dirty; // dirty bit (in directory)
560	sc_signal<size_t> r_llsc_way; // way in directory
561	sc_signal<size_t> r_llsc_set; // set in directory
562	sc_signal<data_t> r_llsc_tag; // cache line tag (in directory)
563	sc_signal<size_t> r_llsc_trt_index; // Transaction Table index
564	sc_signal<size_t> r_llsc_upt_index; // Update Table index
565
566	// Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)
567	sc_signal<bool> r_llsc_to_ixr_cmd_req; // valid request
568	sc_signal<addr_t> r_llsc_to_ixr_cmd_nline; // cache line index
569	sc_signal<size_t> r_llsc_to_ixr_cmd_trdid; // index in Transaction Table
570	sc_signal<bool> r_llsc_to_ixr_cmd_write; // write request
571	sc_signal<data_t> *r_llsc_to_ixr_cmd_data; // cache line data
572
573
574	// Buffer between LLSC fsm and TGT_RSP fsm
575	sc_signal<bool> r_llsc_to_tgt_rsp_req; // valid request
576	sc_signal<data_t> r_llsc_to_tgt_rsp_data; // read data word
577	sc_signal<size_t> r_llsc_to_tgt_rsp_srcid; // Transaction srcid
578	sc_signal<size_t> r_llsc_to_tgt_rsp_trdid; // Transaction trdid
579	sc_signal<size_t> r_llsc_to_tgt_rsp_pktid; // Transaction pktid
580
581	// Buffer between LLSC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
582	sc_signal<bool> r_llsc_to_init_cmd_multi_req; // valid request
583	sc_signal<bool> r_llsc_to_init_cmd_brdcast_req; // brdcast request
584	sc_signal<addr_t> r_llsc_to_init_cmd_nline; // cache line index
585	sc_signal<size_t> r_llsc_to_init_cmd_trdid; // index in Update Table
586	sc_signal<data_t> r_llsc_to_init_cmd_wdata; // data (one word)
587	sc_signal<bool> r_llsc_to_init_cmd_is_long; // it is a 64 bits SC
588	sc_signal<data_t> r_llsc_to_init_cmd_wdata_high; // data high (one word)
589	sc_signal<size_t> r_llsc_to_init_cmd_index; // index of the word in line
590	GenericFifo<bool> m_llsc_to_init_cmd_inst_fifo; // fifo for the L1 type
591	GenericFifo<size_t> m_llsc_to_init_cmd_srcid_fifo; // fifo for srcids
592
593	// Buffer between LLSC fsm and INIT_RSP fsm (Decrement UPT entry)
594	sc_signal<bool> r_llsc_to_init_rsp_req; // valid request
595	sc_signal<size_t> r_llsc_to_init_rsp_upt_index; // index in update table
596
597	////////////////////////////////////////////////////
598	// Registers controlled by the IXR_RSP fsm
599	////////////////////////////////////////////////////
600
601	sc_signal<int> r_ixr_rsp_fsm; // FSM state
602	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
603	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
604
605	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
606	sc_signal<bool> *r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
607
608	////////////////////////////////////////////////////
609	// Registers controlled by the XRAM_RSP fsm
610	////////////////////////////////////////////////////
611
612	sc_signal<int> r_xram_rsp_fsm; // FSM state
613	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
614	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
615	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
616	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
617	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
618	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
619	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
620	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
621	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
622	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
623	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
624	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
625	sc_signal<data_t> *r_xram_rsp_victim_data; // victim line data
626	sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index
627	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
628
629	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
630	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
631	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
632	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
633	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
634	sc_signal<data_t> *r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
635	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
636	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length;// length of the response
637	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror;// send error to requester
638
639	// Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
640	sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request
641	sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request
642	sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index;
643	sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry
644	GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type
645	GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids
646
647	// Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
648	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
649	sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index
650	sc_signal<data_t> *r_xram_rsp_to_ixr_cmd_data; // cache line data
651	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
652
653	////////////////////////////////////////////////////
654	// Registers controlled by the IXR_CMD fsm
655	////////////////////////////////////////////////////
656
657	sc_signal<int> r_ixr_cmd_fsm;
658	sc_signal<size_t> r_ixr_cmd_cpt;
659
660	////////////////////////////////////////////////////
661	// Registers controlled by TGT_RSP fsm
662	////////////////////////////////////////////////////
663
664	sc_signal<int> r_tgt_rsp_fsm;
665	sc_signal<size_t> r_tgt_rsp_cpt;
666
667	////////////////////////////////////////////////////
668	// Registers controlled by INIT_CMD fsm
669	////////////////////////////////////////////////////
670
671	sc_signal<int> r_init_cmd_fsm;
672	sc_signal<size_t> r_init_cmd_cpt;
673	sc_signal<bool> r_init_cmd_inst;
674
675	////////////////////////////////////////////////////
676	// Registers controlled by ALLOC_DIR fsm
677	////////////////////////////////////////////////////
678
679	sc_signal<int> r_alloc_dir_fsm;
680
681	////////////////////////////////////////////////////
682	// Registers controlled by ALLOC_TRT fsm
683	////////////////////////////////////////////////////
684
685	sc_signal<int> r_alloc_trt_fsm;
686
687	////////////////////////////////////////////////////
688	// Registers controlled by ALLOC_UPT fsm
689	////////////////////////////////////////////////////
690
691	sc_signal<int> r_alloc_upt_fsm;
692
693	////////////////////////////////////////////////////
694	// Registers controlled by ALLOC_HEAP fsm
695	////////////////////////////////////////////////////
696
697	sc_signal<int> r_alloc_heap_fsm;
698
699	}; // end class VciMemCacheV4
700
701	}}
702
703	#endif
704
705	// Local Variables:
706	// tab-width: 4
707	// c-basic-offset: 4
708	// c-file-offsets:((innamespace . 0)(inline-open . 0))
709	// indent-tabs-mode: nil
710	// End:
711
712	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
713

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