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vci_mem_cache_v4.h @ 184

Last change on this file since 184 was 184, checked in by alain, 12 years ago
mproving the debug mechanisms
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1	/* -- c++ --
2	* File : vci_mem_cache_v4.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu
28	*/
29	/*
30	*
31	* Modifications done by Christophe Choichillon on the 7/04/2009:
32	* - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
33	* - Adding a new VCI target port for the CLEANUP network
34	* - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
35	*
36	* Modifications to do :
37	* - Adding new variables used by the CLEANUP FSM
38	*
39	*/
40
41	#ifndef SOCLIB_CABA_MEM_CACHE_V4_H
42	#define SOCLIB_CABA_MEM_CACHE_V4_H
43
44	#include <inttypes.h>
45	#include <systemc>
46	#include <list>
47	#include <cassert>
48	#include "arithmetics.h"
49	#include "alloc_elems.h"
50	#include "caba_base_module.h"
51	#include "vci_target.h"
52	#include "vci_initiator.h"
53	#include "generic_fifo.h"
54	#include "mapping_table.h"
55	#include "int_tab.h"
56	#include "mem_cache_directory_v4.h"
57	#include "xram_transaction_v4.h"
58	#include "update_tab_v4.h"
59
60	#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
61	#define UPDATE_TAB_LINES 4 // Number of lines in the update tab
62
63	namespace soclib { namespace caba {
64	using namespace sc_core;
65
66	template<typename vci_param>
67	class VciMemCacheV4
68	: public soclib::caba::BaseModule
69	{
70	typedef sc_dt::sc_uint<40> addr_t;
71	typedef typename vci_param::fast_addr_t vci_addr_t;
72	typedef uint32_t data_t;
73	typedef uint32_t tag_t;
74	typedef uint32_t size_t;
75	typedef uint32_t be_t;
76	typedef uint32_t copy_t;
77
78	/* States of the TGT_CMD fsm */
79	enum tgt_cmd_fsm_state_e{
80	TGT_CMD_IDLE,
81	TGT_CMD_READ,
82	TGT_CMD_WRITE,
83	TGT_CMD_ATOMIC,
84	};
85
86	/* States of the TGT_RSP fsm */
87	enum tgt_rsp_fsm_state_e{
88	TGT_RSP_READ_IDLE,
89	TGT_RSP_WRITE_IDLE,
90	TGT_RSP_SC_IDLE,
91	TGT_RSP_XRAM_IDLE,
92	TGT_RSP_INIT_IDLE,
93	TGT_RSP_CLEANUP_IDLE,
94	TGT_RSP_READ,
95	TGT_RSP_WRITE,
96	TGT_RSP_SC,
97	TGT_RSP_XRAM,
98	TGT_RSP_INIT,
99	TGT_RSP_CLEANUP,
100	};
101
102	/* States of the INIT_CMD fsm */
103	enum init_cmd_fsm_state_e{
104	INIT_CMD_INVAL_IDLE,
105	INIT_CMD_INVAL_NLINE,
106	INIT_CMD_XRAM_BRDCAST,
107	INIT_CMD_UPDT_IDLE,
108	INIT_CMD_WRITE_BRDCAST,
109	INIT_CMD_UPDT_NLINE,
110	INIT_CMD_UPDT_INDEX,
111	INIT_CMD_UPDT_DATA,
112	INIT_CMD_SC_UPDT_IDLE,
113	INIT_CMD_SC_BRDCAST,
114	INIT_CMD_SC_UPDT_NLINE,
115	INIT_CMD_SC_UPDT_INDEX,
116	INIT_CMD_SC_UPDT_DATA,
117	INIT_CMD_SC_UPDT_DATA_HIGH,
118	};
119
120	/* States of the INIT_RSP fsm */
121	enum init_rsp_fsm_state_e{
122	INIT_RSP_IDLE,
123	INIT_RSP_UPT_LOCK,
124	INIT_RSP_UPT_CLEAR,
125	INIT_RSP_END,
126	};
127
128	/* States of the READ fsm */
129	enum read_fsm_state_e{
130	READ_IDLE,
131	READ_DIR_LOCK,
132	READ_DIR_HIT,
133	READ_HEAP_LOCK,
134	READ_HEAP_WRITE,
135	READ_HEAP_ERASE,
136	READ_HEAP_LAST,
137	READ_RSP,
138	READ_TRT_LOCK,
139	READ_TRT_SET,
140	READ_TRT_REQ,
141	};
142
143	/* States of the WRITE fsm */
144	enum write_fsm_state_e{
145	WRITE_IDLE,
146	WRITE_NEXT,
147	WRITE_DIR_LOCK,
148	WRITE_DIR_HIT_READ,
149	WRITE_DIR_HIT,
150	WRITE_UPT_LOCK,
151	WRITE_HEAP_LOCK,
152	WRITE_UPT_REQ,
153	WRITE_UPDATE,
154	WRITE_UPT_DEC,
155	WRITE_RSP,
156	WRITE_TRT_LOCK,
157	WRITE_TRT_DATA,
158	WRITE_TRT_SET,
159	WRITE_WAIT,
160	WRITE_XRAM_REQ,
161	WRITE_TRT_WRITE_LOCK,
162	WRITE_INVAL_LOCK,
163	WRITE_DIR_INVAL,
164	WRITE_INVAL,
165	WRITE_XRAM_SEND,
166	};
167
168	/* States of the IXR_RSP fsm */
169	enum ixr_rsp_fsm_state_e{
170	IXR_RSP_IDLE,
171	IXR_RSP_ACK,
172	IXR_RSP_TRT_ERASE,
173	IXR_RSP_TRT_READ,
174	};
175
176	/* States of the XRAM_RSP fsm */
177	enum xram_rsp_fsm_state_e{
178	XRAM_RSP_IDLE,
179	XRAM_RSP_TRT_COPY,
180	XRAM_RSP_TRT_DIRTY,
181	XRAM_RSP_DIR_LOCK,
182	XRAM_RSP_DIR_UPDT,
183	XRAM_RSP_DIR_RSP,
184	XRAM_RSP_INVAL_LOCK,
185	XRAM_RSP_INVAL_WAIT,
186	XRAM_RSP_INVAL,
187	XRAM_RSP_WRITE_DIRTY,
188	XRAM_RSP_HEAP_ERASE,
189	XRAM_RSP_HEAP_LAST,
190	XRAM_RSP_ERROR_ERASE,
191	XRAM_RSP_ERROR_RSP,
192	};
193
194	/* States of the IXR_CMD fsm */
195	enum ixr_cmd_fsm_state_e{
196	IXR_CMD_READ_IDLE,
197	IXR_CMD_WRITE_IDLE,
198	IXR_CMD_SC_IDLE,
199	IXR_CMD_XRAM_IDLE,
200	IXR_CMD_READ_NLINE,
201	IXR_CMD_WRITE_NLINE,
202	IXR_CMD_SC_NLINE,
203	IXR_CMD_XRAM_DATA,
204	};
205
206	/* States of the SC fsm */
207	enum sc_fsm_state_e{
208	SC_IDLE,
209	SC_DIR_LOCK,
210	SC_DIR_HIT_READ,
211	SC_DIR_HIT_WRITE,
212	SC_UPT_LOCK,
213	SC_WAIT,
214	SC_HEAP_LOCK,
215	SC_UPT_REQ,
216	SC_UPT_NEXT,
217	SC_TRT_PUT_LOCK,
218	SC_INVAL_LOCK,
219	SC_DIR_INVAL,
220	SC_INVAL,
221	SC_TRT_PUT_REQ,
222	SC_RSP_FAIL,
223	SC_RSP_SUCCESS,
224	SC_TRT_GET_LOCK,
225	SC_TRT_GET_SET,
226	SC_TRT_GET_REQ,
227	};
228
229	/* States of the CLEANUP fsm */
230	enum cleanup_fsm_state_e{
231	CLEANUP_IDLE,
232	CLEANUP_DIR_LOCK,
233	CLEANUP_DIR_WRITE,
234	CLEANUP_HEAP_LOCK,
235	CLEANUP_HEAP_SEARCH,
236	CLEANUP_HEAP_CLEAN,
237	CLEANUP_HEAP_FREE,
238	CLEANUP_UPT_LOCK,
239	CLEANUP_UPT_WRITE,
240	CLEANUP_WRITE_RSP,
241	CLEANUP_RSP,
242	};
243
244	/* States of the ALLOC_DIR fsm */
245	enum alloc_dir_fsm_state_e{
246	ALLOC_DIR_READ,
247	ALLOC_DIR_WRITE,
248	ALLOC_DIR_SC,
249	ALLOC_DIR_CLEANUP,
250	ALLOC_DIR_XRAM_RSP,
251	};
252
253	/* States of the ALLOC_TRT fsm */
254	enum alloc_trt_fsm_state_e{
255	ALLOC_TRT_READ,
256	ALLOC_TRT_WRITE,
257	ALLOC_TRT_SC,
258	ALLOC_TRT_XRAM_RSP,
259	ALLOC_TRT_IXR_RSP,
260	};
261
262	/* States of the ALLOC_UPT fsm */
263	enum alloc_upt_fsm_state_e{
264	ALLOC_UPT_WRITE,
265	ALLOC_UPT_XRAM_RSP,
266	ALLOC_UPT_INIT_RSP,
267	ALLOC_UPT_CLEANUP,
268	ALLOC_UPT_SC,
269	};
270
271	/* States of the ALLOC_HEAP fsm */
272	enum alloc_heap_fsm_state_e{
273	ALLOC_HEAP_READ,
274	ALLOC_HEAP_WRITE,
275	ALLOC_HEAP_SC,
276	ALLOC_HEAP_CLEANUP,
277	ALLOC_HEAP_XRAM_RSP,
278	};
279
280	// debug variables (for each FSM)
281	size_t m_debug_start_cycle;
282	bool m_debug_ok;
283	bool m_debug_global;
284	bool m_debug_tgt_cmd_fsm;
285	bool m_debug_tgt_rsp_fsm;
286	bool m_debug_init_cmd_fsm;
287	bool m_debug_init_rsp_fsm;
288	bool m_debug_read_fsm;
289	bool m_debug_write_fsm;
290	bool m_debug_sc_fsm;
291	bool m_debug_cleanup_fsm;
292	bool m_debug_ixr_cmd_fsm;
293	bool m_debug_ixr_rsp_fsm;
294	bool m_debug_xram_rsp_fsm;
295	bool m_debug_previous_hit;
296	size_t m_debug_previous_count;
297
298	// instrumentation counters
299	uint32_t m_cpt_cycles; // Counter of cycles
300	uint32_t m_cpt_read; // Number of READ transactions
301	uint32_t m_cpt_read_miss; // Number of MISS READ
302	uint32_t m_cpt_write; // Number of WRITE transactions
303	uint32_t m_cpt_write_miss; // Number of MISS WRITE
304	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
305	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
306	uint32_t m_cpt_update; // Number of UPDATE transactions
307	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
308	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
309	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
310	uint32_t m_cpt_inval; // Number of INVAL transactions
311	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
312	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
313	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
314	uint32_t m_cpt_ll; // Number of LL transactions
315	uint32_t m_cpt_sc; // Number of SC transactions
316
317	size_t m_prev_count;
318
319	protected:
320
321	SC_HAS_PROCESS(VciMemCacheV4);
322
323	public:
324	sc_in<bool> p_clk;
325	sc_in<bool> p_resetn;
326	soclib::caba::VciTarget<vci_param> p_vci_tgt;
327	soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup;
328	soclib::caba::VciInitiator<vci_param> p_vci_ini;
329	soclib::caba::VciInitiator<vci_param> p_vci_ixr;
330
331	VciMemCacheV4(
332	sc_module_name name, // Instance Name
333	const soclib::common::MappingTable &mtp, // Mapping table for primary requets
334	const soclib::common::MappingTable &mtc, // Mapping table for coherence requets
335	const soclib::common::MappingTable &mtx, // Mapping table for XRAM
336	const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator)
337	const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator)
338	const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target)
339	const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup
340	size_t nways, // Number of ways per set
341	size_t nsets, // Number of sets
342	size_t nwords, // Number of words per line
343	size_t heap_size=1024, // Size of the heap
344	size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT
345	size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT
346	size_t debug_start_cycle=0,
347	bool debug_ok=false);
348
349	~VciMemCacheV4();
350
351	void transition();
352	void genMoore();
353	void print_stats();
354	void print_trace();
355	void cache_monitor(vci_addr_t addr);
356
357	private:
358
359	// Component attributes
360	const size_t m_initiators; // Number of initiators
361	const size_t m_heap_size; // Size of the heap
362	const size_t m_ways; // Number of ways in a set
363	const size_t m_sets; // Number of cache sets
364	const size_t m_words; // Number of words in a line
365	const size_t m_srcid_ixr; // Srcid for requests to XRAM
366	const size_t m_srcid_ini; // Srcid for requests to processors
367	std::list<soclib::common::Segment> m_seglist; // memory cached into the cache
368	std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
369	vci_addr_t *m_coherence_table; // address(srcid)
370	uint32_t m_transaction_tab_lines;
371	TransactionTab m_transaction_tab; // xram transaction table
372	uint32_t m_update_tab_lines;
373	UpdateTab m_update_tab; // pending update & invalidate
374	CacheDirectory m_cache_directory; // data cache directory
375	HeapDirectory m_heap; // heap for copies
376
377	data_t ***m_cache_data; // data array[set][way][word]
378
379	// adress masks
380	const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
381	const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
382	const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
383	const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
384
385	// broadcast address
386	vci_addr_t m_broadcast_address;
387
388	//////////////////////////////////////////////////
389	// Others registers
390	//////////////////////////////////////////////////
391	sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
392	sc_signal<size_t> xxx_count;
393
394	//////////////////////////////////////////////////
395	// Registers controlled by the TGT_CMD fsm
396	//////////////////////////////////////////////////
397
398	// Fifo between TGT_CMD fsm and READ fsm
399	GenericFifo<uint64_t> m_cmd_read_addr_fifo;
400	GenericFifo<size_t> m_cmd_read_length_fifo;
401	GenericFifo<size_t> m_cmd_read_srcid_fifo;
402	GenericFifo<size_t> m_cmd_read_trdid_fifo;
403	GenericFifo<size_t> m_cmd_read_pktid_fifo;
404
405	// Fifo between TGT_CMD fsm and WRITE fsm
406	GenericFifo<uint64_t> m_cmd_write_addr_fifo;
407	GenericFifo<bool> m_cmd_write_eop_fifo;
408	GenericFifo<size_t> m_cmd_write_srcid_fifo;
409	GenericFifo<size_t> m_cmd_write_trdid_fifo;
410	GenericFifo<size_t> m_cmd_write_pktid_fifo;
411	GenericFifo<data_t> m_cmd_write_data_fifo;
412	GenericFifo<be_t> m_cmd_write_be_fifo;
413
414	// Fifo between TGT_CMD fsm and SC fsm
415	GenericFifo<uint64_t> m_cmd_sc_addr_fifo;
416	GenericFifo<bool> m_cmd_sc_eop_fifo;
417	GenericFifo<size_t> m_cmd_sc_srcid_fifo;
418	GenericFifo<size_t> m_cmd_sc_trdid_fifo;
419	GenericFifo<size_t> m_cmd_sc_pktid_fifo;
420	GenericFifo<data_t> m_cmd_sc_wdata_fifo;
421
422	sc_signal<int> r_tgt_cmd_fsm;
423
424	size_t nseg;
425	size_t ncseg;
426	soclib::common::Segment **m_seg;
427	soclib::common::Segment **m_cseg;
428	///////////////////////////////////////////////////////
429	// Registers controlled by the READ fsm
430	///////////////////////////////////////////////////////
431
432	sc_signal<int> r_read_fsm; // FSM state
433	sc_signal<size_t> r_read_copy; // Srcid of the first copy
434	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
435	sc_signal<bool> r_read_copy_inst; // Type of the first copy
436	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
437	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
438	sc_signal<bool> r_read_lock; // lock bit (in directory)
439	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
440	sc_signal<size_t> r_read_count; // number of copies
441	sc_signal<size_t> r_read_ptr; // pointer to the heap
442	sc_signal<data_t> *r_read_data; // data (one cache line)
443	sc_signal<size_t> r_read_way; // associative way (in cache)
444	sc_signal<size_t> r_read_trt_index; // Transaction Table index
445	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
446	sc_signal<bool> r_read_last_free; // Last free entry
447
448	// Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
449	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
450	sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index
451	sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table
452
453	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
454	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
455	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
456	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
457	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
458	sc_signal<data_t> *r_read_to_tgt_rsp_data; // data (one cache line)
459	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
460	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
461
462	///////////////////////////////////////////////////////////////
463	// Registers controlled by the WRITE fsm
464	///////////////////////////////////////////////////////////////
465
466	sc_signal<int> r_write_fsm; // FSM state
467	sc_signal<addr_t> r_write_address; // first word address
468	sc_signal<size_t> r_write_word_index; // first word index in line
469	sc_signal<size_t> r_write_word_count; // number of words in line
470	sc_signal<size_t> r_write_srcid; // transaction srcid
471	sc_signal<size_t> r_write_trdid; // transaction trdid
472	sc_signal<size_t> r_write_pktid; // transaction pktid
473	sc_signal<data_t> *r_write_data; // data (one cache line)
474	sc_signal<be_t> *r_write_be; // one byte enable per word
475	sc_signal<bool> r_write_byte; // is it a byte write
476	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
477	sc_signal<bool> r_write_lock; // lock bit (in directory)
478	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
479	sc_signal<size_t> r_write_copy; // first owner of the line
480	sc_signal<size_t> r_write_copy_cache; // first owner of the line
481	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
482	sc_signal<size_t> r_write_count; // number of copies
483	sc_signal<size_t> r_write_ptr; // pointer to the heap
484	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
485	sc_signal<bool> r_write_to_dec; // need to decrement update counter
486	sc_signal<size_t> r_write_way; // way of the line
487	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
488	sc_signal<size_t> r_write_upt_index; // index in Update Table
489
490	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
491	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
492	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
493	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
494	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
495
496	// Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
497	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
498	sc_signal<bool> r_write_to_ixr_cmd_write; // write request
499	sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index
500	sc_signal<data_t> *r_write_to_ixr_cmd_data; // cache line data
501	sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table
502
503	// Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
504	sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request
505	sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request
506	sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index
507	sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table
508	sc_signal<data_t> *r_write_to_init_cmd_data; // data (one cache line)
509	sc_signal<be_t> *r_write_to_init_cmd_be; // word enable
510	sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line
511	sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line
512	GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type
513	GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids
514	GenericFifo<size_t> m_write_to_init_cmd_cache_id_fifo; // fifo for srcids
515
516	// Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
517	sc_signal<bool> r_write_to_init_rsp_req; // valid request
518	sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table
519
520	/////////////////////////////////////////////////////////
521	// Registers controlled by INIT_RSP fsm
522	//////////////////////////////////////////////////////////
523
524	sc_signal<int> r_init_rsp_fsm; // FSM state
525	sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table
526	sc_signal<size_t> r_init_rsp_srcid; // pending write srcid
527	sc_signal<size_t> r_init_rsp_trdid; // pending write trdid
528	sc_signal<size_t> r_init_rsp_pktid; // pending write pktid
529	sc_signal<addr_t> r_init_rsp_nline; // pending write nline
530
531	// Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
532	sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request
533	sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid
534	sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid
535	sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid
536
537	///////////////////////////////////////////////////////
538	// Registers controlled by CLEANUP fsm
539	///////////////////////////////////////////////////////
540
541	sc_signal<int> r_cleanup_fsm; // FSM state
542	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
543	sc_signal<size_t> r_cleanup_trdid; // transaction trdid
544	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
545	sc_signal<addr_t> r_cleanup_nline; // cache line index
546
547	sc_signal<copy_t> r_cleanup_copy; // first copy
548	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
549	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
550	sc_signal<copy_t> r_cleanup_count; // number of copies
551	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
552	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
553	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
554	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
555	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
556	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
557	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
558	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
559	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
560	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
561	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
562
563	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response
564	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
565	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
566	sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp
567
568	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
569
570	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
571	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
572	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
573	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
574	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
575
576	///////////////////////////////////////////////////////
577	// Registers controlled by SC fsm
578	///////////////////////////////////////////////////////
579
580	sc_signal<int> r_sc_fsm; // FSM state
581	sc_signal<data_t> r_sc_wdata; // write data word
582	sc_signal<data_t> *r_sc_rdata; // read data word
583	sc_signal<uint32_t> r_sc_lfsr; // lfsr for random introducing
584	sc_signal<size_t> r_sc_cpt; // size of command
585	sc_signal<copy_t> r_sc_copy; // Srcid of the first copy
586	sc_signal<copy_t> r_sc_copy_cache; // Srcid of the first copy
587	sc_signal<bool> r_sc_copy_inst; // Type of the first copy
588	sc_signal<size_t> r_sc_count; // number of copies
589	sc_signal<size_t> r_sc_ptr; // pointer to the heap
590	sc_signal<size_t> r_sc_next_ptr; // next pointer to the heap
591	sc_signal<bool> r_sc_is_cnt; // is_cnt bit (in directory)
592	sc_signal<bool> r_sc_dirty; // dirty bit (in directory)
593	sc_signal<size_t> r_sc_way; // way in directory
594	sc_signal<size_t> r_sc_set; // set in directory
595	sc_signal<data_t> r_sc_tag; // cache line tag (in directory)
596	sc_signal<size_t> r_sc_trt_index; // Transaction Table index
597	sc_signal<size_t> r_sc_upt_index; // Update Table index
598
599	// Buffer between SC fsm and INIT_CMD fsm (XRAM read)
600	sc_signal<bool> r_sc_to_ixr_cmd_req; // valid request
601	sc_signal<addr_t> r_sc_to_ixr_cmd_nline; // cache line index
602	sc_signal<size_t> r_sc_to_ixr_cmd_trdid; // index in Transaction Table
603	sc_signal<bool> r_sc_to_ixr_cmd_write; // write request
604	sc_signal<data_t> *r_sc_to_ixr_cmd_data; // cache line data
605
606
607	// Buffer between SC fsm and TGT_RSP fsm
608	sc_signal<bool> r_sc_to_tgt_rsp_req; // valid request
609	sc_signal<data_t> r_sc_to_tgt_rsp_data; // read data word
610	sc_signal<size_t> r_sc_to_tgt_rsp_srcid; // Transaction srcid
611	sc_signal<size_t> r_sc_to_tgt_rsp_trdid; // Transaction trdid
612	sc_signal<size_t> r_sc_to_tgt_rsp_pktid; // Transaction pktid
613
614	// Buffer between SC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
615	sc_signal<bool> r_sc_to_init_cmd_multi_req; // valid request
616	sc_signal<bool> r_sc_to_init_cmd_brdcast_req; // brdcast request
617	sc_signal<addr_t> r_sc_to_init_cmd_nline; // cache line index
618	sc_signal<size_t> r_sc_to_init_cmd_trdid; // index in Update Table
619	sc_signal<data_t> r_sc_to_init_cmd_wdata; // data (one word)
620	sc_signal<bool> r_sc_to_init_cmd_is_long; // it is a 64 bits SC
621	sc_signal<data_t> r_sc_to_init_cmd_wdata_high; // data high (one word)
622	sc_signal<size_t> r_sc_to_init_cmd_index; // index of the word in line
623	GenericFifo<bool> m_sc_to_init_cmd_inst_fifo; // fifo for the L1 type
624	GenericFifo<size_t> m_sc_to_init_cmd_srcid_fifo; // fifo for srcids
625	GenericFifo<size_t> m_sc_to_init_cmd_cache_id_fifo; // fifo for srcids
626
627	// Buffer between SC fsm and INIT_RSP fsm (Decrement UPT entry)
628	sc_signal<bool> r_sc_to_init_rsp_req; // valid request
629	sc_signal<size_t> r_sc_to_init_rsp_upt_index; // index in update table
630
631	////////////////////////////////////////////////////
632	// Registers controlled by the IXR_RSP fsm
633	////////////////////////////////////////////////////
634
635	sc_signal<int> r_ixr_rsp_fsm; // FSM state
636	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
637	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
638
639	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
640	sc_signal<bool> *r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
641
642	////////////////////////////////////////////////////
643	// Registers controlled by the XRAM_RSP fsm
644	////////////////////////////////////////////////////
645
646	sc_signal<int> r_xram_rsp_fsm; // FSM state
647	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
648	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
649	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
650	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
651	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
652	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
653	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
654	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
655	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
656	sc_signal<copy_t> r_xram_rsp_victim_copy_cache;// victim line first copy
657	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
658	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
659	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
660	sc_signal<data_t> *r_xram_rsp_victim_data; // victim line data
661	sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index
662	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
663
664	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
665	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
666	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
667	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
668	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
669	sc_signal<data_t> *r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
670	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
671	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length;// length of the response
672	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror;// send error to requester
673
674	// Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
675	sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request
676	sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request
677	sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index;
678	sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry
679	GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type
680	GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids
681	GenericFifo<size_t> m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids
682
683	// Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
684	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
685	sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index
686	sc_signal<data_t> *r_xram_rsp_to_ixr_cmd_data; // cache line data
687	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
688
689	////////////////////////////////////////////////////
690	// Registers controlled by the IXR_CMD fsm
691	////////////////////////////////////////////////////
692
693	sc_signal<int> r_ixr_cmd_fsm;
694	sc_signal<size_t> r_ixr_cmd_cpt;
695
696	////////////////////////////////////////////////////
697	// Registers controlled by TGT_RSP fsm
698	////////////////////////////////////////////////////
699
700	sc_signal<int> r_tgt_rsp_fsm;
701	sc_signal<size_t> r_tgt_rsp_cpt;
702
703	////////////////////////////////////////////////////
704	// Registers controlled by INIT_CMD fsm
705	////////////////////////////////////////////////////
706
707	sc_signal<int> r_init_cmd_fsm;
708	sc_signal<size_t> r_init_cmd_cpt;
709	sc_signal<bool> r_init_cmd_inst;
710
711	////////////////////////////////////////////////////
712	// Registers controlled by ALLOC_DIR fsm
713	////////////////////////////////////////////////////
714
715	sc_signal<int> r_alloc_dir_fsm;
716
717	////////////////////////////////////////////////////
718	// Registers controlled by ALLOC_TRT fsm
719	////////////////////////////////////////////////////
720
721	sc_signal<int> r_alloc_trt_fsm;
722
723	////////////////////////////////////////////////////
724	// Registers controlled by ALLOC_UPT fsm
725	////////////////////////////////////////////////////
726
727	sc_signal<int> r_alloc_upt_fsm;
728
729	////////////////////////////////////////////////////
730	// Registers controlled by ALLOC_HEAP fsm
731	////////////////////////////////////////////////////
732
733	sc_signal<int> r_alloc_heap_fsm;
734
735	}; // end class VciMemCacheV4
736
737	}}
738
739	#endif
740
741	// Local Variables:
742	// tab-width: 2
743	// c-basic-offset: 2
744	// c-file-offsets:((innamespace . 0)(inline-open . 0))
745	// indent-tabs-mode: nil
746	// End:
747
748	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
749

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