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vci_mem_cache_v4.h @ 284

Last change on this file since 284 was 284, checked in by joannou, 11 years ago

Updated of the vci trdid/rtrdid and pktid/rpktid fields for the direct network.
The pktid values are commented in the components'headers that use them.

In the vci_vdspin_*_wrapper components
- added the transmission of the pktid/rpktid field
In the vci_cc_vcache_wrapper_v4
- updated gen_moore() to transmit a valid pktid
- updated transition(), RSP_FSM now checks the rpktid
In the vci_mem_cache_v4
- transition(), tests originally performed on trdid now use pktid
- gen_moore() transmit rpktid
- !!! THE L1_MULTI_CACHE MECHANISM IS NO LONGER COMPATIBLE !!!
In vci_block_device_tsar_v4
- updated gen_moore function to transmit a valid pktid

Also renamed the "SC" states in "CAS" states in the concerned FSMs on the vci_cc_vcache_wrapper_v4 and the vci_mem_cache_v4

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File size: 33.7 KB

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1	/* -- c++ --
2	* File : vci_mem_cache_v4.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu
28	* cesar.fuguet-tortolero@lip6.fr
29	* alexandre.joannou@lip6.fr
30	*
31	* Modifications done by Christophe Choichillon on the 7/04/2009:
32	* - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
33	* - Adding a new VCI target port for the CLEANUP network
34	* - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
35	*
36	* Modifications to do :
37	* - Adding new variables used by the CLEANUP FSM
38	*
39	*/
40
41	#ifndef SOCLIB_CABA_MEM_CACHE_V4_H
42	#define SOCLIB_CABA_MEM_CACHE_V4_H
43
44	#include <inttypes.h>
45	#include <systemc>
46	#include <list>
47	#include <cassert>
48	#include "arithmetics.h"
49	#include "alloc_elems.h"
50	#include "caba_base_module.h"
51	#include "vci_target.h"
52	#include "vci_initiator.h"
53	#include "generic_fifo.h"
54	#include "mapping_table.h"
55	#include "int_tab.h"
56	#include "mem_cache_directory_v4.h"
57	#include "xram_transaction_v4.h"
58	#include "update_tab_v4.h"
59
60	#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
61	#define UPDATE_TAB_LINES 4 // Number of lines in the update tab
62
63	namespace soclib { namespace caba {
64	using namespace sc_core;
65
66	template<typename vci_param>
67	class VciMemCacheV4
68	: public soclib::caba::BaseModule
69	{
70	typedef sc_dt::sc_uint<40> addr_t;
71	typedef typename vci_param::fast_addr_t vci_addr_t;
72	typedef uint32_t data_t;
73	typedef uint32_t tag_t;
74	typedef uint32_t size_t;
75	typedef uint32_t be_t;
76	typedef uint32_t copy_t;
77
78	/* States of the TGT_CMD fsm */
79	enum tgt_cmd_fsm_state_e{
80	TGT_CMD_IDLE,
81	TGT_CMD_READ,
82	TGT_CMD_WRITE,
83	TGT_CMD_CAS
84	};
85
86	/* States of the TGT_RSP fsm */
87	enum tgt_rsp_fsm_state_e{
88	TGT_RSP_READ_IDLE,
89	TGT_RSP_WRITE_IDLE,
90	TGT_RSP_CAS_IDLE,
91	TGT_RSP_XRAM_IDLE,
92	TGT_RSP_INIT_IDLE,
93	TGT_RSP_CLEANUP_IDLE,
94	TGT_RSP_READ,
95	TGT_RSP_WRITE,
96	TGT_RSP_CAS,
97	TGT_RSP_XRAM,
98	TGT_RSP_INIT,
99	TGT_RSP_CLEANUP
100	};
101
102	/* States of the INIT_CMD fsm */
103	enum init_cmd_fsm_state_e{
104	INIT_CMD_INVAL_IDLE,
105	INIT_CMD_INVAL_NLINE,
106	INIT_CMD_XRAM_BRDCAST,
107	INIT_CMD_UPDT_IDLE,
108	INIT_CMD_WRITE_BRDCAST,
109	INIT_CMD_UPDT_NLINE,
110	INIT_CMD_UPDT_INDEX,
111	INIT_CMD_UPDT_DATA,
112	INIT_CMD_CAS_UPDT_IDLE,
113	INIT_CMD_CAS_BRDCAST,
114	INIT_CMD_CAS_UPDT_NLINE,
115	INIT_CMD_CAS_UPDT_INDEX,
116	INIT_CMD_CAS_UPDT_DATA,
117	INIT_CMD_CAS_UPDT_DATA_HIGH
118	};
119
120	/* States of the INIT_RSP fsm */
121	enum init_rsp_fsm_state_e{
122	INIT_RSP_IDLE,
123	INIT_RSP_UPT_LOCK,
124	INIT_RSP_UPT_CLEAR,
125	INIT_RSP_END
126	};
127
128	/* States of the READ fsm */
129	enum read_fsm_state_e{
130	READ_IDLE,
131	READ_DIR_REQ,
132	READ_DIR_LOCK,
133	READ_DIR_HIT,
134	READ_HEAP_REQ,
135	READ_HEAP_LOCK,
136	READ_HEAP_WRITE,
137	READ_HEAP_ERASE,
138	READ_HEAP_LAST,
139	READ_RSP,
140	READ_TRT_LOCK,
141	READ_TRT_SET,
142	READ_TRT_REQ
143	};
144
145	/* States of the WRITE fsm */
146	enum write_fsm_state_e{
147	WRITE_IDLE,
148	WRITE_NEXT,
149	WRITE_DIR_REQ,
150	WRITE_DIR_LOCK,
151	WRITE_DIR_READ,
152	WRITE_DIR_HIT,
153	WRITE_UPT_LOCK,
154	WRITE_UPT_HEAP_LOCK,
155	WRITE_UPT_REQ,
156	WRITE_UPT_NEXT,
157	WRITE_UPT_DEC,
158	WRITE_RSP,
159	WRITE_MISS_TRT_LOCK,
160	WRITE_MISS_TRT_DATA,
161	WRITE_MISS_TRT_SET,
162	WRITE_MISS_XRAM_REQ,
163	WRITE_BC_TRT_LOCK,
164	WRITE_BC_UPT_LOCK,
165	WRITE_BC_DIR_INVAL,
166	WRITE_BC_CC_SEND,
167	WRITE_BC_XRAM_REQ,
168	WRITE_WAIT
169	};
170
171	/* States of the IXR_RSP fsm */
172	enum ixr_rsp_fsm_state_e{
173	IXR_RSP_IDLE,
174	IXR_RSP_ACK,
175	IXR_RSP_TRT_ERASE,
176	IXR_RSP_TRT_READ
177	};
178
179	/* States of the XRAM_RSP fsm */
180	enum xram_rsp_fsm_state_e{
181	XRAM_RSP_IDLE,
182	XRAM_RSP_TRT_COPY,
183	XRAM_RSP_TRT_DIRTY,
184	XRAM_RSP_DIR_LOCK,
185	XRAM_RSP_DIR_UPDT,
186	XRAM_RSP_DIR_RSP,
187	XRAM_RSP_INVAL_LOCK,
188	XRAM_RSP_INVAL_WAIT,
189	XRAM_RSP_INVAL,
190	XRAM_RSP_WRITE_DIRTY,
191	XRAM_RSP_HEAP_REQ,
192	XRAM_RSP_HEAP_ERASE,
193	XRAM_RSP_HEAP_LAST,
194	XRAM_RSP_ERROR_ERASE,
195	XRAM_RSP_ERROR_RSP
196	};
197
198	/* States of the IXR_CMD fsm */
199	enum ixr_cmd_fsm_state_e{
200	IXR_CMD_READ_IDLE,
201	IXR_CMD_WRITE_IDLE,
202	IXR_CMD_CAS_IDLE,
203	IXR_CMD_XRAM_IDLE,
204	IXR_CMD_READ_NLINE,
205	IXR_CMD_WRITE_NLINE,
206	IXR_CMD_CAS_NLINE,
207	IXR_CMD_XRAM_DATA
208	};
209
210	/* States of the CAS fsm */
211	enum cas_fsm_state_e{
212	CAS_IDLE,
213	CAS_DIR_REQ,
214	CAS_DIR_LOCK,
215	CAS_DIR_HIT_READ,
216	CAS_DIR_HIT_WRITE,
217	CAS_UPT_LOCK,
218	CAS_UPT_HEAP_LOCK,
219	CAS_UPT_REQ,
220	CAS_UPT_NEXT,
221	CAS_BC_TRT_LOCK,
222	CAS_BC_UPT_LOCK,
223	CAS_BC_DIR_INVAL,
224	CAS_BC_CC_SEND,
225	CAS_BC_XRAM_REQ,
226	CAS_RSP_FAIL,
227	CAS_RSP_SUCCESS,
228	CAS_MISS_TRT_LOCK,
229	CAS_MISS_TRT_SET,
230	CAS_MISS_XRAM_REQ,
231	CAS_WAIT
232	};
233
234	/* States of the CLEANUP fsm */
235	enum cleanup_fsm_state_e{
236	CLEANUP_IDLE,
237	CLEANUP_DIR_REQ,
238	CLEANUP_DIR_LOCK,
239	CLEANUP_DIR_WRITE,
240	CLEANUP_HEAP_REQ,
241	CLEANUP_HEAP_LOCK,
242	CLEANUP_HEAP_SEARCH,
243	CLEANUP_HEAP_CLEAN,
244	CLEANUP_HEAP_FREE,
245	CLEANUP_UPT_LOCK,
246	CLEANUP_UPT_WRITE,
247	CLEANUP_WRITE_RSP,
248	CLEANUP_RSP
249	};
250
251	/* States of the ALLOC_DIR fsm */
252	enum alloc_dir_fsm_state_e{
253	ALLOC_DIR_RESET,
254	ALLOC_DIR_READ,
255	ALLOC_DIR_WRITE,
256	ALLOC_DIR_CAS,
257	ALLOC_DIR_CLEANUP,
258	ALLOC_DIR_XRAM_RSP
259	};
260
261	/* States of the ALLOC_TRT fsm */
262	enum alloc_trt_fsm_state_e{
263	ALLOC_TRT_READ,
264	ALLOC_TRT_WRITE,
265	ALLOC_TRT_CAS,
266	ALLOC_TRT_XRAM_RSP,
267	ALLOC_TRT_IXR_RSP
268	};
269
270	/* States of the ALLOC_UPT fsm */
271	enum alloc_upt_fsm_state_e{
272	ALLOC_UPT_WRITE,
273	ALLOC_UPT_XRAM_RSP,
274	ALLOC_UPT_INIT_RSP,
275	ALLOC_UPT_CLEANUP,
276	ALLOC_UPT_CAS
277	};
278
279	/* States of the ALLOC_HEAP fsm */
280	enum alloc_heap_fsm_state_e{
281	ALLOC_HEAP_RESET,
282	ALLOC_HEAP_READ,
283	ALLOC_HEAP_WRITE,
284	ALLOC_HEAP_CAS,
285	ALLOC_HEAP_CLEANUP,
286	ALLOC_HEAP_XRAM_RSP
287	};
288
289	/* transaction type, pktid field */
290	enum transaction_type_e
291	{
292	// b3 unused
293	// b2 READ / NOT READ
294	// Si READ
295	// b1 DATA / INS
296	// b0 UNC / MISS
297	// Si NOT READ
298	// b1 accÃšs table llsc type SW / other
299	// b2 WRITE/CAS/LL/SC
300	TYPE_READ_DATA_UNC = 0x0,
301	TYPE_READ_DATA_MISS = 0x1,
302	TYPE_READ_INS_UNC = 0x2,
303	TYPE_READ_INS_MISS = 0x3,
304	TYPE_WRITE = 0x4,
305	TYPE_CAS = 0x5,
306	TYPE_LL = 0x6,
307	TYPE_SC = 0x7
308	};
309
310	/* SC return values */
311	enum sc_status_type_e
312	{
313	SC_SUCCESS = 0x00000000,
314	SC_FAIL = 0x00000001
315	};
316
317	// debug variables (for each FSM)
318	size_t m_debug_start_cycle;
319	bool m_debug_ok;
320	bool m_debug_global;
321	bool m_debug_tgt_cmd_fsm;
322	bool m_debug_tgt_rsp_fsm;
323	bool m_debug_init_cmd_fsm;
324	bool m_debug_init_rsp_fsm;
325	bool m_debug_read_fsm;
326	bool m_debug_write_fsm;
327	bool m_debug_cas_fsm;
328	bool m_debug_cleanup_fsm;
329	bool m_debug_ixr_cmd_fsm;
330	bool m_debug_ixr_rsp_fsm;
331	bool m_debug_xram_rsp_fsm;
332	bool m_debug_previous_hit;
333	size_t m_debug_previous_count;
334
335	bool m_monitor_ok;
336	vci_addr_t m_monitor_base;
337	vci_addr_t m_monitor_length;
338
339	// instrumentation counters
340	uint32_t m_cpt_cycles; // Counter of cycles
341	uint32_t m_cpt_read; // Number of READ transactions
342	uint32_t m_cpt_read_miss; // Number of MISS READ
343	uint32_t m_cpt_write; // Number of WRITE transactions
344	uint32_t m_cpt_write_miss; // Number of MISS WRITE
345	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
346	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
347	uint32_t m_cpt_update; // Number of UPDATE transactions
348	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
349	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
350	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
351	uint32_t m_cpt_inval; // Number of INVAL transactions
352	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
353	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
354	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
355	uint32_t m_cpt_ll; // Number of LL transactions
356	uint32_t m_cpt_sc; // Number of SC transactions
357	uint32_t m_cpt_cas; // Number of CAS transactions
358
359	size_t m_prev_count;
360
361	protected:
362
363	SC_HAS_PROCESS(VciMemCacheV4);
364
365	public:
366	sc_in<bool> p_clk;
367	sc_in<bool> p_resetn;
368	soclib::caba::VciTarget<vci_param> p_vci_tgt;
369	soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup;
370	soclib::caba::VciInitiator<vci_param> p_vci_ini;
371	soclib::caba::VciInitiator<vci_param> p_vci_ixr;
372
373	VciMemCacheV4(
374	sc_module_name name, // Instance Name
375	const soclib::common::MappingTable &mtp, // Mapping table for primary requets
376	const soclib::common::MappingTable &mtc, // Mapping table for coherence requets
377	const soclib::common::MappingTable &mtx, // Mapping table for XRAM
378	const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator)
379	const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator)
380	const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target)
381	const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup
382	size_t nways, // Number of ways per set
383	size_t nsets, // Number of sets
384	size_t nwords, // Number of words per line
385	size_t heap_size=1024, // Size of the heap
386	size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT
387	size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT
388	size_t debug_start_cycle=0,
389	bool debug_ok=false);
390
391	~VciMemCacheV4();
392
393	void print_stats();
394	void print_trace();
395	void copies_monitor(vci_addr_t addr);
396	void start_monitor(vci_addr_t addr, vci_addr_t length);
397	void stop_monitor();
398
399	private:
400
401	void transition();
402	void genMoore();
403	void check_monitor( const char *buf, vci_addr_t addr, data_t data);
404
405	// Component attributes
406	std::list<soclib::common::Segment> m_seglist; // memory cached into the cache
407	std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
408
409	const size_t m_initiators; // Number of initiators
410	const size_t m_heap_size; // Size of the heap
411	const size_t m_ways; // Number of ways in a set
412	const size_t m_sets; // Number of cache sets
413	const size_t m_words; // Number of words in a line
414	const size_t m_srcid_ixr; // Srcid for requests to XRAM
415	const size_t m_srcid_ini; // Srcid for requests to processors
416
417	uint32_t m_transaction_tab_lines;
418	TransactionTab m_transaction_tab; // xram transaction table
419	uint32_t m_update_tab_lines;
420	UpdateTab m_update_tab; // pending update & invalidate
421	CacheDirectory m_cache_directory; // data cache directory
422	HeapDirectory m_heap; // heap for copies
423
424	data_t *** m_cache_data; // data array[set][way][word]
425
426	// adress masks
427	const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
428	const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
429	const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
430	const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
431
432	// broadcast address
433	vci_addr_t m_broadcast_address;
434
435	//////////////////////////////////////////////////
436	// Others registers
437	//////////////////////////////////////////////////
438	sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
439	sc_signal<size_t> xxx_count;
440
441	//////////////////////////////////////////////////
442	// Registers controlled by the TGT_CMD fsm
443	//////////////////////////////////////////////////
444
445	// Fifo between TGT_CMD fsm and READ fsm
446	GenericFifo<uint64_t> m_cmd_read_addr_fifo;
447	GenericFifo<size_t> m_cmd_read_length_fifo;
448	GenericFifo<size_t> m_cmd_read_srcid_fifo;
449	GenericFifo<size_t> m_cmd_read_trdid_fifo;
450	GenericFifo<size_t> m_cmd_read_pktid_fifo;
451
452	// Fifo between TGT_CMD fsm and WRITE fsm
453	GenericFifo<uint64_t> m_cmd_write_addr_fifo;
454	GenericFifo<bool> m_cmd_write_eop_fifo;
455	GenericFifo<size_t> m_cmd_write_srcid_fifo;
456	GenericFifo<size_t> m_cmd_write_trdid_fifo;
457	GenericFifo<size_t> m_cmd_write_pktid_fifo;
458	GenericFifo<data_t> m_cmd_write_data_fifo;
459	GenericFifo<be_t> m_cmd_write_be_fifo;
460
461	// Fifo between TGT_CMD fsm and CAS fsm
462	GenericFifo<uint64_t> m_cmd_cas_addr_fifo;
463	GenericFifo<bool> m_cmd_cas_eop_fifo;
464	GenericFifo<size_t> m_cmd_cas_srcid_fifo;
465	GenericFifo<size_t> m_cmd_cas_trdid_fifo;
466	GenericFifo<size_t> m_cmd_cas_pktid_fifo;
467	GenericFifo<data_t> m_cmd_cas_wdata_fifo;
468
469	sc_signal<int> r_tgt_cmd_fsm;
470
471	size_t m_nseg;
472	size_t m_ncseg;
473	soclib::common::Segment **m_seg;
474	soclib::common::Segment **m_cseg;
475	///////////////////////////////////////////////////////
476	// Registers controlled by the READ fsm
477	///////////////////////////////////////////////////////
478
479	sc_signal<int> r_read_fsm; // FSM state
480	sc_signal<size_t> r_read_copy; // Srcid of the first copy
481	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
482	sc_signal<bool> r_read_copy_inst; // Type of the first copy
483	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
484	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
485	sc_signal<bool> r_read_lock; // lock bit (in directory)
486	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
487	sc_signal<size_t> r_read_count; // number of copies
488	sc_signal<size_t> r_read_ptr; // pointer to the heap
489	sc_signal<data_t> * r_read_data; // data (one cache line)
490	sc_signal<size_t> r_read_way; // associative way (in cache)
491	sc_signal<size_t> r_read_trt_index; // Transaction Table index
492	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
493	sc_signal<bool> r_read_last_free; // Last free entry
494
495	// Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
496	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
497	sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index
498	sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table
499
500	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
501	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
502	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
503	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
504	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
505	sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)
506	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
507	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
508
509	///////////////////////////////////////////////////////////////
510	// Registers controlled by the WRITE fsm
511	///////////////////////////////////////////////////////////////
512
513	sc_signal<int> r_write_fsm; // FSM state
514	sc_signal<addr_t> r_write_address; // first word address
515	sc_signal<size_t> r_write_word_index; // first word index in line
516	sc_signal<size_t> r_write_word_count; // number of words in line
517	sc_signal<size_t> r_write_srcid; // transaction srcid
518	sc_signal<size_t> r_write_trdid; // transaction trdid
519	sc_signal<size_t> r_write_pktid; // transaction pktid
520	sc_signal<data_t> * r_write_data; // data (one cache line)
521	sc_signal<be_t> * r_write_be; // one byte enable per word
522	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
523	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
524	sc_signal<bool> r_write_lock; // lock bit (in directory)
525	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
526	sc_signal<size_t> r_write_copy; // first owner of the line
527	sc_signal<size_t> r_write_copy_cache; // first owner of the line
528	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
529	sc_signal<size_t> r_write_count; // number of copies
530	sc_signal<size_t> r_write_ptr; // pointer to the heap
531	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
532	sc_signal<bool> r_write_to_dec; // need to decrement update counter
533	sc_signal<size_t> r_write_way; // way of the line
534	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
535	sc_signal<size_t> r_write_upt_index; // index in Update Table
536
537	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
538	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
539	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
540	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
541	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
542
543	// Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
544	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
545	sc_signal<bool> r_write_to_ixr_cmd_write; // write request
546	sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index
547	sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data
548	sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table
549
550	// Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
551	sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request
552	sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request
553	sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index
554	sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table
555	sc_signal<data_t> * r_write_to_init_cmd_data; // data (one cache line)
556	sc_signal<be_t> * r_write_to_init_cmd_be; // word enable
557	sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line
558	sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line
559	GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type
560	GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids
561	#if L1_MULTI_CACHE
562	GenericFifo<size_t> m_write_to_init_cmd_cache_id_fifo; // fifo for srcids
563	#endif
564
565	// Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
566	sc_signal<bool> r_write_to_init_rsp_req; // valid request
567	sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table
568
569	/////////////////////////////////////////////////////////
570	// Registers controlled by INIT_RSP fsm
571	//////////////////////////////////////////////////////////
572
573	sc_signal<int> r_init_rsp_fsm; // FSM state
574	sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table
575	sc_signal<size_t> r_init_rsp_srcid; // pending write srcid
576	sc_signal<size_t> r_init_rsp_trdid; // pending write trdid
577	sc_signal<size_t> r_init_rsp_pktid; // pending write pktid
578	sc_signal<addr_t> r_init_rsp_nline; // pending write nline
579
580	// Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
581	sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request
582	sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid
583	sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid
584	sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid
585
586	///////////////////////////////////////////////////////
587	// Registers controlled by CLEANUP fsm
588	///////////////////////////////////////////////////////
589
590	sc_signal<int> r_cleanup_fsm; // FSM state
591	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
592	sc_signal<size_t> r_cleanup_trdid; // transaction trdid
593	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
594	sc_signal<addr_t> r_cleanup_nline; // cache line index
595
596	sc_signal<copy_t> r_cleanup_copy; // first copy
597	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
598	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
599	sc_signal<copy_t> r_cleanup_count; // number of copies
600	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
601	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
602	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
603	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
604	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
605	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
606	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
607	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
608	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
609	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
610	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
611
612	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response
613	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
614	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
615	sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp
616
617	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
618
619	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
620	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
621	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
622	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
623	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
624
625	///////////////////////////////////////////////////////
626	// Registers controlled by CAS fsm
627	///////////////////////////////////////////////////////
628
629	sc_signal<int> r_cas_fsm; // FSM state
630	sc_signal<data_t> r_cas_wdata; // write data word
631	sc_signal<data_t> * r_cas_rdata; // read data word
632	sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing
633	sc_signal<size_t> r_cas_cpt; // size of command
634	sc_signal<copy_t> r_cas_copy; // Srcid of the first copy
635	sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy
636	sc_signal<bool> r_cas_copy_inst; // Type of the first copy
637	sc_signal<size_t> r_cas_count; // number of copies
638	sc_signal<size_t> r_cas_ptr; // pointer to the heap
639	sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap
640	sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)
641	sc_signal<bool> r_cas_dirty; // dirty bit (in directory)
642	sc_signal<size_t> r_cas_way; // way in directory
643	sc_signal<size_t> r_cas_set; // set in directory
644	sc_signal<data_t> r_cas_tag; // cache line tag (in directory)
645	sc_signal<size_t> r_cas_trt_index; // Transaction Table index
646	sc_signal<size_t> r_cas_upt_index; // Update Table index
647
648	// Buffer between CAS fsm and INIT_CMD fsm (XRAM read)
649	sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request
650	sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index
651	sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table
652	sc_signal<bool> r_cas_to_ixr_cmd_write; // write request
653	sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data
654
655
656	// Buffer between CAS fsm and TGT_RSP fsm
657	sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request
658	sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word
659	sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid
660	sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid
661	sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid
662
663	// Buffer between CAS fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
664	sc_signal<bool> r_cas_to_init_cmd_multi_req; // valid request
665	sc_signal<bool> r_cas_to_init_cmd_brdcast_req; // brdcast request
666	sc_signal<addr_t> r_cas_to_init_cmd_nline; // cache line index
667	sc_signal<size_t> r_cas_to_init_cmd_trdid; // index in Update Table
668	sc_signal<data_t> r_cas_to_init_cmd_wdata; // data (one word)
669	sc_signal<bool> r_cas_to_init_cmd_is_long; // it is a 64 bits CAS
670	sc_signal<data_t> r_cas_to_init_cmd_wdata_high; // data high (one word)
671	sc_signal<size_t> r_cas_to_init_cmd_index; // index of the word in line
672	GenericFifo<bool> m_cas_to_init_cmd_inst_fifo; // fifo for the L1 type
673	GenericFifo<size_t> m_cas_to_init_cmd_srcid_fifo; // fifo for srcids
674	#if L1_MULTI_CACHE
675	GenericFifo<size_t> m_cas_to_init_cmd_cache_id_fifo; // fifo for srcids
676	#endif
677
678	// Buffer between CAS fsm and INIT_RSP fsm (Decrement UPT entry)
679	sc_signal<bool> r_cas_to_init_rsp_req; // valid request
680	sc_signal<size_t> r_cas_to_init_rsp_upt_index; // index in update table
681
682	////////////////////////////////////////////////////
683	// Registers controlled by the IXR_RSP fsm
684	////////////////////////////////////////////////////
685
686	sc_signal<int> r_ixr_rsp_fsm; // FSM state
687	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
688	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
689
690	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
691	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
692
693	////////////////////////////////////////////////////
694	// Registers controlled by the XRAM_RSP fsm
695	////////////////////////////////////////////////////
696
697	sc_signal<int> r_xram_rsp_fsm; // FSM state
698	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
699	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
700	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
701	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
702	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
703	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
704	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
705	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
706	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
707	sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy
708	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
709	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
710	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
711	sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data
712	sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index
713	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
714
715	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
716	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
717	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
718	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
719	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
720	sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
721	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
722	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response
723	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
724
725	// Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
726	sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request
727	sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request
728	sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index;
729	sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry
730	GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type
731	GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids
732	#if L1_MULTI_CACHE
733	GenericFifo<size_t> m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids
734	#endif
735
736	// Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
737	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
738	sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index
739	sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data
740	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
741
742	////////////////////////////////////////////////////
743	// Registers controlled by the IXR_CMD fsm
744	////////////////////////////////////////////////////
745
746	sc_signal<int> r_ixr_cmd_fsm;
747	sc_signal<size_t> r_ixr_cmd_cpt;
748
749	////////////////////////////////////////////////////
750	// Registers controlled by TGT_RSP fsm
751	////////////////////////////////////////////////////
752
753	sc_signal<int> r_tgt_rsp_fsm;
754	sc_signal<size_t> r_tgt_rsp_cpt;
755
756	////////////////////////////////////////////////////
757	// Registers controlled by INIT_CMD fsm
758	////////////////////////////////////////////////////
759
760	sc_signal<int> r_init_cmd_fsm;
761	sc_signal<size_t> r_init_cmd_cpt;
762	sc_signal<bool> r_init_cmd_inst;
763
764	////////////////////////////////////////////////////
765	// Registers controlled by ALLOC_DIR fsm
766	////////////////////////////////////////////////////
767
768	sc_signal<int> r_alloc_dir_fsm;
769	sc_signal<unsigned> r_alloc_dir_reset_cpt;
770
771	////////////////////////////////////////////////////
772	// Registers controlled by ALLOC_TRT fsm
773	////////////////////////////////////////////////////
774
775	sc_signal<int> r_alloc_trt_fsm;
776
777	////////////////////////////////////////////////////
778	// Registers controlled by ALLOC_UPT fsm
779	////////////////////////////////////////////////////
780
781	sc_signal<int> r_alloc_upt_fsm;
782
783	////////////////////////////////////////////////////
784	// Registers controlled by ALLOC_HEAP fsm
785	////////////////////////////////////////////////////
786
787	sc_signal<int> r_alloc_heap_fsm;
788	sc_signal<unsigned> r_alloc_heap_reset_cpt;
789	}; // end class VciMemCacheV4
790
791	}}
792
793	#endif
794
795	// Local Variables:
796	// tab-width: 2
797	// c-basic-offset: 2
798	// c-file-offsets:((innamespace . 0)(inline-open . 0))
799	// indent-tabs-mode: nil
800	// End:
801
802	// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
803

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