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vci_mem_cache_v4.h @ 361

Last change on this file since 361 was 361, checked in by cfuguet, 11 years ago

Bugfix in vci_mem_cache_v4:

In function "copy()" of the xram_transaction table the LL key was not
copied into register. Hence, the key coming from the XRAM_RSP to the
TGT_RSP FSM was never correct.

In TGT_RSP FSM, in case of LL response, the two response flits were
inverted. We must send first the key and then the data.

Add:

Add the COMPARE_HIT_COMPARE state in the CAS FSM to optimize timing.
(This modification has been already done in the vci_mem_cache v5).

Add output ports for debug. This ports are used only if the
MONITOR_MEMCACHE_FSM compilation directive is gave.

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File size: 35.4 KB

Line
1	/* -- c++ --
2	* File : vci_mem_cache_v4.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu
28	* cesar.fuguet-tortolero@lip6.fr
29	* alexandre.joannou@lip6.fr
30	*
31	*/
32
33	#ifndef SOCLIB_CABA_MEM_CACHE_V4_H
34	#define SOCLIB_CABA_MEM_CACHE_V4_H
35
36	#include <inttypes.h>
37	#include <systemc>
38	#include <list>
39	#include <cassert>
40	#include "arithmetics.h"
41	#include "alloc_elems.h"
42	#include "caba_base_module.h"
43	#include "vci_target.h"
44	#include "vci_initiator.h"
45	#include "generic_fifo.h"
46	#include "mapping_table.h"
47	#include "int_tab.h"
48	#include "generic_llsc_global_table.h"
49	#include "mem_cache_directory_v4.h"
50	#include "xram_transaction_v4.h"
51	#include "update_tab_v4.h"
52
53	#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
54	#define UPDATE_TAB_LINES 4 // Number of lines in the update tab
55
56	namespace soclib { namespace caba {
57	using namespace sc_core;
58
59	template<typename vci_param>
60	class VciMemCacheV4
61	: public soclib::caba::BaseModule
62	{
63	typedef sc_dt::sc_uint<40> addr_t;
64	typedef typename vci_param::fast_addr_t vci_addr_t;
65	typedef uint32_t data_t;
66	typedef uint32_t tag_t;
67	typedef uint32_t size_t;
68	typedef uint32_t be_t;
69	typedef uint32_t copy_t;
70
71	/* States of the TGT_CMD fsm */
72	enum tgt_cmd_fsm_state_e{
73	TGT_CMD_IDLE,
74	TGT_CMD_READ,
75	TGT_CMD_WRITE,
76	TGT_CMD_CAS
77	};
78
79	/* States of the TGT_RSP fsm */
80	enum tgt_rsp_fsm_state_e{
81	TGT_RSP_READ_IDLE,
82	TGT_RSP_WRITE_IDLE,
83	TGT_RSP_CAS_IDLE,
84	TGT_RSP_XRAM_IDLE,
85	TGT_RSP_INIT_IDLE,
86	TGT_RSP_CLEANUP_IDLE,
87	TGT_RSP_READ,
88	TGT_RSP_WRITE,
89	TGT_RSP_CAS,
90	TGT_RSP_XRAM,
91	TGT_RSP_INIT,
92	TGT_RSP_CLEANUP
93	};
94
95	/* States of the INIT_CMD fsm */
96	enum init_cmd_fsm_state_e{
97	INIT_CMD_INVAL_IDLE,
98	INIT_CMD_INVAL_NLINE,
99	INIT_CMD_XRAM_BRDCAST,
100	INIT_CMD_WRITE_BRDCAST,
101	INIT_CMD_CAS_BRDCAST,
102	INIT_CMD_UPDT_IDLE,
103	INIT_CMD_UPDT_NLINE,
104	INIT_CMD_UPDT_INDEX,
105	INIT_CMD_UPDT_DATA,
106	INIT_CMD_CAS_UPDT_IDLE,
107	INIT_CMD_CAS_UPDT_NLINE,
108	INIT_CMD_CAS_UPDT_INDEX,
109	INIT_CMD_CAS_UPDT_DATA,
110	INIT_CMD_CAS_UPDT_DATA_HIGH
111	};
112
113	/* States of the INIT_RSP fsm */
114	enum init_rsp_fsm_state_e{
115	INIT_RSP_IDLE,
116	INIT_RSP_UPT_LOCK,
117	INIT_RSP_UPT_CLEAR,
118	INIT_RSP_END
119	};
120
121	/* States of the READ fsm */
122	enum read_fsm_state_e{
123	READ_IDLE,
124	READ_DIR_REQ,
125	READ_DIR_LOCK,
126	READ_DIR_HIT,
127	READ_HEAP_REQ,
128	READ_HEAP_LOCK,
129	READ_HEAP_WRITE,
130	READ_HEAP_ERASE,
131	READ_HEAP_LAST,
132	READ_RSP,
133	READ_TRT_LOCK,
134	READ_TRT_SET,
135	READ_TRT_REQ
136	};
137
138	/* States of the WRITE fsm */
139	enum write_fsm_state_e{
140	WRITE_IDLE,
141	WRITE_NEXT,
142	WRITE_DIR_REQ,
143	WRITE_DIR_LOCK,
144	WRITE_DIR_READ,
145	WRITE_DIR_HIT,
146	WRITE_UPT_LOCK,
147	WRITE_UPT_HEAP_LOCK,
148	WRITE_UPT_REQ,
149	WRITE_UPT_NEXT,
150	WRITE_UPT_DEC,
151	WRITE_RSP,
152	WRITE_MISS_TRT_LOCK,
153	WRITE_MISS_TRT_DATA,
154	WRITE_MISS_TRT_SET,
155	WRITE_MISS_XRAM_REQ,
156	WRITE_BC_TRT_LOCK,
157	WRITE_BC_UPT_LOCK,
158	WRITE_BC_DIR_INVAL,
159	WRITE_BC_CC_SEND,
160	WRITE_BC_XRAM_REQ,
161	WRITE_WAIT
162	};
163
164	/* States of the IXR_RSP fsm */
165	enum ixr_rsp_fsm_state_e{
166	IXR_RSP_IDLE,
167	IXR_RSP_ACK,
168	IXR_RSP_TRT_ERASE,
169	IXR_RSP_TRT_READ
170	};
171
172	/* States of the XRAM_RSP fsm */
173	enum xram_rsp_fsm_state_e{
174	XRAM_RSP_IDLE,
175	XRAM_RSP_TRT_COPY,
176	XRAM_RSP_TRT_DIRTY,
177	XRAM_RSP_DIR_LOCK,
178	XRAM_RSP_DIR_UPDT,
179	XRAM_RSP_DIR_RSP,
180	XRAM_RSP_INVAL_LOCK,
181	XRAM_RSP_INVAL_WAIT,
182	XRAM_RSP_INVAL,
183	XRAM_RSP_WRITE_DIRTY,
184	XRAM_RSP_HEAP_REQ,
185	XRAM_RSP_HEAP_ERASE,
186	XRAM_RSP_HEAP_LAST,
187	XRAM_RSP_ERROR_ERASE,
188	XRAM_RSP_ERROR_RSP
189	};
190
191	/* States of the IXR_CMD fsm */
192	enum ixr_cmd_fsm_state_e{
193	IXR_CMD_READ_IDLE,
194	IXR_CMD_WRITE_IDLE,
195	IXR_CMD_CAS_IDLE,
196	IXR_CMD_XRAM_IDLE,
197	IXR_CMD_READ_NLINE,
198	IXR_CMD_WRITE_NLINE,
199	IXR_CMD_CAS_NLINE,
200	IXR_CMD_XRAM_DATA
201	};
202
203	/* States of the CAS fsm */
204	enum cas_fsm_state_e{
205	CAS_IDLE,
206	CAS_DIR_REQ,
207	CAS_DIR_LOCK,
208	CAS_DIR_HIT_READ,
209	CAS_DIR_HIT_COMPARE,
210	CAS_DIR_HIT_WRITE,
211	CAS_UPT_LOCK,
212	CAS_UPT_HEAP_LOCK,
213	CAS_UPT_REQ,
214	CAS_UPT_NEXT,
215	CAS_BC_TRT_LOCK,
216	CAS_BC_UPT_LOCK,
217	CAS_BC_DIR_INVAL,
218	CAS_BC_CC_SEND,
219	CAS_BC_XRAM_REQ,
220	CAS_RSP_FAIL,
221	CAS_RSP_SUCCESS,
222	CAS_MISS_TRT_LOCK,
223	CAS_MISS_TRT_SET,
224	CAS_MISS_XRAM_REQ,
225	CAS_WAIT
226	};
227
228	/* States of the CLEANUP fsm */
229	enum cleanup_fsm_state_e{
230	CLEANUP_IDLE,
231	CLEANUP_DIR_REQ,
232	CLEANUP_DIR_LOCK,
233	CLEANUP_DIR_WRITE,
234	CLEANUP_HEAP_REQ,
235	CLEANUP_HEAP_LOCK,
236	CLEANUP_HEAP_SEARCH,
237	CLEANUP_HEAP_CLEAN,
238	CLEANUP_HEAP_FREE,
239	CLEANUP_UPT_LOCK,
240	CLEANUP_UPT_WRITE,
241	CLEANUP_WRITE_RSP,
242	CLEANUP_RSP
243	};
244
245	/* States of the ALLOC_DIR fsm */
246	enum alloc_dir_fsm_state_e{
247	ALLOC_DIR_RESET,
248	ALLOC_DIR_READ,
249	ALLOC_DIR_WRITE,
250	ALLOC_DIR_CAS,
251	ALLOC_DIR_CLEANUP,
252	ALLOC_DIR_XRAM_RSP
253	};
254
255	/* States of the ALLOC_TRT fsm */
256	enum alloc_trt_fsm_state_e{
257	ALLOC_TRT_READ,
258	ALLOC_TRT_WRITE,
259	ALLOC_TRT_CAS,
260	ALLOC_TRT_XRAM_RSP,
261	ALLOC_TRT_IXR_RSP
262	};
263
264	/* States of the ALLOC_UPT fsm */
265	enum alloc_upt_fsm_state_e{
266	ALLOC_UPT_WRITE,
267	ALLOC_UPT_XRAM_RSP,
268	ALLOC_UPT_INIT_RSP,
269	ALLOC_UPT_CLEANUP,
270	ALLOC_UPT_CAS
271	};
272
273	/* States of the ALLOC_HEAP fsm */
274	enum alloc_heap_fsm_state_e{
275	ALLOC_HEAP_RESET,
276	ALLOC_HEAP_READ,
277	ALLOC_HEAP_WRITE,
278	ALLOC_HEAP_CAS,
279	ALLOC_HEAP_CLEANUP,
280	ALLOC_HEAP_XRAM_RSP
281	};
282
283	/* transaction type, pktid field */
284	enum transaction_type_e
285	{
286	// b3 unused
287	// b2 READ / NOT READ
288	// Si READ
289	// b1 DATA / INS
290	// b0 UNC / MISS
291	// Si NOT READ
292	// b1 accÃšs table llsc type SW / other
293	// b2 WRITE/CAS/LL/SC
294	TYPE_READ_DATA_UNC = 0x0,
295	TYPE_READ_DATA_MISS = 0x1,
296	TYPE_READ_INS_UNC = 0x2,
297	TYPE_READ_INS_MISS = 0x3,
298	TYPE_WRITE = 0x4,
299	TYPE_CAS = 0x5,
300	TYPE_LL = 0x6,
301	TYPE_SC = 0x7
302	};
303
304	/* SC return values */
305	enum sc_status_type_e
306	{
307	SC_SUCCESS = 0x00000000,
308	SC_FAIL = 0x00000001
309	};
310
311	// debug variables (for each FSM)
312	size_t m_debug_start_cycle;
313	bool m_debug_ok;
314	bool m_debug_global;
315	bool m_debug_tgt_cmd_fsm;
316	bool m_debug_tgt_rsp_fsm;
317	bool m_debug_init_cmd_fsm;
318	bool m_debug_init_rsp_fsm;
319	bool m_debug_read_fsm;
320	bool m_debug_write_fsm;
321	bool m_debug_cas_fsm;
322	bool m_debug_cleanup_fsm;
323	bool m_debug_ixr_cmd_fsm;
324	bool m_debug_ixr_rsp_fsm;
325	bool m_debug_xram_rsp_fsm;
326	bool m_debug_previous_hit;
327	size_t m_debug_previous_count;
328
329	bool m_monitor_ok;
330	vci_addr_t m_monitor_base;
331	vci_addr_t m_monitor_length;
332
333	// instrumentation counters
334	uint32_t m_cpt_cycles; // Counter of cycles
335	uint32_t m_cpt_read; // Number of READ transactions
336	uint32_t m_cpt_read_miss; // Number of MISS READ
337	uint32_t m_cpt_write; // Number of WRITE transactions
338	uint32_t m_cpt_write_miss; // Number of MISS WRITE
339	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
340	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
341	uint32_t m_cpt_update; // Number of UPDATE transactions
342	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
343	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
344	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
345	uint32_t m_cpt_inval; // Number of INVAL transactions
346	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
347	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
348	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
349	uint32_t m_cpt_ll; // Number of LL transactions
350	uint32_t m_cpt_sc; // Number of SC transactions
351	uint32_t m_cpt_cas; // Number of CAS transactions
352
353	size_t m_prev_count;
354
355	protected:
356
357	SC_HAS_PROCESS(VciMemCacheV4);
358
359	public:
360	sc_in<bool> p_clk;
361	sc_in<bool> p_resetn;
362	soclib::caba::VciTarget<vci_param> p_vci_tgt;
363	soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup;
364	soclib::caba::VciInitiator<vci_param> p_vci_ini;
365	soclib::caba::VciInitiator<vci_param> p_vci_ixr;
366
367	#if MONITOR_MEMCACHE_FSM
368	sc_out<int> p_read_fsm;
369	sc_out<int> p_write_fsm;
370	sc_out<int> p_xram_rsp_fsm;
371	sc_out<int> p_cas_fsm;
372	sc_out<int> p_cleanup_fsm;
373	sc_out<int> p_alloc_heap_fsm;
374	sc_out<int> p_alloc_dir_fsm;
375	sc_out<int> p_alloc_trt_fsm;
376	sc_out<int> p_alloc_upt_fsm;
377	sc_out<int> p_tgt_cmd_fsm;
378	sc_out<int> p_tgt_rsp_fsm;
379	sc_out<int> p_ixr_cmd_fsm;
380	sc_out<int> p_ixr_rsp_fsm;
381	sc_out<int> p_init_cmd_fsm;
382	sc_out<int> p_init_rsp_fsm;
383	#endif
384
385	VciMemCacheV4(
386	sc_module_name name, // Instance Name
387	const soclib::common::MappingTable &mtp, // Mapping table for primary requets
388	const soclib::common::MappingTable &mtc, // Mapping table for coherence requets
389	const soclib::common::MappingTable &mtx, // Mapping table for XRAM
390	const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator)
391	const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator)
392	const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target)
393	const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup
394	size_t nways, // Number of ways per set
395	size_t nsets, // Number of sets
396	size_t nwords, // Number of words per line
397	size_t heap_size=1024, // Size of the heap
398	size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT
399	size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT
400	size_t debug_start_cycle=0,
401	bool debug_ok=false);
402
403	~VciMemCacheV4();
404
405	void print_stats();
406	void print_trace();
407	void copies_monitor(vci_addr_t addr);
408	void start_monitor(vci_addr_t addr, vci_addr_t length);
409	void stop_monitor();
410
411	private:
412
413	void transition();
414	void genMoore();
415	void check_monitor( const char *buf, vci_addr_t addr, data_t data);
416
417	// Component attributes
418	std::list<soclib::common::Segment> m_seglist; // memory cached into the cache
419	std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
420
421	const size_t m_initiators; // Number of initiators
422	const size_t m_heap_size; // Size of the heap
423	const size_t m_ways; // Number of ways in a set
424	const size_t m_sets; // Number of cache sets
425	const size_t m_words; // Number of words in a line
426	const size_t m_srcid_ixr; // Srcid for requests to XRAM
427	const size_t m_srcid_ini; // Srcid for requests to processors
428
429	uint32_t m_transaction_tab_lines;
430	TransactionTab m_transaction_tab; // xram transaction table
431	uint32_t m_update_tab_lines;
432	UpdateTab m_update_tab; // pending update & invalidate
433	CacheDirectory m_cache_directory; // data cache directory
434	CacheData m_cache_data; // data array[set][way][word]
435	HeapDirectory m_heap; // heap for copies
436	GenericLLSCGlobalTable
437	<
438	32 , // desired number of slots
439	4096, // number of processors in the system
440	8000, // registratioÃ§n life span (in # of LL operations)
441	typename vci_param::fast_addr_t // address type
442	>
443	m_llsc_table; // ll/sc global registration table
444
445	// adress masks
446	const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
447	const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
448	const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
449	const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
450
451	// broadcast address
452	vci_addr_t m_broadcast_address;
453
454	//////////////////////////////////////////////////
455	// Others registers
456	//////////////////////////////////////////////////
457	sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
458	sc_signal<size_t> xxx_count;
459
460	//////////////////////////////////////////////////
461	// Registers controlled by the TGT_CMD fsm
462	//////////////////////////////////////////////////
463
464	// Fifo between TGT_CMD fsm and READ fsm
465	GenericFifo<uint64_t> m_cmd_read_addr_fifo;
466	GenericFifo<size_t> m_cmd_read_length_fifo;
467	GenericFifo<size_t> m_cmd_read_srcid_fifo;
468	GenericFifo<size_t> m_cmd_read_trdid_fifo;
469	GenericFifo<size_t> m_cmd_read_pktid_fifo;
470
471	// Fifo between TGT_CMD fsm and WRITE fsm
472	GenericFifo<uint64_t> m_cmd_write_addr_fifo;
473	GenericFifo<bool> m_cmd_write_eop_fifo;
474	GenericFifo<size_t> m_cmd_write_srcid_fifo;
475	GenericFifo<size_t> m_cmd_write_trdid_fifo;
476	GenericFifo<size_t> m_cmd_write_pktid_fifo;
477	GenericFifo<data_t> m_cmd_write_data_fifo;
478	GenericFifo<be_t> m_cmd_write_be_fifo;
479
480	// Fifo between TGT_CMD fsm and CAS fsm
481	GenericFifo<uint64_t> m_cmd_cas_addr_fifo;
482	GenericFifo<bool> m_cmd_cas_eop_fifo;
483	GenericFifo<size_t> m_cmd_cas_srcid_fifo;
484	GenericFifo<size_t> m_cmd_cas_trdid_fifo;
485	GenericFifo<size_t> m_cmd_cas_pktid_fifo;
486	GenericFifo<data_t> m_cmd_cas_wdata_fifo;
487
488	sc_signal<int> r_tgt_cmd_fsm;
489
490	size_t m_nseg;
491	size_t m_ncseg;
492	soclib::common::Segment **m_seg;
493	soclib::common::Segment **m_cseg;
494	///////////////////////////////////////////////////////
495	// Registers controlled by the READ fsm
496	///////////////////////////////////////////////////////
497
498	sc_signal<int> r_read_fsm; // FSM state
499	sc_signal<size_t> r_read_copy; // Srcid of the first copy
500	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
501	sc_signal<bool> r_read_copy_inst; // Type of the first copy
502	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
503	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
504	sc_signal<bool> r_read_lock; // lock bit (in directory)
505	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
506	sc_signal<size_t> r_read_count; // number of copies
507	sc_signal<size_t> r_read_ptr; // pointer to the heap
508	sc_signal<data_t> * r_read_data; // data (one cache line)
509	sc_signal<size_t> r_read_way; // associative way (in cache)
510	sc_signal<size_t> r_read_trt_index; // Transaction Table index
511	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
512	sc_signal<bool> r_read_last_free; // Last free entry
513	sc_signal<typename vci_param::fast_addr_t>
514	r_read_ll_key; // LL key returned by the llsc_global_table
515
516	// Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
517	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
518	sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index
519	sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table
520
521	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
522	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
523	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
524	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
525	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
526	sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)
527	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
528	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
529	sc_signal<typename vci_param::fast_addr_t>
530	r_read_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
531
532	///////////////////////////////////////////////////////////////
533	// Registers controlled by the WRITE fsm
534	///////////////////////////////////////////////////////////////
535
536	sc_signal<int> r_write_fsm; // FSM state
537	sc_signal<addr_t> r_write_address; // first word address
538	sc_signal<size_t> r_write_word_index; // first word index in line
539	sc_signal<size_t> r_write_word_count; // number of words in line
540	sc_signal<size_t> r_write_srcid; // transaction srcid
541	sc_signal<size_t> r_write_trdid; // transaction trdid
542	sc_signal<size_t> r_write_pktid; // transaction pktid
543	sc_signal<data_t> * r_write_data; // data (one cache line)
544	sc_signal<be_t> * r_write_be; // one byte enable per word
545	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
546	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
547	sc_signal<bool> r_write_lock; // lock bit (in directory)
548	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
549	sc_signal<size_t> r_write_copy; // first owner of the line
550	sc_signal<size_t> r_write_copy_cache; // first owner of the line
551	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
552	sc_signal<size_t> r_write_count; // number of copies
553	sc_signal<size_t> r_write_ptr; // pointer to the heap
554	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
555	sc_signal<bool> r_write_to_dec; // need to decrement update counter
556	sc_signal<size_t> r_write_way; // way of the line
557	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
558	sc_signal<size_t> r_write_upt_index; // index in Update Table
559	sc_signal<bool> r_write_sc_fail; // sc command failed
560	sc_signal<bool> r_write_pending_sc; // sc command pending in WRITE fsm
561
562	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
563	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
564	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
565	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
566	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
567	sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed
568
569	// Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
570	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
571	sc_signal<bool> r_write_to_ixr_cmd_write; // write request
572	sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index
573	sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data
574	sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table
575
576	// Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
577	sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request
578	sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request
579	sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index
580	sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table
581	sc_signal<data_t> * r_write_to_init_cmd_data; // data (one cache line)
582	sc_signal<be_t> * r_write_to_init_cmd_be; // word enable
583	sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line
584	sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line
585	GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type
586	GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids
587	#if L1_MULTI_CACHE
588	GenericFifo<size_t> m_write_to_init_cmd_cache_id_fifo; // fifo for srcids
589	#endif
590
591	// Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
592	sc_signal<bool> r_write_to_init_rsp_req; // valid request
593	sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table
594
595	/////////////////////////////////////////////////////////
596	// Registers controlled by INIT_RSP fsm
597	//////////////////////////////////////////////////////////
598
599	sc_signal<int> r_init_rsp_fsm; // FSM state
600	sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table
601	sc_signal<size_t> r_init_rsp_srcid; // pending write srcid
602	sc_signal<size_t> r_init_rsp_trdid; // pending write trdid
603	sc_signal<size_t> r_init_rsp_pktid; // pending write pktid
604	sc_signal<addr_t> r_init_rsp_nline; // pending write nline
605
606	// Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
607	sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request
608	sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid
609	sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid
610	sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid
611
612	///////////////////////////////////////////////////////
613	// Registers controlled by CLEANUP fsm
614	///////////////////////////////////////////////////////
615
616	sc_signal<int> r_cleanup_fsm; // FSM state
617	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
618	sc_signal<size_t> r_cleanup_trdid; // transaction trdid
619	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
620	sc_signal<addr_t> r_cleanup_nline; // cache line index
621
622	sc_signal<copy_t> r_cleanup_copy; // first copy
623	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
624	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
625	sc_signal<copy_t> r_cleanup_count; // number of copies
626	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
627	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
628	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
629	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
630	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
631	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
632	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
633	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
634	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
635	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
636	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
637
638	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response
639	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
640	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
641	sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp
642
643	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
644
645	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
646	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
647	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
648	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
649	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
650
651	///////////////////////////////////////////////////////
652	// Registers controlled by CAS fsm
653	///////////////////////////////////////////////////////
654
655	sc_signal<int> r_cas_fsm; // FSM state
656	sc_signal<data_t> r_cas_wdata; // write data word
657	sc_signal<data_t> * r_cas_rdata; // read data word
658	sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing
659	sc_signal<size_t> r_cas_cpt; // size of command
660	sc_signal<copy_t> r_cas_copy; // Srcid of the first copy
661	sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy
662	sc_signal<bool> r_cas_copy_inst; // Type of the first copy
663	sc_signal<size_t> r_cas_count; // number of copies
664	sc_signal<size_t> r_cas_ptr; // pointer to the heap
665	sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap
666	sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)
667	sc_signal<bool> r_cas_dirty; // dirty bit (in directory)
668	sc_signal<size_t> r_cas_way; // way in directory
669	sc_signal<size_t> r_cas_set; // set in directory
670	sc_signal<data_t> r_cas_tag; // cache line tag (in directory)
671	sc_signal<size_t> r_cas_trt_index; // Transaction Table index
672	sc_signal<size_t> r_cas_upt_index; // Update Table index
673	sc_signal<data_t> * r_cas_data; // cache line data
674
675	// Buffer between CAS fsm and INIT_CMD fsm (XRAM read)
676	sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request
677	sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index
678	sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table
679	sc_signal<bool> r_cas_to_ixr_cmd_write; // write request
680	sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data
681
682
683	// Buffer between CAS fsm and TGT_RSP fsm
684	sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request
685	sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word
686	sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid
687	sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid
688	sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid
689
690	// Buffer between CAS fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
691	sc_signal<bool> r_cas_to_init_cmd_multi_req; // valid request
692	sc_signal<bool> r_cas_to_init_cmd_brdcast_req; // brdcast request
693	sc_signal<addr_t> r_cas_to_init_cmd_nline; // cache line index
694	sc_signal<size_t> r_cas_to_init_cmd_trdid; // index in Update Table
695	sc_signal<data_t> r_cas_to_init_cmd_wdata; // data (one word)
696	sc_signal<bool> r_cas_to_init_cmd_is_long; // it is a 64 bits CAS
697	sc_signal<data_t> r_cas_to_init_cmd_wdata_high; // data high (one word)
698	sc_signal<size_t> r_cas_to_init_cmd_index; // index of the word in line
699	GenericFifo<bool> m_cas_to_init_cmd_inst_fifo; // fifo for the L1 type
700	GenericFifo<size_t> m_cas_to_init_cmd_srcid_fifo; // fifo for srcids
701	#if L1_MULTI_CACHE
702	GenericFifo<size_t> m_cas_to_init_cmd_cache_id_fifo; // fifo for srcids
703	#endif
704
705	// Buffer between CAS fsm and INIT_RSP fsm (Decrement UPT entry)
706	sc_signal<bool> r_cas_to_init_rsp_req; // valid request
707	sc_signal<size_t> r_cas_to_init_rsp_upt_index; // index in update table
708
709	////////////////////////////////////////////////////
710	// Registers controlled by the IXR_RSP fsm
711	////////////////////////////////////////////////////
712
713	sc_signal<int> r_ixr_rsp_fsm; // FSM state
714	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
715	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
716
717	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
718	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
719
720	////////////////////////////////////////////////////
721	// Registers controlled by the XRAM_RSP fsm
722	////////////////////////////////////////////////////
723
724	sc_signal<int> r_xram_rsp_fsm; // FSM state
725	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
726	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
727	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
728	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
729	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
730	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
731	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
732	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
733	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
734	sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy
735	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
736	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
737	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
738	sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data
739	sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index
740	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
741
742	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
743	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
744	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
745	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
746	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
747	sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
748	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
749	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response
750	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
751	sc_signal<typename vci_param::fast_addr_t>
752	r_xram_rsp_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
753
754	// Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
755	sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request
756	sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request
757	sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index;
758	sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry
759	GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type
760	GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids
761	#if L1_MULTI_CACHE
762	GenericFifo<size_t> m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids
763	#endif
764
765	// Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
766	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
767	sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index
768	sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data
769	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
770
771	////////////////////////////////////////////////////
772	// Registers controlled by the IXR_CMD fsm
773	////////////////////////////////////////////////////
774
775	sc_signal<int> r_ixr_cmd_fsm;
776	sc_signal<size_t> r_ixr_cmd_cpt;
777
778	////////////////////////////////////////////////////
779	// Registers controlled by TGT_RSP fsm
780	////////////////////////////////////////////////////
781
782	sc_signal<int> r_tgt_rsp_fsm;
783	sc_signal<size_t> r_tgt_rsp_cpt;
784	sc_signal<bool> r_tgt_rsp_key_sent;
785
786	////////////////////////////////////////////////////
787	// Registers controlled by INIT_CMD fsm
788	////////////////////////////////////////////////////
789
790	sc_signal<int> r_init_cmd_fsm;
791	sc_signal<size_t> r_init_cmd_cpt;
792	sc_signal<bool> r_init_cmd_inst;
793
794	////////////////////////////////////////////////////
795	// Registers controlled by ALLOC_DIR fsm
796	////////////////////////////////////////////////////
797
798	sc_signal<int> r_alloc_dir_fsm;
799	sc_signal<unsigned> r_alloc_dir_reset_cpt;
800
801	////////////////////////////////////////////////////
802	// Registers controlled by ALLOC_TRT fsm
803	////////////////////////////////////////////////////
804
805	sc_signal<int> r_alloc_trt_fsm;
806
807	////////////////////////////////////////////////////
808	// Registers controlled by ALLOC_UPT fsm
809	////////////////////////////////////////////////////
810
811	sc_signal<int> r_alloc_upt_fsm;
812
813	////////////////////////////////////////////////////
814	// Registers controlled by ALLOC_HEAP fsm
815	////////////////////////////////////////////////////
816
817	sc_signal<int> r_alloc_heap_fsm;
818	sc_signal<unsigned> r_alloc_heap_reset_cpt;
819	}; // end class VciMemCacheV4
820
821	}}
822
823	#endif
824
825	// Local Variables:
826	// tab-width: 2
827	// c-basic-offset: 2
828	// c-file-offsets:((innamespace . 0)(inline-open . 0))
829	// indent-tabs-mode: nil
830	// End:
831
832	// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
833

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