[551] | 1 | /* -*- c++ -*- |
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| 2 | * |
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| 3 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 4 | * |
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| 5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 6 | * |
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| 7 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 8 | * under the terms of the GNU Lesser General Public License as published |
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| 9 | * by the Free Software Foundation; version 2.1 of the License. |
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| 10 | * |
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| 11 | * SoCLib is distributed in the hope that it will be useful, but |
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| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | * Lesser General Public License for more details. |
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| 15 | * |
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| 16 | * You should have received a copy of the GNU Lesser General Public |
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| 17 | * License along with SoCLib; if not, write to the Free Software |
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| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 19 | * 02110-1301 USA |
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| 20 | * |
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| 21 | * SOCLIB_LGPL_HEADER_END |
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| 22 | * |
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| 23 | * Copyright (c) UPMC, Lip6, SoC |
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[558] | 24 | * manuel.bouyer@lip6.fr october 2013 |
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[551] | 25 | * |
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| 26 | * Maintainers: bouyer |
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| 27 | */ |
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| 28 | |
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| 29 | #include <stdint.h> |
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| 30 | #include <iostream> |
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[579] | 31 | #include <arithmetics.h> |
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[551] | 32 | #include <fcntl.h> |
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| 33 | #include "vci_spi.h" |
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| 34 | #include "vcispi.h" |
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| 35 | |
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| 36 | namespace soclib { namespace caba { |
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| 37 | |
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| 38 | #define tmpl(t) template<typename vci_param> t VciSpi<vci_param> |
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| 39 | |
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| 40 | using namespace soclib::caba; |
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| 41 | using namespace soclib::common; |
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| 42 | |
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| 43 | //////////////////////// |
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| 44 | tmpl(void)::transition() |
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| 45 | { |
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[579] | 46 | |
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| 47 | bool s_dma_bsy = (r_initiator_fsm != M_IDLE); |
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[1052] | 48 | |
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[551] | 49 | if(p_resetn.read() == false) |
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| 50 | { |
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[1052] | 51 | r_initiator_fsm = M_IDLE; |
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| 52 | r_target_fsm = T_IDLE; |
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| 53 | r_spi_fsm = S_IDLE; |
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| 54 | r_ss = 0; |
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| 55 | r_divider = 0xffff; |
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| 56 | r_ctrl_char_len = 0; |
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| 57 | r_ctrl_ie = false; |
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| 58 | r_ctrl_cpol = false; |
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| 59 | r_ctrl_cpha = false; |
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| 60 | r_spi_bsy = false; |
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| 61 | r_dma_count = 0; |
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| 62 | r_dma_error = false; |
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| 63 | r_spi_clk_counter = 0xffff; |
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| 64 | r_spi_clk = 0; |
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| 65 | r_spi_done = false; |
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[551] | 66 | |
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[1052] | 67 | r_irq = false; |
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| 68 | r_read = false; |
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[551] | 69 | |
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[1052] | 70 | r_dma_fifo_read.init(); |
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| 71 | r_dma_fifo_write.init(); |
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[579] | 72 | |
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[1052] | 73 | return; |
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[551] | 74 | } |
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| 75 | |
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| 76 | ////////////////////////////////////////////////////////////////////////////// |
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[1052] | 77 | // The Target FSM handles the software access to addressable registers |
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[551] | 78 | ////////////////////////////////////////////////////////////////////////////// |
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| 79 | |
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[565] | 80 | if (r_spi_done) |
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[579] | 81 | r_spi_bsy = false; |
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[565] | 82 | |
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[1052] | 83 | switch(r_target_fsm) |
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| 84 | { |
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[551] | 85 | //////////// |
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| 86 | case T_IDLE: |
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| 87 | { |
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[1052] | 88 | if ( p_vci_target.cmdval.read() ) |
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| 89 | { |
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| 90 | r_srcid = p_vci_target.srcid.read(); |
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| 91 | r_trdid = p_vci_target.trdid.read(); |
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| 92 | r_pktid = p_vci_target.pktid.read(); |
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| 93 | uint32_t wdata = p_vci_target.wdata.read(); |
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| 94 | sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read(); |
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[551] | 95 | |
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[1052] | 96 | bool found = false; |
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| 97 | std::list<soclib::common::Segment>::iterator seg; |
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| 98 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
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| 99 | { |
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| 100 | if ( seg->contains(address) ) found = true; |
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| 101 | } |
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[551] | 102 | |
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[1052] | 103 | if (not found) |
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| 104 | { |
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| 105 | if (p_vci_target.cmd.read() == vci_param::CMD_WRITE) |
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| 106 | r_target_fsm = T_ERROR_WRITE; |
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| 107 | else |
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| 108 | r_target_fsm = T_ERROR_READ; |
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| 109 | } |
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| 110 | else if (p_vci_target.cmd.read() != vci_param::CMD_READ && |
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| 111 | p_vci_target.cmd.read() != vci_param::CMD_WRITE) |
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| 112 | { |
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| 113 | r_target_fsm = T_ERROR_READ; |
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| 114 | } |
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| 115 | else |
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| 116 | { |
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| 117 | bool write = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) |
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| 118 | & !r_spi_bsy & !s_dma_bsy; |
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| 119 | uint32_t cell = (uint32_t)((address & 0x3F)>>2); |
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| 120 | switch(cell) |
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| 121 | { |
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| 122 | case SPI_DATA_TXRX0: |
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| 123 | r_rdata = r_txrx[0] & (uint64_t)0x00000000ffffffffULL; |
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| 124 | if (write) |
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| 125 | { |
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| 126 | r_txrx[0] = (r_txrx[0] & (uint64_t)0xffffffff00000000ULL) | |
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| 127 | ((uint64_t)wdata); |
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| 128 | } |
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| 129 | r_target_fsm = (p_vci_target.cmd.read() |
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| 130 | == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 131 | break; |
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| 132 | case SPI_DATA_TXRX1: |
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| 133 | r_rdata = r_txrx[0] >> 32; |
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| 134 | if (write) |
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| 135 | { |
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| 136 | r_txrx[0] = (r_txrx[0] & (uint64_t)0x00000000ffffffffULL) | |
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| 137 | ((uint64_t)wdata << 32); |
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| 138 | } |
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| 139 | r_target_fsm = (p_vci_target.cmd.read() |
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| 140 | == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 141 | break; |
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| 142 | case SPI_DATA_TXRX2: |
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| 143 | r_rdata = r_txrx[1] & (uint64_t)0x00000000ffffffffULL; |
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| 144 | if (write) |
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| 145 | { |
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| 146 | r_txrx[1] = (r_txrx[1] & (uint64_t)0xffffffff00000000ULL) | |
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| 147 | ((uint64_t)wdata); |
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| 148 | } |
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| 149 | r_target_fsm = (p_vci_target.cmd.read() |
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| 150 | == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 151 | break; |
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| 152 | case SPI_DATA_TXRX3: |
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| 153 | r_rdata = r_txrx[1] >> 32; |
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| 154 | if (write) |
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| 155 | { |
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| 156 | r_txrx[1] = (r_txrx[1] & (uint64_t)0x00000000ffffffffULL) | |
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| 157 | ((uint64_t)wdata << 32); |
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| 158 | } |
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| 159 | r_target_fsm = (p_vci_target.cmd.read() |
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| 160 | == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 161 | break; |
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| 162 | case SPI_CTRL: |
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| 163 | uint32_t data = 0; |
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| 164 | if (r_ctrl_cpol.read()) data |= SPI_CTRL_CPOL; |
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| 165 | if (r_ctrl_cpha.read()) data |= SPI_CTRL_CPHA; |
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| 166 | if (r_ctrl_ie.read()) data |= SPI_CTRL_IE_EN; |
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| 167 | if (r_spi_bsy.read()) data |= SPI_CTRL_GO_BSY; |
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| 168 | if (s_dma_bsy) data |= SPI_CTRL_DMA_BSY; |
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| 169 | if (r_dma_error) data |= SPI_CTRL_DMA_ERR; |
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| 170 | data |= (uint32_t)r_ctrl_char_len.read(); |
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| 171 | r_rdata = data; |
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| 172 | if (write) |
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| 173 | { |
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| 174 | r_ctrl_cpol = ((wdata & SPI_CTRL_CPOL) != 0); |
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| 175 | r_ctrl_cpha = ((wdata & SPI_CTRL_CPHA) != 0); |
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| 176 | r_ctrl_ie = ((wdata & SPI_CTRL_IE_EN) != 0); |
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| 177 | if (wdata & SPI_CTRL_GO_BSY) r_spi_bsy = true; |
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| 178 | r_ctrl_char_len = (wdata & SPI_CTRL_CHAR_LEN_MASK); |
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[551] | 179 | |
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| 180 | #ifdef SOCLIB_MODULE_DEBUG |
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[558] | 181 | if ((wdata & SPI_CTRL_GO_BSY) != 0) { |
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| 182 | std::cout << name() << " start xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; |
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| 183 | } |
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| 184 | #endif |
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[1052] | 185 | } |
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| 186 | else |
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| 187 | { |
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| 188 | r_irq = false; |
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| 189 | } |
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| 190 | r_target_fsm = (p_vci_target.cmd.read() |
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| 191 | == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 192 | break; |
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| 193 | case SPI_DIVIDER: |
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| 194 | r_rdata = r_divider.read(); |
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| 195 | if (write) r_divider = wdata; |
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| 196 | |
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[558] | 197 | #ifdef SOCLIB_MODULE_DEBUG |
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| 198 | std::cout << name() << " divider set to " << std::dec << wdata << std::endl; |
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[551] | 199 | #endif |
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[1052] | 200 | r_target_fsm = (p_vci_target.cmd.read() |
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| 201 | == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 202 | break; |
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| 203 | case SPI_SS: |
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| 204 | r_rdata = r_ss.read(); |
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| 205 | if (write) r_ss = wdata; |
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| 206 | r_target_fsm = (p_vci_target.cmd.read() |
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| 207 | == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 208 | break; |
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| 209 | case SPI_DMA_BASE: |
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| 210 | r_rdata = r_buf_address.read(); |
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| 211 | if (write) r_buf_address = (r_buf_address.read & |
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| 212 | (uint64_t)0xffffffff00000000) | wdata; |
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| 213 | r_target_fsm = (p_vci_target.cmd.read() |
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| 214 | == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 215 | break; |
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| 216 | case SPI_DMA_BASEH: |
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| 217 | r_rdata = r_buf_address >> 32; |
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| 218 | if (write) r_buf_address = (r_buf_address & |
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| 219 | (uint64_t)0x00000000ffffffff) | ((uint64_t)wdata << 32); |
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| 220 | r_target_fsm = (p_vci_target.cmd.read() |
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| 221 | == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 222 | break; |
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| 223 | case SPI_DMA_COUNT: |
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| 224 | r_rdata = (r_dma_count.read() << m_byte2burst_shift) | r_read; |
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| 225 | if (write) |
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| 226 | { |
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| 227 | r_read = (wdata & 0x1); |
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| 228 | r_dma_count = wdata >> m_byte2burst_shift; |
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| 229 | r_ctrl_char_len = vci_param::B * 8; |
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| 230 | } |
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| 231 | r_target_fsm = (p_vci_target.cmd.read() |
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| 232 | == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 233 | break; |
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| 234 | default: |
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| 235 | r_target_fsm = (p_vci_target.cmd.read() |
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| 236 | == vci_param::CMD_WRITE) ? T_ERROR_WRITE : T_ERROR_READ; |
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| 237 | break; |
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| 238 | } |
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| 239 | } |
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[551] | 240 | } |
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[1052] | 241 | break; |
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[551] | 242 | } |
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[558] | 243 | //////////////////// |
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| 244 | case T_RSP_READ: |
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| 245 | case T_RSP_WRITE: |
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| 246 | case T_ERROR_READ: |
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| 247 | case T_ERROR_WRITE: |
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[1052] | 248 | { |
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| 249 | if (p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 250 | break; |
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| 251 | } |
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[551] | 252 | } // end switch target fsm |
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| 253 | |
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| 254 | |
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| 255 | |
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| 256 | |
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| 257 | ////////////////////////////////////////////////////////////////////////////// |
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| 258 | // the SPI FSM controls SPI signals |
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| 259 | ////////////////////////////////////////////////////////////////////////////// |
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[579] | 260 | if (r_spi_bsy == false) |
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[565] | 261 | r_spi_done = false; |
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[1052] | 262 | |
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| 263 | switch (r_spi_fsm) |
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[579] | 264 | { |
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[1052] | 265 | //////////// |
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| 266 | case S_IDLE: // polling the (r_dma_count/r_read) registers for dma request |
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| 267 | // polling the r_spi_bsy register for config request |
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| 268 | { |
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| 269 | r_spi_clk_counter = r_divider.read(); |
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| 270 | r_spi_clk = 0; |
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| 271 | r_spi_clk_previous = r_ctrl_cpha; |
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| 272 | r_spi_clk_ignore = r_ctrl_cpha; |
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| 273 | r_spi_bit_count = r_ctrl_char_len; |
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| 274 | if (r_dma_count != 0) |
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| 275 | { |
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| 276 | if (r_read.read()) r_spi_fsm = S_DMA_SEND_START; |
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| 277 | else r_spi_fsm = S_DMA_RECEIVE; |
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| 278 | } |
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| 279 | else if (r_spi_bsy.read() && !r_spi_done.read()) |
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| 280 | { |
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[579] | 281 | r_spi_fsm = S_XMIT; |
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[1052] | 282 | r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) |
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| 283 | & (uint64_t)0x0000000000000001ULL; |
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[579] | 284 | } |
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[1052] | 285 | break; |
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[579] | 286 | } |
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[1052] | 287 | /////////////////// |
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| 288 | case S_DMA_RECEIVE: // copy one word from fifo_write to shift register |
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| 289 | { |
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| 290 | r_spi_clk_counter = r_divider.read(); |
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| 291 | r_spi_clk = 0; |
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| 292 | r_spi_clk_previous = r_ctrl_cpha; |
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| 293 | r_spi_clk_ignore = r_ctrl_cpha; |
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| 294 | r_spi_bit_count = r_ctrl_char_len; |
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| 295 | if (r_initiator_fsm != M_WRITE_RSP || !p_vci_initiator.rspval.read()) |
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| 296 | { |
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| 297 | if (r_dma_fifo_write.rok()) |
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| 298 | { |
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| 299 | typename vci_param::data_t v = r_dma_fifo_write.read(); |
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| 300 | r_dma_fifo_write.simple_get(); |
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| 301 | r_txrx[0] = v; |
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| 302 | r_spi_out = (v >> ((vci_param::B * 8) - 1)) & 0x1; |
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| 303 | r_spi_fsm = S_XMIT; |
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| 304 | } |
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| 305 | else if (r_initiator_fsm == M_WRITE_END) |
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| 306 | { |
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| 307 | r_spi_fsm = S_IDLE; |
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| 308 | } |
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| 309 | } |
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| 310 | break; |
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| 311 | } |
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| 312 | ////////////////////// |
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[579] | 313 | case S_DMA_SEND_START: |
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[1052] | 314 | { |
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| 315 | r_spi_word_count = (r_dma_count << (m_byte2burst_shift - 2)) - 1; |
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| 316 | r_spi_out = 1; |
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| 317 | r_txrx[0] = 0xffffffff; |
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| 318 | r_spi_fsm = S_XMIT; |
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| 319 | break; |
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| 320 | } |
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| 321 | //////////////// |
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[579] | 322 | case S_DMA_SEND: |
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[1052] | 323 | { |
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| 324 | r_spi_out = 1; |
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| 325 | r_spi_clk_counter = r_divider.read(); |
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| 326 | r_spi_clk = 0; |
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| 327 | r_spi_clk_previous = r_ctrl_cpha; |
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| 328 | r_spi_clk_ignore = r_ctrl_cpha; |
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| 329 | r_spi_bit_count = r_ctrl_char_len; |
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| 330 | if (r_initiator_fsm != M_READ_CMD) |
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| 331 | { |
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| 332 | if (r_dma_fifo_read.wok()) |
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| 333 | { |
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| 334 | r_dma_fifo_read.simple_put( (typename vci_param::data_t)r_txrx[0] ); |
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| 335 | r_spi_word_count = r_spi_word_count - 1; |
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| 336 | r_txrx[0] = 0xffffffff; |
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| 337 | if ( r_spi_word_count == 0 ) r_spi_fsm = S_DMA_SEND_END; |
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| 338 | else r_spi_fsm = S_XMIT; |
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[579] | 339 | } |
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| 340 | } |
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[1052] | 341 | break; |
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| 342 | } |
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| 343 | //////////////////// |
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| 344 | case S_DMA_SEND_END: |
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| 345 | { |
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| 346 | if (r_initiator_fsm == M_IDLE) r_spi_fsm = S_IDLE; |
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| 347 | break; |
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| 348 | } |
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| 349 | //////////// |
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| 350 | case S_XMIT: // on SPI clock transitions, sample input line, and shift data |
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| 351 | { |
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| 352 | bool s_clk_sample; |
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| 353 | // on clock transition, sample input line, and shift data |
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| 354 | s_clk_sample = r_spi_clk ^ r_ctrl_cpha; |
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| 355 | |
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| 356 | if ( !r_spi_clk_ignore ) |
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| 357 | { |
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| 358 | if (r_spi_clk_previous == 0 && s_clk_sample == 1) |
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| 359 | { |
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| 360 | // low to high transition: shift and sample |
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| 361 | r_txrx[1] = (r_txrx[1] << 1) | (r_txrx[0] >> 63); |
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| 362 | r_txrx[0] = (r_txrx[0] << 1) | p_spi_miso; |
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| 363 | r_spi_bit_count = r_spi_bit_count - 1; |
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| 364 | } |
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| 365 | else if (r_spi_clk_previous == 1 && s_clk_sample == 0) |
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| 366 | { |
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| 367 | // high to low transition: change output, or stop |
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| 368 | if (r_spi_bit_count == 0) |
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| 369 | { |
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| 370 | if (r_initiator_fsm != M_IDLE) |
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| 371 | { |
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| 372 | if (r_read) r_spi_fsm = S_DMA_SEND; |
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| 373 | else r_spi_fsm = S_DMA_RECEIVE; |
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| 374 | } |
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| 375 | else |
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| 376 | { |
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| 377 | r_spi_fsm = S_IDLE; |
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| 378 | r_irq = r_ctrl_ie; |
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| 379 | r_spi_done = true; |
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| 380 | } |
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[558] | 381 | #ifdef SOCLIB_MODULE_DEBUG0 |
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[551] | 382 | std::cout << name() << " end xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; |
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| 383 | #endif |
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[1052] | 384 | } |
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| 385 | else |
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| 386 | { |
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| 387 | r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) |
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| 388 | & (uint64_t)0x0000000000000001ULL; |
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| 389 | } |
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| 390 | } |
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[551] | 391 | } |
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[1052] | 392 | r_spi_clk_previous = s_clk_sample; |
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| 393 | |
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| 394 | // generate the SPI clock |
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| 395 | if (r_spi_clk_counter.read() == 0) |
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| 396 | { |
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| 397 | r_spi_clk_counter = r_divider.read(); |
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| 398 | r_spi_clk = !r_spi_clk.read(); |
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| 399 | r_spi_clk_ignore = false; |
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| 400 | } |
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| 401 | else |
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| 402 | { |
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| 403 | r_spi_clk_counter = r_spi_clk_counter.read() - 1; |
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| 404 | } |
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| 405 | break; |
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[551] | 406 | } |
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[1052] | 407 | } // end r_spi_fsm |
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| 408 | |
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[551] | 409 | ////////////////////////////////////////////////////////////////////////////// |
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[579] | 410 | // The initiator FSM executes a loop, transfering one burst per iteration. |
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| 411 | // data comes from or goes to fifos, the other end of the fifos is |
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| 412 | // feed by or eaten by the SPI fsm. |
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[551] | 413 | ////////////////////////////////////////////////////////////////////////////// |
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| 414 | |
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[1052] | 415 | switch( r_initiator_fsm.read() ) |
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| 416 | { |
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[551] | 417 | //////////// |
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[1052] | 418 | case M_IDLE: // poll the r_dma_count and r_read registers |
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[551] | 419 | { |
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[1052] | 420 | if ( r_dma_count != 0 ) |
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| 421 | { |
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| 422 | // start transfer |
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| 423 | if ( r_read.read() ) r_initiator_fsm = M_READ_WAIT; |
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| 424 | else r_initiator_fsm = M_WRITE_WAIT; |
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| 425 | } |
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| 426 | break; |
---|
[551] | 427 | } |
---|
[1052] | 428 | ///////////////// |
---|
[579] | 429 | case M_READ_WAIT: // wait for the FIFO to be full |
---|
[1052] | 430 | { |
---|
| 431 | if (!r_dma_fifo_read.wok()) |
---|
| 432 | { |
---|
| 433 | r_burst_word = m_words_per_burst - 1; |
---|
| 434 | r_initiator_fsm = M_READ_CMD; |
---|
| 435 | } |
---|
| 436 | break; |
---|
| 437 | } |
---|
[551] | 438 | //////////////// |
---|
[1052] | 439 | case M_READ_CMD: // multi-flits VCI WRITE command for one burst |
---|
[551] | 440 | { |
---|
[1052] | 441 | if ( p_vci_initiator.cmdack.read() ) |
---|
[558] | 442 | { |
---|
[1052] | 443 | if ( r_burst_word == 0 ) // last flit |
---|
| 444 | { |
---|
| 445 | r_initiator_fsm = M_READ_RSP; |
---|
| 446 | } |
---|
| 447 | else // not the last flit |
---|
| 448 | { |
---|
| 449 | r_burst_word = r_burst_word.read() - 1; |
---|
| 450 | } |
---|
| 451 | |
---|
| 452 | r_dma_fifo_read.simple_get(); // consume one fifo word |
---|
| 453 | // compute next word address |
---|
| 454 | r_buf_address = r_buf_address.read() + vci_param::B; |
---|
[558] | 455 | } |
---|
[1052] | 456 | break; |
---|
[551] | 457 | } |
---|
| 458 | //////////////// |
---|
| 459 | case M_READ_RSP: // Wait a single flit VCI WRITE response |
---|
| 460 | { |
---|
[1052] | 461 | if ( p_vci_initiator.rspval.read() ) |
---|
[558] | 462 | { |
---|
[1052] | 463 | if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
---|
| 464 | { |
---|
| 465 | r_burst_word = 0; |
---|
| 466 | r_dma_count = 0; |
---|
| 467 | r_dma_error = true; |
---|
| 468 | r_initiator_fsm = M_INTR; |
---|
| 469 | |
---|
[551] | 470 | #ifdef SOCLIB_MODULE_DEBUG |
---|
| 471 | std::cout << "vci_bd M_READ_ERROR" << std::endl; |
---|
| 472 | #endif |
---|
[1052] | 473 | |
---|
| 474 | } |
---|
| 475 | else if ( r_spi_fsm == S_DMA_SEND_END ) // last burst |
---|
| 476 | { |
---|
| 477 | r_dma_count = 0; |
---|
| 478 | r_initiator_fsm = M_INTR; |
---|
| 479 | r_dma_error = false; |
---|
| 480 | |
---|
[551] | 481 | #ifdef SOCLIB_MODULE_DEBUG |
---|
[579] | 482 | std::cout << "vci_bd M_READ_SUCCESS" << std::endl; |
---|
[551] | 483 | #endif |
---|
[1052] | 484 | |
---|
| 485 | } |
---|
| 486 | else // keep on reading |
---|
| 487 | { |
---|
| 488 | r_dma_count = r_dma_count - 1; |
---|
| 489 | r_initiator_fsm = M_READ_WAIT; |
---|
| 490 | } |
---|
[558] | 491 | } |
---|
[1052] | 492 | break; |
---|
[551] | 493 | } |
---|
| 494 | /////////////////// |
---|
[595] | 495 | case M_INTR: |
---|
[1052] | 496 | { |
---|
| 497 | r_initiator_fsm = M_IDLE; |
---|
| 498 | r_irq = true; |
---|
| 499 | break; |
---|
| 500 | } |
---|
[594] | 501 | /////////////////// |
---|
[579] | 502 | case M_WRITE_WAIT: // wait for the FIFO to be empty |
---|
[1052] | 503 | { |
---|
| 504 | if (!r_dma_fifo_write.rok()) |
---|
| 505 | { |
---|
| 506 | r_burst_word = m_words_per_burst - 1; |
---|
| 507 | r_dma_count = r_dma_count - 1; |
---|
| 508 | r_initiator_fsm = M_WRITE_CMD; |
---|
| 509 | } |
---|
| 510 | break; |
---|
| 511 | } |
---|
[551] | 512 | ///////////////// |
---|
[1052] | 513 | case M_WRITE_CMD: // single flit VCI READ command for one burst |
---|
[551] | 514 | { |
---|
[1052] | 515 | if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; |
---|
| 516 | break; |
---|
[551] | 517 | } |
---|
| 518 | ///////////////// |
---|
[1052] | 519 | case M_WRITE_RSP: // wait multi-words VCI READ response |
---|
[551] | 520 | { |
---|
[1052] | 521 | if ( p_vci_initiator.rspval.read() ) |
---|
[558] | 522 | { |
---|
[1052] | 523 | typename vci_param::data_t v = p_vci_initiator.rdata.read(); |
---|
| 524 | typename vci_param::data_t f = 0; |
---|
| 525 | // byte-swap |
---|
| 526 | for (int i = 0; i < (vci_param::B * 8); i += 8) |
---|
| 527 | { |
---|
| 528 | f |= ((v >> i) & 0xff) << ((vci_param::B * 8) - 8 - i); |
---|
| 529 | } |
---|
| 530 | r_dma_fifo_write.simple_put(f); |
---|
| 531 | r_burst_word = r_burst_word.read() - 1; |
---|
| 532 | if ( p_vci_initiator.reop.read() ) // last flit of the burst |
---|
| 533 | { |
---|
| 534 | r_buf_address = r_buf_address.read() + m_burst_size; |
---|
[551] | 535 | |
---|
[1052] | 536 | if( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
---|
| 537 | { |
---|
| 538 | r_dma_count = 0; |
---|
| 539 | r_dma_error = 1; |
---|
| 540 | r_initiator_fsm = M_WRITE_END; |
---|
| 541 | |
---|
[551] | 542 | #ifdef SOCLIB_MODULE_DEBUG |
---|
[1052] | 543 | std::cout << "vci_spi M_WRITE_ERROR" << std::endl; |
---|
[551] | 544 | #endif |
---|
[1052] | 545 | } |
---|
| 546 | else if ( r_dma_count.read() == 0) // last burst |
---|
| 547 | { |
---|
| 548 | r_dma_error = 0; |
---|
| 549 | r_initiator_fsm = M_WRITE_END; |
---|
| 550 | } |
---|
| 551 | else // not the last burst |
---|
| 552 | { |
---|
| 553 | r_initiator_fsm = M_WRITE_WAIT; |
---|
| 554 | } |
---|
| 555 | } |
---|
[558] | 556 | } |
---|
[1052] | 557 | break; |
---|
[551] | 558 | } |
---|
[579] | 559 | ///////////////// |
---|
[1052] | 560 | case M_WRITE_END: // wait for the write to be completed by SPI FSM |
---|
[551] | 561 | { |
---|
[1052] | 562 | if (r_spi_fsm == S_IDLE) r_initiator_fsm = M_INTR; |
---|
| 563 | break; |
---|
[551] | 564 | } |
---|
[1052] | 565 | } // end switch r_initiator_fsm |
---|
[551] | 566 | } // end transition |
---|
| 567 | |
---|
| 568 | ////////////////////// |
---|
| 569 | tmpl(void)::genMoore() |
---|
| 570 | { |
---|
| 571 | // p_vci_target port |
---|
| 572 | p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read(); |
---|
| 573 | p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read(); |
---|
| 574 | p_vci_target.rpktid = (sc_dt::sc_uint<vci_param::P>)r_pktid.read(); |
---|
| 575 | p_vci_target.reop = true; |
---|
| 576 | |
---|
| 577 | switch(r_target_fsm) { |
---|
| 578 | case T_IDLE: |
---|
[558] | 579 | p_vci_target.cmdack = true; |
---|
| 580 | p_vci_target.rspval = false; |
---|
| 581 | p_vci_target.rdata = 0; |
---|
| 582 | break; |
---|
| 583 | case T_RSP_READ: |
---|
| 584 | p_vci_target.cmdack = false; |
---|
| 585 | p_vci_target.rspval = true; |
---|
| 586 | p_vci_target.rdata = r_rdata; |
---|
| 587 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 588 | break; |
---|
| 589 | case T_RSP_WRITE: |
---|
| 590 | p_vci_target.cmdack = false; |
---|
| 591 | p_vci_target.rspval = true; |
---|
| 592 | p_vci_target.rdata = 0; |
---|
| 593 | p_vci_target.rerror = VCI_WRITE_OK; |
---|
| 594 | break; |
---|
| 595 | case T_ERROR_READ: |
---|
| 596 | p_vci_target.cmdack = false; |
---|
| 597 | p_vci_target.rspval = true; |
---|
| 598 | p_vci_target.rdata = 0; |
---|
| 599 | p_vci_target.rerror = VCI_READ_ERROR; |
---|
| 600 | break; |
---|
| 601 | case T_ERROR_WRITE: |
---|
| 602 | p_vci_target.cmdack = false; |
---|
| 603 | p_vci_target.rspval = true; |
---|
| 604 | p_vci_target.rdata = 0; |
---|
| 605 | p_vci_target.rerror = VCI_WRITE_ERROR; |
---|
| 606 | break; |
---|
[551] | 607 | } // end switch target fsm |
---|
| 608 | |
---|
| 609 | // p_vci_initiator port |
---|
| 610 | p_vci_initiator.srcid = (sc_dt::sc_uint<vci_param::S>)m_srcid; |
---|
| 611 | p_vci_initiator.trdid = 0; |
---|
| 612 | p_vci_initiator.contig = true; |
---|
| 613 | p_vci_initiator.cons = false; |
---|
| 614 | p_vci_initiator.wrap = false; |
---|
| 615 | p_vci_initiator.cfixed = false; |
---|
| 616 | p_vci_initiator.clen = 0; |
---|
| 617 | |
---|
| 618 | switch (r_initiator_fsm) { |
---|
| 619 | case M_WRITE_CMD: // It is actually a single flit VCI read command |
---|
[558] | 620 | p_vci_initiator.rspack = false; |
---|
| 621 | p_vci_initiator.cmdval = true; |
---|
| 622 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
| 623 | p_vci_initiator.cmd = vci_param::CMD_READ; |
---|
| 624 | p_vci_initiator.pktid = TYPE_READ_DATA_UNC; |
---|
| 625 | p_vci_initiator.wdata = 0; |
---|
| 626 | p_vci_initiator.be = 0; |
---|
[579] | 627 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(m_burst_size); |
---|
[558] | 628 | p_vci_initiator.eop = true; |
---|
| 629 | break; |
---|
[551] | 630 | case M_READ_CMD: // It is actually a multi-words VCI WRITE command |
---|
[579] | 631 | { |
---|
| 632 | typename vci_param::data_t v = 0; |
---|
| 633 | typename vci_param::data_t f; |
---|
[558] | 634 | p_vci_initiator.rspack = false; |
---|
| 635 | p_vci_initiator.cmdval = true; |
---|
[579] | 636 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
[558] | 637 | p_vci_initiator.cmd = vci_param::CMD_WRITE; |
---|
| 638 | p_vci_initiator.pktid = TYPE_WRITE; |
---|
[579] | 639 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(m_burst_size); |
---|
| 640 | f = r_dma_fifo_read.read(); |
---|
| 641 | // byte-swap |
---|
| 642 | for (int i = 0; i < (vci_param::B * 8); i += 8) { |
---|
| 643 | v |= ((f >> i) & 0xff) << ((vci_param::B * 8) - 8 - i); |
---|
| 644 | } |
---|
| 645 | p_vci_initiator.wdata = v; |
---|
| 646 | p_vci_initiator.eop = ( r_burst_word.read() == 0); |
---|
| 647 | if (vci_param::B == 8) |
---|
[558] | 648 | { |
---|
| 649 | p_vci_initiator.be = 0xFF; |
---|
| 650 | } |
---|
| 651 | else |
---|
| 652 | { |
---|
| 653 | p_vci_initiator.be = 0xF; |
---|
| 654 | } |
---|
| 655 | break; |
---|
[579] | 656 | } |
---|
[551] | 657 | case M_READ_RSP: |
---|
| 658 | case M_WRITE_RSP: |
---|
[558] | 659 | p_vci_initiator.rspack = true; |
---|
| 660 | p_vci_initiator.cmdval = false; |
---|
| 661 | break; |
---|
[551] | 662 | default: |
---|
[558] | 663 | p_vci_initiator.rspack = false; |
---|
| 664 | p_vci_initiator.cmdval = false; |
---|
| 665 | break; |
---|
[551] | 666 | } |
---|
| 667 | |
---|
[1052] | 668 | ////////////// SPI signals |
---|
[551] | 669 | p_spi_ss = ((r_ss & 0x1) == 0); |
---|
[1052] | 670 | |
---|
| 671 | switch(r_spi_fsm) |
---|
| 672 | { |
---|
[579] | 673 | default: |
---|
[1052] | 674 | p_spi_mosi = r_spi_out; |
---|
| 675 | p_spi_clk = 0; |
---|
| 676 | break; |
---|
[551] | 677 | case S_XMIT: |
---|
[1052] | 678 | { |
---|
| 679 | bool s_clk_sample = r_spi_clk ^ r_ctrl_cpha; |
---|
| 680 | p_spi_clk = r_spi_clk ^ r_ctrl_cpol; |
---|
| 681 | if (s_clk_sample == 0) |
---|
| 682 | { |
---|
| 683 | // clock low: get data directly from shift register |
---|
| 684 | // as r_spi_out may be delayed by one clock cycle |
---|
| 685 | p_spi_mosi = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; |
---|
| 686 | } |
---|
| 687 | else |
---|
| 688 | { |
---|
| 689 | // clock high: get data from saved value, as the shift register |
---|
| 690 | // may have changed |
---|
| 691 | p_spi_mosi = r_spi_out; |
---|
| 692 | } |
---|
| 693 | break; |
---|
[551] | 694 | } |
---|
[1052] | 695 | } |
---|
[551] | 696 | |
---|
| 697 | // IRQ signal |
---|
| 698 | p_irq = r_irq; |
---|
| 699 | } // end GenMoore() |
---|
| 700 | |
---|
| 701 | ////////////////////////////////////////////////////////////////////////////// |
---|
[1052] | 702 | tmpl(/**/)::VciSpi( sc_core::sc_module_name name, |
---|
[558] | 703 | const soclib::common::MappingTable &mt, |
---|
[1052] | 704 | const soclib::common::IntTab &srcid, |
---|
| 705 | const soclib::common::IntTab &tgtid, |
---|
| 706 | const uint32_t burst_size) |
---|
[551] | 707 | |
---|
| 708 | : caba::BaseModule(name), |
---|
| 709 | m_seglist(mt.getSegmentList(tgtid)), |
---|
| 710 | m_srcid(mt.indexForId(srcid)), |
---|
[579] | 711 | m_burst_size(burst_size), |
---|
| 712 | m_words_per_burst(burst_size / vci_param::B), |
---|
| 713 | m_byte2burst_shift(soclib::common::uint32_log2(burst_size)), |
---|
[551] | 714 | p_clk("p_clk"), |
---|
| 715 | p_resetn("p_resetn"), |
---|
| 716 | p_vci_initiator("p_vci_initiator"), |
---|
| 717 | p_vci_target("p_vci_target"), |
---|
| 718 | p_irq("p_irq"), |
---|
| 719 | p_spi_ss("p_spi_ss"), |
---|
| 720 | p_spi_clk("p_spi_clk"), |
---|
| 721 | p_spi_mosi("p_spi_mosi"), |
---|
[579] | 722 | p_spi_miso("p_spi_miso"), |
---|
| 723 | |
---|
| 724 | r_dma_fifo_read("r_dma_fifo_read", burst_size / vci_param::B), // one cache line |
---|
| 725 | r_dma_fifo_write("r_dma_fifo_read", burst_size / vci_param::B) // one cache line |
---|
[551] | 726 | { |
---|
| 727 | std::cout << " - Building VciSpi " << name << std::endl; |
---|
| 728 | |
---|
| 729 | SC_METHOD(transition); |
---|
| 730 | dont_initialize(); |
---|
| 731 | sensitive << p_clk.pos(); |
---|
| 732 | |
---|
| 733 | SC_METHOD(genMoore); |
---|
| 734 | dont_initialize(); |
---|
| 735 | sensitive << p_clk.neg(); |
---|
| 736 | |
---|
| 737 | size_t nbsegs = 0; |
---|
| 738 | std::list<soclib::common::Segment>::iterator seg; |
---|
| 739 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
---|
| 740 | { |
---|
[558] | 741 | nbsegs++; |
---|
| 742 | |
---|
[551] | 743 | if ( (seg->baseAddress() & 0x0000003F) != 0 ) |
---|
| 744 | { |
---|
| 745 | std::cout << "Error in component VciSpi : " << name |
---|
[558] | 746 | << "The base address of segment " << seg->name() |
---|
| 747 | << " must be multiple of 64 bytes" << std::endl; |
---|
[551] | 748 | exit(1); |
---|
| 749 | } |
---|
| 750 | if ( seg->size() < 64 ) |
---|
| 751 | { |
---|
| 752 | std::cout << "Error in component VciSpi : " << name |
---|
[558] | 753 | << "The size of segment " << seg->name() |
---|
| 754 | << " cannot be smaller than 64 bytes" << std::endl; |
---|
[551] | 755 | exit(1); |
---|
| 756 | } |
---|
[558] | 757 | std::cout << " => segment " << seg->name() |
---|
| 758 | << " / base = " << std::hex << seg->baseAddress() |
---|
| 759 | << " / size = " << seg->size() << std::endl; |
---|
[551] | 760 | } |
---|
| 761 | |
---|
| 762 | if( nbsegs == 0 ) |
---|
| 763 | { |
---|
| 764 | std::cout << "Error in component VciSpi : " << name |
---|
[558] | 765 | << " No segment allocated" << std::endl; |
---|
[551] | 766 | exit(1); |
---|
| 767 | } |
---|
| 768 | |
---|
| 769 | if( (burst_size != 8 ) && |
---|
| 770 | (burst_size != 16) && |
---|
| 771 | (burst_size != 32) && |
---|
| 772 | (burst_size != 64) ) |
---|
| 773 | { |
---|
| 774 | std::cout << "Error in component VciSpi : " << name |
---|
[558] | 775 | << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl; |
---|
[551] | 776 | exit(1); |
---|
| 777 | } |
---|
| 778 | |
---|
| 779 | if ( (vci_param::B != 4) and (vci_param::B != 8) ) |
---|
| 780 | { |
---|
[558] | 781 | std::cout << "Error in component VciSpi : " << name |
---|
| 782 | << " The VCI data fields must have 32 bits or 64 bits" << std::endl; |
---|
[551] | 783 | exit(1); |
---|
| 784 | } |
---|
| 785 | |
---|
| 786 | } // end constructor |
---|
| 787 | |
---|
| 788 | tmpl(/**/)::~VciSpi() |
---|
| 789 | { |
---|
| 790 | } |
---|
| 791 | |
---|
| 792 | |
---|
| 793 | ////////////////////////// |
---|
| 794 | tmpl(void)::print_trace() |
---|
| 795 | { |
---|
| 796 | const char* initiator_str[] = |
---|
| 797 | { |
---|
| 798 | "M_IDLE", |
---|
| 799 | |
---|
[579] | 800 | "M_READ_WAIT", |
---|
[551] | 801 | "M_READ_CMD", |
---|
| 802 | "M_READ_RSP", |
---|
[595] | 803 | "M_INTR", |
---|
[551] | 804 | |
---|
[579] | 805 | "M_WRITE_WAIT", |
---|
[551] | 806 | "M_WRITE_CMD", |
---|
| 807 | "M_WRITE_RSP", |
---|
[579] | 808 | "M_WRITE_END", |
---|
[551] | 809 | }; |
---|
| 810 | const char* target_str[] = |
---|
[558] | 811 | { |
---|
[551] | 812 | "T_IDLE", |
---|
[558] | 813 | "T_RSP_READ", |
---|
| 814 | "T_RSP_WRITE", |
---|
| 815 | "T_ERROR_READ", |
---|
| 816 | "T_ERROR_WRITE", |
---|
[551] | 817 | }; |
---|
| 818 | const char* spi_str[] = |
---|
[558] | 819 | { |
---|
[551] | 820 | "S_IDLE", |
---|
[579] | 821 | "S_DMA_RECEIVE", |
---|
| 822 | "S_DMA_SEND_START", |
---|
| 823 | "S_DMA_SEND", |
---|
| 824 | "S_DMA_SEND_END", |
---|
[551] | 825 | "S_XMIT", |
---|
| 826 | }; |
---|
| 827 | |
---|
| 828 | std::cout << name() << " _TGT : " << target_str[r_target_fsm.read()] |
---|
| 829 | << std::endl; |
---|
| 830 | std::cout << name() << " _SPI : " << spi_str[r_spi_fsm.read()] |
---|
[565] | 831 | << " clk_counter " << r_spi_clk_counter.read() |
---|
| 832 | << " r_spi_bit_count " << r_spi_bit_count.read() |
---|
[579] | 833 | << " r_spi_bsy " << (int)r_spi_bsy.read() << std::endl; |
---|
[551] | 834 | std::cout << name() << " _SPI : " |
---|
| 835 | << " r_spi_clk " << r_spi_clk.read() |
---|
| 836 | << " cpol " << r_ctrl_cpol.read() |
---|
| 837 | << " cpha " << r_ctrl_cpha.read() |
---|
| 838 | << " r_spi_clk_ignore " << r_spi_clk_ignore.read() |
---|
| 839 | << " r_txrx 0x" << std::hex |
---|
| 840 | << r_txrx[1].read() << " " << r_txrx[0].read() |
---|
[579] | 841 | |
---|
[551] | 842 | << std::endl; |
---|
| 843 | std::cout << name() << " _INI : " << initiator_str[r_initiator_fsm.read()] |
---|
[558] | 844 | << " buf = " << std::hex << r_buf_address.read() |
---|
[579] | 845 | << " burst = " << r_burst_word.read() |
---|
| 846 | << " count = " << r_dma_count.read() |
---|
| 847 | << " spi_count = " << r_spi_word_count.read() |
---|
| 848 | <<std::endl; |
---|
[551] | 849 | } |
---|
| 850 | |
---|
| 851 | }} // end namespace |
---|
| 852 | |
---|
| 853 | // Local Variables: |
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| 854 | // tab-width: 4 |
---|
| 855 | // c-basic-offset: 4 |
---|
| 856 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 857 | // indent-tabs-mode: nil |
---|
| 858 | // End: |
---|
| 859 | |
---|
| 860 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
| 861 | |
---|