[77] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_traffic_generator.cpp |
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| 3 | * Date : 26/08/2010 |
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| 4 | * Copyright : UPMC / LIP6 |
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| 5 | * Authors : Christophe Choichillon |
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| 6 | * |
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| 7 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 8 | * |
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| 9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 10 | * |
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| 11 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 12 | * under the terms of the GNU Lesser General Public License as published |
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| 13 | * by the Free Software Foundation; version 2.1 of the License. |
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| 14 | * |
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| 15 | * SoCLib is distributed in the hope that it will be useful, but |
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| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | * Lesser General Public License for more details. |
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| 19 | * |
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| 20 | * You should have received a copy of the GNU Lesser General Public |
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| 21 | * License along with SoCLib; if not, write to the Free Software |
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| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 23 | * 02110-1301 USA |
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| 24 | * |
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| 25 | * SOCLIB_LGPL_HEADER_END |
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| 26 | * |
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| 27 | * Maintainers: christophe.choichillon@lip6.fr |
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| 28 | */ |
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| 29 | |
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[78] | 30 | #include "../include/vci_synthetic_initiator.h" |
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[77] | 31 | |
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| 32 | |
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| 33 | |
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| 34 | namespace soclib { namespace caba { |
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| 35 | |
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| 36 | |
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[78] | 37 | #define tmpl(x) template<typename vci_param> x VciSyntheticInitiator<vci_param> |
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[77] | 38 | |
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[78] | 39 | //using soclib::common::uint32_log2; |
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| 40 | |
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[77] | 41 | //////////////////////////////// |
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| 42 | // Constructor |
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| 43 | //////////////////////////////// |
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| 44 | |
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[78] | 45 | tmpl(/**/)::VciSyntheticInitiator( |
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[77] | 46 | sc_module_name name, |
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[78] | 47 | size_t length, // Packet length (flit numbers) |
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| 48 | float rho, // Packets ratio on the network |
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| 49 | size_t depth, // Fifo depth |
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| 50 | size_t x, // |
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| 51 | size_t y, // |
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| 52 | size_t xmesh, |
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| 53 | size_t ymesh, |
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| 54 | size_t bc_period, // Broadcast period, if no broadcast => 0 |
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| 55 | size_t xmin, |
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| 56 | size_t xmax, |
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| 57 | size_t ymin, |
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| 58 | size_t ymax |
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| 59 | ) |
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[77] | 60 | |
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| 61 | : soclib::caba::BaseModule(name), |
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| 62 | |
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| 63 | p_clk("clk"), |
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| 64 | p_resetn("resetn"), |
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| 65 | p_vci("vci_ini"), |
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| 66 | |
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| 67 | m_srcid_ini( mtc.indexForId(vci_ini_index) ), |
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| 68 | // FIFOs |
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[78] | 69 | m_date_fifo("m_date_fifo", depth), |
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[77] | 70 | |
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| 71 | r_tgt_cmd_fsm("r_tgt_cmd_fsm"), |
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| 72 | { |
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| 73 | |
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| 74 | // Memory cache allocation & initialisation |
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| 75 | m_cache_data = new data_t**[nways]; |
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| 76 | for ( size_t i=0 ; i<nways ; ++i ) { |
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| 77 | m_cache_data[i] = new data_t*[nsets]; |
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| 78 | } |
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| 79 | for ( size_t i=0; i<nways; ++i ) { |
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| 80 | for ( size_t j=0; j<nsets; ++j ) { |
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| 81 | m_cache_data[i][j] = new data_t[nwords]; |
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| 82 | for ( size_t k=0; k<nwords; k++){ |
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| 83 | m_cache_data[i][j][k]=0; |
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| 84 | } |
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| 85 | } |
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| 86 | } |
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| 87 | |
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| 88 | SC_METHOD(transition); |
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| 89 | dont_initialize(); |
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| 90 | sensitive << p_clk.pos(); |
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| 91 | |
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| 92 | SC_METHOD(genMoore); |
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| 93 | dont_initialize(); |
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| 94 | sensitive << p_clk.neg(); |
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| 95 | |
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| 96 | } // end constructor |
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| 97 | |
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| 98 | |
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| 99 | ///////////////////////////////// |
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[78] | 100 | tmpl(/**/)::~VciSyntheticInitiator() |
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[77] | 101 | ///////////////////////////////// |
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| 102 | { |
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| 103 | delete [] r_write_to_init_cmd_data; |
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| 104 | } |
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| 105 | |
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| 106 | ////////////////////////////////// |
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| 107 | tmpl(void)::transition() |
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| 108 | ////////////////////////////////// |
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| 109 | { |
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[78] | 110 | //using soclib::common::uint32_log2; |
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[77] | 111 | // RESET |
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| 112 | if ( ! p_resetn.read() ) { |
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| 113 | |
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| 114 | // Initializing FSMs |
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| 115 | r_tgt_cmd_fsm = TGT_CMD_IDLE; |
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| 116 | |
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| 117 | // initializing FIFOs and communication Buffers |
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| 118 | |
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[78] | 119 | m_date_fifo.init(); |
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[77] | 120 | |
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| 121 | r_read_to_tgt_rsp_req = false; |
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| 122 | r_read_to_xram_cmd_req = false; |
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| 123 | |
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| 124 | r_write_to_tgt_rsp_req = false; |
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| 125 | r_write_to_xram_cmd_req = false; |
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| 126 | r_write_to_init_cmd_req = false; |
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| 127 | |
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| 128 | |
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| 129 | // Activity counters |
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| 130 | m_cpt_cycles = 0; |
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| 131 | |
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| 132 | return; |
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| 133 | } |
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| 134 | |
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| 135 | bool cmd_read_fifo_put = false; |
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| 136 | bool cmd_read_fifo_get = false; |
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| 137 | |
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[78] | 138 | switch ( r_vci_fsm.read() ) { |
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[77] | 139 | |
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| 140 | ////////////////// |
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[78] | 141 | case VCI_IDLE: |
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[77] | 142 | { |
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| 143 | break; |
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| 144 | } |
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| 145 | ////////////////// |
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[78] | 146 | case VCI_SINGLE_SEND: |
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[77] | 147 | { |
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| 148 | break; |
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| 149 | } |
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| 150 | ////////////////////// |
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[78] | 151 | case VCI_SINGLE_RECEIVE: |
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[77] | 152 | { |
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| 153 | break; |
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| 154 | } |
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| 155 | /////////////////// |
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[78] | 156 | case VCI_BC_SEND: |
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[77] | 157 | { |
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| 158 | break; |
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| 159 | } |
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| 160 | //////////////////// |
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[78] | 161 | case VCI_BC_RECEIVE: |
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[77] | 162 | { |
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| 163 | break; |
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| 164 | } |
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[78] | 165 | } // end switch vci_fsm |
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[77] | 166 | |
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| 167 | |
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| 168 | if ( cmd_cleanup_fifo_put ) { |
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| 169 | if ( cmd_cleanup_fifo_get ) { |
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| 170 | m_cmd_cleanup_srcid_fifo.put_and_get(p_vci_tgt.srcid.read()); |
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| 171 | m_cmd_cleanup_trdid_fifo.put_and_get(p_vci_tgt.trdid.read()); |
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| 172 | m_cmd_cleanup_pktid_fifo.put_and_get(p_vci_tgt.pktid.read()); |
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| 173 | m_cmd_cleanup_nline_fifo.put_and_get(p_vci_tgt.wdata.read()); |
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| 174 | } else { |
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| 175 | m_cmd_cleanup_srcid_fifo.simple_put(p_vci_tgt.srcid.read()); |
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| 176 | m_cmd_cleanup_trdid_fifo.simple_put(p_vci_tgt.trdid.read()); |
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| 177 | m_cmd_cleanup_pktid_fifo.simple_put(p_vci_tgt.pktid.read()); |
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| 178 | m_cmd_cleanup_nline_fifo.simple_put(p_vci_tgt.wdata.read()); |
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| 179 | } |
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| 180 | } else { |
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| 181 | if ( cmd_cleanup_fifo_get ) { |
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| 182 | m_cmd_cleanup_srcid_fifo.simple_get(); |
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| 183 | m_cmd_cleanup_trdid_fifo.simple_get(); |
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| 184 | m_cmd_cleanup_pktid_fifo.simple_get(); |
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| 185 | m_cmd_cleanup_nline_fifo.simple_get(); |
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| 186 | } |
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| 187 | } |
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| 188 | |
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| 189 | m_cpt_cycles++; |
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| 190 | |
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| 191 | } // end transition() |
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| 192 | |
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| 193 | ///////////////////////////// |
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| 194 | tmpl(void)::genMoore() |
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| 195 | ///////////////////////////// |
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| 196 | { |
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| 197 | //////////////////////////////////////////////////////////// |
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| 198 | // Command signals on the p_vci_ixr port |
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| 199 | //////////////////////////////////////////////////////////// |
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| 200 | |
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| 201 | |
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[78] | 202 | switch ( r_vci_fsm.read() ) { |
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[77] | 203 | |
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[78] | 204 | ////////////////// |
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| 205 | case VCI_IDLE: |
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| 206 | { |
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| 207 | break; |
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| 208 | } |
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| 209 | ////////////////// |
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| 210 | case VCI_SINGLE_SEND: |
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| 211 | { |
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| 212 | break; |
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| 213 | } |
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| 214 | ////////////////////// |
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| 215 | case VCI_SINGLE_RECEIVE: |
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| 216 | { |
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| 217 | break; |
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| 218 | } |
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| 219 | /////////////////// |
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| 220 | case VCI_BC_SEND: |
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| 221 | { |
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| 222 | break; |
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| 223 | } |
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| 224 | //////////////////// |
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| 225 | case VCI_BC_RECEIVE: |
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| 226 | { |
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| 227 | break; |
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| 228 | } |
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| 229 | } // end switch vci_fsm |
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[77] | 230 | |
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| 231 | } // end genMoore() |
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| 232 | |
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| 233 | }} // end name space |
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