[148] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_vdspin_target_wrapper.cpp |
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| 3 | * Copyright (c) UPMC, Lip6 |
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| 4 | * Author : Alain Greiner |
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| 5 | * |
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| 6 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 7 | * |
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| 8 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 9 | * |
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| 10 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU Lesser General Public License as published |
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| 12 | * by the Free Software Foundation; version 2.1 of the License. |
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| 13 | * |
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| 14 | * SoCLib is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * Lesser General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU Lesser General Public |
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| 20 | * License along with SoCLib; if not, write to the Free Software |
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| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 22 | * 02110-1301 USA |
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| 23 | * |
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| 24 | * SOCLIB_LGPL_HEADER_END |
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| 25 | */ |
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| 26 | |
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| 27 | #include "../include/vci_vdspin_target_wrapper.h" |
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| 28 | |
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| 29 | namespace soclib { namespace caba { |
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| 30 | |
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| 31 | #define tmpl(x) template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> x VciVdspinTargetWrapper<vci_param, dspin_cmd_width, dspin_rsp_width> |
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| 32 | |
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| 33 | //////////////////////////////////////////////////////////://////////////////////////////// |
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| 34 | tmpl(/**/)::VciVdspinTargetWrapper(sc_module_name name, |
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| 35 | size_t cmd_fifo_depth, |
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| 36 | size_t rsp_fifo_depth) |
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| 37 | : soclib::caba::BaseModule(name), |
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| 38 | p_clk("p_clk"), |
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| 39 | p_resetn("p_resetn"), |
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| 40 | p_dspin_out("p_dspin_out"), |
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| 41 | p_dspin_in("p_dspin_in"), |
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| 42 | p_vci("p_vci"), |
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| 43 | r_cmd_fsm("r_cmd_fsm"), |
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| 44 | r_rsp_fsm("r_rsp_fsm"), |
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| 45 | r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth), |
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| 46 | r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth) |
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| 47 | { |
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| 48 | SC_METHOD (transition); |
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| 49 | dont_initialize(); |
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| 50 | sensitive << p_clk.pos(); |
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| 51 | SC_METHOD (genMoore); |
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| 52 | dont_initialize(); |
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| 53 | sensitive << p_clk.neg(); |
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| 54 | |
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| 55 | assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits"); |
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| 56 | assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits"); |
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| 57 | assert( (vci_param::N <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); |
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| 58 | assert( (vci_param::B == 4) && "The VCI DATA filds must have 32 bits"); |
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| 59 | assert( (vci_param::K == 8) && "The VCI PLEN field cannot have more than 8 bits"); |
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| 60 | assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 8 bits"); |
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| 61 | assert( (vci_param::T <= 8) && "The VCI TRDID field cannot have more than 8 bits"); |
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| 62 | assert( (vci_param::E == 2) && "The VCI RERROR field cannot have more than 2 bits"); |
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| 63 | |
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| 64 | } // end constructor |
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| 65 | |
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| 66 | ///////////////////////// |
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| 67 | tmpl(void)::transition() |
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| 68 | { |
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| 69 | sc_uint<dspin_cmd_width> cmd_fifo_data; |
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| 70 | bool cmd_fifo_write; |
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| 71 | bool cmd_fifo_read; |
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| 72 | |
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| 73 | sc_uint<dspin_rsp_width> rsp_fifo_data; |
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| 74 | bool rsp_fifo_write; |
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| 75 | bool rsp_fifo_read; |
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| 76 | |
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| 77 | if (p_resetn == false) |
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| 78 | { |
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| 79 | r_fifo_cmd.init(); |
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| 80 | r_fifo_rsp.init(); |
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| 81 | r_cmd_fsm = CMD_IDLE; |
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| 82 | r_rsp_fsm = RSP_IDLE; |
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| 83 | return; |
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| 84 | } // end reset |
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| 85 | |
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| 86 | ///////////////////////////////////////////////////////////// |
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| 87 | // VCI response packet to DSPIN response packet. |
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| 88 | // The VCI packet is analysed, translated, |
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| 89 | // and the DSPIN packet is stored in the fifo_rsp |
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| 90 | ///////////////////////////////////////////////////////////// |
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| 91 | // - A single flit VCI write response packet is translated |
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| 92 | // to a single flit DSPIN response. |
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| 93 | // - A N flits VCI read response packet is translated |
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| 94 | // to a N+1 flits DSPIN response |
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| 95 | // In the RSP_IDLE state, the first DSPIN flit is written |
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| 96 | // in fifo_rsp , but no VCI flit is consumed. The VCI flits |
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| 97 | // are consumed in the RSP_READ or RSP_WRITE states. |
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| 98 | ////////////////////////////////////////////////////////////// |
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| 99 | |
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| 100 | // rsp_fifo_read |
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| 101 | rsp_fifo_read = p_dspin_out.read.read(); |
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| 102 | |
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| 103 | // r_rsp_fsm, rsp_fifo_write and rsp_fifo_data |
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| 104 | switch(r_rsp_fsm) { |
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| 105 | case RSP_IDLE: // write first DSPIN flit into rsp_fifo |
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| 106 | { |
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| 107 | if( p_vci.rspval && r_fifo_rsp.wok() ) |
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| 108 | { |
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| 109 | bool is_read = ( (p_vci.rerror.read() & 0x2) == 0); |
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| 110 | |
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| 111 | rsp_fifo_write = true; |
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| 112 | rsp_fifo_data = (((sc_uint<dspin_rsp_width>)p_vci.rsrcid.read()) << 18) | |
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| 113 | (((sc_uint<dspin_rsp_width>)p_vci.rerror.read()) << 16) | |
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| 114 | (((sc_uint<dspin_rsp_width>)p_vci.rtrdid.read()) << 8); |
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| 115 | if ( is_read ) |
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| 116 | { |
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| 117 | r_rsp_fsm = RSP_READ; |
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| 118 | } |
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| 119 | else |
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| 120 | { |
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| 121 | rsp_fifo_data = rsp_fifo_data | 0x100000000; |
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| 122 | r_rsp_fsm = RSP_WRITE; |
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| 123 | } |
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| 124 | } |
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| 125 | else |
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| 126 | { |
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| 127 | rsp_fifo_write = false; |
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| 128 | } |
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| 129 | break; |
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| 130 | } |
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| 131 | case RSP_READ: // write DSPIN data flit in case of read |
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| 132 | { |
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| 133 | if( p_vci.rspval && r_fifo_rsp.wok() ) |
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| 134 | { |
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| 135 | rsp_fifo_write = true; |
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| 136 | rsp_fifo_data = ((sc_uint<dspin_rsp_width>)p_vci.rdata.read()); |
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| 137 | if ( p_vci.reop ) |
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| 138 | { |
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| 139 | rsp_fifo_data = rsp_fifo_data | 0x100000000; |
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| 140 | r_rsp_fsm = RSP_IDLE; |
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| 141 | } |
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| 142 | } |
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| 143 | else |
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| 144 | { |
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| 145 | rsp_fifo_write = false; |
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| 146 | } |
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| 147 | break; |
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| 148 | } |
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| 149 | case RSP_WRITE: |
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| 150 | { |
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| 151 | rsp_fifo_write = false; |
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| 152 | if ( r_fifo_rsp.wok() ) r_rsp_fsm = RSP_IDLE; |
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| 153 | break; |
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| 154 | } |
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| 155 | } // end switch r_cmd_fsm |
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| 156 | |
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| 157 | // fifo_rsp |
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| 158 | if((rsp_fifo_write == true) && (rsp_fifo_read == false)) { r_fifo_rsp.simple_put(rsp_fifo_data); } |
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| 159 | if((rsp_fifo_write == true) && (rsp_fifo_read == true)) { r_fifo_rsp.put_and_get(rsp_fifo_data); } |
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| 160 | if((rsp_fifo_write == false) && (rsp_fifo_read == true)) { r_fifo_rsp.simple_get(); } |
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| 161 | |
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| 162 | ////////////////////////////////////////////////////////////// |
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| 163 | // DSPIN command packet to VCI command packet |
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| 164 | // The DSPIN packet is stored in the fifo_rsp |
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| 165 | // The FIFO output is analysed and translated to a VCI packet |
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| 166 | ////////////////////////////////////////////////////////////// |
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| 167 | // - A 2 flits DSPIN broadcast command is translated |
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| 168 | // to a 1 flit VCI broadcast command. |
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| 169 | // - A 2 flits DSPIN read command is translated |
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| 170 | // to a 1 flit VCI read command. |
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| 171 | // - A N+2 flits DSPIN write command is translated |
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| 172 | // to a N flits VCI write command. |
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| 173 | // The VCI flits are sent in the CMD_RW, CMD_WDATA |
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| 174 | // & CMD_BROADCAST states. |
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| 175 | // The r_cmd_buf0 et r_cmd_buf1 buffers are used to store |
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| 176 | // the two first DSPIN flits (in case of write). |
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| 177 | ////////////////////////////////////////////////////////////// |
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| 178 | |
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| 179 | // cmd_fifo_write, cmd_fifo_data |
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| 180 | cmd_fifo_write = p_dspin_in.write.read(); |
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| 181 | cmd_fifo_data = p_dspin_in.data.read(); |
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| 182 | |
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| 183 | // r_cmd_fsm, cmd_fifo_read |
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| 184 | switch(r_cmd_fsm) { |
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| 185 | case CMD_IDLE: |
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| 186 | { |
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| 187 | if( r_fifo_cmd.rok() && p_vci.cmdack ) |
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| 188 | { |
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| 189 | bool is_broadcast = ( (r_fifo_cmd.read() & 0x1) == 0x1); |
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| 190 | |
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| 191 | cmd_fifo_read = true; |
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| 192 | r_cmd_buf0 = r_fifo_cmd.read(); |
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| 193 | if ( is_broadcast ) r_cmd_fsm = CMD_BROADCAST; |
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| 194 | else r_cmd_fsm = CMD_RW; |
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| 195 | } |
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| 196 | else |
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| 197 | { |
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| 198 | cmd_fifo_read = false; |
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| 199 | } |
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| 200 | break; |
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| 201 | } |
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| 202 | case CMD_BROADCAST: |
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| 203 | { |
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| 204 | if( r_fifo_cmd.rok() && p_vci.cmdack ) |
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| 205 | { |
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| 206 | cmd_fifo_read = true; |
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| 207 | r_cmd_fsm = CMD_IDLE; |
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| 208 | } |
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| 209 | else |
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| 210 | { |
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| 211 | cmd_fifo_read = false; |
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| 212 | } |
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| 213 | break; |
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| 214 | } |
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| 215 | case CMD_RW: |
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| 216 | { |
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| 217 | if( r_fifo_cmd.rok() && p_vci.cmdack ) |
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| 218 | { |
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| 219 | cmd_fifo_read = true; |
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| 220 | if ( (r_fifo_cmd.read() & 0x8000000000) ) // read command |
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| 221 | { |
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| 222 | r_cmd_fsm = CMD_IDLE; |
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| 223 | } |
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| 224 | else // write command |
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| 225 | { |
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| 226 | r_cmd_fsm = CMD_WDATA; |
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| 227 | r_cmd_buf1 = r_fifo_cmd.read(); |
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| 228 | } |
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| 229 | } |
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| 230 | else |
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| 231 | { |
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| 232 | cmd_fifo_read = false; |
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| 233 | } |
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| 234 | break; |
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| 235 | } |
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| 236 | case CMD_WDATA: |
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| 237 | { |
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| 238 | if( r_fifo_cmd.rok() && p_vci.cmdack ) |
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| 239 | { |
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| 240 | cmd_fifo_read = true; |
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| 241 | if ( (r_fifo_cmd.read() & 0x8000000000) ) r_cmd_fsm = CMD_IDLE; |
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| 242 | } |
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| 243 | else |
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| 244 | { |
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| 245 | cmd_fifo_read = false; |
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| 246 | } |
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| 247 | break; |
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| 248 | } |
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| 249 | } // end switch r_cmd_fsm |
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| 250 | |
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| 251 | // fifo_cmd |
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| 252 | if((cmd_fifo_write == true) && (cmd_fifo_read == false)) { r_fifo_cmd.simple_put(cmd_fifo_data); } |
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| 253 | if((cmd_fifo_write == true) && (cmd_fifo_read == true)) { r_fifo_cmd.put_and_get(cmd_fifo_data); } |
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| 254 | if((cmd_fifo_write == false) && (cmd_fifo_read == true)) { r_fifo_cmd.simple_get(); } |
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| 255 | |
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| 256 | }; // end transition |
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| 257 | |
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| 258 | ////////////////////// |
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| 259 | tmpl(void)::genMoore() |
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| 260 | { |
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| 261 | // VCI RSP interface |
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| 262 | if ( r_rsp_fsm.read() == RSP_IDLE ) p_vci.rspack = false; |
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| 263 | else p_vci.rspack = r_fifo_rsp.wok(); |
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| 264 | |
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| 265 | // VCI CMD interface |
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| 266 | if ( r_cmd_fsm.read() == CMD_IDLE ) |
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| 267 | { |
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| 268 | p_vci.cmdval = false; |
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| 269 | } |
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| 270 | else if ( r_cmd_fsm.read() == CMD_BROADCAST ) // VCI CMD broadcast |
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| 271 | { |
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| 272 | if ( r_fifo_cmd.rok() ) |
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| 273 | { |
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| 274 | p_vci.cmdval = true; |
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| 275 | p_vci.address = (sc_uint<vci_param::N>)((r_cmd_buf0.read() & 0x7FFFF80000) << 1) | 0x3; |
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| 276 | p_vci.cmd = vci_param::CMD_WRITE; |
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| 277 | p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFF); |
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| 278 | p_vci.be = (sc_uint<vci_param::B>)((r_fifo_cmd.read() & 0x0F00000000) >> 32); |
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| 279 | p_vci.srcid = (sc_uint<vci_param::S>)((r_cmd_buf0.read() & 0x000007FFE0) >> 5); |
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| 280 | p_vci.trdid = (sc_uint<vci_param::T>)((r_cmd_buf0.read() & 0x000000001E) >> 1); |
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| 281 | p_vci.pktid = 0; |
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| 282 | p_vci.plen = vci_param::B; |
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| 283 | p_vci.eop = true; |
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| 284 | } |
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| 285 | else |
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| 286 | { |
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| 287 | p_vci.cmdval = false; |
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| 288 | } |
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| 289 | } |
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| 290 | else if ( r_cmd_fsm.read() == CMD_RW ) // VCI read if eop |
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| 291 | { |
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| 292 | if ( r_fifo_cmd.rok() & ((r_fifo_cmd.read() & 0x8000000000) == 0x8000000000) ) |
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| 293 | { |
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| 294 | p_vci.cmdval = true; |
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| 295 | p_vci.address = (sc_uint<vci_param::N>)((r_cmd_buf0.read() & 0x7FFFFFFFFE) << 1); |
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| 296 | p_vci.cmd = (sc_uint<2>)((r_fifo_cmd.read() & 0x0001800000) >> 23); |
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| 297 | p_vci.wdata = 0; |
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| 298 | p_vci.be = (sc_uint<vci_param::B>)((r_fifo_cmd.read() & 0x000000001E) >> 1); |
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| 299 | p_vci.srcid = (sc_uint<vci_param::S>)((r_fifo_cmd.read() & 0x7FFE000000) >> 25); |
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| 300 | p_vci.trdid = (sc_uint<vci_param::T>)((r_fifo_cmd.read() & 0x0000001FE0) >> 5); |
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| 301 | p_vci.pktid = 0; |
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| 302 | p_vci.plen = (sc_uint<vci_param::K>)((r_fifo_cmd.read() & 0x00001FE000) >> 13); |
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| 303 | p_vci.eop = true; |
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| 304 | } |
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| 305 | else |
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| 306 | { |
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| 307 | p_vci.cmdval = false; |
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| 308 | } |
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| 309 | } |
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| 310 | else if ( r_cmd_fsm.read() == CMD_WDATA ) // VCI write |
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| 311 | { |
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| 312 | if ( r_fifo_cmd.rok() ) |
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| 313 | { |
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| 314 | p_vci.cmdval = true; |
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| 315 | p_vci.address = (sc_uint<vci_param::N>)((r_cmd_buf0.read() & 0x7FFFFFFFFE) << 1); |
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| 316 | p_vci.cmd = (sc_uint<2>)((r_cmd_buf1.read() & 0x0001800000) >> 23); |
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| 317 | p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFF); |
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| 318 | p_vci.be = (sc_uint<vci_param::B>)((r_fifo_cmd.read() & 0x0F00000000) >> 32); |
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| 319 | p_vci.srcid = (sc_uint<vci_param::S>)((r_cmd_buf1.read() & 0x7FFE000000) >> 25); |
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| 320 | p_vci.trdid = (sc_uint<vci_param::T>)((r_cmd_buf1.read() & 0x0000001FE0) >> 5); |
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| 321 | p_vci.pktid = 0; |
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| 322 | p_vci.plen = (sc_uint<vci_param::K>)((r_cmd_buf1.read() & 0x00001FE000) >> 13); |
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| 323 | p_vci.eop = ((r_fifo_cmd.read() & 0x8000000000) == 0x8000000000); |
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| 324 | } |
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| 325 | else |
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| 326 | { |
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| 327 | p_vci.cmdval = false; |
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| 328 | } |
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| 329 | } |
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| 330 | |
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| 331 | // DSPIN_OUT interface |
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| 332 | p_dspin_out.write = r_fifo_rsp.rok(); |
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| 333 | p_dspin_out.data = r_fifo_rsp.read(); |
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| 334 | |
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| 335 | // DSPIN_IN interface |
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| 336 | p_dspin_in.read = r_fifo_cmd.wok(); |
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| 337 | |
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| 338 | }; // end genMoore |
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| 339 | |
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| 340 | }} // end namespace |
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| 341 | |
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| 342 | // Local Variables: |
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| 343 | // tab-width: 4 |
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| 344 | // c-basic-offset: 4 |
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| 345 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 346 | // indent-tabs-mode: nil |
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| 347 | // End: |
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| 348 | |
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| 349 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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