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tsar_xbar_cluster.cpp @ 1040

Last change on this file since 1040 was 1040, checked in by bouyer, 8 years ago
Add a platform using the new dspin 3d router. Only giet-vm is suported at this time. The software is not aware of the 3d layout; the software's y dimention is subdivided in hardware y and z.
File size: 34.7 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_xbar_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : march 2011
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// This file define a TSAR cluster architecture with virtual memory:
9	// - It uses two virtual_dspin_router as distributed global interconnect
10	// - It uses four dspin_local_crossbar as local interconnect
11	// - It uses the vci_cc_vcache_wrapper
12	// - It uses the vci_mem_cache
13	// - It contains a private RAM with a variable latency to emulate the L3 cache
14	// - It can contains 1, 2 or 4 processors
15	// - Each processor has a private dma channel (vci_multi_dma)
16	// - It uses the vci_xicu interrupt controller
17	// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
18	// - The Multi-TTY component controls up to 15 terminals.
19	// - Each Multi-DMA component controls up to 8 DMA channels.
20	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
21	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
22	// - The BDEV IRQ is connected to IRQ_IN[31]
23	//////////////////////////////////////////////////////////////////////////////////
24
25	#include <systemc>
26	#include <sys/time.h>
27	#include <iostream>
28	#include <sstream>
29	#include <cstdlib>
30	#include <cstdarg>
31	#include <stdint.h>
32	#include "tsar_xbar_cluster.h"
33
34	namespace soclib {
35	namespace caba {
36
37	////////////////////////////////////////////////////////////////////////////////////
38	template<size_t dspin_cmd_width,
39	size_t dspin_rsp_width,
40	typename vci_param_int,
41	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
42	dspin_rsp_width,
43	vci_param_int,
44	vci_param_ext>::TsarXbarCluster(
45	////////////////////////////////////////////////////////////////////////////////////
46	sc_module_name insname,
47	size_t nb_procs,
48	size_t nb_ttys,
49	size_t nb_dmas,
50	size_t x_id,
51	size_t y_id,
52	size_t z_id,
53	size_t cluster_id,
54	size_t elevator_x,
55	size_t elevator_y,
56	const soclib::common::MappingTable &mtd,
57	const soclib::common::MappingTable &mtx,
58	size_t x_width,
59	size_t y_width,
60	size_t z_width,
61	size_t l_width,
62	size_t p_width,
63	size_t tgtid_memc,
64	size_t tgtid_xicu,
65	size_t tgtid_mdma,
66	size_t tgtid_fbuf,
67	size_t tgtid_mtty,
68	size_t tgtid_brom,
69	size_t tgtid_mnic,
70	size_t tgtid_chbuf,
71	size_t tgtid_bdev,
72	size_t tgtid_simh,
73	size_t memc_ways,
74	size_t memc_sets,
75	size_t l1_i_ways,
76	size_t l1_i_sets,
77	size_t l1_d_ways,
78	size_t l1_d_sets,
79	size_t irq_per_processor,
80	size_t xram_latency,
81	bool io,
82	size_t xfb,
83	size_t yfb,
84	char* disk_name,
85	size_t block_size,
86	size_t nic_channels,
87	char* nic_rx_name,
88	char* nic_tx_name,
89	uint32_t nic_timeout,
90	size_t chbufdma_channels,
91	const Loader & loader,
92	uint32_t frozen_cycles,
93	uint32_t debug_start_cycle,
94	bool memc_debug_ok,
95	bool proc_debug_ok)
96	: soclib::caba::BaseModule(insname),
97	p_clk("clk"),
98	p_resetn("resetn") {
99
100	n_procs = nb_procs;
101
102	/////////////////////////////////////////////////////////////////////////////
103	// Vectors of ports definition and allocation
104	/////////////////////////////////////////////////////////////////////////////
105
106	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cmd_in", 6);
107	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cmd_out", 6);
108
109	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_rsp_in", 6);
110	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_rsp_out", 6);
111
112	p_m2p_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_m2p_in", 6);
113	p_m2p_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_m2p_out", 6);
114
115	p_p2m_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_p2m_in", 6);
116	p_p2m_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_p2m_out", 6);
117
118	p_cla_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cla_in", 6);
119	p_cla_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cla_out", 6);
120
121	/////////////////////////////////////////////////////////////////////////////
122	// Components definition
123	/////////////////////////////////////////////////////////////////////////////
124
125	for (size_t p = 0; p < nb_procs; p++) {
126	std::ostringstream sproc;
127	sproc << "proc_" << x_id << "_" << y_id << "_" << z_id << "_" << p;
128	proc[p] = new VciCcVCacheWrapper<vci_param_int,
129	dspin_cmd_width,
130	dspin_rsp_width,
131	GdbServer<Mips32ElIss> >(
132	sproc.str().c_str(),
133	(cluster_id << p_width) + p, // GLOBAL PROC_ID
134	mtd, // Mapping Table
135	IntTab(cluster_id, p), // SRCID
136	(cluster_id << l_width) + p, // CC_GLOBAL_ID
137	8, // ITLB ways
138	8, // ITLB sets
139	8, // DTLB ways
140	8, // DTLB sets
141	l1_i_ways,l1_i_sets, 16, // ICACHE size
142	l1_d_ways,l1_d_sets, 16, // DCACHE size
143	4, // WBUF nlines
144	4, // WBUF nwords
145	x_width,
146	y_width + z_width,
147	frozen_cycles, // max frozen cycles
148	debug_start_cycle,
149	proc_debug_ok);
150
151	}
152
153	/////////////////////////////////////////////////////////////////////////////
154	std::ostringstream smemc;
155	smemc << "memc_" << x_id << "_" << y_id << "_" << z_id;
156	memc = new VciMemCache<vci_param_int,
157	vci_param_ext,
158	dspin_rsp_width,
159	dspin_cmd_width>(
160	smemc.str().c_str(),
161	mtd, // Mapping Table direct space
162	mtx, // Mapping Table external space
163	IntTab(cluster_id), // SRCID external space
164	IntTab(cluster_id, tgtid_memc), // TGTID direct space
165	x_width, // Number of x bits in platform
166	y_width + z_width, // Number of y bits in platform
167	memc_ways, memc_sets, 16, // CACHE SIZE
168	3, // MAX NUMBER OF COPIES
169	4096, // HEAP SIZE
170	8, // TRANSACTION TABLE DEPTH
171	8, // UPDATE TABLE DEPTH
172	8, // INVALIDATE TABLE DEPTH
173	debug_start_cycle,
174	memc_debug_ok);
175
176
177	/////////////////////////////////////////////////////////////////////////////
178	std::ostringstream sxram;
179	sxram << "xram_" << x_id << "_" << y_id << "_" << z_id;
180	xram = new VciSimpleRam<vci_param_ext>(
181	sxram.str().c_str(),
182	IntTab(cluster_id),
183	mtx,
184	loader,
185	xram_latency);
186
187	/////////////////////////////////////////////////////////////////////////////
188	std::ostringstream sxicu;
189	sxicu << "xicu_" << x_id << "_" << y_id << "_" << z_id;
190	xicu = new VciXicu<vci_param_int>(
191	sxicu.str().c_str(),
192	mtd, // mapping table
193	IntTab(cluster_id, tgtid_xicu), // TGTID_D
194	nb_procs, // number of timer IRQs
195	32, // number of hard IRQs
196	32, // number of soft IRQs
197	nb_procs * irq_per_processor); // number of output IRQs
198
199
200	/////////////////////////////////////////////////////////////////////////////
201	std::ostringstream smdma;
202	smdma << "mdma_" << x_id << "_" << y_id << "_" << z_id;
203	mdma = new VciMultiDma<vci_param_int>(
204	smdma.str().c_str(),
205	mtd,
206	IntTab(cluster_id, nb_procs), // SRCID
207	IntTab(cluster_id, tgtid_mdma), // TGTID
208	64, // burst size
209	nb_dmas); // number of IRQs
210
211
212	/////////////////////////////////////////////////////////////////////////////
213	size_t nb_direct_initiators = nb_procs + 1;
214	size_t nb_direct_targets = 3;
215	if (io) {
216	nb_direct_initiators = nb_procs + 3;
217	nb_direct_targets = 10;
218	}
219
220	std::ostringstream sxbar;
221	sxbar << "xbar_" << x_id << "_" << y_id << "_" << z_id;
222	xbar_d = new VciLocalCrossbar<vci_param_int>(
223	sxbar.str().c_str(),
224	mtd, // mapping table
225	//x_id, y_id, // cluster coordinates
226	cluster_id,
227	nb_direct_initiators, // number of local of sources
228	nb_direct_targets, // number of local dests
229	tgtid_memc); // Default target
230
231	////////////// vci_dspin wrappers
232	std::ostringstream swtxbar;
233	swtxbar << "wt_xbar_" << x_id << "_" << y_id << "_" << z_id;
234	wt_xbar_d = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
235	swtxbar.str().c_str(),
236	x_width + y_width + z_width + l_width);
237
238	std::ostringstream swixbar;
239	swixbar << "wi_xbar_" << x_id << "_" << y_id << "_" << z_id;
240	wi_xbar_d = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
241	swixbar.str().c_str(),
242	x_width + y_width + z_width + l_width );
243
244	/////////////////////////////////////////////////////////////////////////////
245	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
246	"xbar_m2p_c",
247	mtd, // mapping table
248	x_id, z_id + (y_id << z_width),// cluster coordinates
249	x_width, y_width + z_width, l_width,
250	1, // number of local sources
251	nb_procs, // number of local targets
252	2, 2, // fifo depths
253	true, // CMD
254	false, // don't use local routing table
255	true ); // broadcast
256
257	/////////////////////////////////////////////////////////////////////////////
258	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
259	"xbar_p2m_c",
260	mtd, // mapping table
261	x_id, z_id + (y_id << z_width),// cluster coordinates
262	x_width, y_width + z_width, 0, // l_width unused on p2m network
263	nb_procs, // number of local sources
264	1, // number of local dests
265	2, 2, // fifo depths
266	false, // RSP
267	false, // don't use local routing table
268	false ); // no broadcast
269
270	/////////////////////////////////////////////////////////////////////////////
271	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
272	"xbar_clack_c",
273	mtd, // mapping table
274	x_id, z_id + (y_id << z_width),// cluster coordinates
275	x_width, y_width + z_width, l_width,
276	1, // number of local sources
277	nb_procs, // number of local targets
278	1, 1, // fifo depths
279	true, // CMD
280	false, // don't use local routing table
281	false); // broadcast
282
283	/////////////////////////////////////////////////////////////////////////////
284	std::ostringstream s_router_cmd;
285	s_router_cmd << "router_cmd_" << x_id << "_" << y_id << "_" << z_id;
286	router_cmd = new DspinRouter3d<dspin_cmd_width>(
287	s_router_cmd.str().c_str(),
288	x_id,y_id,z_id, // coordinate in the mesh
289	x_width, y_width,z_width, // x & y fields width
290	elevator_x, elevator_y, // coordinate of the elevator
291	4,4); // input & output fifo depths
292
293	/////////////////////////////////////////////////////////////////////////////
294	std::ostringstream s_router_rsp;
295	s_router_rsp << "router_rsp_" << x_id << "_" << y_id << "_" << z_id;
296	router_rsp = new DspinRouter3d<dspin_rsp_width>(
297	s_router_rsp.str().c_str(),
298	x_id,y_id,z_id, // coordinates in mesh
299	x_width, y_width, z_width, // x & y fields width
300	elevator_x, elevator_y, // coordinate of the elevator
301	4,4); // input & output fifo depths
302
303	/////////////////////////////////////////////////////////////////////////////
304	std::ostringstream s_router_m2p;
305	s_router_m2p << "router_m2p_" << x_id << "_" << y_id << "_" << z_id;
306	router_m2p = new DspinRouter3d<dspin_cmd_width>(
307	s_router_m2p.str().c_str(),
308	x_id,y_id,z_id, // coordinate in the mesh
309	x_width, y_width, z_width, // x & y fields width
310	elevator_x, elevator_y, // coordinate of the elevator
311	4,4, // input & output fifo depths
312	true); // broadcast supported
313
314	/////////////////////////////////////////////////////////////////////////////
315	std::ostringstream s_router_p2m;
316	s_router_p2m << "router_p2m_" << x_id << "_" << y_id << "_" << z_id;
317	router_p2m = new DspinRouter3d<dspin_rsp_width>(
318	s_router_p2m.str().c_str(),
319	x_id,y_id,z_id, // coordinates in mesh
320	x_width, y_width, z_width, // x & y fields width
321	elevator_x, elevator_y, // coordinate of the elevator
322	4,4); // input & output fifo depths
323
324	/////////////////////////////////////////////////////////////////////////////
325	std::ostringstream s_router_cla;
326	s_router_cla << "router_cla_" << x_id << "_" << y_id << "_" << z_id;
327	router_cla = new DspinRouter3d<dspin_cmd_width>(
328	s_router_cla.str().c_str(),
329	x_id,y_id,z_id, // coordinate in the mesh
330	x_width, y_width, z_width, // x & y fields width
331	elevator_x, elevator_y, // coordinate of the elevator
332	4,4); // input & output fifo depths
333
334	// IO cluster components
335	if (io) {
336	/////////////////////////////////////////////
337	brom = new VciSimpleRom<vci_param_int>(
338	"brom",
339	IntTab(cluster_id, tgtid_brom),
340	mtd,
341	loader);
342
343	/////////////////////////////////////////////
344	fbuf = new VciFrameBuffer<vci_param_int>(
345	"fbuf",
346	IntTab(cluster_id, tgtid_fbuf),
347	mtd,
348	xfb, yfb);
349
350	/////////////////////////////////////////////
351	bdev = new VciBlockDeviceTsar<vci_param_int>(
352	"bdev",
353	mtd,
354	IntTab(cluster_id, nb_procs + 1),
355	IntTab(cluster_id, tgtid_bdev),
356	disk_name,
357	block_size,
358	64); // burst size
359
360	int mac = 0xBEEF0000;
361	mnic = new VciMultiNic<vci_param_int>(
362	"mnic",
363	IntTab(cluster_id, tgtid_mnic),
364	mtd,
365	nic_channels,
366	mac, // mac_4 address
367	0xBABE, // mac_2 address
368	1, // NIC_MODE_SYNTHESIS
369	12 ); // INTER_FRAME_GAP
370
371
372
373	/////////////////////////////////////////////
374	chbuf = new VciChbufDma<vci_param_int>(
375	"chbuf_dma",
376	mtd,
377	IntTab(cluster_id, nb_procs + 2),
378	IntTab(cluster_id, tgtid_chbuf),
379	64,
380	chbufdma_channels);
381
382	/////////////////////////////////////////////
383	std::vector<std::string> vect_names;
384	for (size_t tid = 0; tid < nb_ttys; tid++) {
385	std::ostringstream term_name;
386	term_name << "term" << tid;
387	vect_names.push_back(term_name.str().c_str());
388	}
389	mtty = new VciMultiTty<vci_param_int>(
390	"mtty",
391	IntTab(cluster_id, tgtid_mtty),
392	mtd,
393	vect_names);
394
395	simhelper = new VciSimhelper<vci_param_int>(
396	"sim_helper",
397	IntTab(cluster_id, tgtid_simh),
398	mtd);
399	}
400
401	////////////////////////////////////
402	// Connections are defined here
403	////////////////////////////////////
404
405	//////////////////////// ROUTERS
406	router_cmd->p_clk (this->p_clk);
407	router_cmd->p_resetn (this->p_resetn);
408	router_rsp->p_clk (this->p_clk);
409	router_rsp->p_resetn (this->p_resetn);
410	router_m2p->p_clk (this->p_clk);
411	router_m2p->p_resetn (this->p_resetn);
412	router_p2m->p_clk (this->p_clk);
413	router_p2m->p_resetn (this->p_resetn);
414	router_cla->p_clk (this->p_clk);
415	router_cla->p_resetn (this->p_resetn);
416
417	// loop on N/S/E/W/U/D ports
418	const size_t nports = (x_id == elevator_x && y_id == elevator_y) ? 6 : 6;
419	for (size_t i = 0; i < nports; i++) {
420	std::cout << "connect router port " << i << " / " << nports <<std::endl;
421	router_cmd->p_out[i+1] (this->p_cmd_out[i]);
422	router_cmd->p_in[i+1] (this->p_cmd_in[i]);
423
424	router_rsp->p_out[i+1] (this->p_rsp_out[i]);
425	router_rsp->p_in[i+1] (this->p_rsp_in[i]);
426
427	router_m2p->p_out[i+1] (this->p_m2p_out[i]);
428	router_m2p->p_in[i+1] (this->p_m2p_in[i]);
429
430	router_p2m->p_out[i+1] (this->p_p2m_out[i]);
431	router_p2m->p_in[i+1] (this->p_p2m_in[i]);
432
433	router_cla->p_out[i+1] (this->p_cla_out[i]);
434	router_cla->p_in[i+1] (this->p_cla_in[i]);
435	}
436
437	router_cmd->p_out[0] (signal_dspin_cmd_g2l_d);
438	router_cmd->p_in[0] (signal_dspin_cmd_l2g_d);
439
440	router_rsp->p_out[0] (signal_dspin_rsp_g2l_d);
441	router_rsp->p_in[0] (signal_dspin_rsp_l2g_d);
442
443	router_m2p->p_out[0] (signal_dspin_m2p_g2l_c);
444	router_m2p->p_in[0] (signal_dspin_m2p_l2g_c);
445
446	router_p2m->p_out[0] (signal_dspin_p2m_g2l_c);
447	router_p2m->p_in[0] (signal_dspin_p2m_l2g_c);
448
449	router_cla->p_out[0] (signal_dspin_clack_g2l_c);
450	router_cla->p_in[0] (signal_dspin_clack_l2g_c);
451
452	std::cout << " - routers connected" << std::endl;
453
454	wi_xbar_d->p_clk (this->p_clk);
455	wi_xbar_d->p_resetn (this->p_resetn);
456	wi_xbar_d->p_vci (signal_vci_l2g_d);
457	wi_xbar_d->p_dspin_cmd (signal_dspin_cmd_l2g_d);
458	wi_xbar_d->p_dspin_rsp (signal_dspin_rsp_g2l_d);
459
460	std::cout << " - Wrapper Ini VCI2DSPIN Direct connected" << std::endl;
461
462	wt_xbar_d->p_clk (this->p_clk);
463	wt_xbar_d->p_resetn (this->p_resetn);
464	wt_xbar_d->p_vci (signal_vci_g2l_d);
465	wt_xbar_d->p_dspin_cmd (signal_dspin_cmd_g2l_d);
466	wt_xbar_d->p_dspin_rsp (signal_dspin_rsp_l2g_d);
467
468	std::cout << " - Wrapper Tgt VCI2DSPIN Direct connected" << std::endl;
469
470	///////////////////// CMD VCI local crossbar direct
471	xbar_d->p_clk (this->p_clk);
472	xbar_d->p_resetn (this->p_resetn);
473	xbar_d->p_target_to_up (signal_vci_g2l_d);
474	xbar_d->p_initiator_to_up (signal_vci_l2g_d);
475
476	xbar_d->p_to_target[tgtid_memc] (signal_vci_tgt_memc);
477	xbar_d->p_to_target[tgtid_xicu] (signal_vci_tgt_xicu);
478	xbar_d->p_to_target[tgtid_mdma] (signal_vci_tgt_mdma);
479
480	xbar_d->p_to_initiator[nb_procs] (signal_vci_ini_mdma);
481
482	for (size_t p = 0; p < nb_procs; p++) {
483	xbar_d->p_to_initiator[p] (signal_vci_ini_proc[p]);
484	}
485
486	if (io) {
487	xbar_d->p_to_target[tgtid_mtty] (signal_vci_tgt_mtty);
488	xbar_d->p_to_target[tgtid_brom] (signal_vci_tgt_brom);
489	xbar_d->p_to_target[tgtid_bdev] (signal_vci_tgt_bdev);
490	xbar_d->p_to_target[tgtid_fbuf] (signal_vci_tgt_fbuf);
491	xbar_d->p_to_target[tgtid_mnic] (signal_vci_tgt_mnic);
492	xbar_d->p_to_target[tgtid_chbuf] (signal_vci_tgt_chbuf);
493	xbar_d->p_to_target[tgtid_simh] (signal_vci_tgt_simh);
494
495	xbar_d->p_to_initiator[nb_procs + 1] (signal_vci_ini_bdev);
496	xbar_d->p_to_initiator[nb_procs + 2] (signal_vci_ini_chbuf);
497	}
498
499	std::cout << " - Direct crossbar connected" << std::endl;
500
501	////////////////////// M2P DSPIN local crossbar coherence
502	xbar_m2p_c->p_clk (this->p_clk);
503	xbar_m2p_c->p_resetn (this->p_resetn);
504	xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c);
505	xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c);
506	xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc);
507	for (size_t p = 0; p < nb_procs; p++) {
508	xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]);
509	}
510
511	std::cout << " - M2P Coherence crossbar connected" << std::endl;
512
513	////////////////////// CLACK DSPIN local crossbar coherence
514	xbar_clack_c->p_clk (this->p_clk);
515	xbar_clack_c->p_resetn (this->p_resetn);
516	xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c);
517	xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c);
518	xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc);
519	for (size_t p = 0; p < nb_procs; p++) {
520	xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]);
521	}
522
523	std::cout << " - Clack Coherence crossbar connected" << std::endl;
524
525	////////////////////////// P2M DSPIN local crossbar coherence
526	xbar_p2m_c->p_clk (this->p_clk);
527	xbar_p2m_c->p_resetn (this->p_resetn);
528	xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c);
529	xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c);
530	xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc);
531	for (size_t p = 0; p < nb_procs; p++) {
532	xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]);
533	}
534
535	std::cout << " - P2M Coherence crossbar connected" << std::endl;
536
537
538	//////////////////////////////////// Processors
539	for (size_t p = 0; p < nb_procs; p++) {
540	proc[p]->p_clk (this->p_clk);
541	proc[p]->p_resetn (this->p_resetn);
542	proc[p]->p_vci (signal_vci_ini_proc[p]);
543	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
544	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
545	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
546
547	for ( size_t i = 0; i < irq_per_processor; i++) {
548	proc[p]->p_irq[i] (signal_proc_it[p*irq_per_processor + i]);
549	}
550	for ( size_t j = irq_per_processor; j < 6; j++) {
551	// 6 = number of irqs in the MIPS
552	proc[p]->p_irq[j] (signal_false);
553	}
554
555	}
556
557	std::cout << " - Processors connected" << std::endl;
558
559	///////////////////////////////////// XICU
560	xicu->p_clk (this->p_clk);
561	xicu->p_resetn (this->p_resetn);
562	xicu->p_vci (signal_vci_tgt_xicu);
563	for (size_t p = 0; p < nb_procs * irq_per_processor; p++) {
564	xicu->p_irq[p] (signal_proc_it[p]);
565	}
566	for (size_t i = 0; i < 32; i++) {
567	if (io) {
568	// I/O cluster
569	if (i < 8) xicu->p_hwi[i] (signal_false);
570	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
571	else if (i < 16) xicu->p_hwi[i] (signal_false);
572	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i - 16]);
573	else if (i < 30) xicu->p_hwi[i] (signal_false);
574	else if (i < 31) xicu->p_hwi[i] (signal_irq_memc);
575	else xicu->p_hwi[i] (signal_irq_bdev);
576	}
577	else {
578	// other clusters
579	if (i < 8) xicu->p_hwi[i] (signal_false);
580	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
581	else if (i < 30) xicu->p_hwi[i] (signal_false);
582	else if (i < 31) xicu->p_hwi[i] (signal_irq_memc);
583	else xicu->p_hwi[i] (signal_false);
584	}
585	}
586
587	std::cout << " - XICU connected" << std::endl;
588
589	//////////////////////////////////////////////// MEMC
590	memc->p_clk (this->p_clk);
591	memc->p_resetn (this->p_resetn);
592	memc->p_irq (signal_irq_memc);
593	memc->p_vci_ixr (signal_vci_xram);
594	memc->p_vci_tgt (signal_vci_tgt_memc);
595	memc->p_dspin_p2m (signal_dspin_p2m_memc);
596	memc->p_dspin_m2p (signal_dspin_m2p_memc);
597	memc->p_dspin_clack (signal_dspin_clack_memc);
598
599	std::cout << " - MEMC connected" << std::endl;
600
601	/////////////////////////////////////////////// XRAM
602	xram->p_clk (this->p_clk);
603	xram->p_resetn (this->p_resetn);
604	xram->p_vci (signal_vci_xram);
605
606	std::cout << " - XRAM connected" << std::endl;
607
608	////////////////////////////////////////////// MDMA
609	mdma->p_clk (this->p_clk);
610	mdma->p_resetn (this->p_resetn);
611	mdma->p_vci_target (signal_vci_tgt_mdma);
612	mdma->p_vci_initiator (signal_vci_ini_mdma);
613	for (size_t i = 0; i < nb_dmas; i++) {
614	mdma->p_irq[i] (signal_irq_mdma[i]);
615	}
616
617	std::cout << " - MDMA connected" << std::endl;
618
619	/////////////////////////////// Components in I/O cluster
620
621	if (io) {
622	// BDEV
623	bdev->p_clk (this->p_clk);
624	bdev->p_resetn (this->p_resetn);
625	bdev->p_irq (signal_irq_bdev);
626	bdev->p_vci_target (signal_vci_tgt_bdev);
627	bdev->p_vci_initiator (signal_vci_ini_bdev);
628
629	std::cout << " - BDEV connected" << std::endl;
630
631	// FBUF
632	fbuf->p_clk (this->p_clk);
633	fbuf->p_resetn (this->p_resetn);
634	fbuf->p_vci (signal_vci_tgt_fbuf);
635
636	std::cout << " - FBUF connected" << std::endl;
637
638	// MNIC
639	mnic->p_clk (this->p_clk);
640	mnic->p_resetn (this->p_resetn);
641	mnic->p_vci (signal_vci_tgt_mnic);
642	for (size_t i = 0; i < nic_channels; i++) {
643	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
644	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
645	}
646
647	std::cout << " - MNIC connected" << std::endl;
648
649	// CHBUF
650	chbuf->p_clk (this->p_clk);
651	chbuf->p_resetn (this->p_resetn);
652	chbuf->p_vci_target (signal_vci_tgt_chbuf);
653	chbuf->p_vci_initiator (signal_vci_ini_chbuf);
654	for (size_t i = 0; i < chbufdma_channels; i++) {
655	chbuf->p_irq[i] (signal_irq_chbuf[i]);
656	}
657
658	std::cout << " - CHBUF connected" << std::endl;
659
660	// BROM
661	brom->p_clk (this->p_clk);
662	brom->p_resetn (this->p_resetn);
663	brom->p_vci (signal_vci_tgt_brom);
664
665	std::cout << " - BROM connected" << std::endl;
666
667	// MTTY
668	mtty->p_clk (this->p_clk);
669	mtty->p_resetn (this->p_resetn);
670	mtty->p_vci (signal_vci_tgt_mtty);
671	for (size_t i = 0; i < nb_ttys; i++) {
672	mtty->p_irq[i] (signal_irq_mtty[i]);
673	}
674
675	std::cout << " - MTTY connected" << std::endl;
676
677
678	// Sim Helper
679	simhelper->p_clk (this->p_clk);
680	simhelper->p_resetn (this->p_resetn);
681	simhelper->p_vci (signal_vci_tgt_simh);
682
683	std::cout << " - SIMH connected" << std::endl;
684	}
685	} // end constructor
686
687
688
689	template<size_t dspin_cmd_width,
690	size_t dspin_rsp_width,
691	typename vci_param_int,
692	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
693	dspin_rsp_width,
694	vci_param_int,
695	vci_param_ext>::~TsarXbarCluster() {
696
697	dealloc_elems<DspinInput<dspin_cmd_width> > (p_cmd_in, 6);
698	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cmd_out, 6);
699
700	dealloc_elems<DspinInput<dspin_rsp_width> > (p_rsp_in, 6);
701	dealloc_elems<DspinOutput<dspin_rsp_width> >(p_rsp_out, 6);
702
703	dealloc_elems<DspinInput<dspin_cmd_width> > (p_m2p_in, 6);
704	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_m2p_out, 6);
705
706	dealloc_elems<DspinInput<dspin_rsp_width> > (p_p2m_in, 6);
707	dealloc_elems<DspinOutput<dspin_rsp_width> >(p_p2m_out, 6);
708
709	dealloc_elems<DspinInput<dspin_cmd_width> > (p_cla_in, 6);
710	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cla_out, 6);
711
712	for (size_t p = 0; p < n_procs; p++) {
713	delete proc[p];
714	}
715
716	delete memc;
717	delete xram;
718	delete xicu;
719	delete mdma;
720	delete xbar_d;
721	delete wt_xbar_d;
722	delete wi_xbar_d;
723	delete xbar_m2p_c;
724	delete xbar_p2m_c;
725	delete xbar_clack_c;
726	delete router_cmd;
727	delete router_rsp;
728	if (brom != NULL) {
729	delete brom;
730	delete fbuf;
731	delete bdev;
732	delete mnic;
733	delete chbuf;
734	delete mtty;
735	delete simhelper;
736	}
737	}
738
739
740	template<size_t dspin_cmd_width,
741	size_t dspin_rsp_width,
742	typename vci_param_int,
743	typename vci_param_ext>
744	void TsarXbarCluster<dspin_cmd_width,
745	dspin_rsp_width,
746	vci_param_int,
747	vci_param_ext>::trace(sc_core::sc_trace_file * tf, const std::string & name) {
748
749	#define __trace(x) sc_core::sc_trace(tf, x, name + "_" + #x)
750	__trace(signal_vci_l2g_d);
751	__trace(signal_vci_g2l_d);
752	__trace(signal_vci_tgt_memc);
753	__trace(signal_vci_tgt_xicu);
754	__trace(signal_vci_tgt_mdma);
755	__trace(signal_vci_ini_mdma);
756
757	for (size_t p = 0; p < n_procs; p++) {
758	std::ostringstream signame;
759	signame << "vci_ini_proc_" << p;
760	sc_core::sc_trace(tf, signal_vci_ini_proc[p], signame.str());
761	}
762	__trace(signal_vci_tgt_mtty);
763	__trace(signal_vci_tgt_brom);
764	__trace(signal_vci_tgt_bdev);
765	__trace(signal_vci_tgt_fbuf);
766	__trace(signal_vci_tgt_simh);
767	__trace(signal_vci_ini_bdev);
768	__trace(signal_vci_tgt_memc);
769	__trace(signal_vci_xram);
770	#undef __trace
771	}
772
773	}}
774
775	// Local Variables:
776	// tab-width: 4
777	// c-basic-offset: 4
778	// c-file-offsets:((innamespace . 0)(inline-open . 0))
779	// indent-tabs-mode: nil
780	// End:
781
782	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
783

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source: trunk/platforms/tsar_generic_3d/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp @ 1040

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