[793] | 1 | #!/usr/bin/env python |
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| 2 | |
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[803] | 3 | from math import log, ceil |
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[793] | 4 | from mapping import * |
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| 5 | |
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| 6 | ############################################################################### |
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[803] | 7 | # file : arch.py (for the tsar_generic_leti architecture) |
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[793] | 8 | # date : may 2014 |
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| 9 | # author : Alain Greiner |
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| 10 | ############################################################################### |
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[803] | 11 | # This file contains a mapping generator for the "tsar_generic_leti" platform. |
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[793] | 12 | # This includes both the hardware architecture (clusters, processors, |
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| 13 | # peripherals, physical space segmentation) and the mapping of all kernel |
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[803] | 14 | # objects (global vsegs). |
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[793] | 15 | # |
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| 16 | # The "constructor" parameters are: |
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| 17 | # - x_size : number of clusters in a row |
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| 18 | # - y_size : number of clusters in a column |
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| 19 | # - nb_procs : number of processors per cluster |
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| 20 | # |
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| 21 | # The "hidden" parameters (defined below) are: |
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| 22 | # - nb_ttys : number of TTY channels |
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| 23 | # - nb_nics : number of NIC channels |
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| 24 | # - fbf_width : frame_buffer width = frame_buffer heigth |
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| 25 | # - x_io : cluster_io x coordinate |
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| 26 | # - y_io : cluster_io y coordinate |
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| 27 | # - x_width : number of bits for x coordinate |
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| 28 | # - y_width : number of bits for y coordinate |
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| 29 | # - paddr_width : number of bits for physical address |
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| 30 | # - irq_per_proc : number of input IRQs per processor |
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| 31 | # - use_ramdisk : use a ramdisk when True |
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| 32 | # - peri_increment : address increment for replicated peripherals |
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| 33 | ############################################################################### |
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| 34 | |
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| 35 | ######################## |
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[819] | 36 | def arch( x_size = 2, |
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| 37 | y_size = 2, |
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| 38 | nb_procs = 2, |
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| 39 | fbf_width = 128 ): |
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[793] | 40 | |
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| 41 | ### define architecture constants |
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| 42 | |
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| 43 | nb_ttys = 1 |
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| 44 | nb_nics = 2 |
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| 45 | x_io = 0 |
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| 46 | y_io = 0 |
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| 47 | x_width = 4 |
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| 48 | y_width = 4 |
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[819] | 49 | p_width = 4 |
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[793] | 50 | paddr_width = 40 |
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| 51 | irq_per_proc = 4 |
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| 52 | use_ramdisk = True |
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[819] | 53 | peri_increment = 0x10000 # distributed peripherals vbase address increment |
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| 54 | sched_increment = 0x10000 # distributed schedulers vbase address increment |
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| 55 | ptab_increment = 0x200000 # distributed page tables vbase address increment |
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[793] | 56 | reset_address = 0x00000000 |
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[803] | 57 | distributed_ptabs = False |
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[793] | 58 | |
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| 59 | ### parameters checking |
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| 60 | |
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[803] | 61 | assert( nb_procs <= (1 << p_width) ) |
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[793] | 62 | |
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| 63 | assert( (x_size == 1) or (x_size == 2) or (x_size == 4) |
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| 64 | or (x_size == 8) or (x_size == 16) ) |
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| 65 | |
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| 66 | assert( (y_size == 1) or (y_size == 2) or (y_size == 4) |
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| 67 | or (y_size == 8) or (y_size == 16) ) |
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| 68 | |
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| 69 | assert( nb_ttys == 1 ) |
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| 70 | |
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| 71 | assert( ((x_io == 0) and (y_io == 0)) or |
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| 72 | ((x_io == x_size-1) and (y_io == y_size-1)) ) |
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| 73 | |
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[803] | 74 | platform_name = 'tsar_leti_%d_%d_%d' % ( x_size, y_size, nb_procs ) |
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[793] | 75 | |
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| 76 | ### define physical segments |
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| 77 | |
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| 78 | ram_base = 0x0000000000 |
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| 79 | ram_size = 0x4000000 # 64 Mbytes |
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| 80 | |
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| 81 | xcu_base = 0x00F0000000 |
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| 82 | xcu_size = 0x1000 # 4 Kbytes |
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| 83 | |
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| 84 | mmc_base = 0x00E0000000 |
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| 85 | mmc_size = 0x1000 # 4 Kbytes |
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| 86 | |
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| 87 | offset_io = ((x_io << y_width) + y_io) << (paddr_width - x_width - y_width) |
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| 88 | |
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| 89 | bdv_base = 0x00F2000000 + offset_io |
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| 90 | bdv_size = 0x1000 # 4kbytes |
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| 91 | |
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| 92 | tty_base = 0x00F4000000 + offset_io |
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| 93 | tty_size = 0x4000 # 16 Kbytes |
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| 94 | |
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| 95 | nic_base = 0x00F7000000 + offset_io |
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| 96 | nic_size = 0x80000 # 512 kbytes |
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| 97 | |
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| 98 | cma_base = 0x00F8000000 + offset_io |
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| 99 | cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics |
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| 100 | |
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| 101 | fbf_base = 0x00F3000000 + offset_io |
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| 102 | fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes |
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| 103 | |
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| 104 | pic_base = 0x00F9000000 + offset_io |
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| 105 | pic_size = 0x1000 # 4 Kbytes |
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| 106 | |
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| 107 | rdk_base = 0x02000000 |
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| 108 | rdk_size = 0x02000000 # 32 Mbytes |
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| 109 | |
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[819] | 110 | ### define preloader & bootloader vsegs base addresses and sizes |
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| 111 | ### we want to pack these 5 vsegs in the same big page |
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[803] | 112 | |
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| 113 | preloader_vbase = 0x00000000 # ident |
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| 114 | preloader_size = 0x00010000 # 64 Kbytes |
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| 115 | |
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| 116 | boot_mapping_vbase = 0x00010000 # ident |
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[793] | 117 | boot_mapping_size = 0x00080000 # 512 Kbytes |
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| 118 | |
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[803] | 119 | boot_code_vbase = 0x00090000 # ident |
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[793] | 120 | boot_code_size = 0x00040000 # 256 Kbytes |
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| 121 | |
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[803] | 122 | boot_data_vbase = 0x000D0000 # ident |
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[793] | 123 | boot_data_size = 0x00080000 # 512 Kbytes |
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| 124 | |
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[803] | 125 | boot_stack_vbase = 0x00150000 # ident |
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[793] | 126 | boot_stack_size = 0x00050000 # 320 Kbytes |
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| 127 | |
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| 128 | ### define kernel vsegs base addresses and sizes |
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[819] | 129 | ### we want to pack code, init and data vsegs in one big page |
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| 130 | ### we want to map the ptab vseg in one big page per cluster |
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| 131 | ### we want to map the sched vseg in small pages |
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| 132 | |
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[793] | 133 | kernel_code_vbase = 0x80000000 |
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[819] | 134 | kernel_code_size = 0x00080000 # 512 Kbytes per cluster |
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[793] | 135 | |
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[819] | 136 | kernel_init_vbase = 0x80080000 |
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| 137 | kernel_init_size = 0x00080000 # 512 Kbytes per cluster |
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[793] | 138 | |
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[819] | 139 | kernel_data_vbase = 0x80100000 |
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| 140 | kernel_data_size = 0x00100000 # 1 Mbytes in cluster [0,0] |
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[793] | 141 | |
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[819] | 142 | kernel_ptab_vbase = 0xB0000000 |
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| 143 | kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster |
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[793] | 144 | |
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[819] | 145 | kernel_uncdata_vbase = 0x90000000 |
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| 146 | kernel_uncdata_size = 0x00001000 # 4 Kbytes |
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[793] | 147 | |
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[819] | 148 | kernel_sched_vbase = 0xA0000000 # distributed in all clusters |
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| 149 | kernel_sched_size = 0x00002000 * nb_procs # 8 kbytes per processor |
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| 150 | |
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[793] | 151 | ### create mapping |
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| 152 | |
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| 153 | mapping = Mapping( name = platform_name, |
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| 154 | x_size = x_size, |
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| 155 | y_size = y_size, |
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[819] | 156 | nprocs = nb_procs, |
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[793] | 157 | x_width = x_width, |
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| 158 | y_width = y_width, |
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[803] | 159 | p_width = p_width, |
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[793] | 160 | paddr_width = paddr_width, |
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| 161 | coherence = True, |
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| 162 | irq_per_proc = irq_per_proc, |
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| 163 | use_ramdisk = use_ramdisk, |
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| 164 | x_io = x_io, |
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| 165 | y_io = y_io, |
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| 166 | peri_increment = peri_increment, |
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| 167 | reset_address = reset_address, |
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| 168 | ram_base = ram_base, |
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| 169 | ram_size = ram_size ) |
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| 170 | |
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| 171 | ### external peripherals (accessible in cluster[0,0] only for this mapping) |
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| 172 | |
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[797] | 173 | bdv = mapping.addPeriph( 'BDV', base = bdv_base, size = bdv_size, |
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| 174 | ptype = 'IOC', subtype = 'BDV' ) |
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[793] | 175 | |
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| 176 | tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, |
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| 177 | ptype = 'TTY', channels = nb_ttys ) |
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| 178 | |
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| 179 | nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, |
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| 180 | ptype = 'NIC', channels = nb_nics ) |
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| 181 | |
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| 182 | cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, |
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| 183 | ptype = 'CMA', channels = 2*nb_nics ) |
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| 184 | |
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| 185 | fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, |
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| 186 | ptype = 'FBF', arg = fbf_width ) |
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| 187 | |
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| 188 | pic = mapping.addPeriph( 'PIC', base = pic_base, size = pic_size, |
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| 189 | ptype = 'PIC', channels = 32 ) |
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| 190 | |
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| 191 | mapping.addIrq( pic, index = 0 , isrtype = 'ISR_NIC_RX', channel = 0 ) |
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| 192 | mapping.addIrq( pic, index = 1 , isrtype = 'ISR_NIC_RX', channel = 1 ) |
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| 193 | mapping.addIrq( pic, index = 2 , isrtype = 'ISR_NIC_TX', channel = 0 ) |
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| 194 | mapping.addIrq( pic, index = 3 , isrtype = 'ISR_NIC_TX', channel = 1 ) |
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| 195 | mapping.addIrq( pic, index = 4 , isrtype = 'ISR_CMA' , channel = 0 ) |
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| 196 | mapping.addIrq( pic, index = 5 , isrtype = 'ISR_CMA' , channel = 1 ) |
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| 197 | mapping.addIrq( pic, index = 6 , isrtype = 'ISR_CMA' , channel = 2 ) |
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| 198 | mapping.addIrq( pic, index = 7 , isrtype = 'ISR_CMA' , channel = 3 ) |
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| 199 | mapping.addIrq( pic, index = 8 , isrtype = 'ISR_BDV' , channel = 0 ) |
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| 200 | mapping.addIrq( pic, index = 16, isrtype = 'ISR_TTY_RX', channel = 0 ) |
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| 201 | |
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| 202 | ### hardware components replicated in all clusters |
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| 203 | |
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| 204 | for x in xrange( x_size ): |
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| 205 | for y in xrange( y_size ): |
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| 206 | cluster_xy = (x << y_width) + y; |
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| 207 | offset = cluster_xy << (paddr_width - x_width - y_width) |
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| 208 | |
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| 209 | ram = mapping.addRam( 'RAM', base = ram_base + offset, |
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| 210 | size = ram_size ) |
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| 211 | |
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| 212 | mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, |
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| 213 | size = mmc_size, ptype = 'MMC' ) |
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| 214 | |
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| 215 | xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, |
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| 216 | size = xcu_size, ptype = 'XCU', |
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| 217 | channels = nb_procs * irq_per_proc, |
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| 218 | arg = 16 ) |
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| 219 | |
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| 220 | # IRQs replicated in all clusters |
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| 221 | mapping.addIrq( xcu, index = 8, isrtype = 'ISR_MMC' ) |
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| 222 | |
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| 223 | # IRQ in IO cluster (0,0) |
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| 224 | if x == 0 and y == 0: |
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| 225 | mapping.addIrq( xcu, index = 9 , isrtype = 'ISR_BDV' ) |
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| 226 | mapping.addIrq( xcu, index = 10, isrtype = 'ISR_TTY_RX' ) |
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| 227 | |
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| 228 | # processors |
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| 229 | for p in xrange ( nb_procs ): |
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| 230 | mapping.addProc( x, y, p ) |
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| 231 | |
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[803] | 232 | ### global vseg for preloader |
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[793] | 233 | |
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[803] | 234 | ### global vseg for ram disk |
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| 235 | |
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| 236 | if use_ramdisk: |
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| 237 | mapping.addGlobal( 'seg_rdk', rdk_base, rdk_size, '__W_', |
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| 238 | vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 239 | identity = True ) |
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| 240 | |
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[793] | 241 | ### global vsegs for external peripherals / identity mapping |
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| 242 | |
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[797] | 243 | mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', |
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| 244 | vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', |
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| 245 | identity = True ) |
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[793] | 246 | |
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| 247 | mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', |
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| 248 | vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', |
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| 249 | identity = True ) |
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| 250 | |
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| 251 | mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', |
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| 252 | vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', |
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| 253 | identity = True ) |
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| 254 | |
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| 255 | mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', |
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| 256 | vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', |
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| 257 | identity = True ) |
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| 258 | |
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| 259 | mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', |
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| 260 | vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', |
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| 261 | identity = True ) |
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| 262 | |
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| 263 | mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', |
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| 264 | vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', |
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| 265 | identity = True ) |
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| 266 | |
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| 267 | ### global vsegs for internal peripherals, and for schedulers |
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| 268 | ### name is indexed by (x,y) / vbase address is incremented by (cluster_xy * peri_increment) |
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| 269 | |
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| 270 | for x in xrange( x_size ): |
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| 271 | for y in xrange( y_size ): |
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| 272 | cluster_xy = (x << y_width) + y; |
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| 273 | offset = cluster_xy * peri_increment |
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| 274 | |
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| 275 | mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size, |
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| 276 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU' ) |
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| 277 | |
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| 278 | mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size, |
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| 279 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC' ) |
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| 280 | |
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| 281 | mapping.addGlobal( 'seg_sched_%d_%d' %(x,y), kernel_sched_vbase + offset, kernel_sched_size, |
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| 282 | 'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM' ) |
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| 283 | |
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[819] | 284 | ### global vsegs for preloader and boot_loader |
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| 285 | ### identity mapping / non local / big page |
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[793] | 286 | |
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[819] | 287 | mapping.addGlobal( 'seg_preloader', preloader_vbase, preloader_size, |
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| 288 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 289 | identity = True, local = False, big = True ) |
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| 290 | |
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[793] | 291 | mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, |
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[819] | 292 | 'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', |
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| 293 | identity = True, local = False, big = True ) |
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[793] | 294 | |
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| 295 | mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, |
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| 296 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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[819] | 297 | identity = True, local = False, big = True ) |
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[793] | 298 | |
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| 299 | mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, |
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[819] | 300 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 301 | identity = True, local = False, big = True ) |
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[793] | 302 | |
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| 303 | mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, |
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[819] | 304 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 305 | identity = True, local = False, big = True ) |
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[793] | 306 | |
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[819] | 307 | ### global vsegs kernel_code, kernel_init |
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| 308 | for x in xrange( x_size ): |
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| 309 | for y in xrange( y_size ): |
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| 310 | cluster_xy = (x << y_width) + y; |
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[793] | 311 | |
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[819] | 312 | mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size, |
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| 313 | 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', |
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| 314 | binpath = 'build/kernel/kernel.elf', |
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| 315 | local = True, big = True ) |
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[793] | 316 | |
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[819] | 317 | mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size, |
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| 318 | 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', |
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| 319 | binpath = 'build/kernel/kernel.elf', |
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| 320 | local = True, big = True ) |
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[793] | 321 | |
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[819] | 322 | |
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[793] | 323 | |
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| 324 | mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, |
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| 325 | 'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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| 326 | binpath = 'build/kernel/kernel.elf', local = False ) |
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| 327 | |
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| 328 | mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, |
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| 329 | '__W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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| 330 | binpath = 'build/kernel/kernel.elf', local = False ) |
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| 331 | |
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| 332 | ### return mapping ### |
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| 333 | |
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| 334 | return mapping |
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| 335 | |
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| 336 | ################################# platform test ####################################################### |
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| 337 | |
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| 338 | if __name__ == '__main__': |
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| 339 | |
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| 340 | mapping = arch( x_size = 2, |
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| 341 | y_size = 2, |
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| 342 | nb_procs = 2 ) |
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| 343 | |
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| 344 | # print mapping.netbsd_dts() |
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| 345 | |
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| 346 | print mapping.xml() |
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| 347 | |
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| 348 | # print mapping.giet_vsegs() |
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| 349 | |
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| 350 | |
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| 351 | # Local Variables: |
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| 352 | # tab-width: 4; |
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| 353 | # c-basic-offset: 4; |
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| 354 | # c-file-offsets:((innamespace . 0)(inline-open . 0)); |
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| 355 | # indent-tabs-mode: nil; |
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| 356 | # End: |
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| 357 | # |
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| 358 | # vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 359 | |
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