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source: trunk/platforms/tsar_generic_leti/top.cpp @ 849

Last change on this file since 849 was 849, checked in by porquet, 10 years ago
tsar_generic_leti: avoid warnings at compilation
File size: 56.0 KB

Rev	Line
[621]	1	/////////////////////////////////////////////////////////////////////////
[664]	2	// File: top.cpp (for tsar_generic_leti)
[792]	3	// Author: Alain Greiner
[621]	4	// Copyright: UPMC/LIP6
[628]	5	// Date : february 2014
[621]	6	// This program is released under the GNU public license
	7	/////////////////////////////////////////////////////////////////////////
[681]	8	// This file define a generic TSAR architecture, fully compatible
	9	// with the VLSI Hardware prototype developped by CEA-LETI and LIP6
	10	// in the framework of the SHARP project.
[792]	11	//
[621]	12	// The processor is a MIPS32 processor wrapped in a GDB server
	13	// (this is defined in the tsar_xbar_cluster).
[792]	14	//
[681]	15	// It does not use an external ROM, as the boot code is (pre)loaded
	16	// in cluster (0,0) memory at address 0x0.
[621]	17	//
	18	// The physical address space is 40 bits.
	19	// The 8 address MSB bits define the cluster index.
	20	//
[681]	21	// The main hardware parameters are the mesh size (X_SIZE & Y_SIZE),
	22	// and the number of processors per cluster (NB_PROCS_MAX).
	23	// The number of clusters cannot be larger than 128.
[621]	24	// The number of processors per cluster cannot be larger than 4.
[792]	25	//
[628]	26	// Each cluster contains:
	27	// - 5 dspin_local_crossbar (local interconnect)
	28	// - 5 dspin_router (global interconnect)
	29	// - up to 4 vci_cc_vcache wrapping a MIPS32 processor
	30	// - 1 vci_mem_cache
	31	// - 1 vci_xicu
	32	// - 1 vci_simple_ram (to model the L3 cache).
[621]	33	//
[681]	34	// Each processor receives 4 consecutive IRQ lines from the local XICU.
[664]	35	//
[628]	36	// In all clusters, the MEMC IRQ line (signaling a late write error)
	37	// is connected to XICU HWI[8]
[681]	38	// The cluster (0,0) contains two "backup" peripherals:
[628]	39	// - one block device controller, whose IRQ is connected to XICU HWI[9].
	40	// - one single channel TTY controller, whose IRQ is connected to XICU HWI[10].
[621]	41	//
[628]	42	// The cluster internal architecture is defined in file tsar_leti_cluster,
	43	// that must be considered as an extension of this top.cpp file.
[621]	44	//
[792]	45	// Besides the hardware components in clusters, "external" peripherals
[628]	46	// are connected to an external IO bus (implemented as a vci_local_crossbar):
[792]	47	// - one disk controller
	48	// - one multi-channel ethernet controller
[628]	49	// - one multi-channel chained buffer dma controller
[792]	50	// - one multi-channel tty controller
	51	// - one frame buffer controller
[664]	52	// - one 32 channels iopic controller
[628]	53	//
[792]	54	// This IOBUS is connected to the north port of the DIR_CMD
[681]	55	// and DIR_RSP routers, in cluster(X_SIZE-1, Y_SIZE-1).
[628]	56	// For all external peripherals, the hardware interrupts (HWI) are
[664]	57	// translated to write interrupts (WTI) by the iopic component:
	58	// - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0]
[792]	59	// - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0]
[664]	60	// - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]]
	61	// - IOPIC HWI[8] connected to IRQ_BDEV
	62	// - IOPIC HWI[15:9] unused (grounded)
	63	// - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]]
	64	// - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]]
[628]	65	////////////////////////////////////////////////////////////////////////////
	66	// The following parameters must be defined in the hard_config.h file :
[621]	67	// - X_WIDTH : number of bits for x coordinate (must be 4)
	68	// - Y_WIDTH : number of bits for y coordinate (must be 4)
[681]	69	// - X_SIZE : number of clusters in a row (1,2,4,8,16)
	70	// - Y_SIZE : number of clusters in a column (1,2,4,8)
[628]	71	// - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4)
[664]	72	// - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (4 max)
	73	// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (8 max)
[628]	74	// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max)
[792]	75	//
[621]	76	// Some other hardware parameters are not used when compiling the OS,
[628]	77	// and are only defined in this top.cpp file:
[792]	78	// - XRAM_LATENCY : external ram latency
[621]	79	// - MEMC_WAYS : L2 cache number of ways
	80	// - MEMC_SETS : L2 cache number of sets
[628]	81	// - L1_IWAYS : L1 cache instruction number of ways
	82	// - L1_ISETS : L1 cache instruction number of sets
	83	// - L1_DWAYS : L1 cache data number of ways
	84	// - L1_DSETS : L1 cache data number of sets
[621]	85	// - FBUF_X_SIZE : width of frame buffer (pixels)
	86	// - FBUF_Y_SIZE : heigth of frame buffer (lines)
[792]	87	// - BDEV_IMAGE_NAME : file pathname for block device
[621]	88	// - NIC_RX_NAME : file pathname for NIC received packets
	89	// - NIC_TX_NAME : file pathname for NIC transmited packets
[628]	90	// - NIC_MAC4 : MAC address
	91	// - NIC_MAC2 : MAC address
[621]	92	/////////////////////////////////////////////////////////////////////////
	93	// General policy for 40 bits physical address decoding:
	94	// All physical segments base addresses are multiple of 1 Mbytes
[792]	95	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
[621]	96	// The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define
	97	// the cluster index, and the LADR bits define the local index:
	98	// \|X_ID\|Y_ID\| LADR \| OFFSET \|
	99	// \| 4 \| 4 \| 8 \| 24 \|
	100	/////////////////////////////////////////////////////////////////////////
	101	// General policy for 14 bits SRCID decoding:
	102	// Each component is identified by (x_id, y_id, l_id) tuple.
	103	// \|X_ID\|Y_ID\| L_ID \|
	104	// \| 4 \| 4 \| 6 \|
	105	/////////////////////////////////////////////////////////////////////////
	106
	107	#include <systemc>
	108	#include <sys/time.h>
	109	#include <iostream>
	110	#include <sstream>
	111	#include <cstdlib>
	112	#include <cstdarg>
	113	#include <stdint.h>
	114
	115	#include "gdbserver.h"
	116	#include "mapping_table.h"
	117	#include "tsar_leti_cluster.h"
[628]	118	#include "vci_local_crossbar.h"
	119	#include "vci_dspin_initiator_wrapper.h"
	120	#include "vci_dspin_target_wrapper.h"
	121	#include "vci_multi_tty.h"
	122	#include "vci_multi_nic.h"
	123	#include "vci_chbuf_dma.h"
	124	#include "vci_block_device_tsar.h"
	125	#include "vci_framebuffer.h"
	126	#include "vci_iopic.h"
[621]	127	#include "alloc_elems.h"
	128
[792]	129	#include "hard_config.h"
[621]	130
	131	///////////////////////////////////////////////////
	132	// Parallelisation
	133	///////////////////////////////////////////////////
[708]	134	#define USE_OPENMP _OPENMP
[621]	135
	136	#if USE_OPENMP
	137	#include <omp.h>
	138	#endif
	139
	140	///////////////////////////////////////////////////
	141	// cluster index (from x,y coordinates)
	142	///////////////////////////////////////////////////
	143
[692]	144	#define cluster(x,y) ((y) + ((x) << Y_WIDTH))
[621]	145
	146	///////////////////////////////////////////////////////////
[792]	147	// DSPIN parameters
[621]	148	///////////////////////////////////////////////////////////
	149
	150	#define dspin_cmd_width 39
	151	#define dspin_rsp_width 32
	152
	153	///////////////////////////////////////////////////////////
[792]	154	// VCI parameters
[621]	155	///////////////////////////////////////////////////////////
	156
	157	#define vci_cell_width_int 4
	158	#define vci_cell_width_ext 8
	159	#define vci_address_width 40
	160	#define vci_plen_width 8
	161	#define vci_rerror_width 1
	162	#define vci_clen_width 1
	163	#define vci_rflag_width 1
	164	#define vci_srcid_width 14
	165	#define vci_pktid_width 4
	166	#define vci_trdid_width 4
	167	#define vci_wrplen_width 1
	168
	169
[664]	170	/////////////////////////////////////////////////////////////////////////////////////////
[792]	171	// Secondary Hardware Parameters
[664]	172	/////////////////////////////////////////////////////////////////////////////////////////
[621]	173
[664]	174	#define MAX_TTY_CHANNELS 8
	175	#define MAX_CMA_CHANNELS 4
	176	#define MAX_NIC_CHANNELS 2
	177
[621]	178	#define XRAM_LATENCY 0
	179
	180	#define MEMC_WAYS 16
	181	#define MEMC_SETS 256
	182
	183	#define L1_IWAYS 4
	184	#define L1_ISETS 64
	185
	186	#define L1_DWAYS 4
	187	#define L1_DSETS 64
	188
[628]	189	#define NIC_MAC4 0XBABEF00D
	190	#define NIC_MAC2 0xBEEF
[708]	191	#define NIC_RX_NAME "/dev/null"
	192	#define NIC_TX_NAME "/dev/null"
[621]	193
	194	#define NORTH 0
	195	#define SOUTH 1
	196	#define EAST 2
	197	#define WEST 3
	198
[664]	199	///////////////////////////////////////////////////////////////////////////////////////
[792]	200	// DEBUG Parameters default values
[664]	201	///////////////////////////////////////////////////////////////////////////////////////
[621]	202
[681]	203	#define MAX_FROZEN_CYCLES 500000
[621]	204
[664]	205	///////////////////////////////////////////////////////////////////////////////////////
[792]	206	// LOCAL TGTID & SRCID definition
[621]	207	// For all components: global TGTID = global SRCID = cluster_index
[664]	208	///////////////////////////////////////////////////////////////////////////////////////
[621]	209
[664]	210	#define MEMC_TGTID 0
	211	#define XICU_TGTID 1
	212	#define MTTY_TGTID 2
	213	#define BDEV_TGTID 3
	214	#define FBUF_TGTID 4
	215	#define MNIC_TGTID 5
	216	#define CDMA_TGTID 6
	217	#define IOPI_TGTID 7
[621]	218
[664]	219	#define BDEV_SRCID NB_PROCS_MAX
	220	#define CDMA_SRCID NB_PROCS_MAX + 1
	221	#define IOPI_SRCID NB_PROCS_MAX + 2
[628]	222
[621]	223	bool stop_called = false;
	224
	225	/////////////////////////////////
	226	int _main(int argc, char *argv[])
	227	{
	228	using namespace sc_core;
	229	using namespace soclib::caba;
	230	using namespace soclib::common;
	231
[692]	232	uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles
	233	size_t threads = 1; // simulator's threads number
	234	bool trace_ok = false; // trace activated
	235	uint32_t trace_from = 0; // trace start cycle
	236	bool trace_proc_ok = false; // detailed proc trace activated
	237	size_t trace_memc_ok = false; // detailed memc trace activated
[792]	238	size_t trace_memc_id = 0; // index of memc to be traced
[692]	239	size_t trace_proc_id = 0; // index of proc to be traced
	240	uint32_t frozen_cycles = MAX_FROZEN_CYCLES;
[792]	241	char soft_name[256] = "soft.elf";
	242	char disk_name[256] = "disk.img";
[621]	243	struct timeval t1,t2;
	244	uint64_t ms1,ms2;
	245
	246	////////////// command line arguments //////////////////////
	247	if (argc > 1)
	248	{
	249	for (int n = 1; n < argc; n = n + 2)
	250	{
	251	if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc))
	252	{
	253	ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0);
	254	}
	255	else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc))
	256	{
	257	trace_ok = true;
	258	trace_from = (uint32_t) strtol(argv[n + 1], NULL, 0);
	259	}
	260	else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc))
	261	{
	262	trace_memc_ok = true;
	263	trace_memc_id = (size_t) strtol(argv[n + 1], NULL, 0);
	264	size_t x = trace_memc_id >> Y_WIDTH;
	265	size_t y = trace_memc_id & ((1<<Y_WIDTH)-1);
	266
[681]	267	assert( (x < X_SIZE) and (y < (Y_SIZE)) and
[621]	268	"MEMCID parameter refers a not valid memory cache");
	269	}
	270	else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc))
	271	{
	272	trace_proc_ok = true;
	273	trace_proc_id = (size_t) strtol(argv[n + 1], NULL, 0);
[803]	274	size_t cluster_xy = trace_proc_id >> P_WIDTH ;
[621]	275	size_t x = cluster_xy >> Y_WIDTH;
	276	size_t y = cluster_xy & ((1<<Y_WIDTH)-1);
[803]	277	size_t l = trace_proc_id & ((1<<P_WIDTH)-1) ;
[621]	278
[692]	279	assert( (x < X_SIZE) and (y < Y_SIZE) and (l < NB_PROCS_MAX) and
[621]	280	"PROCID parameter refers a not valid processor");
	281	}
[692]	282	else if ((strcmp(argv[n], "-SOFT") == 0) && ((n + 1) < argc))
	283	{
[792]	284	strcpy(soft_name, argv[n + 1]);
[692]	285	}
	286	else if ((strcmp(argv[n], "-DISK") == 0) && ((n + 1) < argc))
	287	{
	288	strcpy(disk_name, argv[n + 1]);
	289	}
[621]	290	else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc))
	291	{
[628]	292	threads = (size_t) strtol(argv[n + 1], NULL, 0);
	293	threads = (threads < 1) ? 1 : threads;
[621]	294	}
	295	else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc))
	296	{
	297	frozen_cycles = (uint32_t) strtol(argv[n + 1], NULL, 0);
	298	}
	299	else
	300	{
	301	std::cout << " Arguments are (key,value) couples." << std::endl;
	302	std::cout << " The order is not important." << std::endl;
	303	std::cout << " Accepted arguments are :" << std::endl << std::endl;
	304	std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
	305	std::cout << " -DEBUG debug_start_cycle" << std::endl;
[692]	306	std::cout << " -SOFT path to soft" << std::endl;
	307	std::cout << " -DISK path to disk image" << std::endl;
[621]	308	std::cout << " -THREADS simulator's threads number" << std::endl;
	309	std::cout << " -FROZEN max_number_of_lines" << std::endl;
	310	std::cout << " -PERIOD number_of_cycles between trace" << std::endl;
	311	std::cout << " -MEMCID index_memc_to_be_traced" << std::endl;
	312	std::cout << " -PROCID index_proc_to_be_traced" << std::endl;
	313	exit(0);
	314	}
	315	}
	316	}
	317
	318	// checking hardware parameters
[792]	319	assert( ((X_SIZE==1) or (X_SIZE==2) or (X_SIZE==4) or (X_SIZE==8) or
	320	(X_SIZE==16)) and
[681]	321	"Illegal X_SIZE parameter" );
[621]	322
[792]	323	assert( ((Y_SIZE==1) or (Y_SIZE==2) or (Y_SIZE==4) or (Y_SIZE==8)) and
[681]	324	"Illegal Y_SIZE parameter" );
[621]	325
[803]	326	assert( (P_WIDTH <= 2) and
	327	"P_WIDTH parameter cannot be larger than 2" );
	328
[664]	329	assert( (NB_PROCS_MAX <= 4) and
[681]	330	"Illegal NB_PROCS_MAX parameter" );
[621]	331
[664]	332	assert( (NB_CMA_CHANNELS <= MAX_CMA_CHANNELS) and
[628]	333	"The NB_CMA_CHANNELS parameter cannot be larger than 4" );
[621]	334
[664]	335	assert( (NB_TTY_CHANNELS <= MAX_TTY_CHANNELS) and
	336	"The NB_TTY_CHANNELS parameter cannot be larger than 8" );
[621]	337
[664]	338	assert( (NB_NIC_CHANNELS <= MAX_NIC_CHANNELS) and
[628]	339	"The NB_NIC_CHANNELS parameter cannot be larger than 2" );
[621]	340
	341	assert( (vci_address_width == 40) and
	342	"VCI address width with the GIET must be 40 bits" );
	343
	344	assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and
	345	"ERROR: you must have X_WIDTH == Y_WIDTH == 4");
[792]	346
[621]	347	std::cout << std::endl;
	348
	349	std::cout << " - X_SIZE = " << X_SIZE << std::endl;
	350	std::cout << " - Y_SIZE = " << Y_SIZE << std::endl;
	351	std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
	352	std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
	353	std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
	354	std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
	355	std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
	356	std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
	357	std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
	358	std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
	359	std::cout << " - MAX_CYCLES = " << ncycles << std::endl;
	360	std::cout << " - RESET_ADDRESS = " << RESET_ADDRESS << std::endl;
[692]	361	std::cout << " - SOFT_FILENAME = " << soft_name << std::endl;
	362	std::cout << " - DISK_IMAGENAME = " << disk_name << std::endl;
	363	std::cout << " - OPENMP THREADS = " << threads << std::endl;
[621]	364
	365	std::cout << std::endl;
	366
	367	// Internal and External VCI parameters definition
	368	typedef soclib::caba::VciParams<vci_cell_width_int,
	369	vci_plen_width,
	370	vci_address_width,
	371	vci_rerror_width,
	372	vci_clen_width,
	373	vci_rflag_width,
	374	vci_srcid_width,
	375	vci_pktid_width,
	376	vci_trdid_width,
	377	vci_wrplen_width> vci_param_int;
	378
	379	typedef soclib::caba::VciParams<vci_cell_width_ext,
	380	vci_plen_width,
	381	vci_address_width,
	382	vci_rerror_width,
	383	vci_clen_width,
	384	vci_rflag_width,
	385	vci_srcid_width,
	386	vci_pktid_width,
	387	vci_trdid_width,
	388	vci_wrplen_width> vci_param_ext;
	389
	390	#if USE_OPENMP
	391	omp_set_dynamic(false);
[628]	392	omp_set_num_threads(threads);
[621]	393	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
	394	#endif
	395
	396
[628]	397	///////////////////////////////////////
	398	// Direct Network Mapping Table
	399	///////////////////////////////////////
[621]	400
[792]	401	MappingTable maptabd(vci_address_width,
	402	IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
	403	IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
[628]	404	0x00FF000000ULL);
[621]	405
[628]	406	// replicated segments
[621]	407	for (size_t x = 0; x < X_SIZE; x++)
	408	{
[681]	409	for (size_t y = 0; y < (Y_SIZE) ; y++)
[621]	410	{
	411	sc_uint<vci_address_width> offset;
[628]	412	offset = ((sc_uint<vci_address_width>)cluster(x,y)) << 32;
[621]	413
	414	std::ostringstream si;
	415	si << "seg_xicu_" << x << "_" << y;
[792]	416	maptabd.add(Segment(si.str(), SEG_XCU_BASE + offset, SEG_XCU_SIZE,
[621]	417	IntTab(cluster(x,y),XICU_TGTID), false));
	418
	419	std::ostringstream sd;
[628]	420	sd << "seg_mcfg_" << x << "_" << y;
[792]	421	maptabd.add(Segment(sd.str(), SEG_MMC_BASE + offset, SEG_MMC_SIZE,
[628]	422	IntTab(cluster(x,y),MEMC_TGTID), false));
[621]	423
	424	std::ostringstream sh;
	425	sh << "seg_memc_" << x << "_" << y;
[792]	426	maptabd.add(Segment(sh.str(), SEG_RAM_BASE + offset, SEG_RAM_SIZE,
[621]	427	IntTab(cluster(x,y),MEMC_TGTID), true));
	428	}
	429	}
[628]	430
[664]	431	// segments for peripherals in cluster(0,0)
[792]	432	maptabd.add(Segment("seg_tty0", SEG_TTY_BASE, SEG_TTY_SIZE,
[628]	433	IntTab(cluster(0,0),MTTY_TGTID), false));
	434
[792]	435	maptabd.add(Segment("seg_ioc0", SEG_IOC_BASE, SEG_IOC_SIZE,
[628]	436	IntTab(cluster(0,0),BDEV_TGTID), false));
	437
[681]	438	// segments for peripherals in cluster_io (X_SIZE-1,Y_SIZE)
[628]	439	sc_uint<vci_address_width> offset;
[681]	440	offset = ((sc_uint<vci_address_width>)cluster(X_SIZE-1,Y_SIZE)) << 32;
[628]	441
[792]	442	maptabd.add(Segment("seg_mtty", SEG_TTY_BASE + offset, SEG_TTY_SIZE,
[681]	443	IntTab(cluster(X_SIZE-1, Y_SIZE),MTTY_TGTID), false));
[628]	444
[792]	445	maptabd.add(Segment("seg_fbuf", SEG_FBF_BASE + offset, SEG_FBF_SIZE,
[681]	446	IntTab(cluster(X_SIZE-1, Y_SIZE),FBUF_TGTID), false));
[628]	447
[792]	448	maptabd.add(Segment("seg_bdev", SEG_IOC_BASE + offset, SEG_IOC_SIZE,
[681]	449	IntTab(cluster(X_SIZE-1, Y_SIZE),BDEV_TGTID), false));
[628]	450
[792]	451	maptabd.add(Segment("seg_mnic", SEG_NIC_BASE + offset, SEG_NIC_SIZE,
[681]	452	IntTab(cluster(X_SIZE-1, Y_SIZE),MNIC_TGTID), false));
[628]	453
[792]	454	maptabd.add(Segment("seg_cdma", SEG_CMA_BASE + offset, SEG_CMA_SIZE,
[681]	455	IntTab(cluster(X_SIZE-1, Y_SIZE),CDMA_TGTID), false));
[628]	456
[792]	457	maptabd.add(Segment("seg_iopi", SEG_PIC_BASE + offset, SEG_PIC_SIZE,
[681]	458	IntTab(cluster(X_SIZE-1, Y_SIZE),IOPI_TGTID), false));
[628]	459
[621]	460	std::cout << maptabd << std::endl;
	461
[628]	462	/////////////////////////////////////////////////
	463	// Ram network mapping table
	464	/////////////////////////////////////////////////
[621]	465
[792]	466	MappingTable maptabx(vci_address_width,
	467	IntTab(X_WIDTH+Y_WIDTH),
	468	IntTab(X_WIDTH+Y_WIDTH),
[628]	469	0x00FF000000ULL);
[621]	470
[628]	471	for (size_t x = 0; x < X_SIZE; x++)
	472	{
[681]	473	for (size_t y = 0; y < (Y_SIZE) ; y++)
[792]	474	{
[628]	475	sc_uint<vci_address_width> offset;
[792]	476	offset = (sc_uint<vci_address_width>)cluster(x,y)
[628]	477	<< (vci_address_width-X_WIDTH-Y_WIDTH);
[621]	478
[628]	479	std::ostringstream sh;
	480	sh << "x_seg_memc_" << x << "_" << y;
[621]	481
[792]	482	maptabx.add(Segment(sh.str(), SEG_RAM_BASE + offset,
	483	SEG_RAM_SIZE, IntTab(cluster(x,y)), false));
[628]	484	}
	485	}
	486	std::cout << maptabx << std::endl;
[621]	487
[628]	488	////////////////////
	489	// Signals
	490	///////////////////
[621]	491
[628]	492	sc_clock signal_clk("clk");
	493	sc_signal<bool> signal_resetn("resetn");
[621]	494
[628]	495	// IRQs from external peripherals
	496	sc_signal<bool> signal_irq_bdev;
	497	sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];
	498	sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];
[664]	499	sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS];
	500	// sc_signal<bool> signal_irq_mtty_tx[NB_TTY_CHANNELS];
[628]	501	sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS];
	502	sc_signal<bool> signal_irq_false;
	503
[621]	504	// Horizontal inter-clusters DSPIN signals
[628]	505	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc =
[681]	506	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE);
[628]	507	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec =
[681]	508	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE);
[621]	509
[628]	510	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc =
[681]	511	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE);
[628]	512	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec =
[681]	513	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE);
[628]	514
	515	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc =
[681]	516	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE-1, Y_SIZE);
[628]	517	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec =
[681]	518	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE-1, Y_SIZE);
[628]	519
	520	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc =
[681]	521	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE-1, Y_SIZE);
[628]	522	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec =
[681]	523	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE-1, Y_SIZE);
[628]	524
	525	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc =
[681]	526	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE-1, Y_SIZE);
[628]	527	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec =
[681]	528	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE-1, Y_SIZE);
[628]	529
[621]	530	// Vertical inter-clusters DSPIN signals
[628]	531	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc =
[681]	532	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1);
[628]	533	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec =
[681]	534	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1);
[621]	535
[628]	536	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc =
[681]	537	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1);
[628]	538	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec =
[681]	539	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1);
[621]	540
[628]	541	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc =
[681]	542	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE-1);
[628]	543	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec =
[681]	544	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE-1);
[621]	545
[628]	546	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc =
[681]	547	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE-1);
[628]	548	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec =
[681]	549	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE-1);
[628]	550
	551	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc =
[681]	552	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE-1);
[628]	553	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec =
[681]	554	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE-1);
[628]	555
	556	// Mesh boundaries DSPIN signals (Most of those signals are not used...)
	557	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in =
[681]	558	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , X_SIZE, Y_SIZE, 4);
[628]	559	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out =
[681]	560	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", X_SIZE, Y_SIZE, 4);
[628]	561
	562	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in =
[681]	563	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , X_SIZE, Y_SIZE, 4);
[628]	564	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out =
[681]	565	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", X_SIZE, Y_SIZE, 4);
[628]	566
	567	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in =
[681]	568	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , X_SIZE, Y_SIZE, 4);
[628]	569	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out =
[681]	570	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", X_SIZE, Y_SIZE, 4);
[628]	571
	572	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in =
[681]	573	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , X_SIZE, Y_SIZE, 4);
[628]	574	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out =
[681]	575	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", X_SIZE, Y_SIZE, 4);
[628]	576
	577	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in =
[681]	578	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , X_SIZE, Y_SIZE, 4);
[628]	579	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out =
[681]	580	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", X_SIZE, Y_SIZE, 4);
[628]	581
	582	// VCI signals for iobus and peripherals
	583	VciSignals<vci_param_int> signal_vci_ini_bdev("signal_vci_ini_bdev");
	584	VciSignals<vci_param_int> signal_vci_ini_cdma("signal_vci_ini_cdma");
	585	VciSignals<vci_param_int> signal_vci_ini_iopi("signal_vci_ini_iopi");
	586
[792]	587	VciSignals<vci_param_int>* signal_vci_ini_proc =
[628]	588	alloc_elems<VciSignals<vci_param_int> >("signal_vci_ini_proc", NB_PROCS_MAX );
	589
	590	VciSignals<vci_param_int> signal_vci_tgt_memc("signal_vci_tgt_memc");
	591	VciSignals<vci_param_int> signal_vci_tgt_xicu("signal_vci_tgt_xicu");
	592	VciSignals<vci_param_int> signal_vci_tgt_bdev("signal_vci_tgt_bdev");
	593	VciSignals<vci_param_int> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
	594	VciSignals<vci_param_int> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
	595	VciSignals<vci_param_int> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
	596	VciSignals<vci_param_int> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
	597	VciSignals<vci_param_int> signal_vci_tgt_iopi("signal_vci_tgt_iopi");
	598
	599	VciSignals<vci_param_int> signal_vci_cmd_to_noc("signal_vci_cmd_to_noc");
	600	VciSignals<vci_param_int> signal_vci_cmd_from_noc("signal_vci_cmd_from_noc");
[792]	601
[621]	602	////////////////////////////
[792]	603	// Loader
[621]	604	////////////////////////////
	605
[796]	606	#if USE_IOC_RDK
[795]	607	std::ostringstream ramdisk_name;
	608	ramdisk_name << disk_name << "@" << std::hex << SEG_RDK_BASE << ":";
	609	soclib::common::Loader loader( soft_name, ramdisk_name.str().c_str() );
[664]	610	#else
[692]	611	soclib::common::Loader loader( soft_name );
[664]	612	#endif
[708]	613	loader.memory_default(0xAA);
[621]	614
[630]	615	///////////////////////////
	616	// processor iss
	617	///////////////////////////
	618
[621]	619	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
[630]	620	proc_iss::set_loader( loader );
[621]	621
[664]	622	//////////////////////////////////////////////////////////////
[681]	623	// mesh construction: only (X_SIZE) * (Y_SIZE) clusters
[664]	624	//////////////////////////////////////////////////////////////
[621]	625
	626	TsarLetiCluster<dspin_cmd_width,
	627	dspin_rsp_width,
	628	vci_param_int,
[681]	629	vci_param_ext>* clusters[X_SIZE][Y_SIZE];
[621]	630
	631	#if USE_OPENMP
	632	#pragma omp parallel
	633	{
	634	#pragma omp for
	635	#endif
[681]	636	for (size_t i = 0; i < (X_SIZE * (Y_SIZE)); i++)
[621]	637	{
[681]	638	size_t x = i / (Y_SIZE);
	639	size_t y = i % (Y_SIZE);
[621]	640
	641	#if USE_OPENMP
	642	#pragma omp critical
	643	{
	644	#endif
	645	std::cout << std::endl;
[792]	646	std::cout << "Cluster_" << std::dec << x << "_" << y
[628]	647	<< " with cluster_xy = " << std::hex << cluster(x,y) << std::endl;
[621]	648	std::cout << std::endl;
	649
[664]	650	std::ostringstream cluster_name;
	651	cluster_name << "cluster_" << std::dec << x << "_" << y;
	652
[621]	653	clusters[x][y] = new TsarLetiCluster<dspin_cmd_width,
	654	dspin_rsp_width,
	655	vci_param_int,
	656	vci_param_ext>
	657	(
[664]	658	cluster_name.str().c_str(),
[621]	659	NB_PROCS_MAX,
	660	x,
	661	y,
	662	cluster(x,y),
	663	maptabd,
	664	maptabx,
	665	RESET_ADDRESS,
	666	X_WIDTH,
	667	Y_WIDTH,
	668	vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width,
[803]	669	P_WIDTH,
[621]	670	MEMC_TGTID,
	671	XICU_TGTID,
	672	MTTY_TGTID,
	673	BDEV_TGTID,
[692]	674	disk_name,
[621]	675	MEMC_WAYS,
	676	MEMC_SETS,
	677	L1_IWAYS,
	678	L1_ISETS,
	679	L1_DWAYS,
	680	L1_DSETS,
	681	XRAM_LATENCY,
	682	loader,
	683	frozen_cycles,
	684	trace_from,
[792]	685	trace_proc_ok,
[621]	686	trace_proc_id,
[792]	687	trace_memc_ok,
[621]	688	trace_memc_id
	689	);
	690
	691	#if USE_OPENMP
	692	} // end critical
	693	#endif
	694	} // end for
	695	#if USE_OPENMP
	696	}
	697	#endif
	698
[826]	699
	700	#if USE_PIC
[628]	701	//////////////////////////////////////////////////////////////////
	702	// IO bus and external peripherals in cluster[X_SIZE-1,Y_SIZE]
[664]	703	// - 6 local targets : FBF, TTY, CMA, NIC, PIC, IOC
	704	// - 3 local initiators : IOC, CMA, PIC
	705	// There is no PROC, no MEMC and no XICU in this cluster,
	706	// but the crossbar has (NB_PROCS_MAX + 3) intiators and
	707	// 8 targets, in order to use the same SRCID and TGTID space
[792]	708	// (same mapping table for the internal components,
	709	// and for the external peripherals)
[628]	710	//////////////////////////////////////////////////////////////////
[621]	711
[664]	712	std::cout << std::endl;
	713	std::cout << " Building IO cluster (external peripherals)" << std::endl;
	714	std::cout << std::endl;
[792]	715
[681]	716	size_t cluster_io = cluster(X_SIZE-1, Y_SIZE);
[621]	717
[792]	718	//////////// vci_local_crossbar
[628]	719	VciLocalCrossbar<vci_param_int>*
	720	iobus = new VciLocalCrossbar<vci_param_int>(
	721	"iobus",
	722	maptabd, // mapping table
	723	cluster_io, // cluster_xy
	724	NB_PROCS_MAX + 3, // number of local initiators
	725	8, // number of local targets
	726	BDEV_TGTID ); // default target index
[621]	727
[792]	728	//////////// vci_framebuffer
[628]	729	VciFrameBuffer<vci_param_int>*
	730	fbuf = new VciFrameBuffer<vci_param_int>(
	731	"fbuf",
	732	IntTab(cluster_io, FBUF_TGTID),
	733	maptabd,
	734	FBUF_X_SIZE, FBUF_Y_SIZE );
[621]	735
[792]	736	//////////// vci_block_device
[628]	737	VciBlockDeviceTsar<vci_param_int>*
	738	bdev = new VciBlockDeviceTsar<vci_param_int>(
	739	"bdev",
	740	maptabd,
	741	IntTab(cluster_io, BDEV_SRCID),
	742	IntTab(cluster_io, BDEV_TGTID),
[692]	743	disk_name,
[628]	744	512, // block size
	745	64 ); // burst size
	746
[792]	747	//////////// vci_multi_nic
[628]	748	VciMultiNic<vci_param_int>*
	749	mnic = new VciMultiNic<vci_param_int>(
[681]	750	"mnic",
[628]	751	IntTab(cluster_io, MNIC_TGTID),
	752	maptabd,
	753	NB_NIC_CHANNELS,
	754	NIC_MAC4,
	755	NIC_MAC2,
	756	NIC_RX_NAME,
	757	NIC_TX_NAME );
	758
[792]	759	///////////// vci_chbuf_dma
[628]	760	VciChbufDma<vci_param_int>*
	761	cdma = new VciChbufDma<vci_param_int>(
	762	"cdma",
	763	maptabd,
	764	IntTab(cluster_io, CDMA_SRCID),
	765	IntTab(cluster_io, CDMA_TGTID),
	766	64, // burst size
[792]	767	NB_CMA_CHANNELS );
[628]	768
	769	////////////// vci_multi_tty
	770	std::vector<std::string> vect_names;
	771	for (size_t id = 0; id < NB_TTY_CHANNELS; id++)
	772	{
	773	std::ostringstream term_name;
	774	term_name << "ext_" << id;
	775	vect_names.push_back(term_name.str().c_str());
	776	}
	777
[792]	778	VciMultiTty<vci_param_int>*
[628]	779	mtty = new VciMultiTty<vci_param_int>(
	780	"mtty",
	781	IntTab(cluster_io, MTTY_TGTID),
	782	maptabd,
	783	vect_names );
	784
	785	///////////// vci_iopic
	786	VciIopic<vci_param_int>*
	787	iopic = new VciIopic<vci_param_int>(
	788	"iopic",
	789	maptabd,
	790	IntTab(cluster_io, IOPI_SRCID),
	791	IntTab(cluster_io, IOPI_TGTID),
[792]	792	32 );
[628]	793
[792]	794	////////////// vci_dspin wrappers
[628]	795	VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
	796	wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
	797	"wt_bdev",
	798	vci_srcid_width );
	799
	800	VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
	801	wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
	802	"wi_bdev",
	803	vci_srcid_width );
	804
	805	///////////////////////////////////////////////////////////////
[792]	806	// Net-list
[628]	807	///////////////////////////////////////////////////////////////
	808
[792]	809	// iobus
	810	iobus->p_clk (signal_clk);
[628]	811	iobus->p_resetn (signal_resetn);
	812
	813	iobus->p_target_to_up (signal_vci_cmd_from_noc);
	814	iobus->p_initiator_to_up (signal_vci_cmd_to_noc);
	815
	816	iobus->p_to_target[MEMC_TGTID] (signal_vci_tgt_memc);
	817	iobus->p_to_target[XICU_TGTID] (signal_vci_tgt_xicu);
	818	iobus->p_to_target[MTTY_TGTID] (signal_vci_tgt_mtty);
	819	iobus->p_to_target[FBUF_TGTID] (signal_vci_tgt_fbuf);
	820	iobus->p_to_target[MNIC_TGTID] (signal_vci_tgt_mnic);
	821	iobus->p_to_target[BDEV_TGTID] (signal_vci_tgt_bdev);
	822	iobus->p_to_target[CDMA_TGTID] (signal_vci_tgt_cdma);
	823	iobus->p_to_target[IOPI_TGTID] (signal_vci_tgt_iopi);
	824
	825	for( size_t p=0 ; p<NB_PROCS_MAX ; p++ )
	826	{
	827	iobus->p_to_initiator[p] (signal_vci_ini_proc[p]);
	828	}
	829	iobus->p_to_initiator[BDEV_SRCID] (signal_vci_ini_bdev);
	830	iobus->p_to_initiator[CDMA_SRCID] (signal_vci_ini_cdma);
	831	iobus->p_to_initiator[IOPI_SRCID] (signal_vci_ini_iopi);
	832
	833	std::cout << " - IOBUS connected" << std::endl;
	834
	835	// block_device
	836	bdev->p_clk (signal_clk);
	837	bdev->p_resetn (signal_resetn);
	838	bdev->p_vci_target (signal_vci_tgt_bdev);
	839	bdev->p_vci_initiator (signal_vci_ini_bdev);
	840	bdev->p_irq (signal_irq_bdev);
	841
	842	std::cout << " - BDEV connected" << std::endl;
	843
	844	// frame_buffer
	845	fbuf->p_clk (signal_clk);
	846	fbuf->p_resetn (signal_resetn);
	847	fbuf->p_vci (signal_vci_tgt_fbuf);
	848
	849	std::cout << " - FBUF connected" << std::endl;
	850
	851	// multi_nic
	852	mnic->p_clk (signal_clk);
	853	mnic->p_resetn (signal_resetn);
	854	mnic->p_vci (signal_vci_tgt_mnic);
	855	for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ )
	856	{
	857	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
	858	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
	859	}
	860
	861	std::cout << " - MNIC connected" << std::endl;
	862
	863	// chbuf_dma
	864	cdma->p_clk (signal_clk);
	865	cdma->p_resetn (signal_resetn);
	866	cdma->p_vci_target (signal_vci_tgt_cdma);
	867	cdma->p_vci_initiator (signal_vci_ini_cdma);
	868	for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++)
	869	{
	870	cdma->p_irq[i] (signal_irq_cdma[i]);
	871	}
	872
	873	std::cout << " - CDMA connected" << std::endl;
	874
	875	// multi_tty
	876	mtty->p_clk (signal_clk);
	877	mtty->p_resetn (signal_resetn);
	878	mtty->p_vci (signal_vci_tgt_mtty);
	879	for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ )
	880	{
[664]	881	mtty->p_irq[i] (signal_irq_mtty_rx[i]);
[628]	882	}
	883
	884	std::cout << " - MTTY connected" << std::endl;
	885
	886	// iopic
[664]	887	// NB_NIC_CHANNELS <= 2
	888	// NB_CMA_CHANNELS <= 4
	889	// NB_TTY_CHANNELS <= 8
[628]	890	iopic->p_clk (signal_clk);
	891	iopic->p_resetn (signal_resetn);
	892	iopic->p_vci_target (signal_vci_tgt_iopi);
	893	iopic->p_vci_initiator (signal_vci_ini_iopi);
[664]	894	for ( size_t i=0 ; i<32 ; i++)
[628]	895	{
	896	if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]);
	897	else if(i < 2 ) iopic->p_hwi[i] (signal_irq_false);
	898	else if(i < 2+NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_tx[i-2]);
	899	else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false);
	900	else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]);
[664]	901	else if(i < 8) iopic->p_hwi[i] (signal_irq_false);
	902	else if(i == 8) iopic->p_hwi[i] (signal_irq_bdev);
	903	else if(i < 16) iopic->p_hwi[i] (signal_irq_false);
	904	else if(i < 16+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_rx[i-16]);
	905	else if(i < 24) iopic->p_hwi[i] (signal_irq_false);
	906	else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_false);
	907	// else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_tx[i-24]);
[628]	908	else iopic->p_hwi[i] (signal_irq_false);
	909	}
	910
[664]	911	std::cout << " - IOPIC connected" << std::endl;
	912
[628]	913	// vci/dspin wrappers
	914	wi_iobus->p_clk (signal_clk);
	915	wi_iobus->p_resetn (signal_resetn);
	916	wi_iobus->p_vci (signal_vci_cmd_to_noc);
[681]	917	wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[X_SIZE-1][Y_SIZE-1][NORTH]);
	918	wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[X_SIZE-1][Y_SIZE-1][NORTH]);
[628]	919
	920	// vci/dspin wrappers
	921	wt_iobus->p_clk (signal_clk);
	922	wt_iobus->p_resetn (signal_resetn);
	923	wt_iobus->p_vci (signal_vci_cmd_from_noc);
[681]	924	wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[X_SIZE-1][Y_SIZE-1][NORTH]);
	925	wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[X_SIZE-1][Y_SIZE-1][NORTH]);
[628]	926
[826]	927	#endif // USE_PIC
	928
[628]	929	// Clock & RESET for clusters
	930	for (size_t x = 0; x < (X_SIZE); x++)
	931	{
[681]	932	for (size_t y = 0; y < (Y_SIZE); y++)
[628]	933	{
	934	clusters[x][y]->p_clk (signal_clk);
	935	clusters[x][y]->p_resetn (signal_resetn);
	936	}
	937	}
	938
	939	// Inter Clusters horizontal connections
	940	if (X_SIZE > 1)
	941	{
	942	for (size_t x = 0; x < (X_SIZE-1); x++)
	943	{
[681]	944	for (size_t y = 0; y < (Y_SIZE); y++)
[628]	945	{
	946	clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]);
	947	clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]);
	948	clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]);
	949	clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]);
	950
	951	clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]);
	952	clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]);
	953	clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]);
	954	clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]);
	955
	956	clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]);
	957	clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]);
	958	clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]);
	959	clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]);
	960
	961	clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]);
	962	clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]);
	963	clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]);
	964	clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]);
	965
	966	clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]);
	967	clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]);
	968	clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]);
	969	clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]);
[621]	970	}
[628]	971	}
	972	}
[792]	973	std::cout << std::endl << "Horizontal connections done" << std::endl;
[621]	974
[628]	975	// Inter Clusters vertical connections
[792]	976	if (Y_SIZE > 1)
[628]	977	{
[681]	978	for (size_t y = 0; y < (Y_SIZE-1); y++)
[628]	979	{
	980	for (size_t x = 0; x < X_SIZE; x++)
	981	{
	982	clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]);
	983	clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]);
	984	clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]);
	985	clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]);
	986
	987	clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]);
	988	clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]);
	989	clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]);
	990	clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]);
	991
	992	clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]);
	993	clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]);
	994	clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]);
	995	clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]);
	996
	997	clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]);
	998	clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]);
	999	clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]);
	1000	clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]);
	1001
	1002	clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]);
	1003	clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]);
	1004	clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]);
	1005	clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]);
[621]	1006	}
[628]	1007	}
	1008	}
	1009	std::cout << std::endl << "Vertical connections done" << std::endl;
[621]	1010
[628]	1011	// East & West boundary cluster connections
[681]	1012	for (size_t y = 0; y < (Y_SIZE); y++)
[628]	1013	{
	1014	clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]);
	1015	clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]);
	1016	clusters[X_SIZE-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[X_SIZE-1][y][EAST]);
	1017	clusters[X_SIZE-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[X_SIZE-1][y][EAST]);
[621]	1018
[628]	1019	clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]);
	1020	clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]);
	1021	clusters[X_SIZE-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[X_SIZE-1][y][EAST]);
	1022	clusters[X_SIZE-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[X_SIZE-1][y][EAST]);
[621]	1023
[628]	1024	clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]);
	1025	clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]);
	1026	clusters[X_SIZE-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[X_SIZE-1][y][EAST]);
	1027	clusters[X_SIZE-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[X_SIZE-1][y][EAST]);
[621]	1028
[628]	1029	clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]);
	1030	clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]);
	1031	clusters[X_SIZE-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[X_SIZE-1][y][EAST]);
	1032	clusters[X_SIZE-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[X_SIZE-1][y][EAST]);
[621]	1033
[628]	1034	clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]);
	1035	clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]);
	1036	clusters[X_SIZE-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[X_SIZE-1][y][EAST]);
	1037	clusters[X_SIZE-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[X_SIZE-1][y][EAST]);
	1038	}
[621]	1039
[664]	1040	std::cout << std::endl << "West & East boundaries connections done" << std::endl;
	1041
[628]	1042	// North & South boundary clusters connections
	1043	for (size_t x = 0; x < X_SIZE; x++)
	1044	{
	1045	clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]);
	1046	clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]);
[681]	1047	clusters[x][Y_SIZE-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE-1][NORTH]);
	1048	clusters[x][Y_SIZE-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][Y_SIZE-1][NORTH]);
[621]	1049
[628]	1050	clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]);
	1051	clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]);
[681]	1052	clusters[x][Y_SIZE-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE-1][NORTH]);
	1053	clusters[x][Y_SIZE-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][Y_SIZE-1][NORTH]);
[621]	1054
[628]	1055	clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]);
	1056	clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]);
[681]	1057	clusters[x][Y_SIZE-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE-1][NORTH]);
	1058	clusters[x][Y_SIZE-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][Y_SIZE-1][NORTH]);
[621]	1059
[628]	1060	clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]);
	1061	clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]);
[681]	1062	clusters[x][Y_SIZE-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE-1][NORTH]);
	1063	clusters[x][Y_SIZE-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][Y_SIZE-1][NORTH]);
[628]	1064
	1065	clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]);
	1066	clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]);
[681]	1067	clusters[x][Y_SIZE-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE-1][NORTH]);
	1068	clusters[x][Y_SIZE-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][Y_SIZE-1][NORTH]);
[628]	1069	}
	1070
[664]	1071	std::cout << std::endl << "North & South boundaries connections done" << std::endl;
	1072
[628]	1073	std::cout << std::endl;
	1074
	1075	////////////////////////////////////////////////////////
	1076	// Simulation
	1077	///////////////////////////////////////////////////////
	1078
	1079	sc_start(sc_core::sc_time(0, SC_NS));
	1080	signal_resetn = false;
	1081	signal_irq_false = false;
	1082
	1083	// set network boundaries signals default values
	1084	// for all boundary clusters but the IO cluster
	1085	for (size_t x = 0; x < X_SIZE ; x++)
	1086	{
[681]	1087	for (size_t y = 0; y < Y_SIZE ; y++)
[628]	1088	{
	1089	for (size_t face = 0; face < 4; face++)
	1090	{
[681]	1091	if ( (x != X_SIZE-1) or (y != Y_SIZE-1) or (face != NORTH) )
[628]	1092	{
	1093	signal_dspin_bound_cmd_in [x][y][face].write = false;
	1094	signal_dspin_bound_cmd_in [x][y][face].read = true;
	1095	signal_dspin_bound_cmd_out[x][y][face].write = false;
	1096	signal_dspin_bound_cmd_out[x][y][face].read = true;
	1097
	1098	signal_dspin_bound_rsp_in [x][y][face].write = false;
	1099	signal_dspin_bound_rsp_in [x][y][face].read = true;
	1100	signal_dspin_bound_rsp_out[x][y][face].write = false;
	1101	signal_dspin_bound_rsp_out[x][y][face].read = true;
	1102	}
	1103
	1104	signal_dspin_bound_m2p_in [x][y][face].write = false;
	1105	signal_dspin_bound_m2p_in [x][y][face].read = true;
	1106	signal_dspin_bound_m2p_out[x][y][face].write = false;
	1107	signal_dspin_bound_m2p_out[x][y][face].read = true;
	1108
	1109	signal_dspin_bound_p2m_in [x][y][face].write = false;
	1110	signal_dspin_bound_p2m_in [x][y][face].read = true;
	1111	signal_dspin_bound_p2m_out[x][y][face].write = false;
	1112	signal_dspin_bound_p2m_out[x][y][face].read = true;
	1113
	1114	signal_dspin_bound_cla_in [x][y][face].write = false;
	1115	signal_dspin_bound_cla_in [x][y][face].read = true;
	1116	signal_dspin_bound_cla_out[x][y][face].write = false;
	1117	signal_dspin_bound_cla_out[x][y][face].read = true;
[621]	1118	}
[628]	1119	}
	1120	}
[621]	1121
[826]	1122	#if USE_PIC == 0
	1123	signal_dspin_bound_cmd_in[X_SIZE-1][Y_SIZE-1][NORTH].write = false;
	1124	signal_dspin_bound_rsp_out[X_SIZE-1][Y_SIZE-1][NORTH].read = true;
	1125	signal_dspin_bound_cmd_out[X_SIZE-1][Y_SIZE-1][NORTH].read = true;
	1126	signal_dspin_bound_rsp_in[X_SIZE-1][Y_SIZE-1][NORTH].write = false;
	1127	#endif
	1128
[792]	1129	// set default values for VCI signals connected to unused ports on iobus
[664]	1130	signal_vci_tgt_memc.rspval = false;
	1131	signal_vci_tgt_xicu.rspval = false;
	1132	for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) signal_vci_ini_proc[p].cmdval = false;
	1133
[628]	1134	sc_start(sc_core::sc_time(1, SC_NS));
	1135	signal_resetn = true;
[621]	1136
[792]	1137	if (gettimeofday(&t1, NULL) != 0)
[628]	1138	{
	1139	perror("gettimeofday");
	1140	return EXIT_FAILURE;
	1141	}
[621]	1142
[849]	1143	#if USE_PIC
[664]	1144	// variable used for IRQ trace
	1145	bool prev_irq_bdev = false;
	1146	bool prev_irq_mtty_rx[8];
	1147	bool prev_irq_proc[16][16][4];
[621]	1148
[664]	1149	for( size_t x = 0 ; x<8 ; x++ ) prev_irq_mtty_rx[x] = false;
[621]	1150
[664]	1151	for( size_t x = 0 ; x<16 ; x++ )
	1152	for( size_t y = 0 ; y<16 ; y++ )
	1153	for( size_t i = 0 ; i<4 ; i++ ) prev_irq_proc[x][y][i] = false;
[849]	1154	#endif
[621]	1155
[664]	1156	for (uint64_t n = 1; n < ncycles && !stop_called; n++)
	1157	{
	1158	// Monitor a specific address for L1 & L2 caches
	1159	// clusters[0][0]->proc[0]->cache_monitor(0x110002C078ULL);
	1160	// clusters[1][1]->memc->cache_monitor(0x110002c078ULL);
[621]	1161
[664]	1162	// stats display
	1163	if( (n % 5000000) == 0)
	1164	{
[621]	1165
[792]	1166	if (gettimeofday(&t2, NULL) != 0)
[664]	1167	{
	1168	perror("gettimeofday");
	1169	return EXIT_FAILURE;
	1170	}
[621]	1171
[664]	1172	ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
	1173	ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
[792]	1174	std::cerr << "platform clock frequency "
[664]	1175	<< (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl;
[621]	1176
[792]	1177	if (gettimeofday(&t1, NULL) != 0)
[664]	1178	{
	1179	perror("gettimeofday");
	1180	return EXIT_FAILURE;
	1181	}
	1182	}
[621]	1183
[664]	1184	// trace display
	1185	if ( trace_ok and (n > trace_from) )
	1186	{
	1187	std::cout << "****************** cycle " << std::dec << n ;
	1188	std::cout << " ************************************************" << std::endl;
[621]	1189
[664]	1190	size_t l = 0;
	1191	size_t x = 0;
	1192	size_t y = 0;
[621]	1193
[664]	1194	if ( trace_proc_ok )
	1195	{
[803]	1196	l = trace_proc_id & ((1<<P_WIDTH)-1) ;
	1197	x = (trace_proc_id >> P_WIDTH) >> Y_WIDTH ;
	1198	y = (trace_proc_id >> P_WIDTH) & ((1<<Y_WIDTH) - 1);
[621]	1199
[664]	1200	std::ostringstream proc_signame;
	1201	proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
[681]	1202	clusters[x][y]->proc[l]->print_trace(1);
[664]	1203	clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
[628]	1204
[664]	1205	std::ostringstream xicu_signame;
	1206	xicu_signame << "[SIG]XICU_" << x << "_" << y ;
	1207	clusters[x][y]->xicu->print_trace(0);
	1208	clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str());
	1209	}
[628]	1210
[664]	1211	if ( trace_memc_ok )
	1212	{
	1213	x = trace_memc_id >> Y_WIDTH;
	1214	y = trace_memc_id & ((1<<Y_WIDTH) - 1);
	1215
	1216	std::ostringstream smemc;
	1217	smemc << "[SIG]MEMC_" << x << "_" << y;
	1218	std::ostringstream sxram;
	1219	sxram << "[SIG]XRAM_" << x << "_" << y;
	1220
	1221	clusters[x][y]->memc->print_trace();
	1222	clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
	1223	clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
[792]	1224	}
[664]	1225
	1226	// trace coherence signals
	1227	// clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]");
	1228	// clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]");
	1229	// clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]");
	1230	// clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]");
	1231
	1232	// clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]");
	1233	// clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]");
	1234	// clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]");
	1235	// clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]");
	1236
	1237	// trace xbar(s) m2p
	1238	// clusters[0][0]->xbar_m2p->print_trace();
	1239	// clusters[1][0]->xbar_m2p->print_trace();
	1240	// clusters[0][1]->xbar_m2p->print_trace();
	1241	// clusters[1][1]->xbar_m2p->print_trace();
[792]	1242
[664]	1243	// trace router(s) m2p
	1244	// clusters[0][0]->router_m2p->print_trace();
	1245	// clusters[1][0]->router_m2p->print_trace();
	1246	// clusters[0][1]->router_m2p->print_trace();
	1247	// clusters[1][1]->router_m2p->print_trace();
[792]	1248
[826]	1249	#if USE_PIC
[664]	1250	// trace external ioc
	1251	bdev->print_trace();
	1252	signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT");
	1253	signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI");
[621]	1254
[664]	1255	// trace external iopic
	1256	iopic->print_trace();
	1257	signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT");
	1258	signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI");
[826]	1259	#endif
[621]	1260
[664]	1261	// trace internal tty
	1262	// clusters[0][0]->mtty->print_trace();
	1263	// clusters[0][0]->signal_vci_tgt_mtty.print_trace("[SIG]MTTY");
[628]	1264
[664]	1265	} // end trace
[621]	1266
[826]	1267	#if 0
	1268	#if USE_PIC
	1269	// trace BDV interrupts events
	1270	if ( signal_irq_bdev.read() != prev_irq_bdev )
[664]	1271	{
[826]	1272	prev_irq_bdev = signal_irq_bdev.read();
	1273	std::cout << std::dec << "@@@ IRQ_BDEV = " << signal_irq_bdev.read()
	1274	<< " at cycle " << n << std::endl;
	1275	}
[792]	1276
[826]	1277	// trace TTY interrupts events
	1278	for ( size_t x = 0 ; x < 8 ; x++ )
	1279	{
	1280	if ( signal_irq_mtty_rx[x].read() != prev_irq_mtty_rx[x] )
	1281	{
	1282	prev_irq_mtty_rx[x] = signal_irq_mtty_rx[x].read();
	1283	std::cout << std::dec << "@@@ IRQ_MTTY["<<x<<"] = "
	1284	<< signal_irq_mtty_rx[x].read()
	1285	<< " at cycle " << n << std::endl;
	1286	}
	1287	}
	1288	// trace VCI transactions on IOPIC and XCU(0,0)
	1289	signal_vci_tgt_iopi.print_trace("@@@ IOPI_TGT");
	1290	signal_vci_ini_iopi.print_trace("@@@ IOPI_INI");
	1291	#endif
[621]	1292
[826]	1293	// trace processor interrupts events
	1294	for ( size_t x = 0 ; x < X_SIZE ; x++ )
	1295	for ( size_t y = 0 ; y < Y_SIZE ; y++ )
	1296	for ( size_t i = 0 ; i < NB_PROCS_MAX ; i++ )
	1297	{
	1298	if ( clusters[x][y]->signal_proc_irq[i] != prev_irq_proc[x][y][i] )
	1299	{
[664]	1300	prev_irq_proc[x][y][i] = clusters[x][y]->signal_proc_irq[i];
	1301	std::cout << std::dec << "@@@ IRQ_PROC["<<x<<","<<y<<","<<i<<"] = "
[826]	1302	<< clusters[x][y]->signal_proc_irq[i]
	1303	<< " at cycle " << n << std::endl;
	1304	}
	1305	}
[664]	1306
[826]	1307	clusters[0][0]->signal_vci_tgt_xicu.print_trace("@@@ XCU_0_0");
	1308	#endif
[664]	1309
	1310	sc_start(sc_core::sc_time(1, SC_NS));
	1311	}
	1312	// Free memory
[681]	1313	for (size_t i = 0 ; i < (X_SIZE * Y_SIZE) ; i++)
[664]	1314	{
[681]	1315	size_t x = i / (Y_SIZE);
	1316	size_t y = i % (Y_SIZE);
[664]	1317	delete clusters[x][y];
	1318	}
	1319
	1320	return EXIT_SUCCESS;
[621]	1321	}
	1322
[792]	1323	void handler(int dummy = 0)
[628]	1324	{
[621]	1325	stop_called = true;
	1326	sc_stop();
	1327	}
	1328
	1329	void voidhandler(int dummy = 0) {}
	1330
	1331	int sc_main (int argc, char *argv[])
	1332	{
	1333	signal(SIGINT, handler);
	1334	signal(SIGPIPE, voidhandler);
	1335
	1336	try {
	1337	return _main(argc, argv);
	1338	} catch (std::exception &e) {
	1339	std::cout << e.what() << std::endl;
	1340	} catch (...) {
	1341	std::cout << "Unknown exception occured" << std::endl;
	1342	throw;
	1343	}
	1344	return 1;
	1345	}
	1346
	1347
	1348	// Local Variables:
	1349	// tab-width: 3
	1350	// c-basic-offset: 3
	1351	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	1352	// indent-tabs-mode: nil
	1353	// End:
	1354
	1355	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
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