Context Navigation

source: trunk/platforms/tsar_generic_leti/top.cpp @ 993

Last change on this file since 993 was 993, checked in by cfuguet, 9 years ago

Reintroduce the -SOFT and -DISK simulator arguments to pass the ROM code
and the DISK image respectively without the need of recompilation.

Remove the nic_tx_file when doing the "make clean" of the platform.

File size: 55.9 KB

Rev	Line
[621]	1	/////////////////////////////////////////////////////////////////////////
[967]	2	// File: top.cpp (for tsar_generic_leti platform)
[792]	3	// Author: Alain Greiner
[621]	4	// Copyright: UPMC/LIP6
[937]	5	// Date : february 2013 / updated january 2015
[621]	6	// This program is released under the GNU public license
	7	/////////////////////////////////////////////////////////////////////////
[681]	8	// This file define a generic TSAR architecture, fully compatible
	9	// with the VLSI Hardware prototype developped by CEA-LETI and LIP6
	10	// in the framework of the SHARP project.
[792]	11	//
[621]	12	// The processor is a MIPS32 processor wrapped in a GDB server
[967]	13	// (this is defined in the tsar_leti_cluster).
[792]	14	//
[937]	15	// The main hardware parameters are the mesh size (X_SIZE & Y_SIZE),
	16	// and the number of processors per cluster (NB_PROCS_MAX).
	17	// The NB_PROCS_MAX parameter cannot be larger than 4.
[967]	18	// Others parameters are the frame buffer size, the disk controller type
	19	// (BDV or HBA), the number of TTY channels, the number of NIC channels,
	20	// and the number of CMA channels.
[621]	21	//
[937]	22	// All external peripherals are located in cluster[X_SIZE-1][Y_SIZE-1],
	23	// and are connected to an IO bus (implemented as a vci_local_crossbar):
[967]	24	// - DISK : block device controller (BDV / HBA)
	25	// - MNIC : multi-channel ethernet controller
	26	// - CDMA : multi-channel chained buffer dma controller
	27	// - MTTY : multi-channel tty controller
	28	// - FBUF : frame buffer controller
	29	// - IOPI : HWI to SWI translator
	30	//
[937]	31	// This IO bus is directly connected to the north ports of the CMD/RSP
	32	// routers in cluster[X_SIZE-1][y_SIZE-2] through VCI/DSPIN wrappers.
	33	// All other clusters in the upper row are empty: no processors,
	34	// no ram, no routers.
	35	// The X_SIZE parameter must be larger than 0, but no larger than 16.
	36	// The Y_SIZE parameter must be larger than 1, but no larger than 16.
	37	//
	38	// We don't use an external ROM, as the boot code is (pre)loaded
	39	// in RAM in cluster[0][0] at address 0x0.
	40	//
	41	// An optional RAMDISK of 32 Mbytes can be used in RAM of cluster[0][0].
	42	//
[621]	43	// The physical address space is 40 bits.
	44	// The 8 address MSB bits define the cluster index.
	45	//
[937]	46	// Besides the processors, each cluster contains:
	47	// - 5 L1/L2 DSPIN routers implementing 5 separated NOCs
[628]	48	// - 1 vci_mem_cache
	49	// - 1 vci_xicu
[937]	50	// - 1 vci_simple_ram (to emulate the L3 cache).
[621]	51	//
[681]	52	// Each processor receives 4 consecutive IRQ lines from the local XICU.
[967]	53	// The number of PTI and WTI IRQs is bounded to 16.
[664]	54	//
[628]	55	// In all clusters, the MEMC IRQ line (signaling a late write error)
	56	// is connected to XICU HWI[8]
[621]	57	//
[628]	58	// For all external peripherals, the hardware interrupts (HWI) are
[664]	59	// translated to write interrupts (WTI) by the iopic component:
	60	// - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0]
[792]	61	// - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0]
[664]	62	// - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]]
[967]	63	// - IOPIC HWI[8] connected to IRQ_DISK
[664]	64	// - IOPIC HWI[15:9] unused (grounded)
	65	// - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]]
	66	// - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]]
[937]	67	//
	68	// The cluster internal architecture is defined in file tsar_leti_cluster,
	69	// that must be considered as an extension of this top.cpp file.
[628]	70	////////////////////////////////////////////////////////////////////////////
	71	// The following parameters must be defined in the hard_config.h file :
[621]	72	// - X_WIDTH : number of bits for x coordinate (must be 4)
	73	// - Y_WIDTH : number of bits for y coordinate (must be 4)
[967]	74	// - P_WIDTH : number of bits for local processor coordinate
[681]	75	// - X_SIZE : number of clusters in a row (1,2,4,8,16)
	76	// - Y_SIZE : number of clusters in a column (1,2,4,8)
[628]	77	// - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4)
[664]	78	// - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (4 max)
	79	// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (8 max)
[628]	80	// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max)
[937]	81	// - FBUF_X_SIZE : number of pixels per line for frame buffer
	82	// - FBUF_Y_SIZE : number of lines for frame buffer
[967]	83	// - XCU_NB_HWI : number of XCU HWIs (must be 16)
	84	// - XCU_NB_PTI : number of XCU PTIs (must be 16)
	85	// - XCU_NB_WTI : number of XCU WTIs (must be 16)
	86	// - XCU_NB_OUT : number of XCU output (must be 16)
	87	// - USE_IOC_XYZ : IOC type (XYZ in HBA / BDV / SDC / RDK)
[792]	88	//
[621]	89	// Some other hardware parameters are not used when compiling the OS,
[628]	90	// and are only defined in this top.cpp file:
[792]	91	// - XRAM_LATENCY : external ram latency
[628]	92	// - L1_IWAYS : L1 cache instruction number of ways
	93	// - L1_ISETS : L1 cache instruction number of sets
	94	// - L1_DWAYS : L1 cache data number of ways
	95	// - L1_DSETS : L1 cache data number of sets
[967]	96	// - DISK_IMAGE_NAME : pathname for block device disk image
[621]	97	/////////////////////////////////////////////////////////////////////////
	98	// General policy for 40 bits physical address decoding:
	99	// All physical segments base addresses are multiple of 1 Mbytes
[792]	100	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
[621]	101	// The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define
	102	// the cluster index, and the LADR bits define the local index:
	103	// \|X_ID\|Y_ID\| LADR \| OFFSET \|
	104	// \| 4 \| 4 \| 8 \| 24 \|
	105	/////////////////////////////////////////////////////////////////////////
	106	// General policy for 14 bits SRCID decoding:
	107	// Each component is identified by (x_id, y_id, l_id) tuple.
	108	// \|X_ID\|Y_ID\| L_ID \|
	109	// \| 4 \| 4 \| 6 \|
	110	/////////////////////////////////////////////////////////////////////////
	111
	112	#include <systemc>
	113	#include <sys/time.h>
	114	#include <iostream>
	115	#include <sstream>
	116	#include <cstdlib>
	117	#include <cstdarg>
	118	#include <stdint.h>
	119
	120	#include "gdbserver.h"
	121	#include "mapping_table.h"
[967]	122
[621]	123	#include "tsar_leti_cluster.h"
[628]	124	#include "vci_local_crossbar.h"
	125	#include "vci_dspin_initiator_wrapper.h"
	126	#include "vci_dspin_target_wrapper.h"
	127	#include "vci_multi_tty.h"
	128	#include "vci_multi_nic.h"
	129	#include "vci_chbuf_dma.h"
	130	#include "vci_block_device_tsar.h"
[967]	131	#include "vci_multi_ahci.h"
[628]	132	#include "vci_framebuffer.h"
	133	#include "vci_iopic.h"
[967]	134
[621]	135	#include "alloc_elems.h"
	136
[967]	137	///////////////////////////////////////////////////
	138	// Main hardware parameters values
	139	///////////////////////////////////////////////////
	140
[792]	141	#include "hard_config.h"
[621]	142
[967]	143	///////////////////////////////////////////////////////////////////////////////////////
	144	// Secondary Hardware Parameters
	145	///////////////////////////////////////////////////////////////////////////////////////
	146
	147	#define XMAX X_SIZE // actual number of columns in 2D mesh
	148	#define YMAX (Y_SIZE - 1) // actual number of rows in 2D mesh
	149
	150	#define XRAM_LATENCY 0
	151
	152	#define MEMC_WAYS 16
	153	#define MEMC_SETS 256
	154
	155	#define L1_IWAYS 4
	156	#define L1_ISETS 64
	157
	158	#define L1_DWAYS 4
	159	#define L1_DSETS 64
	160
	161	#define DISK_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg"
	162
	163	#define ROM_SOFT_NAME "../../softs/tsar_boot/preloader.elf"
	164
	165	#define NORTH 0
	166	#define SOUTH 1
	167	#define EAST 2
	168	#define WEST 3
	169
[621]	170	///////////////////////////////////////////////////
	171	// Parallelisation
	172	///////////////////////////////////////////////////
[967]	173
[708]	174	#define USE_OPENMP _OPENMP
[621]	175
	176	#if USE_OPENMP
	177	#include <omp.h>
	178	#endif
	179
	180	///////////////////////////////////////////////////
	181	// cluster index (from x,y coordinates)
	182	///////////////////////////////////////////////////
	183
[692]	184	#define cluster(x,y) ((y) + ((x) << Y_WIDTH))
[621]	185
	186	///////////////////////////////////////////////////////////
[792]	187	// DSPIN parameters
[621]	188	///////////////////////////////////////////////////////////
	189
	190	#define dspin_cmd_width 39
	191	#define dspin_rsp_width 32
	192
	193	///////////////////////////////////////////////////////////
[792]	194	// VCI parameters
[621]	195	///////////////////////////////////////////////////////////
	196
	197	#define vci_cell_width_int 4
	198	#define vci_cell_width_ext 8
	199	#define vci_address_width 40
	200	#define vci_plen_width 8
	201	#define vci_rerror_width 1
	202	#define vci_clen_width 1
	203	#define vci_rflag_width 1
	204	#define vci_srcid_width 14
	205	#define vci_pktid_width 4
	206	#define vci_trdid_width 4
	207	#define vci_wrplen_width 1
	208
	209
	210
[664]	211	///////////////////////////////////////////////////////////////////////////////////////
[792]	212	// DEBUG Parameters default values
[664]	213	///////////////////////////////////////////////////////////////////////////////////////
[621]	214
[681]	215	#define MAX_FROZEN_CYCLES 500000
[621]	216
[664]	217	///////////////////////////////////////////////////////////////////////////////////////
[792]	218	// LOCAL TGTID & SRCID definition
[621]	219	// For all components: global TGTID = global SRCID = cluster_index
[664]	220	///////////////////////////////////////////////////////////////////////////////////////
[621]	221
[664]	222	#define MEMC_TGTID 0
	223	#define XICU_TGTID 1
	224	#define MTTY_TGTID 2
[967]	225	#define DISK_TGTID 3
[664]	226	#define FBUF_TGTID 4
	227	#define MNIC_TGTID 5
	228	#define CDMA_TGTID 6
	229	#define IOPI_TGTID 7
[621]	230
[967]	231	#define DISK_SRCID NB_PROCS_MAX
[664]	232	#define CDMA_SRCID NB_PROCS_MAX + 1
	233	#define IOPI_SRCID NB_PROCS_MAX + 2
[628]	234
[621]	235	bool stop_called = false;
	236
	237	/////////////////////////////////
	238	int _main(int argc, char *argv[])
	239	{
	240	using namespace sc_core;
	241	using namespace soclib::caba;
	242	using namespace soclib::common;
	243
[937]	244	uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles
	245	size_t threads = 1; // simulator's threads number
	246	bool trace_ok = false; // trace activated
	247	uint32_t trace_from = 0; // trace start cycle
	248	bool trace_proc_ok = false; // detailed proc trace activated
	249	size_t trace_memc_ok = false; // detailed memc trace activated
	250	size_t trace_memc_id = 0; // index of memc to be traced
	251	size_t trace_proc_id = 0; // index of proc to be traced
	252	char soft_name[256] = ROM_SOFT_NAME; // pathname for ROM binary code
[967]	253	char disk_name[256] = DISK_IMAGE_NAME; // pathname for DISK image
[937]	254	uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // for debug
[621]	255	struct timeval t1,t2;
	256	uint64_t ms1,ms2;
	257
	258	////////////// command line arguments //////////////////////
	259	if (argc > 1)
	260	{
	261	for (int n = 1; n < argc; n = n + 2)
	262	{
	263	if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc))
	264	{
	265	ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0);
	266	}
[993]	267	else if ((strcmp(argv[n],"-SOFT") == 0) && (n + 1 < argc))
	268	{
	269	strcpy(soft_name, argv[n + 1]);
	270	}
	271	else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc))
	272	{
	273	strcpy(disk_name, argv[n + 1]);
	274	}
[621]	275	else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc))
	276	{
	277	trace_ok = true;
	278	trace_from = (uint32_t) strtol(argv[n + 1], NULL, 0);
	279	}
	280	else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc))
	281	{
	282	trace_memc_ok = true;
	283	trace_memc_id = (size_t) strtol(argv[n + 1], NULL, 0);
	284	size_t x = trace_memc_id >> Y_WIDTH;
	285	size_t y = trace_memc_id & ((1<<Y_WIDTH)-1);
	286
[937]	287	assert( (x < XMAX) and (y < (YMAX)) and
[967]	288	"MEMCID parameter doesxn't fit valid XMAX/YMAX");
[621]	289	}
	290	else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc))
	291	{
	292	trace_proc_ok = true;
	293	trace_proc_id = (size_t) strtol(argv[n + 1], NULL, 0);
[803]	294	size_t cluster_xy = trace_proc_id >> P_WIDTH ;
[621]	295	size_t x = cluster_xy >> Y_WIDTH;
	296	size_t y = cluster_xy & ((1<<Y_WIDTH)-1);
[803]	297	size_t l = trace_proc_id & ((1<<P_WIDTH)-1) ;
[621]	298
[937]	299	assert( (x < XMAX) and (y < YMAX) and (l < NB_PROCS_MAX) and
[621]	300	"PROCID parameter refers a not valid processor");
	301	}
	302	else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc))
	303	{
[628]	304	threads = (size_t) strtol(argv[n + 1], NULL, 0);
	305	threads = (threads < 1) ? 1 : threads;
[621]	306	}
	307	else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc))
	308	{
	309	frozen_cycles = (uint32_t) strtol(argv[n + 1], NULL, 0);
	310	}
	311	else
	312	{
	313	std::cout << " Arguments are (key,value) couples." << std::endl;
	314	std::cout << " The order is not important." << std::endl;
	315	std::cout << " Accepted arguments are :" << std::endl << std::endl;
[937]	316	std::cout << " - NCYCLES number_of_simulated_cycles" << std::endl;
	317	std::cout << " - DEBUG debug_start_cycle" << std::endl;
	318	std::cout << " - THREADS simulator's threads number" << std::endl;
	319	std::cout << " - FROZEN max_number_of_lines" << std::endl;
	320	std::cout << " - MEMCID index_memc_to_be_traced" << std::endl;
	321	std::cout << " - PROCID index_proc_to_be_traced" << std::endl;
[621]	322	exit(0);
	323	}
	324	}
	325	}
	326
	327	// checking hardware parameters
[937]	328	assert( ((X_SIZE <= 16) and (X_SIZE > 0)) and
[681]	329	"Illegal X_SIZE parameter" );
[621]	330
[937]	331	assert( ((Y_SIZE <= 16) and (Y_SIZE > 1)) and
[681]	332	"Illegal Y_SIZE parameter" );
[621]	333
[803]	334	assert( (P_WIDTH <= 2) and
	335	"P_WIDTH parameter cannot be larger than 2" );
	336
[664]	337	assert( (NB_PROCS_MAX <= 4) and
[681]	338	"Illegal NB_PROCS_MAX parameter" );
[621]	339
[967]	340	assert( (XCU_NB_HWI == 16) and
	341	"XCU_NB_HWI must be 16" );
	342
	343	assert( (XCU_NB_PTI == 16) and
	344	"XCU_NB_PTI must be 16" );
	345
	346	assert( (XCU_NB_WTI == 16) and
	347	"XCU_NB_WTI must be 16" );
	348
	349	assert( (XCU_NB_OUT == 16) and
	350	"XCU_NB_OUT must be 16" );
	351
[937]	352	assert( (NB_CMA_CHANNELS <= 4) and
[628]	353	"The NB_CMA_CHANNELS parameter cannot be larger than 4" );
[621]	354
[937]	355	assert( (NB_TTY_CHANNELS <= 8) and
[967]	356	"The NB_TTY_CHANNELS parameter cannot be larger than 8" );
[621]	357
[937]	358	assert( (NB_NIC_CHANNELS <= 2) and
[628]	359	"The NB_NIC_CHANNELS parameter cannot be larger than 2" );
[621]	360
	361	assert( (vci_address_width == 40) and
	362	"VCI address width with the GIET must be 40 bits" );
	363
	364	assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and
[937]	365	"You must have X_WIDTH == Y_WIDTH == 4");
[792]	366
[621]	367	std::cout << std::endl;
	368
[967]	369	std::cout << " - XMAX = " << XMAX << std::endl
	370	<< " - YMAX = " << YMAX << std::endl
	371	<< " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl
	372	<< " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl
	373	<< " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl
	374	<< " - NB_CMA_CHANNELS = " << NB_CMA_CHANNELS << std::endl
	375	<< " - MEMC_WAYS = " << MEMC_WAYS << std::endl
	376	<< " - MEMC_SETS = " << MEMC_SETS << std::endl
	377	<< " - RAM_LATENCY = " << XRAM_LATENCY << std::endl
	378	<< " - MAX_FROZEN = " << frozen_cycles << std::endl
	379	<< " - MAX_CYCLES = " << ncycles << std::endl
	380	<< " - RESET_ADDRESS = " << RESET_ADDRESS << std::endl
	381	<< " - SOFT_FILENAME = " << soft_name << std::endl
	382	<< " - DISK_IMAGENAME = " << disk_name << std::endl
	383	<< " - OPENMP THREADS = " << threads << std::endl
	384	<< " - DEBUG_PROCID = " << trace_proc_id << std::endl
	385	<< " - DEBUG_MEMCID = " << trace_memc_id << std::endl;
[621]	386
	387	std::cout << std::endl;
	388
	389	// Internal and External VCI parameters definition
	390	typedef soclib::caba::VciParams<vci_cell_width_int,
	391	vci_plen_width,
	392	vci_address_width,
	393	vci_rerror_width,
	394	vci_clen_width,
	395	vci_rflag_width,
	396	vci_srcid_width,
	397	vci_pktid_width,
	398	vci_trdid_width,
	399	vci_wrplen_width> vci_param_int;
	400
	401	typedef soclib::caba::VciParams<vci_cell_width_ext,
	402	vci_plen_width,
	403	vci_address_width,
	404	vci_rerror_width,
	405	vci_clen_width,
	406	vci_rflag_width,
	407	vci_srcid_width,
	408	vci_pktid_width,
	409	vci_trdid_width,
	410	vci_wrplen_width> vci_param_ext;
	411
	412	#if USE_OPENMP
	413	omp_set_dynamic(false);
[628]	414	omp_set_num_threads(threads);
[621]	415	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
	416	#endif
	417
	418
[628]	419	///////////////////////////////////////
	420	// Direct Network Mapping Table
	421	///////////////////////////////////////
[621]	422
[792]	423	MappingTable maptabd(vci_address_width,
	424	IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
	425	IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
[628]	426	0x00FF000000ULL);
[621]	427
[628]	428	// replicated segments
[937]	429	for (size_t x = 0; x < XMAX; x++)
[621]	430	{
[937]	431	for (size_t y = 0; y < (YMAX) ; y++)
[621]	432	{
	433	sc_uint<vci_address_width> offset;
[628]	434	offset = ((sc_uint<vci_address_width>)cluster(x,y)) << 32;
[621]	435
	436	std::ostringstream si;
	437	si << "seg_xicu_" << x << "_" << y;
[792]	438	maptabd.add(Segment(si.str(), SEG_XCU_BASE + offset, SEG_XCU_SIZE,
[621]	439	IntTab(cluster(x,y),XICU_TGTID), false));
	440
	441	std::ostringstream sd;
[628]	442	sd << "seg_mcfg_" << x << "_" << y;
[792]	443	maptabd.add(Segment(sd.str(), SEG_MMC_BASE + offset, SEG_MMC_SIZE,
[628]	444	IntTab(cluster(x,y),MEMC_TGTID), false));
[621]	445
	446	std::ostringstream sh;
	447	sh << "seg_memc_" << x << "_" << y;
[792]	448	maptabd.add(Segment(sh.str(), SEG_RAM_BASE + offset, SEG_RAM_SIZE,
[621]	449	IntTab(cluster(x,y),MEMC_TGTID), true));
	450	}
	451	}
[628]	452
[664]	453	// segments for peripherals in cluster(0,0)
[792]	454	maptabd.add(Segment("seg_tty0", SEG_TTY_BASE, SEG_TTY_SIZE,
[628]	455	IntTab(cluster(0,0),MTTY_TGTID), false));
	456
[792]	457	maptabd.add(Segment("seg_ioc0", SEG_IOC_BASE, SEG_IOC_SIZE,
[967]	458	IntTab(cluster(0,0),DISK_TGTID), false));
[628]	459
[937]	460	// segments for peripherals in cluster_io (XMAX-1,YMAX)
[628]	461	sc_uint<vci_address_width> offset;
[937]	462	offset = ((sc_uint<vci_address_width>)cluster(XMAX-1,YMAX)) << 32;
[628]	463
[792]	464	maptabd.add(Segment("seg_mtty", SEG_TTY_BASE + offset, SEG_TTY_SIZE,
[937]	465	IntTab(cluster(XMAX-1, YMAX),MTTY_TGTID), false));
[628]	466
[792]	467	maptabd.add(Segment("seg_fbuf", SEG_FBF_BASE + offset, SEG_FBF_SIZE,
[937]	468	IntTab(cluster(XMAX-1, YMAX),FBUF_TGTID), false));
[628]	469
[967]	470	maptabd.add(Segment("seg_disk", SEG_IOC_BASE + offset, SEG_IOC_SIZE,
	471	IntTab(cluster(XMAX-1, YMAX),DISK_TGTID), false));
[628]	472
[792]	473	maptabd.add(Segment("seg_mnic", SEG_NIC_BASE + offset, SEG_NIC_SIZE,
[937]	474	IntTab(cluster(XMAX-1, YMAX),MNIC_TGTID), false));
[628]	475
[792]	476	maptabd.add(Segment("seg_cdma", SEG_CMA_BASE + offset, SEG_CMA_SIZE,
[937]	477	IntTab(cluster(XMAX-1, YMAX),CDMA_TGTID), false));
[628]	478
[792]	479	maptabd.add(Segment("seg_iopi", SEG_PIC_BASE + offset, SEG_PIC_SIZE,
[937]	480	IntTab(cluster(XMAX-1, YMAX),IOPI_TGTID), false));
[628]	481
[621]	482	std::cout << maptabd << std::endl;
	483
[628]	484	/////////////////////////////////////////////////
	485	// Ram network mapping table
	486	/////////////////////////////////////////////////
[621]	487
[792]	488	MappingTable maptabx(vci_address_width,
	489	IntTab(X_WIDTH+Y_WIDTH),
	490	IntTab(X_WIDTH+Y_WIDTH),
[628]	491	0x00FF000000ULL);
[621]	492
[937]	493	for (size_t x = 0; x < XMAX; x++)
[628]	494	{
[937]	495	for (size_t y = 0; y < (YMAX) ; y++)
[792]	496	{
[628]	497	sc_uint<vci_address_width> offset;
[792]	498	offset = (sc_uint<vci_address_width>)cluster(x,y)
[628]	499	<< (vci_address_width-X_WIDTH-Y_WIDTH);
[621]	500
[628]	501	std::ostringstream sh;
	502	sh << "x_seg_memc_" << x << "_" << y;
[621]	503
[792]	504	maptabx.add(Segment(sh.str(), SEG_RAM_BASE + offset,
	505	SEG_RAM_SIZE, IntTab(cluster(x,y)), false));
[628]	506	}
	507	}
	508	std::cout << maptabx << std::endl;
[621]	509
[628]	510	////////////////////
	511	// Signals
	512	///////////////////
[621]	513
[628]	514	sc_clock signal_clk("clk");
	515	sc_signal<bool> signal_resetn("resetn");
[621]	516
[628]	517	// IRQs from external peripherals
[967]	518	sc_signal<bool> signal_irq_disk;
[628]	519	sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];
	520	sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];
[664]	521	sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS];
[628]	522	sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS];
	523	sc_signal<bool> signal_irq_false;
	524
[621]	525	// Horizontal inter-clusters DSPIN signals
[628]	526	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc =
[937]	527	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX);
[628]	528	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec =
[937]	529	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX);
[621]	530
[628]	531	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc =
[937]	532	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX);
[628]	533	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec =
[937]	534	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX);
[628]	535
	536	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc =
[937]	537	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", XMAX-1, YMAX);
[628]	538	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec =
[937]	539	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", XMAX-1, YMAX);
[628]	540
	541	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc =
[937]	542	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", XMAX-1, YMAX);
[628]	543	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec =
[937]	544	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", XMAX-1, YMAX);
[628]	545
	546	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc =
[937]	547	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", XMAX-1, YMAX);
[628]	548	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec =
[937]	549	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", XMAX-1, YMAX);
[628]	550
[621]	551	// Vertical inter-clusters DSPIN signals
[628]	552	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc =
[937]	553	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1);
[628]	554	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec =
[937]	555	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1);
[621]	556
[628]	557	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc =
[937]	558	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1);
[628]	559	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec =
[937]	560	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1);
[621]	561
[628]	562	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc =
[937]	563	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", XMAX, YMAX-1);
[628]	564	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec =
[937]	565	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", XMAX, YMAX-1);
[621]	566
[628]	567	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc =
[937]	568	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", XMAX, YMAX-1);
[628]	569	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec =
[937]	570	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", XMAX, YMAX-1);
[628]	571
	572	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc =
[937]	573	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", XMAX, YMAX-1);
[628]	574	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec =
[937]	575	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", XMAX, YMAX-1);
[628]	576
	577	// Mesh boundaries DSPIN signals (Most of those signals are not used...)
	578	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in =
[937]	579	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , XMAX, YMAX, 4);
[628]	580	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out =
[937]	581	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", XMAX, YMAX, 4);
[628]	582
	583	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in =
[937]	584	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , XMAX, YMAX, 4);
[628]	585	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out =
[937]	586	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", XMAX, YMAX, 4);
[628]	587
	588	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in =
[937]	589	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , XMAX, YMAX, 4);
[628]	590	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out =
[937]	591	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", XMAX, YMAX, 4);
[628]	592
	593	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in =
[937]	594	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , XMAX, YMAX, 4);
[628]	595	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out =
[937]	596	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", XMAX, YMAX, 4);
[628]	597
	598	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in =
[937]	599	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , XMAX, YMAX, 4);
[628]	600	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out =
[937]	601	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", XMAX, YMAX, 4);
[628]	602
	603	// VCI signals for iobus and peripherals
[967]	604	VciSignals<vci_param_int> signal_vci_ini_disk("signal_vci_ini_disk");
[628]	605	VciSignals<vci_param_int> signal_vci_ini_cdma("signal_vci_ini_cdma");
	606	VciSignals<vci_param_int> signal_vci_ini_iopi("signal_vci_ini_iopi");
	607
[792]	608	VciSignals<vci_param_int>* signal_vci_ini_proc =
[628]	609	alloc_elems<VciSignals<vci_param_int> >("signal_vci_ini_proc", NB_PROCS_MAX );
	610
	611	VciSignals<vci_param_int> signal_vci_tgt_memc("signal_vci_tgt_memc");
	612	VciSignals<vci_param_int> signal_vci_tgt_xicu("signal_vci_tgt_xicu");
[967]	613	VciSignals<vci_param_int> signal_vci_tgt_disk("signal_vci_tgt_disk");
[628]	614	VciSignals<vci_param_int> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
	615	VciSignals<vci_param_int> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
	616	VciSignals<vci_param_int> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
	617	VciSignals<vci_param_int> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
	618	VciSignals<vci_param_int> signal_vci_tgt_iopi("signal_vci_tgt_iopi");
	619
	620	VciSignals<vci_param_int> signal_vci_cmd_to_noc("signal_vci_cmd_to_noc");
	621	VciSignals<vci_param_int> signal_vci_cmd_from_noc("signal_vci_cmd_from_noc");
[792]	622
[621]	623	////////////////////////////
[792]	624	// Loader
[621]	625	////////////////////////////
	626
[796]	627	#if USE_IOC_RDK
[795]	628	std::ostringstream ramdisk_name;
	629	ramdisk_name << disk_name << "@" << std::hex << SEG_RDK_BASE << ":";
	630	soclib::common::Loader loader( soft_name, ramdisk_name.str().c_str() );
[664]	631	#else
[692]	632	soclib::common::Loader loader( soft_name );
[664]	633	#endif
[937]	634
[939]	635	loader.memory_default(0x55);
[621]	636
	637	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
[630]	638	proc_iss::set_loader( loader );
[621]	639
[664]	640	//////////////////////////////////////////////////////////////
[937]	641	// mesh construction: XMAX * YMAX clusters
[664]	642	//////////////////////////////////////////////////////////////
[621]	643
	644	TsarLetiCluster<dspin_cmd_width,
	645	dspin_rsp_width,
	646	vci_param_int,
[937]	647	vci_param_ext>* clusters[XMAX][YMAX];
[621]	648
	649	#if USE_OPENMP
	650	#pragma omp parallel
	651	{
	652	#pragma omp for
	653	#endif
[937]	654	for (size_t i = 0; i < (XMAX * YMAX); i++)
[621]	655	{
[937]	656	size_t x = i / (YMAX);
	657	size_t y = i % (YMAX);
[621]	658
	659	#if USE_OPENMP
	660	#pragma omp critical
	661	{
	662	#endif
	663	std::cout << std::endl;
[792]	664	std::cout << "Cluster_" << std::dec << x << "_" << y
[628]	665	<< " with cluster_xy = " << std::hex << cluster(x,y) << std::endl;
[621]	666	std::cout << std::endl;
	667
[664]	668	std::ostringstream cluster_name;
	669	cluster_name << "cluster_" << std::dec << x << "_" << y;
	670
[621]	671	clusters[x][y] = new TsarLetiCluster<dspin_cmd_width,
	672	dspin_rsp_width,
	673	vci_param_int,
	674	vci_param_ext>
	675	(
[664]	676	cluster_name.str().c_str(),
[621]	677	NB_PROCS_MAX,
	678	x,
	679	y,
	680	cluster(x,y),
	681	maptabd,
	682	maptabx,
	683	RESET_ADDRESS,
	684	X_WIDTH,
	685	Y_WIDTH,
	686	vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width,
[803]	687	P_WIDTH,
[621]	688	MEMC_TGTID,
	689	XICU_TGTID,
	690	MTTY_TGTID,
[967]	691	DISK_TGTID,
[692]	692	disk_name,
[621]	693	MEMC_WAYS,
	694	MEMC_SETS,
	695	L1_IWAYS,
	696	L1_ISETS,
	697	L1_DWAYS,
	698	L1_DSETS,
	699	XRAM_LATENCY,
	700	loader,
	701	frozen_cycles,
	702	trace_from,
[792]	703	trace_proc_ok,
[621]	704	trace_proc_id,
[792]	705	trace_memc_ok,
[621]	706	trace_memc_id
	707	);
	708
	709	#if USE_OPENMP
	710	} // end critical
	711	#endif
	712	} // end for
	713	#if USE_OPENMP
	714	}
	715	#endif
	716
[937]	717	#if USE_PIC
[826]	718
[628]	719	//////////////////////////////////////////////////////////////////
[937]	720	// IO bus and external peripherals in cluster[X_SIZE-1][Y_SIZE-1]
[664]	721	// - 6 local targets : FBF, TTY, CMA, NIC, PIC, IOC
	722	// - 3 local initiators : IOC, CMA, PIC
	723	// There is no PROC, no MEMC and no XICU in this cluster,
	724	// but the crossbar has (NB_PROCS_MAX + 3) intiators and
	725	// 8 targets, in order to use the same SRCID and TGTID space
[792]	726	// (same mapping table for the internal components,
	727	// and for the external peripherals)
[628]	728	//////////////////////////////////////////////////////////////////
[621]	729
[664]	730	std::cout << std::endl;
	731	std::cout << " Building IO cluster (external peripherals)" << std::endl;
	732	std::cout << std::endl;
[792]	733
[937]	734	size_t cluster_io = cluster(XMAX-1, YMAX);
[621]	735
[792]	736	//////////// vci_local_crossbar
[628]	737	VciLocalCrossbar<vci_param_int>*
	738	iobus = new VciLocalCrossbar<vci_param_int>(
	739	"iobus",
	740	maptabd, // mapping table
	741	cluster_io, // cluster_xy
	742	NB_PROCS_MAX + 3, // number of local initiators
	743	8, // number of local targets
[967]	744	DISK_TGTID ); // default target index
[621]	745
[792]	746	//////////// vci_framebuffer
[628]	747	VciFrameBuffer<vci_param_int>*
	748	fbuf = new VciFrameBuffer<vci_param_int>(
	749	"fbuf",
	750	IntTab(cluster_io, FBUF_TGTID),
	751	maptabd,
	752	FBUF_X_SIZE, FBUF_Y_SIZE );
[621]	753
[967]	754	#if ( USE_IOC_HBA )
	755
	756	//////////// vci_multi_ahci
	757	std::vector<std::string> filenames;
	758	filenames.push_back(disk_name); // one single disk
	759	VciMultiAhci<vci_param_int>*
	760	disk = new VciMultiAhci<vci_param_int>(
	761	"disk",
	762	maptabd,
	763	IntTab(cluster_io, DISK_SRCID),
	764	IntTab(cluster_io, DISK_TGTID),
	765	filenames,
	766	512, // block size
	767	64, // burst size (bytes)
	768	0 ); // disk latency
	769
	770	#elif ( USE_IOC_BDV or USE_IOC_SDC )
	771
[792]	772	//////////// vci_block_device
[628]	773	VciBlockDeviceTsar<vci_param_int>*
[967]	774	disk = new VciBlockDeviceTsar<vci_param_int>(
	775	"disk",
[628]	776	maptabd,
[967]	777	IntTab(cluster_io, DISK_SRCID),
	778	IntTab(cluster_io, DISK_TGTID),
[692]	779	disk_name,
[628]	780	512, // block size
[967]	781	64, // burst size (bytes)
	782	0 ); // disk latency
	783	#endif
[628]	784
[792]	785	//////////// vci_multi_nic
[628]	786	VciMultiNic<vci_param_int>*
	787	mnic = new VciMultiNic<vci_param_int>(
[681]	788	"mnic",
[628]	789	IntTab(cluster_io, MNIC_TGTID),
	790	maptabd,
	791	NB_NIC_CHANNELS,
[937]	792	0, // default MAC_4 address
	793	0, // default MAC_2 address
	794	1 ); // NIC_MODE_SYNTHESIS
[628]	795
[792]	796	///////////// vci_chbuf_dma
[628]	797	VciChbufDma<vci_param_int>*
	798	cdma = new VciChbufDma<vci_param_int>(
	799	"cdma",
	800	maptabd,
	801	IntTab(cluster_io, CDMA_SRCID),
	802	IntTab(cluster_io, CDMA_TGTID),
[937]	803	64, // burst size
[792]	804	NB_CMA_CHANNELS );
[628]	805
	806	////////////// vci_multi_tty
	807	std::vector<std::string> vect_names;
	808	for (size_t id = 0; id < NB_TTY_CHANNELS; id++)
	809	{
	810	std::ostringstream term_name;
	811	term_name << "ext_" << id;
	812	vect_names.push_back(term_name.str().c_str());
	813	}
	814
[792]	815	VciMultiTty<vci_param_int>*
[628]	816	mtty = new VciMultiTty<vci_param_int>(
	817	"mtty",
	818	IntTab(cluster_io, MTTY_TGTID),
	819	maptabd,
	820	vect_names );
	821
	822	///////////// vci_iopic
	823	VciIopic<vci_param_int>*
	824	iopic = new VciIopic<vci_param_int>(
	825	"iopic",
	826	maptabd,
	827	IntTab(cluster_io, IOPI_SRCID),
	828	IntTab(cluster_io, IOPI_TGTID),
[792]	829	32 );
[628]	830
[792]	831	////////////// vci_dspin wrappers
[628]	832	VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
	833	wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
[937]	834	"wt_iobus",
[628]	835	vci_srcid_width );
	836
	837	VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
	838	wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
[937]	839	"wi_iobus",
[628]	840	vci_srcid_width );
	841
	842	///////////////////////////////////////////////////////////////
[937]	843	// IObus Net-list
[628]	844	///////////////////////////////////////////////////////////////
	845
[792]	846	// iobus
	847	iobus->p_clk (signal_clk);
[628]	848	iobus->p_resetn (signal_resetn);
	849
	850	iobus->p_target_to_up (signal_vci_cmd_from_noc);
	851	iobus->p_initiator_to_up (signal_vci_cmd_to_noc);
	852
	853	iobus->p_to_target[MEMC_TGTID] (signal_vci_tgt_memc);
	854	iobus->p_to_target[XICU_TGTID] (signal_vci_tgt_xicu);
	855	iobus->p_to_target[MTTY_TGTID] (signal_vci_tgt_mtty);
	856	iobus->p_to_target[FBUF_TGTID] (signal_vci_tgt_fbuf);
	857	iobus->p_to_target[MNIC_TGTID] (signal_vci_tgt_mnic);
[967]	858	iobus->p_to_target[DISK_TGTID] (signal_vci_tgt_disk);
[628]	859	iobus->p_to_target[CDMA_TGTID] (signal_vci_tgt_cdma);
	860	iobus->p_to_target[IOPI_TGTID] (signal_vci_tgt_iopi);
	861
	862	for( size_t p=0 ; p<NB_PROCS_MAX ; p++ )
	863	{
	864	iobus->p_to_initiator[p] (signal_vci_ini_proc[p]);
	865	}
[967]	866	iobus->p_to_initiator[DISK_SRCID] (signal_vci_ini_disk);
[628]	867	iobus->p_to_initiator[CDMA_SRCID] (signal_vci_ini_cdma);
	868	iobus->p_to_initiator[IOPI_SRCID] (signal_vci_ini_iopi);
	869
	870	std::cout << " - IOBUS connected" << std::endl;
	871
[967]	872	// disk
	873	disk->p_clk (signal_clk);
	874	disk->p_resetn (signal_resetn);
	875	disk->p_vci_target (signal_vci_tgt_disk);
	876	disk->p_vci_initiator (signal_vci_ini_disk);
	877	#if USE_IOC_HBA
	878	disk->p_channel_irq[0] (signal_irq_disk);
	879	#else
	880	disk->p_irq (signal_irq_disk);
	881	#endif
[628]	882
[967]	883	std::cout << " - DISK connected" << std::endl;
[628]	884
	885	// frame_buffer
	886	fbuf->p_clk (signal_clk);
	887	fbuf->p_resetn (signal_resetn);
	888	fbuf->p_vci (signal_vci_tgt_fbuf);
	889
	890	std::cout << " - FBUF connected" << std::endl;
	891
	892	// multi_nic
	893	mnic->p_clk (signal_clk);
	894	mnic->p_resetn (signal_resetn);
	895	mnic->p_vci (signal_vci_tgt_mnic);
	896	for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ )
	897	{
	898	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
	899	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
	900	}
	901
	902	std::cout << " - MNIC connected" << std::endl;
	903
	904	// chbuf_dma
	905	cdma->p_clk (signal_clk);
	906	cdma->p_resetn (signal_resetn);
	907	cdma->p_vci_target (signal_vci_tgt_cdma);
	908	cdma->p_vci_initiator (signal_vci_ini_cdma);
	909	for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++)
	910	{
	911	cdma->p_irq[i] (signal_irq_cdma[i]);
	912	}
	913
	914	std::cout << " - CDMA connected" << std::endl;
	915
	916	// multi_tty
	917	mtty->p_clk (signal_clk);
	918	mtty->p_resetn (signal_resetn);
	919	mtty->p_vci (signal_vci_tgt_mtty);
	920	for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ )
	921	{
[664]	922	mtty->p_irq[i] (signal_irq_mtty_rx[i]);
[628]	923	}
	924
	925	std::cout << " - MTTY connected" << std::endl;
	926
	927	// iopic
[664]	928	// NB_NIC_CHANNELS <= 2
	929	// NB_CMA_CHANNELS <= 4
[937]	930	// NB_TTY_CHANNELS <= 16
[628]	931	iopic->p_clk (signal_clk);
	932	iopic->p_resetn (signal_resetn);
	933	iopic->p_vci_target (signal_vci_tgt_iopi);
	934	iopic->p_vci_initiator (signal_vci_ini_iopi);
[664]	935	for ( size_t i=0 ; i<32 ; i++)
[628]	936	{
	937	if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]);
	938	else if(i < 2 ) iopic->p_hwi[i] (signal_irq_false);
	939	else if(i < 2+NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_tx[i-2]);
	940	else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false);
	941	else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]);
[664]	942	else if(i < 8) iopic->p_hwi[i] (signal_irq_false);
[967]	943	else if(i == 8) iopic->p_hwi[i] (signal_irq_disk);
[664]	944	else if(i < 16) iopic->p_hwi[i] (signal_irq_false);
	945	else if(i < 16+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_rx[i-16]);
[628]	946	else iopic->p_hwi[i] (signal_irq_false);
	947	}
	948
[664]	949	std::cout << " - IOPIC connected" << std::endl;
	950
[628]	951	// vci/dspin wrappers
	952	wi_iobus->p_clk (signal_clk);
	953	wi_iobus->p_resetn (signal_resetn);
	954	wi_iobus->p_vci (signal_vci_cmd_to_noc);
[937]	955	wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH]);
	956	wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH]);
[628]	957
	958	// vci/dspin wrappers
	959	wt_iobus->p_clk (signal_clk);
	960	wt_iobus->p_resetn (signal_resetn);
	961	wt_iobus->p_vci (signal_vci_cmd_from_noc);
[937]	962	wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH]);
	963	wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH]);
[628]	964
[937]	965	#endif // USE_PIC
[826]	966
[628]	967	// Clock & RESET for clusters
[937]	968	for (size_t x = 0; x < (XMAX); x++)
[628]	969	{
[937]	970	for (size_t y = 0; y < (YMAX); y++)
[628]	971	{
	972	clusters[x][y]->p_clk (signal_clk);
	973	clusters[x][y]->p_resetn (signal_resetn);
	974	}
	975	}
	976
	977	// Inter Clusters horizontal connections
[937]	978	if (XMAX > 1)
[628]	979	{
[937]	980	for (size_t x = 0; x < (XMAX-1); x++)
[628]	981	{
[937]	982	for (size_t y = 0; y < (YMAX); y++)
[628]	983	{
	984	clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]);
	985	clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]);
	986	clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]);
	987	clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]);
	988
	989	clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]);
	990	clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]);
	991	clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]);
	992	clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]);
	993
	994	clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]);
	995	clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]);
	996	clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]);
	997	clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]);
	998
	999	clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]);
	1000	clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]);
	1001	clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]);
	1002	clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]);
	1003
	1004	clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]);
	1005	clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]);
	1006	clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]);
	1007	clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]);
[621]	1008	}
[628]	1009	}
	1010	}
[792]	1011	std::cout << std::endl << "Horizontal connections done" << std::endl;
[621]	1012
[628]	1013	// Inter Clusters vertical connections
[937]	1014	if (YMAX > 1)
[628]	1015	{
[937]	1016	for (size_t y = 0; y < (YMAX-1); y++)
[628]	1017	{
[937]	1018	for (size_t x = 0; x < XMAX; x++)
[628]	1019	{
	1020	clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]);
	1021	clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]);
	1022	clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]);
	1023	clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]);
	1024
	1025	clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]);
	1026	clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]);
	1027	clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]);
	1028	clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]);
	1029
	1030	clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]);
	1031	clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]);
	1032	clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]);
	1033	clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]);
	1034
	1035	clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]);
	1036	clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]);
	1037	clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]);
	1038	clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]);
	1039
	1040	clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]);
	1041	clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]);
	1042	clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]);
	1043	clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]);
[621]	1044	}
[628]	1045	}
	1046	}
	1047	std::cout << std::endl << "Vertical connections done" << std::endl;
[621]	1048
[628]	1049	// East & West boundary cluster connections
[937]	1050	for (size_t y = 0; y < (YMAX); y++)
[628]	1051	{
	1052	clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]);
	1053	clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]);
[937]	1054	clusters[XMAX-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[XMAX-1][y][EAST]);
	1055	clusters[XMAX-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[XMAX-1][y][EAST]);
[621]	1056
[628]	1057	clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]);
	1058	clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]);
[937]	1059	clusters[XMAX-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[XMAX-1][y][EAST]);
	1060	clusters[XMAX-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[XMAX-1][y][EAST]);
[621]	1061
[628]	1062	clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]);
	1063	clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]);
[937]	1064	clusters[XMAX-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[XMAX-1][y][EAST]);
	1065	clusters[XMAX-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[XMAX-1][y][EAST]);
[621]	1066
[628]	1067	clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]);
	1068	clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]);
[937]	1069	clusters[XMAX-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[XMAX-1][y][EAST]);
	1070	clusters[XMAX-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[XMAX-1][y][EAST]);
[621]	1071
[628]	1072	clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]);
	1073	clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]);
[937]	1074	clusters[XMAX-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[XMAX-1][y][EAST]);
	1075	clusters[XMAX-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[XMAX-1][y][EAST]);
[628]	1076	}
[621]	1077
[664]	1078	std::cout << std::endl << "West & East boundaries connections done" << std::endl;
	1079
[628]	1080	// North & South boundary clusters connections
[937]	1081	for (size_t x = 0; x < XMAX; x++)
[628]	1082	{
	1083	clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]);
	1084	clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]);
[937]	1085	clusters[x][YMAX-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][YMAX-1][NORTH]);
	1086	clusters[x][YMAX-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][YMAX-1][NORTH]);
[621]	1087
[628]	1088	clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]);
	1089	clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]);
[937]	1090	clusters[x][YMAX-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][YMAX-1][NORTH]);
	1091	clusters[x][YMAX-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][YMAX-1][NORTH]);
[621]	1092
[628]	1093	clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]);
	1094	clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]);
[937]	1095	clusters[x][YMAX-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][YMAX-1][NORTH]);
	1096	clusters[x][YMAX-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][YMAX-1][NORTH]);
[621]	1097
[628]	1098	clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]);
	1099	clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]);
[937]	1100	clusters[x][YMAX-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][YMAX-1][NORTH]);
	1101	clusters[x][YMAX-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][YMAX-1][NORTH]);
[628]	1102
	1103	clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]);
	1104	clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]);
[937]	1105	clusters[x][YMAX-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][YMAX-1][NORTH]);
	1106	clusters[x][YMAX-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][YMAX-1][NORTH]);
[628]	1107	}
	1108
[664]	1109	std::cout << std::endl << "North & South boundaries connections done" << std::endl;
	1110
[628]	1111	std::cout << std::endl;
	1112
	1113	////////////////////////////////////////////////////////
	1114	// Simulation
	1115	///////////////////////////////////////////////////////
	1116
	1117	sc_start(sc_core::sc_time(0, SC_NS));
	1118	signal_resetn = false;
	1119	signal_irq_false = false;
	1120
	1121	// set network boundaries signals default values
	1122	// for all boundary clusters but the IO cluster
[937]	1123	for (size_t x = 0; x < XMAX ; x++)
[628]	1124	{
[937]	1125	for (size_t y = 0; y < YMAX ; y++)
[628]	1126	{
	1127	for (size_t face = 0; face < 4; face++)
	1128	{
[937]	1129	if ( (x != XMAX-1) or (y != YMAX-1) or (face != NORTH) )
[628]	1130	{
	1131	signal_dspin_bound_cmd_in [x][y][face].write = false;
	1132	signal_dspin_bound_cmd_in [x][y][face].read = true;
	1133	signal_dspin_bound_cmd_out[x][y][face].write = false;
	1134	signal_dspin_bound_cmd_out[x][y][face].read = true;
	1135
	1136	signal_dspin_bound_rsp_in [x][y][face].write = false;
	1137	signal_dspin_bound_rsp_in [x][y][face].read = true;
	1138	signal_dspin_bound_rsp_out[x][y][face].write = false;
	1139	signal_dspin_bound_rsp_out[x][y][face].read = true;
	1140	}
	1141
	1142	signal_dspin_bound_m2p_in [x][y][face].write = false;
	1143	signal_dspin_bound_m2p_in [x][y][face].read = true;
	1144	signal_dspin_bound_m2p_out[x][y][face].write = false;
	1145	signal_dspin_bound_m2p_out[x][y][face].read = true;
	1146
	1147	signal_dspin_bound_p2m_in [x][y][face].write = false;
	1148	signal_dspin_bound_p2m_in [x][y][face].read = true;
	1149	signal_dspin_bound_p2m_out[x][y][face].write = false;
	1150	signal_dspin_bound_p2m_out[x][y][face].read = true;
	1151
	1152	signal_dspin_bound_cla_in [x][y][face].write = false;
	1153	signal_dspin_bound_cla_in [x][y][face].read = true;
	1154	signal_dspin_bound_cla_out[x][y][face].write = false;
	1155	signal_dspin_bound_cla_out[x][y][face].read = true;
[621]	1156	}
[628]	1157	}
	1158	}
[621]	1159
[826]	1160	#if USE_PIC == 0
[937]	1161	signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH].write = false;
	1162	signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH].read = true;
	1163	signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH].read = true;
	1164	signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH].write = false;
[826]	1165	#endif
	1166
[792]	1167	// set default values for VCI signals connected to unused ports on iobus
[664]	1168	signal_vci_tgt_memc.rspval = false;
	1169	signal_vci_tgt_xicu.rspval = false;
	1170	for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) signal_vci_ini_proc[p].cmdval = false;
	1171
[628]	1172	sc_start(sc_core::sc_time(1, SC_NS));
	1173	signal_resetn = true;
[621]	1174
[792]	1175	if (gettimeofday(&t1, NULL) != 0)
[628]	1176	{
	1177	perror("gettimeofday");
	1178	return EXIT_FAILURE;
	1179	}
[621]	1180
[937]	1181	// simulation loop
[664]	1182	for (uint64_t n = 1; n < ncycles && !stop_called; n++)
	1183	{
[937]	1184	// Monitor a specific address for L1 cache
[664]	1185	// clusters[0][0]->proc[0]->cache_monitor(0x110002C078ULL);
[621]	1186
[937]	1187	// Monitor a specific address for L2 cache
[939]	1188	// clusters[0][0]->memc->cache_monitor( 0x0000201E00ULL );
[937]	1189
	1190	// Monitor a specific address for one XRAM
[939]	1191	// clusters[0][0]->xram->start_monitor( 0x0000201E00ULL , 64);
[937]	1192
[664]	1193	// stats display
	1194	if( (n % 5000000) == 0)
	1195	{
[621]	1196
[792]	1197	if (gettimeofday(&t2, NULL) != 0)
[664]	1198	{
	1199	perror("gettimeofday");
	1200	return EXIT_FAILURE;
	1201	}
[621]	1202
[664]	1203	ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
	1204	ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
[792]	1205	std::cerr << "platform clock frequency "
[664]	1206	<< (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl;
[621]	1207
[792]	1208	if (gettimeofday(&t1, NULL) != 0)
[664]	1209	{
	1210	perror("gettimeofday");
	1211	return EXIT_FAILURE;
	1212	}
	1213	}
[621]	1214
[664]	1215	// trace display
	1216	if ( trace_ok and (n > trace_from) )
	1217	{
	1218	std::cout << "****************** cycle " << std::dec << n ;
[937]	1219	std::cout << " ********************************************" << std::endl;
[621]	1220
[664]	1221	size_t l = 0;
	1222	size_t x = 0;
	1223	size_t y = 0;
[621]	1224
[664]	1225	if ( trace_proc_ok )
	1226	{
[803]	1227	l = trace_proc_id & ((1<<P_WIDTH)-1) ;
	1228	x = (trace_proc_id >> P_WIDTH) >> Y_WIDTH ;
	1229	y = (trace_proc_id >> P_WIDTH) & ((1<<Y_WIDTH) - 1);
[621]	1230
[664]	1231	std::ostringstream proc_signame;
	1232	proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
[681]	1233	clusters[x][y]->proc[l]->print_trace(1);
[664]	1234	clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
[628]	1235
[664]	1236	std::ostringstream xicu_signame;
	1237	xicu_signame << "[SIG]XICU_" << x << "_" << y ;
	1238	clusters[x][y]->xicu->print_trace(0);
	1239	clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str());
[937]	1240
	1241	if ( clusters[x][y]->signal_proc_irq[0] )
	1242	std::cout << "### IRQ_PROC_" << x << "_" << y << "_0" << std::endl;
	1243	if ( clusters[x][y]->signal_proc_irq[4] )
	1244	std::cout << "### IRQ_PROC_" << x << "_" << y << "_1" << std::endl;
	1245	if ( clusters[x][y]->signal_proc_irq[8] )
	1246	std::cout << "### IRQ_PROC_" << x << "_" << y << "_2" << std::endl;
	1247	if ( clusters[x][y]->signal_proc_irq[12] )
	1248	std::cout << "### IRQ_PROC_" << x << "_" << y << "_3" << std::endl;
[664]	1249	}
[628]	1250
[664]	1251	if ( trace_memc_ok )
	1252	{
	1253	x = trace_memc_id >> Y_WIDTH;
	1254	y = trace_memc_id & ((1<<Y_WIDTH) - 1);
	1255
	1256	std::ostringstream smemc;
	1257	smemc << "[SIG]MEMC_" << x << "_" << y;
	1258	std::ostringstream sxram;
	1259	sxram << "[SIG]XRAM_" << x << "_" << y;
	1260
	1261	clusters[x][y]->memc->print_trace();
	1262	clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
	1263	clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
[792]	1264	}
[664]	1265
	1266	// trace coherence signals
	1267	// clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]");
	1268	// clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]");
	1269	// clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]");
	1270	// clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]");
	1271
	1272	// clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]");
	1273	// clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]");
	1274	// clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]");
	1275	// clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]");
	1276
	1277	// trace xbar(s) m2p
	1278	// clusters[0][0]->xbar_m2p->print_trace();
	1279	// clusters[1][0]->xbar_m2p->print_trace();
	1280	// clusters[0][1]->xbar_m2p->print_trace();
	1281	// clusters[1][1]->xbar_m2p->print_trace();
[792]	1282
[664]	1283	// trace router(s) m2p
	1284	// clusters[0][0]->router_m2p->print_trace();
	1285	// clusters[1][0]->router_m2p->print_trace();
	1286	// clusters[0][1]->router_m2p->print_trace();
	1287	// clusters[1][1]->router_m2p->print_trace();
[792]	1288
[826]	1289	#if USE_PIC
[664]	1290	// trace external ioc
[967]	1291	disk->print_trace();
	1292	signal_vci_tgt_disk.print_trace("[SIG]DISK_TGT");
	1293	signal_vci_ini_disk.print_trace("[SIG]DISK_INI");
[621]	1294
[664]	1295	// trace external iopic
	1296	iopic->print_trace();
	1297	signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT");
	1298	signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI");
[937]	1299
	1300	// trace external interrupts
[967]	1301	if (signal_irq_disk) std::cout << "### IRQ_DISK" << std::endl;
[897]	1302	#else
[967]	1303	clusters[0][0]->disk->print_trace();
	1304	clusters[0][0]->signal_vci_tgt_disk.print_trace("[SIG]DISK_0_0");
	1305	clusters[0][0]->signal_vci_ini_disk.print_trace("[SIG]DISK_0_0");
[826]	1306	#endif
[621]	1307
[664]	1308	} // end trace
[621]	1309
[664]	1310	sc_start(sc_core::sc_time(1, SC_NS));
	1311	}
	1312	// Free memory
[951]	1313	for (size_t i = 0 ; i < (XMAX * YMAX) ; i++)
[664]	1314	{
[951]	1315	size_t x = i / (YMAX);
	1316	size_t y = i % (YMAX);
[664]	1317	delete clusters[x][y];
	1318	}
	1319
	1320	return EXIT_SUCCESS;
[621]	1321	}
	1322
[792]	1323	void handler(int dummy = 0)
[628]	1324	{
[621]	1325	stop_called = true;
	1326	sc_stop();
	1327	}
	1328
	1329	void voidhandler(int dummy = 0) {}
	1330
	1331	int sc_main (int argc, char *argv[])
	1332	{
	1333	signal(SIGINT, handler);
	1334	signal(SIGPIPE, voidhandler);
	1335
	1336	try {
	1337	return _main(argc, argv);
	1338	} catch (std::exception &e) {
	1339	std::cout << e.what() << std::endl;
	1340	} catch (...) {
	1341	std::cout << "Unknown exception occured" << std::endl;
	1342	throw;
	1343	}
	1344	return 1;
	1345	}
	1346
	1347
	1348	// Local Variables:
	1349	// tab-width: 3
	1350	// c-basic-offset: 3
	1351	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	1352	// indent-tabs-mode: nil
	1353	// End:
	1354
	1355	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
Plural-Forms: nplurals=2; plural=(n != 1)
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Generated-By: Babel 2.8.0