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source: trunk/platforms/tsar_generic_leti/top.cpp @ 991

Last change on this file since 991 was 967, checked in by alain, 9 years ago
Introduce the new parametre ioc_type in the tsar_generic_leti platform.
File size: 55.6 KB

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1	/////////////////////////////////////////////////////////////////////////
2	// File: top.cpp (for tsar_generic_leti platform)
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : february 2013 / updated january 2015
6	// This program is released under the GNU public license
7	/////////////////////////////////////////////////////////////////////////
8	// This file define a generic TSAR architecture, fully compatible
9	// with the VLSI Hardware prototype developped by CEA-LETI and LIP6
10	// in the framework of the SHARP project.
11	//
12	// The processor is a MIPS32 processor wrapped in a GDB server
13	// (this is defined in the tsar_leti_cluster).
14	//
15	// The main hardware parameters are the mesh size (X_SIZE & Y_SIZE),
16	// and the number of processors per cluster (NB_PROCS_MAX).
17	// The NB_PROCS_MAX parameter cannot be larger than 4.
18	// Others parameters are the frame buffer size, the disk controller type
19	// (BDV or HBA), the number of TTY channels, the number of NIC channels,
20	// and the number of CMA channels.
21	//
22	// All external peripherals are located in cluster[X_SIZE-1][Y_SIZE-1],
23	// and are connected to an IO bus (implemented as a vci_local_crossbar):
24	// - DISK : block device controller (BDV / HBA)
25	// - MNIC : multi-channel ethernet controller
26	// - CDMA : multi-channel chained buffer dma controller
27	// - MTTY : multi-channel tty controller
28	// - FBUF : frame buffer controller
29	// - IOPI : HWI to SWI translator
30	//
31	// This IO bus is directly connected to the north ports of the CMD/RSP
32	// routers in cluster[X_SIZE-1][y_SIZE-2] through VCI/DSPIN wrappers.
33	// All other clusters in the upper row are empty: no processors,
34	// no ram, no routers.
35	// The X_SIZE parameter must be larger than 0, but no larger than 16.
36	// The Y_SIZE parameter must be larger than 1, but no larger than 16.
37	//
38	// We don't use an external ROM, as the boot code is (pre)loaded
39	// in RAM in cluster[0][0] at address 0x0.
40	//
41	// An optional RAMDISK of 32 Mbytes can be used in RAM of cluster[0][0].
42	//
43	// The physical address space is 40 bits.
44	// The 8 address MSB bits define the cluster index.
45	//
46	// Besides the processors, each cluster contains:
47	// - 5 L1/L2 DSPIN routers implementing 5 separated NOCs
48	// - 1 vci_mem_cache
49	// - 1 vci_xicu
50	// - 1 vci_simple_ram (to emulate the L3 cache).
51	//
52	// Each processor receives 4 consecutive IRQ lines from the local XICU.
53	// The number of PTI and WTI IRQs is bounded to 16.
54	//
55	// In all clusters, the MEMC IRQ line (signaling a late write error)
56	// is connected to XICU HWI[8]
57	//
58	// For all external peripherals, the hardware interrupts (HWI) are
59	// translated to write interrupts (WTI) by the iopic component:
60	// - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0]
61	// - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0]
62	// - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]]
63	// - IOPIC HWI[8] connected to IRQ_DISK
64	// - IOPIC HWI[15:9] unused (grounded)
65	// - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]]
66	// - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]]
67	//
68	// The cluster internal architecture is defined in file tsar_leti_cluster,
69	// that must be considered as an extension of this top.cpp file.
70	////////////////////////////////////////////////////////////////////////////
71	// The following parameters must be defined in the hard_config.h file :
72	// - X_WIDTH : number of bits for x coordinate (must be 4)
73	// - Y_WIDTH : number of bits for y coordinate (must be 4)
74	// - P_WIDTH : number of bits for local processor coordinate
75	// - X_SIZE : number of clusters in a row (1,2,4,8,16)
76	// - Y_SIZE : number of clusters in a column (1,2,4,8)
77	// - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4)
78	// - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (4 max)
79	// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (8 max)
80	// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max)
81	// - FBUF_X_SIZE : number of pixels per line for frame buffer
82	// - FBUF_Y_SIZE : number of lines for frame buffer
83	// - XCU_NB_HWI : number of XCU HWIs (must be 16)
84	// - XCU_NB_PTI : number of XCU PTIs (must be 16)
85	// - XCU_NB_WTI : number of XCU WTIs (must be 16)
86	// - XCU_NB_OUT : number of XCU output (must be 16)
87	// - USE_IOC_XYZ : IOC type (XYZ in HBA / BDV / SDC / RDK)
88	//
89	// Some other hardware parameters are not used when compiling the OS,
90	// and are only defined in this top.cpp file:
91	// - XRAM_LATENCY : external ram latency
92	// - L1_IWAYS : L1 cache instruction number of ways
93	// - L1_ISETS : L1 cache instruction number of sets
94	// - L1_DWAYS : L1 cache data number of ways
95	// - L1_DSETS : L1 cache data number of sets
96	// - DISK_IMAGE_NAME : pathname for block device disk image
97	/////////////////////////////////////////////////////////////////////////
98	// General policy for 40 bits physical address decoding:
99	// All physical segments base addresses are multiple of 1 Mbytes
100	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
101	// The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define
102	// the cluster index, and the LADR bits define the local index:
103	// \|X_ID\|Y_ID\| LADR \| OFFSET \|
104	// \| 4 \| 4 \| 8 \| 24 \|
105	/////////////////////////////////////////////////////////////////////////
106	// General policy for 14 bits SRCID decoding:
107	// Each component is identified by (x_id, y_id, l_id) tuple.
108	// \|X_ID\|Y_ID\| L_ID \|
109	// \| 4 \| 4 \| 6 \|
110	/////////////////////////////////////////////////////////////////////////
111
112	#include <systemc>
113	#include <sys/time.h>
114	#include <iostream>
115	#include <sstream>
116	#include <cstdlib>
117	#include <cstdarg>
118	#include <stdint.h>
119
120	#include "gdbserver.h"
121	#include "mapping_table.h"
122
123	#include "tsar_leti_cluster.h"
124	#include "vci_local_crossbar.h"
125	#include "vci_dspin_initiator_wrapper.h"
126	#include "vci_dspin_target_wrapper.h"
127	#include "vci_multi_tty.h"
128	#include "vci_multi_nic.h"
129	#include "vci_chbuf_dma.h"
130	#include "vci_block_device_tsar.h"
131	#include "vci_multi_ahci.h"
132	#include "vci_framebuffer.h"
133	#include "vci_iopic.h"
134
135	#include "alloc_elems.h"
136
137	///////////////////////////////////////////////////
138	// Main hardware parameters values
139	///////////////////////////////////////////////////
140
141	#include "hard_config.h"
142
143	///////////////////////////////////////////////////////////////////////////////////////
144	// Secondary Hardware Parameters
145	///////////////////////////////////////////////////////////////////////////////////////
146
147	#define XMAX X_SIZE // actual number of columns in 2D mesh
148	#define YMAX (Y_SIZE - 1) // actual number of rows in 2D mesh
149
150	#define XRAM_LATENCY 0
151
152	#define MEMC_WAYS 16
153	#define MEMC_SETS 256
154
155	#define L1_IWAYS 4
156	#define L1_ISETS 64
157
158	#define L1_DWAYS 4
159	#define L1_DSETS 64
160
161	#define DISK_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg"
162
163	#define ROM_SOFT_NAME "../../softs/tsar_boot/preloader.elf"
164
165	#define NORTH 0
166	#define SOUTH 1
167	#define EAST 2
168	#define WEST 3
169
170	///////////////////////////////////////////////////
171	// Parallelisation
172	///////////////////////////////////////////////////
173
174	#define USE_OPENMP _OPENMP
175
176	#if USE_OPENMP
177	#include <omp.h>
178	#endif
179
180	///////////////////////////////////////////////////
181	// cluster index (from x,y coordinates)
182	///////////////////////////////////////////////////
183
184	#define cluster(x,y) ((y) + ((x) << Y_WIDTH))
185
186	///////////////////////////////////////////////////////////
187	// DSPIN parameters
188	///////////////////////////////////////////////////////////
189
190	#define dspin_cmd_width 39
191	#define dspin_rsp_width 32
192
193	///////////////////////////////////////////////////////////
194	// VCI parameters
195	///////////////////////////////////////////////////////////
196
197	#define vci_cell_width_int 4
198	#define vci_cell_width_ext 8
199	#define vci_address_width 40
200	#define vci_plen_width 8
201	#define vci_rerror_width 1
202	#define vci_clen_width 1
203	#define vci_rflag_width 1
204	#define vci_srcid_width 14
205	#define vci_pktid_width 4
206	#define vci_trdid_width 4
207	#define vci_wrplen_width 1
208
209
210
211	///////////////////////////////////////////////////////////////////////////////////////
212	// DEBUG Parameters default values
213	///////////////////////////////////////////////////////////////////////////////////////
214
215	#define MAX_FROZEN_CYCLES 500000
216
217	///////////////////////////////////////////////////////////////////////////////////////
218	// LOCAL TGTID & SRCID definition
219	// For all components: global TGTID = global SRCID = cluster_index
220	///////////////////////////////////////////////////////////////////////////////////////
221
222	#define MEMC_TGTID 0
223	#define XICU_TGTID 1
224	#define MTTY_TGTID 2
225	#define DISK_TGTID 3
226	#define FBUF_TGTID 4
227	#define MNIC_TGTID 5
228	#define CDMA_TGTID 6
229	#define IOPI_TGTID 7
230
231	#define DISK_SRCID NB_PROCS_MAX
232	#define CDMA_SRCID NB_PROCS_MAX + 1
233	#define IOPI_SRCID NB_PROCS_MAX + 2
234
235	bool stop_called = false;
236
237	/////////////////////////////////
238	int _main(int argc, char *argv[])
239	{
240	using namespace sc_core;
241	using namespace soclib::caba;
242	using namespace soclib::common;
243
244	uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles
245	size_t threads = 1; // simulator's threads number
246	bool trace_ok = false; // trace activated
247	uint32_t trace_from = 0; // trace start cycle
248	bool trace_proc_ok = false; // detailed proc trace activated
249	size_t trace_memc_ok = false; // detailed memc trace activated
250	size_t trace_memc_id = 0; // index of memc to be traced
251	size_t trace_proc_id = 0; // index of proc to be traced
252	char soft_name[256] = ROM_SOFT_NAME; // pathname for ROM binary code
253	char disk_name[256] = DISK_IMAGE_NAME; // pathname for DISK image
254	uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // for debug
255	struct timeval t1,t2;
256	uint64_t ms1,ms2;
257
258	////////////// command line arguments //////////////////////
259	if (argc > 1)
260	{
261	for (int n = 1; n < argc; n = n + 2)
262	{
263	if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc))
264	{
265	ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0);
266	}
267	else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc))
268	{
269	trace_ok = true;
270	trace_from = (uint32_t) strtol(argv[n + 1], NULL, 0);
271	}
272	else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc))
273	{
274	trace_memc_ok = true;
275	trace_memc_id = (size_t) strtol(argv[n + 1], NULL, 0);
276	size_t x = trace_memc_id >> Y_WIDTH;
277	size_t y = trace_memc_id & ((1<<Y_WIDTH)-1);
278
279	assert( (x < XMAX) and (y < (YMAX)) and
280	"MEMCID parameter doesxn't fit valid XMAX/YMAX");
281	}
282	else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc))
283	{
284	trace_proc_ok = true;
285	trace_proc_id = (size_t) strtol(argv[n + 1], NULL, 0);
286	size_t cluster_xy = trace_proc_id >> P_WIDTH ;
287	size_t x = cluster_xy >> Y_WIDTH;
288	size_t y = cluster_xy & ((1<<Y_WIDTH)-1);
289	size_t l = trace_proc_id & ((1<<P_WIDTH)-1) ;
290
291	assert( (x < XMAX) and (y < YMAX) and (l < NB_PROCS_MAX) and
292	"PROCID parameter refers a not valid processor");
293	}
294	else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc))
295	{
296	threads = (size_t) strtol(argv[n + 1], NULL, 0);
297	threads = (threads < 1) ? 1 : threads;
298	}
299	else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc))
300	{
301	frozen_cycles = (uint32_t) strtol(argv[n + 1], NULL, 0);
302	}
303	else
304	{
305	std::cout << " Arguments are (key,value) couples." << std::endl;
306	std::cout << " The order is not important." << std::endl;
307	std::cout << " Accepted arguments are :" << std::endl << std::endl;
308	std::cout << " - NCYCLES number_of_simulated_cycles" << std::endl;
309	std::cout << " - DEBUG debug_start_cycle" << std::endl;
310	std::cout << " - THREADS simulator's threads number" << std::endl;
311	std::cout << " - FROZEN max_number_of_lines" << std::endl;
312	std::cout << " - MEMCID index_memc_to_be_traced" << std::endl;
313	std::cout << " - PROCID index_proc_to_be_traced" << std::endl;
314	exit(0);
315	}
316	}
317	}
318
319	// checking hardware parameters
320	assert( ((X_SIZE <= 16) and (X_SIZE > 0)) and
321	"Illegal X_SIZE parameter" );
322
323	assert( ((Y_SIZE <= 16) and (Y_SIZE > 1)) and
324	"Illegal Y_SIZE parameter" );
325
326	assert( (P_WIDTH <= 2) and
327	"P_WIDTH parameter cannot be larger than 2" );
328
329	assert( (NB_PROCS_MAX <= 4) and
330	"Illegal NB_PROCS_MAX parameter" );
331
332	assert( (XCU_NB_HWI == 16) and
333	"XCU_NB_HWI must be 16" );
334
335	assert( (XCU_NB_PTI == 16) and
336	"XCU_NB_PTI must be 16" );
337
338	assert( (XCU_NB_WTI == 16) and
339	"XCU_NB_WTI must be 16" );
340
341	assert( (XCU_NB_OUT == 16) and
342	"XCU_NB_OUT must be 16" );
343
344	assert( (NB_CMA_CHANNELS <= 4) and
345	"The NB_CMA_CHANNELS parameter cannot be larger than 4" );
346
347	assert( (NB_TTY_CHANNELS <= 8) and
348	"The NB_TTY_CHANNELS parameter cannot be larger than 8" );
349
350	assert( (NB_NIC_CHANNELS <= 2) and
351	"The NB_NIC_CHANNELS parameter cannot be larger than 2" );
352
353	assert( (vci_address_width == 40) and
354	"VCI address width with the GIET must be 40 bits" );
355
356	assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and
357	"You must have X_WIDTH == Y_WIDTH == 4");
358
359	std::cout << std::endl;
360
361	std::cout << " - XMAX = " << XMAX << std::endl
362	<< " - YMAX = " << YMAX << std::endl
363	<< " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl
364	<< " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl
365	<< " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl
366	<< " - NB_CMA_CHANNELS = " << NB_CMA_CHANNELS << std::endl
367	<< " - MEMC_WAYS = " << MEMC_WAYS << std::endl
368	<< " - MEMC_SETS = " << MEMC_SETS << std::endl
369	<< " - RAM_LATENCY = " << XRAM_LATENCY << std::endl
370	<< " - MAX_FROZEN = " << frozen_cycles << std::endl
371	<< " - MAX_CYCLES = " << ncycles << std::endl
372	<< " - RESET_ADDRESS = " << RESET_ADDRESS << std::endl
373	<< " - SOFT_FILENAME = " << soft_name << std::endl
374	<< " - DISK_IMAGENAME = " << disk_name << std::endl
375	<< " - OPENMP THREADS = " << threads << std::endl
376	<< " - DEBUG_PROCID = " << trace_proc_id << std::endl
377	<< " - DEBUG_MEMCID = " << trace_memc_id << std::endl;
378
379	std::cout << std::endl;
380
381	// Internal and External VCI parameters definition
382	typedef soclib::caba::VciParams<vci_cell_width_int,
383	vci_plen_width,
384	vci_address_width,
385	vci_rerror_width,
386	vci_clen_width,
387	vci_rflag_width,
388	vci_srcid_width,
389	vci_pktid_width,
390	vci_trdid_width,
391	vci_wrplen_width> vci_param_int;
392
393	typedef soclib::caba::VciParams<vci_cell_width_ext,
394	vci_plen_width,
395	vci_address_width,
396	vci_rerror_width,
397	vci_clen_width,
398	vci_rflag_width,
399	vci_srcid_width,
400	vci_pktid_width,
401	vci_trdid_width,
402	vci_wrplen_width> vci_param_ext;
403
404	#if USE_OPENMP
405	omp_set_dynamic(false);
406	omp_set_num_threads(threads);
407	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
408	#endif
409
410
411	///////////////////////////////////////
412	// Direct Network Mapping Table
413	///////////////////////////////////////
414
415	MappingTable maptabd(vci_address_width,
416	IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
417	IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
418	0x00FF000000ULL);
419
420	// replicated segments
421	for (size_t x = 0; x < XMAX; x++)
422	{
423	for (size_t y = 0; y < (YMAX) ; y++)
424	{
425	sc_uint<vci_address_width> offset;
426	offset = ((sc_uint<vci_address_width>)cluster(x,y)) << 32;
427
428	std::ostringstream si;
429	si << "seg_xicu_" << x << "_" << y;
430	maptabd.add(Segment(si.str(), SEG_XCU_BASE + offset, SEG_XCU_SIZE,
431	IntTab(cluster(x,y),XICU_TGTID), false));
432
433	std::ostringstream sd;
434	sd << "seg_mcfg_" << x << "_" << y;
435	maptabd.add(Segment(sd.str(), SEG_MMC_BASE + offset, SEG_MMC_SIZE,
436	IntTab(cluster(x,y),MEMC_TGTID), false));
437
438	std::ostringstream sh;
439	sh << "seg_memc_" << x << "_" << y;
440	maptabd.add(Segment(sh.str(), SEG_RAM_BASE + offset, SEG_RAM_SIZE,
441	IntTab(cluster(x,y),MEMC_TGTID), true));
442	}
443	}
444
445	// segments for peripherals in cluster(0,0)
446	maptabd.add(Segment("seg_tty0", SEG_TTY_BASE, SEG_TTY_SIZE,
447	IntTab(cluster(0,0),MTTY_TGTID), false));
448
449	maptabd.add(Segment("seg_ioc0", SEG_IOC_BASE, SEG_IOC_SIZE,
450	IntTab(cluster(0,0),DISK_TGTID), false));
451
452	// segments for peripherals in cluster_io (XMAX-1,YMAX)
453	sc_uint<vci_address_width> offset;
454	offset = ((sc_uint<vci_address_width>)cluster(XMAX-1,YMAX)) << 32;
455
456	maptabd.add(Segment("seg_mtty", SEG_TTY_BASE + offset, SEG_TTY_SIZE,
457	IntTab(cluster(XMAX-1, YMAX),MTTY_TGTID), false));
458
459	maptabd.add(Segment("seg_fbuf", SEG_FBF_BASE + offset, SEG_FBF_SIZE,
460	IntTab(cluster(XMAX-1, YMAX),FBUF_TGTID), false));
461
462	maptabd.add(Segment("seg_disk", SEG_IOC_BASE + offset, SEG_IOC_SIZE,
463	IntTab(cluster(XMAX-1, YMAX),DISK_TGTID), false));
464
465	maptabd.add(Segment("seg_mnic", SEG_NIC_BASE + offset, SEG_NIC_SIZE,
466	IntTab(cluster(XMAX-1, YMAX),MNIC_TGTID), false));
467
468	maptabd.add(Segment("seg_cdma", SEG_CMA_BASE + offset, SEG_CMA_SIZE,
469	IntTab(cluster(XMAX-1, YMAX),CDMA_TGTID), false));
470
471	maptabd.add(Segment("seg_iopi", SEG_PIC_BASE + offset, SEG_PIC_SIZE,
472	IntTab(cluster(XMAX-1, YMAX),IOPI_TGTID), false));
473
474	std::cout << maptabd << std::endl;
475
476	/////////////////////////////////////////////////
477	// Ram network mapping table
478	/////////////////////////////////////////////////
479
480	MappingTable maptabx(vci_address_width,
481	IntTab(X_WIDTH+Y_WIDTH),
482	IntTab(X_WIDTH+Y_WIDTH),
483	0x00FF000000ULL);
484
485	for (size_t x = 0; x < XMAX; x++)
486	{
487	for (size_t y = 0; y < (YMAX) ; y++)
488	{
489	sc_uint<vci_address_width> offset;
490	offset = (sc_uint<vci_address_width>)cluster(x,y)
491	<< (vci_address_width-X_WIDTH-Y_WIDTH);
492
493	std::ostringstream sh;
494	sh << "x_seg_memc_" << x << "_" << y;
495
496	maptabx.add(Segment(sh.str(), SEG_RAM_BASE + offset,
497	SEG_RAM_SIZE, IntTab(cluster(x,y)), false));
498	}
499	}
500	std::cout << maptabx << std::endl;
501
502	////////////////////
503	// Signals
504	///////////////////
505
506	sc_clock signal_clk("clk");
507	sc_signal<bool> signal_resetn("resetn");
508
509	// IRQs from external peripherals
510	sc_signal<bool> signal_irq_disk;
511	sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];
512	sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];
513	sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS];
514	sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS];
515	sc_signal<bool> signal_irq_false;
516
517	// Horizontal inter-clusters DSPIN signals
518	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc =
519	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX);
520	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec =
521	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX);
522
523	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc =
524	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX);
525	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec =
526	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX);
527
528	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc =
529	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", XMAX-1, YMAX);
530	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec =
531	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", XMAX-1, YMAX);
532
533	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc =
534	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", XMAX-1, YMAX);
535	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec =
536	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", XMAX-1, YMAX);
537
538	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc =
539	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", XMAX-1, YMAX);
540	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec =
541	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", XMAX-1, YMAX);
542
543	// Vertical inter-clusters DSPIN signals
544	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc =
545	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1);
546	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec =
547	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1);
548
549	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc =
550	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1);
551	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec =
552	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1);
553
554	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc =
555	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", XMAX, YMAX-1);
556	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec =
557	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", XMAX, YMAX-1);
558
559	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc =
560	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", XMAX, YMAX-1);
561	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec =
562	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", XMAX, YMAX-1);
563
564	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc =
565	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", XMAX, YMAX-1);
566	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec =
567	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", XMAX, YMAX-1);
568
569	// Mesh boundaries DSPIN signals (Most of those signals are not used...)
570	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in =
571	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , XMAX, YMAX, 4);
572	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out =
573	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", XMAX, YMAX, 4);
574
575	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in =
576	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , XMAX, YMAX, 4);
577	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out =
578	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", XMAX, YMAX, 4);
579
580	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in =
581	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , XMAX, YMAX, 4);
582	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out =
583	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", XMAX, YMAX, 4);
584
585	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in =
586	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , XMAX, YMAX, 4);
587	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out =
588	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", XMAX, YMAX, 4);
589
590	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in =
591	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , XMAX, YMAX, 4);
592	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out =
593	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", XMAX, YMAX, 4);
594
595	// VCI signals for iobus and peripherals
596	VciSignals<vci_param_int> signal_vci_ini_disk("signal_vci_ini_disk");
597	VciSignals<vci_param_int> signal_vci_ini_cdma("signal_vci_ini_cdma");
598	VciSignals<vci_param_int> signal_vci_ini_iopi("signal_vci_ini_iopi");
599
600	VciSignals<vci_param_int>* signal_vci_ini_proc =
601	alloc_elems<VciSignals<vci_param_int> >("signal_vci_ini_proc", NB_PROCS_MAX );
602
603	VciSignals<vci_param_int> signal_vci_tgt_memc("signal_vci_tgt_memc");
604	VciSignals<vci_param_int> signal_vci_tgt_xicu("signal_vci_tgt_xicu");
605	VciSignals<vci_param_int> signal_vci_tgt_disk("signal_vci_tgt_disk");
606	VciSignals<vci_param_int> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
607	VciSignals<vci_param_int> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
608	VciSignals<vci_param_int> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
609	VciSignals<vci_param_int> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
610	VciSignals<vci_param_int> signal_vci_tgt_iopi("signal_vci_tgt_iopi");
611
612	VciSignals<vci_param_int> signal_vci_cmd_to_noc("signal_vci_cmd_to_noc");
613	VciSignals<vci_param_int> signal_vci_cmd_from_noc("signal_vci_cmd_from_noc");
614
615	////////////////////////////
616	// Loader
617	////////////////////////////
618
619	#if USE_IOC_RDK
620	std::ostringstream ramdisk_name;
621	ramdisk_name << disk_name << "@" << std::hex << SEG_RDK_BASE << ":";
622	soclib::common::Loader loader( soft_name, ramdisk_name.str().c_str() );
623	#else
624	soclib::common::Loader loader( soft_name );
625	#endif
626
627	loader.memory_default(0x55);
628
629	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
630	proc_iss::set_loader( loader );
631
632	//////////////////////////////////////////////////////////////
633	// mesh construction: XMAX * YMAX clusters
634	//////////////////////////////////////////////////////////////
635
636	TsarLetiCluster<dspin_cmd_width,
637	dspin_rsp_width,
638	vci_param_int,
639	vci_param_ext>* clusters[XMAX][YMAX];
640
641	#if USE_OPENMP
642	#pragma omp parallel
643	{
644	#pragma omp for
645	#endif
646	for (size_t i = 0; i < (XMAX * YMAX); i++)
647	{
648	size_t x = i / (YMAX);
649	size_t y = i % (YMAX);
650
651	#if USE_OPENMP
652	#pragma omp critical
653	{
654	#endif
655	std::cout << std::endl;
656	std::cout << "Cluster_" << std::dec << x << "_" << y
657	<< " with cluster_xy = " << std::hex << cluster(x,y) << std::endl;
658	std::cout << std::endl;
659
660	std::ostringstream cluster_name;
661	cluster_name << "cluster_" << std::dec << x << "_" << y;
662
663	clusters[x][y] = new TsarLetiCluster<dspin_cmd_width,
664	dspin_rsp_width,
665	vci_param_int,
666	vci_param_ext>
667	(
668	cluster_name.str().c_str(),
669	NB_PROCS_MAX,
670	x,
671	y,
672	cluster(x,y),
673	maptabd,
674	maptabx,
675	RESET_ADDRESS,
676	X_WIDTH,
677	Y_WIDTH,
678	vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width,
679	P_WIDTH,
680	MEMC_TGTID,
681	XICU_TGTID,
682	MTTY_TGTID,
683	DISK_TGTID,
684	disk_name,
685	MEMC_WAYS,
686	MEMC_SETS,
687	L1_IWAYS,
688	L1_ISETS,
689	L1_DWAYS,
690	L1_DSETS,
691	XRAM_LATENCY,
692	loader,
693	frozen_cycles,
694	trace_from,
695	trace_proc_ok,
696	trace_proc_id,
697	trace_memc_ok,
698	trace_memc_id
699	);
700
701	#if USE_OPENMP
702	} // end critical
703	#endif
704	} // end for
705	#if USE_OPENMP
706	}
707	#endif
708
709	#if USE_PIC
710
711	//////////////////////////////////////////////////////////////////
712	// IO bus and external peripherals in cluster[X_SIZE-1][Y_SIZE-1]
713	// - 6 local targets : FBF, TTY, CMA, NIC, PIC, IOC
714	// - 3 local initiators : IOC, CMA, PIC
715	// There is no PROC, no MEMC and no XICU in this cluster,
716	// but the crossbar has (NB_PROCS_MAX + 3) intiators and
717	// 8 targets, in order to use the same SRCID and TGTID space
718	// (same mapping table for the internal components,
719	// and for the external peripherals)
720	//////////////////////////////////////////////////////////////////
721
722	std::cout << std::endl;
723	std::cout << " Building IO cluster (external peripherals)" << std::endl;
724	std::cout << std::endl;
725
726	size_t cluster_io = cluster(XMAX-1, YMAX);
727
728	//////////// vci_local_crossbar
729	VciLocalCrossbar<vci_param_int>*
730	iobus = new VciLocalCrossbar<vci_param_int>(
731	"iobus",
732	maptabd, // mapping table
733	cluster_io, // cluster_xy
734	NB_PROCS_MAX + 3, // number of local initiators
735	8, // number of local targets
736	DISK_TGTID ); // default target index
737
738	//////////// vci_framebuffer
739	VciFrameBuffer<vci_param_int>*
740	fbuf = new VciFrameBuffer<vci_param_int>(
741	"fbuf",
742	IntTab(cluster_io, FBUF_TGTID),
743	maptabd,
744	FBUF_X_SIZE, FBUF_Y_SIZE );
745
746	#if ( USE_IOC_HBA )
747
748	//////////// vci_multi_ahci
749	std::vector<std::string> filenames;
750	filenames.push_back(disk_name); // one single disk
751	VciMultiAhci<vci_param_int>*
752	disk = new VciMultiAhci<vci_param_int>(
753	"disk",
754	maptabd,
755	IntTab(cluster_io, DISK_SRCID),
756	IntTab(cluster_io, DISK_TGTID),
757	filenames,
758	512, // block size
759	64, // burst size (bytes)
760	0 ); // disk latency
761
762	#elif ( USE_IOC_BDV or USE_IOC_SDC )
763
764	//////////// vci_block_device
765	VciBlockDeviceTsar<vci_param_int>*
766	disk = new VciBlockDeviceTsar<vci_param_int>(
767	"disk",
768	maptabd,
769	IntTab(cluster_io, DISK_SRCID),
770	IntTab(cluster_io, DISK_TGTID),
771	disk_name,
772	512, // block size
773	64, // burst size (bytes)
774	0 ); // disk latency
775	#endif
776
777	//////////// vci_multi_nic
778	VciMultiNic<vci_param_int>*
779	mnic = new VciMultiNic<vci_param_int>(
780	"mnic",
781	IntTab(cluster_io, MNIC_TGTID),
782	maptabd,
783	NB_NIC_CHANNELS,
784	0, // default MAC_4 address
785	0, // default MAC_2 address
786	1 ); // NIC_MODE_SYNTHESIS
787
788	///////////// vci_chbuf_dma
789	VciChbufDma<vci_param_int>*
790	cdma = new VciChbufDma<vci_param_int>(
791	"cdma",
792	maptabd,
793	IntTab(cluster_io, CDMA_SRCID),
794	IntTab(cluster_io, CDMA_TGTID),
795	64, // burst size
796	NB_CMA_CHANNELS );
797
798	////////////// vci_multi_tty
799	std::vector<std::string> vect_names;
800	for (size_t id = 0; id < NB_TTY_CHANNELS; id++)
801	{
802	std::ostringstream term_name;
803	term_name << "ext_" << id;
804	vect_names.push_back(term_name.str().c_str());
805	}
806
807	VciMultiTty<vci_param_int>*
808	mtty = new VciMultiTty<vci_param_int>(
809	"mtty",
810	IntTab(cluster_io, MTTY_TGTID),
811	maptabd,
812	vect_names );
813
814	///////////// vci_iopic
815	VciIopic<vci_param_int>*
816	iopic = new VciIopic<vci_param_int>(
817	"iopic",
818	maptabd,
819	IntTab(cluster_io, IOPI_SRCID),
820	IntTab(cluster_io, IOPI_TGTID),
821	32 );
822
823	////////////// vci_dspin wrappers
824	VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
825	wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
826	"wt_iobus",
827	vci_srcid_width );
828
829	VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
830	wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
831	"wi_iobus",
832	vci_srcid_width );
833
834	///////////////////////////////////////////////////////////////
835	// IObus Net-list
836	///////////////////////////////////////////////////////////////
837
838	// iobus
839	iobus->p_clk (signal_clk);
840	iobus->p_resetn (signal_resetn);
841
842	iobus->p_target_to_up (signal_vci_cmd_from_noc);
843	iobus->p_initiator_to_up (signal_vci_cmd_to_noc);
844
845	iobus->p_to_target[MEMC_TGTID] (signal_vci_tgt_memc);
846	iobus->p_to_target[XICU_TGTID] (signal_vci_tgt_xicu);
847	iobus->p_to_target[MTTY_TGTID] (signal_vci_tgt_mtty);
848	iobus->p_to_target[FBUF_TGTID] (signal_vci_tgt_fbuf);
849	iobus->p_to_target[MNIC_TGTID] (signal_vci_tgt_mnic);
850	iobus->p_to_target[DISK_TGTID] (signal_vci_tgt_disk);
851	iobus->p_to_target[CDMA_TGTID] (signal_vci_tgt_cdma);
852	iobus->p_to_target[IOPI_TGTID] (signal_vci_tgt_iopi);
853
854	for( size_t p=0 ; p<NB_PROCS_MAX ; p++ )
855	{
856	iobus->p_to_initiator[p] (signal_vci_ini_proc[p]);
857	}
858	iobus->p_to_initiator[DISK_SRCID] (signal_vci_ini_disk);
859	iobus->p_to_initiator[CDMA_SRCID] (signal_vci_ini_cdma);
860	iobus->p_to_initiator[IOPI_SRCID] (signal_vci_ini_iopi);
861
862	std::cout << " - IOBUS connected" << std::endl;
863
864	// disk
865	disk->p_clk (signal_clk);
866	disk->p_resetn (signal_resetn);
867	disk->p_vci_target (signal_vci_tgt_disk);
868	disk->p_vci_initiator (signal_vci_ini_disk);
869	#if USE_IOC_HBA
870	disk->p_channel_irq[0] (signal_irq_disk);
871	#else
872	disk->p_irq (signal_irq_disk);
873	#endif
874
875	std::cout << " - DISK connected" << std::endl;
876
877	// frame_buffer
878	fbuf->p_clk (signal_clk);
879	fbuf->p_resetn (signal_resetn);
880	fbuf->p_vci (signal_vci_tgt_fbuf);
881
882	std::cout << " - FBUF connected" << std::endl;
883
884	// multi_nic
885	mnic->p_clk (signal_clk);
886	mnic->p_resetn (signal_resetn);
887	mnic->p_vci (signal_vci_tgt_mnic);
888	for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ )
889	{
890	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
891	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
892	}
893
894	std::cout << " - MNIC connected" << std::endl;
895
896	// chbuf_dma
897	cdma->p_clk (signal_clk);
898	cdma->p_resetn (signal_resetn);
899	cdma->p_vci_target (signal_vci_tgt_cdma);
900	cdma->p_vci_initiator (signal_vci_ini_cdma);
901	for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++)
902	{
903	cdma->p_irq[i] (signal_irq_cdma[i]);
904	}
905
906	std::cout << " - CDMA connected" << std::endl;
907
908	// multi_tty
909	mtty->p_clk (signal_clk);
910	mtty->p_resetn (signal_resetn);
911	mtty->p_vci (signal_vci_tgt_mtty);
912	for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ )
913	{
914	mtty->p_irq[i] (signal_irq_mtty_rx[i]);
915	}
916
917	std::cout << " - MTTY connected" << std::endl;
918
919	// iopic
920	// NB_NIC_CHANNELS <= 2
921	// NB_CMA_CHANNELS <= 4
922	// NB_TTY_CHANNELS <= 16
923	iopic->p_clk (signal_clk);
924	iopic->p_resetn (signal_resetn);
925	iopic->p_vci_target (signal_vci_tgt_iopi);
926	iopic->p_vci_initiator (signal_vci_ini_iopi);
927	for ( size_t i=0 ; i<32 ; i++)
928	{
929	if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]);
930	else if(i < 2 ) iopic->p_hwi[i] (signal_irq_false);
931	else if(i < 2+NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_tx[i-2]);
932	else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false);
933	else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]);
934	else if(i < 8) iopic->p_hwi[i] (signal_irq_false);
935	else if(i == 8) iopic->p_hwi[i] (signal_irq_disk);
936	else if(i < 16) iopic->p_hwi[i] (signal_irq_false);
937	else if(i < 16+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_rx[i-16]);
938	else iopic->p_hwi[i] (signal_irq_false);
939	}
940
941	std::cout << " - IOPIC connected" << std::endl;
942
943	// vci/dspin wrappers
944	wi_iobus->p_clk (signal_clk);
945	wi_iobus->p_resetn (signal_resetn);
946	wi_iobus->p_vci (signal_vci_cmd_to_noc);
947	wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH]);
948	wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH]);
949
950	// vci/dspin wrappers
951	wt_iobus->p_clk (signal_clk);
952	wt_iobus->p_resetn (signal_resetn);
953	wt_iobus->p_vci (signal_vci_cmd_from_noc);
954	wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH]);
955	wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH]);
956
957	#endif // USE_PIC
958
959	// Clock & RESET for clusters
960	for (size_t x = 0; x < (XMAX); x++)
961	{
962	for (size_t y = 0; y < (YMAX); y++)
963	{
964	clusters[x][y]->p_clk (signal_clk);
965	clusters[x][y]->p_resetn (signal_resetn);
966	}
967	}
968
969	// Inter Clusters horizontal connections
970	if (XMAX > 1)
971	{
972	for (size_t x = 0; x < (XMAX-1); x++)
973	{
974	for (size_t y = 0; y < (YMAX); y++)
975	{
976	clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]);
977	clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]);
978	clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]);
979	clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]);
980
981	clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]);
982	clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]);
983	clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]);
984	clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]);
985
986	clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]);
987	clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]);
988	clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]);
989	clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]);
990
991	clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]);
992	clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]);
993	clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]);
994	clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]);
995
996	clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]);
997	clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]);
998	clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]);
999	clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]);
1000	}
1001	}
1002	}
1003	std::cout << std::endl << "Horizontal connections done" << std::endl;
1004
1005	// Inter Clusters vertical connections
1006	if (YMAX > 1)
1007	{
1008	for (size_t y = 0; y < (YMAX-1); y++)
1009	{
1010	for (size_t x = 0; x < XMAX; x++)
1011	{
1012	clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]);
1013	clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]);
1014	clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]);
1015	clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]);
1016
1017	clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]);
1018	clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]);
1019	clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]);
1020	clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]);
1021
1022	clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]);
1023	clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]);
1024	clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]);
1025	clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]);
1026
1027	clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]);
1028	clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]);
1029	clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]);
1030	clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]);
1031
1032	clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]);
1033	clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]);
1034	clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]);
1035	clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]);
1036	}
1037	}
1038	}
1039	std::cout << std::endl << "Vertical connections done" << std::endl;
1040
1041	// East & West boundary cluster connections
1042	for (size_t y = 0; y < (YMAX); y++)
1043	{
1044	clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]);
1045	clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]);
1046	clusters[XMAX-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[XMAX-1][y][EAST]);
1047	clusters[XMAX-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[XMAX-1][y][EAST]);
1048
1049	clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]);
1050	clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]);
1051	clusters[XMAX-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[XMAX-1][y][EAST]);
1052	clusters[XMAX-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[XMAX-1][y][EAST]);
1053
1054	clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]);
1055	clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]);
1056	clusters[XMAX-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[XMAX-1][y][EAST]);
1057	clusters[XMAX-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[XMAX-1][y][EAST]);
1058
1059	clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]);
1060	clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]);
1061	clusters[XMAX-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[XMAX-1][y][EAST]);
1062	clusters[XMAX-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[XMAX-1][y][EAST]);
1063
1064	clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]);
1065	clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]);
1066	clusters[XMAX-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[XMAX-1][y][EAST]);
1067	clusters[XMAX-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[XMAX-1][y][EAST]);
1068	}
1069
1070	std::cout << std::endl << "West & East boundaries connections done" << std::endl;
1071
1072	// North & South boundary clusters connections
1073	for (size_t x = 0; x < XMAX; x++)
1074	{
1075	clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]);
1076	clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]);
1077	clusters[x][YMAX-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][YMAX-1][NORTH]);
1078	clusters[x][YMAX-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][YMAX-1][NORTH]);
1079
1080	clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]);
1081	clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]);
1082	clusters[x][YMAX-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][YMAX-1][NORTH]);
1083	clusters[x][YMAX-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][YMAX-1][NORTH]);
1084
1085	clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]);
1086	clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]);
1087	clusters[x][YMAX-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][YMAX-1][NORTH]);
1088	clusters[x][YMAX-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][YMAX-1][NORTH]);
1089
1090	clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]);
1091	clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]);
1092	clusters[x][YMAX-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][YMAX-1][NORTH]);
1093	clusters[x][YMAX-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][YMAX-1][NORTH]);
1094
1095	clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]);
1096	clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]);
1097	clusters[x][YMAX-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][YMAX-1][NORTH]);
1098	clusters[x][YMAX-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][YMAX-1][NORTH]);
1099	}
1100
1101	std::cout << std::endl << "North & South boundaries connections done" << std::endl;
1102
1103	std::cout << std::endl;
1104
1105	////////////////////////////////////////////////////////
1106	// Simulation
1107	///////////////////////////////////////////////////////
1108
1109	sc_start(sc_core::sc_time(0, SC_NS));
1110	signal_resetn = false;
1111	signal_irq_false = false;
1112
1113	// set network boundaries signals default values
1114	// for all boundary clusters but the IO cluster
1115	for (size_t x = 0; x < XMAX ; x++)
1116	{
1117	for (size_t y = 0; y < YMAX ; y++)
1118	{
1119	for (size_t face = 0; face < 4; face++)
1120	{
1121	if ( (x != XMAX-1) or (y != YMAX-1) or (face != NORTH) )
1122	{
1123	signal_dspin_bound_cmd_in [x][y][face].write = false;
1124	signal_dspin_bound_cmd_in [x][y][face].read = true;
1125	signal_dspin_bound_cmd_out[x][y][face].write = false;
1126	signal_dspin_bound_cmd_out[x][y][face].read = true;
1127
1128	signal_dspin_bound_rsp_in [x][y][face].write = false;
1129	signal_dspin_bound_rsp_in [x][y][face].read = true;
1130	signal_dspin_bound_rsp_out[x][y][face].write = false;
1131	signal_dspin_bound_rsp_out[x][y][face].read = true;
1132	}
1133
1134	signal_dspin_bound_m2p_in [x][y][face].write = false;
1135	signal_dspin_bound_m2p_in [x][y][face].read = true;
1136	signal_dspin_bound_m2p_out[x][y][face].write = false;
1137	signal_dspin_bound_m2p_out[x][y][face].read = true;
1138
1139	signal_dspin_bound_p2m_in [x][y][face].write = false;
1140	signal_dspin_bound_p2m_in [x][y][face].read = true;
1141	signal_dspin_bound_p2m_out[x][y][face].write = false;
1142	signal_dspin_bound_p2m_out[x][y][face].read = true;
1143
1144	signal_dspin_bound_cla_in [x][y][face].write = false;
1145	signal_dspin_bound_cla_in [x][y][face].read = true;
1146	signal_dspin_bound_cla_out[x][y][face].write = false;
1147	signal_dspin_bound_cla_out[x][y][face].read = true;
1148	}
1149	}
1150	}
1151
1152	#if USE_PIC == 0
1153	signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH].write = false;
1154	signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH].read = true;
1155	signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH].read = true;
1156	signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH].write = false;
1157	#endif
1158
1159	// set default values for VCI signals connected to unused ports on iobus
1160	signal_vci_tgt_memc.rspval = false;
1161	signal_vci_tgt_xicu.rspval = false;
1162	for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) signal_vci_ini_proc[p].cmdval = false;
1163
1164	sc_start(sc_core::sc_time(1, SC_NS));
1165	signal_resetn = true;
1166
1167	if (gettimeofday(&t1, NULL) != 0)
1168	{
1169	perror("gettimeofday");
1170	return EXIT_FAILURE;
1171	}
1172
1173	// simulation loop
1174	for (uint64_t n = 1; n < ncycles && !stop_called; n++)
1175	{
1176	// Monitor a specific address for L1 cache
1177	// clusters[0][0]->proc[0]->cache_monitor(0x110002C078ULL);
1178
1179	// Monitor a specific address for L2 cache
1180	// clusters[0][0]->memc->cache_monitor( 0x0000201E00ULL );
1181
1182	// Monitor a specific address for one XRAM
1183	// clusters[0][0]->xram->start_monitor( 0x0000201E00ULL , 64);
1184
1185	// stats display
1186	if( (n % 5000000) == 0)
1187	{
1188
1189	if (gettimeofday(&t2, NULL) != 0)
1190	{
1191	perror("gettimeofday");
1192	return EXIT_FAILURE;
1193	}
1194
1195	ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
1196	ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
1197	std::cerr << "platform clock frequency "
1198	<< (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl;
1199
1200	if (gettimeofday(&t1, NULL) != 0)
1201	{
1202	perror("gettimeofday");
1203	return EXIT_FAILURE;
1204	}
1205	}
1206
1207	// trace display
1208	if ( trace_ok and (n > trace_from) )
1209	{
1210	std::cout << "****************** cycle " << std::dec << n ;
1211	std::cout << " ********************************************" << std::endl;
1212
1213	size_t l = 0;
1214	size_t x = 0;
1215	size_t y = 0;
1216
1217	if ( trace_proc_ok )
1218	{
1219	l = trace_proc_id & ((1<<P_WIDTH)-1) ;
1220	x = (trace_proc_id >> P_WIDTH) >> Y_WIDTH ;
1221	y = (trace_proc_id >> P_WIDTH) & ((1<<Y_WIDTH) - 1);
1222
1223	std::ostringstream proc_signame;
1224	proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
1225	clusters[x][y]->proc[l]->print_trace(1);
1226	clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
1227
1228	std::ostringstream xicu_signame;
1229	xicu_signame << "[SIG]XICU_" << x << "_" << y ;
1230	clusters[x][y]->xicu->print_trace(0);
1231	clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str());
1232
1233	if ( clusters[x][y]->signal_proc_irq[0] )
1234	std::cout << "### IRQ_PROC_" << x << "_" << y << "_0" << std::endl;
1235	if ( clusters[x][y]->signal_proc_irq[4] )
1236	std::cout << "### IRQ_PROC_" << x << "_" << y << "_1" << std::endl;
1237	if ( clusters[x][y]->signal_proc_irq[8] )
1238	std::cout << "### IRQ_PROC_" << x << "_" << y << "_2" << std::endl;
1239	if ( clusters[x][y]->signal_proc_irq[12] )
1240	std::cout << "### IRQ_PROC_" << x << "_" << y << "_3" << std::endl;
1241	}
1242
1243	if ( trace_memc_ok )
1244	{
1245	x = trace_memc_id >> Y_WIDTH;
1246	y = trace_memc_id & ((1<<Y_WIDTH) - 1);
1247
1248	std::ostringstream smemc;
1249	smemc << "[SIG]MEMC_" << x << "_" << y;
1250	std::ostringstream sxram;
1251	sxram << "[SIG]XRAM_" << x << "_" << y;
1252
1253	clusters[x][y]->memc->print_trace();
1254	clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
1255	clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
1256	}
1257
1258	// trace coherence signals
1259	// clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]");
1260	// clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]");
1261	// clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]");
1262	// clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]");
1263
1264	// clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]");
1265	// clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]");
1266	// clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]");
1267	// clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]");
1268
1269	// trace xbar(s) m2p
1270	// clusters[0][0]->xbar_m2p->print_trace();
1271	// clusters[1][0]->xbar_m2p->print_trace();
1272	// clusters[0][1]->xbar_m2p->print_trace();
1273	// clusters[1][1]->xbar_m2p->print_trace();
1274
1275	// trace router(s) m2p
1276	// clusters[0][0]->router_m2p->print_trace();
1277	// clusters[1][0]->router_m2p->print_trace();
1278	// clusters[0][1]->router_m2p->print_trace();
1279	// clusters[1][1]->router_m2p->print_trace();
1280
1281	#if USE_PIC
1282	// trace external ioc
1283	disk->print_trace();
1284	signal_vci_tgt_disk.print_trace("[SIG]DISK_TGT");
1285	signal_vci_ini_disk.print_trace("[SIG]DISK_INI");
1286
1287	// trace external iopic
1288	iopic->print_trace();
1289	signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT");
1290	signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI");
1291
1292	// trace external interrupts
1293	if (signal_irq_disk) std::cout << "### IRQ_DISK" << std::endl;
1294	#else
1295	clusters[0][0]->disk->print_trace();
1296	clusters[0][0]->signal_vci_tgt_disk.print_trace("[SIG]DISK_0_0");
1297	clusters[0][0]->signal_vci_ini_disk.print_trace("[SIG]DISK_0_0");
1298	#endif
1299
1300	} // end trace
1301
1302	sc_start(sc_core::sc_time(1, SC_NS));
1303	}
1304	// Free memory
1305	for (size_t i = 0 ; i < (XMAX * YMAX) ; i++)
1306	{
1307	size_t x = i / (YMAX);
1308	size_t y = i % (YMAX);
1309	delete clusters[x][y];
1310	}
1311
1312	return EXIT_SUCCESS;
1313	}
1314
1315	void handler(int dummy = 0)
1316	{
1317	stop_called = true;
1318	sc_stop();
1319	}
1320
1321	void voidhandler(int dummy = 0) {}
1322
1323	int sc_main (int argc, char *argv[])
1324	{
1325	signal(SIGINT, handler);
1326	signal(SIGPIPE, voidhandler);
1327
1328	try {
1329	return _main(argc, argv);
1330	} catch (std::exception &e) {
1331	std::cout << e.what() << std::endl;
1332	} catch (...) {
1333	std::cout << "Unknown exception occured" << std::endl;
1334	throw;
1335	}
1336	return 1;
1337	}
1338
1339
1340	// Local Variables:
1341	// tab-width: 3
1342	// c-basic-offset: 3
1343	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1344	// indent-tabs-mode: nil
1345	// End:
1346
1347	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3

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Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
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