[345] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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[378] | 2 | // File: tsar_xbar_cluster_mmu.h |
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[345] | 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : march 2011 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | |
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[378] | 9 | #ifndef SOCLIB_CABA_TSAR_XBAR_CLUSTER_H |
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| 10 | #define SOCLIB_CABA_TSAR_XBAR_CLUSTER_H |
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[345] | 11 | |
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| 12 | #include <systemc> |
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| 13 | #include <sys/time.h> |
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| 14 | #include <iostream> |
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| 15 | #include <sstream> |
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| 16 | #include <cstdlib> |
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| 17 | #include <cstdarg> |
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| 18 | |
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| 19 | #include "gdbserver.h" |
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| 20 | #include "mapping_table.h" |
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| 21 | #include "mips32.h" |
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| 22 | #include "vci_simple_ram.h" |
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| 23 | #include "vci_xicu.h" |
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| 24 | #include "dspin_local_crossbar.h" |
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| 25 | #include "vci_dspin_initiator_wrapper.h" |
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| 26 | #include "vci_dspin_target_wrapper.h" |
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| 27 | #include "virtual_dspin_router.h" |
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| 28 | #include "vci_multi_tty.h" |
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| 29 | #include "vci_multi_nic.h" |
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[378] | 30 | #include "vci_block_device_tsar.h" |
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[345] | 31 | #include "vci_framebuffer.h" |
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| 32 | #include "vci_multi_dma.h" |
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[351] | 33 | #include "vci_mem_cache.h" |
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| 34 | #include "vci_cc_vcache_wrapper.h" |
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[345] | 35 | |
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[389] | 36 | /////////////////////////////////////////////////////////// |
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| 37 | // VCI parameters for DIRECT network |
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| 38 | /////////////////////////////////////////////////////////// |
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| 39 | #define cell_width 4 |
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| 40 | #define address_width 32 |
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| 41 | #define plen_width 8 |
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| 42 | #define error_width 2 |
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| 43 | #define clen_width 1 |
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| 44 | #define rflag_width 1 |
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| 45 | #define srcid_width 14 |
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| 46 | #define pktid_width 4 |
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| 47 | #define trdid_width 4 |
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| 48 | #define wrplen_width 1 |
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[345] | 49 | |
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[389] | 50 | /////////////////////////////////////////////////////////// |
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| 51 | // VCI parameters for EXTERNAL network |
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| 52 | /////////////////////////////////////////////////////////// |
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| 53 | #define cell_width_ext 8 |
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| 54 | #define address_width_ext address_width |
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| 55 | #define plen_width_ext plen_width |
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| 56 | #define error_width_ext error_width |
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| 57 | #define clen_width_ext clen_width |
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| 58 | #define rflag_width_ext rflag_width |
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| 59 | #define srcid_width_ext srcid_width |
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| 60 | #define pktid_width_ext pktid_width |
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| 61 | #define trdid_width_ext trdid_width |
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| 62 | #define wrplen_width_ext wrplen_width |
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| 63 | |
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| 64 | namespace soclib { namespace caba { |
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| 65 | |
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[345] | 66 | /////////////////////////////////////////////////////////////////////////// |
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[389] | 67 | template< |
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| 68 | typename iss_t, int cmd_width, int rsp_width |
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| 69 | > |
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[378] | 70 | class TsarXbarCluster |
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[345] | 71 | /////////////////////////////////////////////////////////////////////////// |
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| 72 | : public soclib::caba::BaseModule |
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| 73 | { |
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[389] | 74 | // Define VCI parameters |
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| 75 | typedef soclib::caba::VciParams<cell_width, |
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| 76 | plen_width, |
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| 77 | address_width, |
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| 78 | error_width, |
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| 79 | clen_width, |
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| 80 | rflag_width, |
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| 81 | srcid_width, |
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| 82 | pktid_width, |
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| 83 | trdid_width, |
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| 84 | wrplen_width> vci_param_d; |
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[345] | 85 | |
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[389] | 86 | typedef soclib::caba::VciParamsBis<cell_width_ext, |
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| 87 | plen_width_ext, |
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| 88 | address_width_ext, |
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| 89 | error_width_ext, |
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| 90 | clen_width_ext, |
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| 91 | rflag_width_ext, |
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| 92 | srcid_width_ext, |
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| 93 | pktid_width_ext, |
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| 94 | trdid_width_ext, |
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| 95 | wrplen_width_ext> vci_param_x; |
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| 96 | |
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[345] | 97 | public: |
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| 98 | |
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[389] | 99 | // Ports |
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| 100 | sc_in<bool> p_clk; |
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| 101 | sc_in<bool> p_resetn; |
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| 102 | soclib::caba::DspinOutput<cmd_width> **p_cmd_out; |
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| 103 | soclib::caba::DspinInput<cmd_width> **p_cmd_in; |
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| 104 | soclib::caba::DspinOutput<rsp_width> **p_rsp_out; |
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| 105 | soclib::caba::DspinInput<rsp_width> **p_rsp_in; |
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[345] | 106 | |
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| 107 | // interrupt signals |
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[389] | 108 | sc_signal<bool> signal_false; |
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| 109 | sc_signal<bool> signal_proc_it[8]; |
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| 110 | sc_signal<bool> signal_irq_mdma[8]; |
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| 111 | sc_signal<bool> signal_irq_mtty[23]; |
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| 112 | sc_signal<bool> signal_irq_mnic_rx[8]; // unused |
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| 113 | sc_signal<bool> signal_irq_mnic_tx[8]; // unused |
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| 114 | sc_signal<bool> signal_irq_bdev; |
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| 115 | |
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| 116 | // DSPIN signals between DSPIN routers and local_crossbars |
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| 117 | DspinSignals<cmd_width> signal_dspin_cmd_l2g_d; |
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| 118 | DspinSignals<cmd_width> signal_dspin_cmd_g2l_d; |
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| 119 | DspinSignals<cmd_width> signal_dspin_m2p_l2g_c; |
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| 120 | DspinSignals<cmd_width> signal_dspin_m2p_g2l_c; |
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| 121 | DspinSignals<rsp_width> signal_dspin_rsp_l2g_d; |
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| 122 | DspinSignals<rsp_width> signal_dspin_rsp_g2l_d; |
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| 123 | DspinSignals<rsp_width> signal_dspin_p2m_l2g_c; |
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| 124 | DspinSignals<rsp_width> signal_dspin_p2m_g2l_c; |
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[345] | 125 | |
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[389] | 126 | // Direct VCI signals to VCI/DSPIN wrappers |
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| 127 | VciSignals<vci_param_d> signal_vci_ini_proc[8]; |
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| 128 | VciSignals<vci_param_d> signal_vci_ini_mdma; |
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| 129 | VciSignals<vci_param_d> signal_vci_ini_bdev; |
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[345] | 130 | |
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[389] | 131 | VciSignals<vci_param_d> signal_vci_tgt_memc; |
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| 132 | VciSignals<vci_param_d> signal_vci_tgt_xicu; |
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| 133 | VciSignals<vci_param_d> signal_vci_tgt_mdma; |
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| 134 | VciSignals<vci_param_d> signal_vci_tgt_mtty; |
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| 135 | VciSignals<vci_param_d> signal_vci_tgt_bdev; |
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| 136 | VciSignals<vci_param_d> signal_vci_tgt_brom; |
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| 137 | VciSignals<vci_param_d> signal_vci_tgt_fbuf; |
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| 138 | VciSignals<vci_param_d> signal_vci_tgt_mnic; |
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[345] | 139 | |
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[389] | 140 | // Direct DSPIN signals to local crossbars |
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| 141 | DspinSignals<cmd_width> signal_dspin_cmd_proc_i[8]; |
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| 142 | DspinSignals<rsp_width> signal_dspin_rsp_proc_i[8]; |
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| 143 | DspinSignals<cmd_width> signal_dspin_cmd_mdma_i; |
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| 144 | DspinSignals<rsp_width> signal_dspin_rsp_mdma_i; |
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| 145 | DspinSignals<cmd_width> signal_dspin_cmd_bdev_i; |
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| 146 | DspinSignals<rsp_width> signal_dspin_rsp_bdev_i; |
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[345] | 147 | |
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[389] | 148 | DspinSignals<cmd_width> signal_dspin_cmd_memc_t; |
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| 149 | DspinSignals<rsp_width> signal_dspin_rsp_memc_t; |
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| 150 | DspinSignals<cmd_width> signal_dspin_cmd_xicu_t; |
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| 151 | DspinSignals<rsp_width> signal_dspin_rsp_xicu_t; |
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| 152 | DspinSignals<cmd_width> signal_dspin_cmd_mdma_t; |
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| 153 | DspinSignals<rsp_width> signal_dspin_rsp_mdma_t; |
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| 154 | DspinSignals<cmd_width> signal_dspin_cmd_mtty_t; |
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| 155 | DspinSignals<rsp_width> signal_dspin_rsp_mtty_t; |
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| 156 | DspinSignals<cmd_width> signal_dspin_cmd_bdev_t; |
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| 157 | DspinSignals<rsp_width> signal_dspin_rsp_bdev_t; |
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| 158 | DspinSignals<cmd_width> signal_dspin_cmd_brom_t; |
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| 159 | DspinSignals<rsp_width> signal_dspin_rsp_brom_t; |
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| 160 | DspinSignals<cmd_width> signal_dspin_cmd_fbuf_t; |
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| 161 | DspinSignals<rsp_width> signal_dspin_rsp_fbuf_t; |
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| 162 | DspinSignals<cmd_width> signal_dspin_cmd_mnic_t; |
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| 163 | DspinSignals<rsp_width> signal_dspin_rsp_mnic_t; |
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[345] | 164 | |
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[389] | 165 | // Coherence DSPIN signals to local crossbar |
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| 166 | DspinSignals<cmd_width> signal_dspin_m2p_memc; |
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| 167 | DspinSignals<rsp_width> signal_dspin_p2m_memc; |
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| 168 | DspinSignals<cmd_width> signal_dspin_m2p_proc[8]; |
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| 169 | DspinSignals<rsp_width> signal_dspin_p2m_proc[8]; |
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[345] | 170 | |
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[389] | 171 | // external RAM VCI signal |
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| 172 | VciSignals<vci_param_x> signal_vci_xram; |
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| 173 | |
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[345] | 174 | // Components |
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| 175 | |
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[389] | 176 | VciCcVCacheWrapper<vci_param_d, cmd_width, rsp_width, iss_t>* proc[8]; |
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| 177 | VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_proc[4]; |
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[345] | 178 | |
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[389] | 179 | VciMemCache<vci_param_d, vci_param_x, rsp_width, cmd_width> * memc; |
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| 180 | VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_memc; |
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[345] | 181 | |
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[389] | 182 | VciXicu<vci_param_d>* xicu; |
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| 183 | VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_xicu; |
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[345] | 184 | |
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[389] | 185 | VciMultiDma<vci_param_d>* mdma; |
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| 186 | VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_mdma; |
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| 187 | VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mdma; |
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[345] | 188 | |
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[389] | 189 | VciSimpleRam<vci_param_x>* xram; |
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[345] | 190 | |
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[389] | 191 | VciSimpleRam<vci_param_d>* brom; |
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| 192 | VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_brom; |
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[345] | 193 | |
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[389] | 194 | VciMultiTty<vci_param_d>* mtty; |
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| 195 | VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mtty; |
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[345] | 196 | |
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[389] | 197 | VciFrameBuffer<vci_param_d>* fbuf; |
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| 198 | VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_fbuf; |
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[345] | 199 | |
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[389] | 200 | VciMultiNic<vci_param_d>* mnic; |
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| 201 | VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mnic; |
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[345] | 202 | |
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[389] | 203 | VciBlockDeviceTsar<vci_param_d>* bdev; |
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| 204 | VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_bdev; |
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| 205 | VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_bdev; |
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[345] | 206 | |
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[389] | 207 | DspinLocalCrossbar<cmd_width>* xbar_cmd_d; |
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| 208 | DspinLocalCrossbar<rsp_width>* xbar_rsp_d; |
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| 209 | DspinLocalCrossbar<cmd_width>* xbar_m2p_c; |
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| 210 | DspinLocalCrossbar<rsp_width>* xbar_p2m_c; |
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[345] | 211 | |
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[389] | 212 | VirtualDspinRouter<cmd_width>* router_cmd; |
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| 213 | VirtualDspinRouter<rsp_width>* router_rsp; |
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[345] | 214 | |
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[389] | 215 | TsarXbarCluster( sc_module_name insname, |
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[345] | 216 | size_t nb_procs, // number of processors |
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| 217 | size_t nb_ttys, // number of TTY terminals |
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| 218 | size_t nb_dmas, // number of DMA channels |
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| 219 | size_t x, // x coordinate |
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| 220 | size_t y, // y coordinate |
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| 221 | size_t cluster, // y + ymax*x |
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| 222 | const soclib::common::MappingTable &mtd, // direct mapping table |
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| 223 | const soclib::common::MappingTable &mtx, // xram mapping table |
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[389] | 224 | size_t x_width, // x field number of bits |
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| 225 | size_t y_width, // y field number of bits |
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| 226 | size_t l_width, // l field number of bits |
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| 227 | size_t tgtid_memc, |
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| 228 | size_t tgtid_xicu, |
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[345] | 229 | size_t tgtid_mdma, |
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[389] | 230 | size_t tgtid_fbuf, |
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[345] | 231 | size_t tgtid_mtty, |
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| 232 | size_t tgtid_brom, |
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| 233 | size_t tgtid_mnic, |
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| 234 | size_t tgtid_bdev, |
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| 235 | size_t memc_ways, |
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| 236 | size_t memc_sets, |
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| 237 | size_t l1_i_ways, |
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| 238 | size_t l1_i_sets, |
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| 239 | size_t l1_d_ways, |
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[389] | 240 | size_t l1_d_sets, |
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[345] | 241 | size_t xram_latency, // external ram latency |
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[389] | 242 | bool io, // I/O cluster if true |
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[345] | 243 | size_t xfb, // frame buffer pixels |
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| 244 | size_t yfb, // frame buffer lines |
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| 245 | char* disk_name, // virtual disk for BDEV |
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| 246 | size_t block_size, // block size for BDEV |
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| 247 | size_t nic_channels, // number of channels |
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| 248 | char* nic_rx_name, // file name rx packets |
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| 249 | char* nic_tx_name, // file name tx packets |
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[389] | 250 | uint32_t nic_timeout, // number of cycles |
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| 251 | const Loader &loader, // loader for BROM |
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[345] | 252 | uint32_t frozen_cycles, // max frozen cycles |
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| 253 | uint32_t start_debug_cycle, |
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| 254 | bool memc_debug_ok, |
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| 255 | bool proc_debug_ok); |
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| 256 | |
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[389] | 257 | ~TsarXbarCluster(); |
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[345] | 258 | }; |
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| 259 | }} |
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| 260 | |
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| 261 | #endif |
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