Context Navigation

source: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp @ 706

Last change on this file since 706 was 706, checked in by meunier, 10 years ago
Replaced vci_dspin_local_crossbar with a vci_local_crossbar in tsar_generic_xbar Added the scripts/ directory in tsar_generic_xbar
File size: 29.5 KB

Rev	Line
[345]	1	//////////////////////////////////////////////////////////////////////////////
[378]	2	// File: tsar_xbar_cluster.cpp
[428]	3	// Author: Alain Greiner
[345]	4	// Copyright: UPMC/LIP6
	5	// Date : march 2011
	6	// This program is released under the GNU public license
	7	//////////////////////////////////////////////////////////////////////////////
	8	// This file define a TSAR cluster architecture with virtual memory:
[428]	9	// - It uses two virtual_dspin_router as distributed global interconnect
	10	// - It uses four dspin_local_crossbar as local interconnect
[345]	11	// - It uses the vci_cc_vcache_wrapper
	12	// - It uses the vci_mem_cache
	13	// - It contains a private RAM with a variable latency to emulate the L3 cache
	14	// - It can contains 1, 2 or 4 processors
	15	// - Each processor has a private dma channel (vci_multi_dma)
	16	// - It uses the vci_xicu interrupt controller
[396]	17	// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
[428]	18	// - The Multi-TTY component controls up to 15 terminals.
[345]	19	// - Each Multi-DMA component controls up to 8 DMA channels.
	20	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
	21	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
	22	// - The BDEV IRQ is connected to IRQ_IN[31]
[428]	23	//////////////////////////////////////////////////////////////////////////////////
[345]	24
[378]	25	#include "../include/tsar_xbar_cluster.h"
[345]	26
[389]	27
[345]	28	namespace soclib {
	29	namespace caba {
	30
[396]	31	////////////////////////////////////////////////////////////////////////////////////
[428]	32	template<size_t dspin_cmd_width,
[396]	33	size_t dspin_rsp_width,
	34	typename vci_param_int,
	35	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
	36	dspin_rsp_width,
	37	vci_param_int,
	38	vci_param_ext>::TsarXbarCluster(
	39	////////////////////////////////////////////////////////////////////////////////////
[345]	40	sc_module_name insname,
	41	size_t nb_procs,
	42	size_t nb_ttys,
	43	size_t nb_dmas,
	44	size_t x_id,
	45	size_t y_id,
	46	size_t cluster_id,
	47	const soclib::common::MappingTable &mtd,
[428]	48	const soclib::common::MappingTable &mtx,
[345]	49	size_t x_width,
	50	size_t y_width,
	51	size_t l_width,
	52	size_t tgtid_memc,
	53	size_t tgtid_xicu,
	54	size_t tgtid_mdma,
	55	size_t tgtid_fbuf,
	56	size_t tgtid_mtty,
	57	size_t tgtid_brom,
	58	size_t tgtid_mnic,
[475]	59	size_t tgtid_chbuf,
[345]	60	size_t tgtid_bdev,
[547]	61	size_t tgtid_simh,
[345]	62	size_t memc_ways,
	63	size_t memc_sets,
	64	size_t l1_i_ways,
	65	size_t l1_i_sets,
	66	size_t l1_d_ways,
	67	size_t l1_d_sets,
[706]	68	size_t irq_per_processor,
[345]	69	size_t xram_latency,
	70	bool io,
	71	size_t xfb,
	72	size_t yfb,
	73	char* disk_name,
	74	size_t block_size,
	75	size_t nic_channels,
	76	char* nic_rx_name,
	77	char* nic_tx_name,
	78	uint32_t nic_timeout,
[485]	79	size_t chbufdma_channels,
[706]	80	const Loader & loader,
[345]	81	uint32_t frozen_cycles,
	82	uint32_t debug_start_cycle,
	83	bool memc_debug_ok,
	84	bool proc_debug_ok)
	85	: soclib::caba::BaseModule(insname),
	86	p_clk("clk"),
	87	p_resetn("resetn")
	88
	89	{
[508]	90
	91	n_procs = nb_procs;
	92
[345]	93	// Vectors of ports definition
[508]	94	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cmd_in", 4, 3);
	95	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cmd_out", 4, 3);
	96	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_rsp_in", 4, 2);
	97	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_rsp_out", 4, 2);
[345]	98
[396]	99	/////////////////////////////////////////////////////////////////////////////
[428]	100	// Components definition
[345]	101	/////////////////////////////////////////////////////////////////////////////
	102
	103	for (size_t p = 0; p < nb_procs; p++)
[428]	104	{
[345]	105	std::ostringstream sproc;
[396]	106	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
	107	proc[p] = new VciCcVCacheWrapper<vci_param_int,
	108	dspin_cmd_width,
[428]	109	dspin_rsp_width,
[396]	110	GdbServer<Mips32ElIss> >(
[345]	111	sproc.str().c_str(),
[508]	112	cluster_id * nb_procs + p, // GLOBAL PROC_ID
[428]	113	mtd, // Mapping Table
[345]	114	IntTab(cluster_id,p), // SRCID
	115	(cluster_id << l_width) + p, // CC_GLOBAL_ID
	116	8, // ITLB ways
	117	8, // ITLB sets
	118	8, // DTLB ways
	119	8, // DTLB sets
[508]	120	l1_i_ways,l1_i_sets, 16, // ICACHE size
	121	l1_d_ways,l1_d_sets, 16, // DCACHE size
[345]	122	4, // WBUF nlines
	123	4, // WBUF nwords
	124	x_width,
	125	y_width,
	126	frozen_cycles, // max frozen cycles
	127	debug_start_cycle,
	128	proc_debug_ok);
	129
	130	}
	131
	132	/////////////////////////////////////////////////////////////////////////////
[396]	133	std::ostringstream smemc;
	134	smemc << "memc_" << x_id << "_" << y_id;
	135	memc = new VciMemCache<vci_param_int,
	136	vci_param_ext,
	137	dspin_rsp_width,
	138	dspin_cmd_width>(
	139	smemc.str().c_str(),
[345]	140	mtd, // Mapping Table direct space
	141	mtx, // Mapping Table external space
	142	IntTab(cluster_id), // SRCID external space
	143	IntTab(cluster_id, tgtid_memc), // TGTID direct space
[706]	144	//(cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID
[504]	145	x_width, // Number of x bits in platform
	146	y_width, // Number of y bits in platform
[345]	147	memc_ways, memc_sets, 16, // CACHE SIZE
	148	3, // MAX NUMBER OF COPIES
	149	4096, // HEAP SIZE
	150	8, // TRANSACTION TABLE DEPTH
	151	8, // UPDATE TABLE DEPTH
[468]	152	8, // INVALIDATE TABLE DEPTH
[345]	153	debug_start_cycle,
[508]	154	memc_debug_ok);
[345]	155
	156
	157	/////////////////////////////////////////////////////////////////////////////
[396]	158	std::ostringstream sxram;
	159	sxram << "xram_" << x_id << "_" << y_id;
	160	xram = new VciSimpleRam<vci_param_ext>(
	161	sxram.str().c_str(),
[345]	162	IntTab(cluster_id),
	163	mtx,
	164	loader,
	165	xram_latency);
[379]	166
[345]	167	/////////////////////////////////////////////////////////////////////////////
[396]	168	std::ostringstream sxicu;
	169	sxicu << "xicu_" << x_id << "_" << y_id;
	170	xicu = new VciXicu<vci_param_int>(
	171	sxicu.str().c_str(),
[345]	172	mtd, // mapping table
	173	IntTab(cluster_id, tgtid_xicu), // TGTID_D
[706]	174	nb_procs, // number of timer IRQs
[345]	175	32, // number of hard IRQs
[389]	176	32, // number of soft IRQs
[706]	177	nb_procs*irq_per_processor); // number of output IRQs
[345]	178
	179
	180	/////////////////////////////////////////////////////////////////////////////
[396]	181	std::ostringstream smdma;
	182	smdma << "mdma_" << x_id << "_" << y_id;
	183	mdma = new VciMultiDma<vci_param_int>(
	184	smdma.str().c_str(),
[345]	185	mtd,
	186	IntTab(cluster_id, nb_procs), // SRCID
	187	IntTab(cluster_id, tgtid_mdma), // TGTID
	188	64, // burst size
[379]	189	nb_dmas); // number of IRQs
[345]	190
	191
	192	/////////////////////////////////////////////////////////////////////////////
	193	size_t nb_direct_initiators = nb_procs + 1;
	194	size_t nb_direct_targets = 3;
[508]	195	if (io)
[345]	196	{
[475]	197	nb_direct_initiators = nb_procs + 3;
[547]	198	nb_direct_targets = 10;
[345]	199	}
	200
[706]	201	std::ostringstream sxbar;
	202	sxbar << "xbar_" << x_id << "_" << y_id;
	203	xbar_d = new VciLocalCrossbar<vci_param_int>(
	204	sxbar.str().c_str(),
	205	mtd, // mapping table
	206	//x_id, y_id, // cluster coordinates
	207	cluster_id,
	208	nb_direct_initiators, // number of local of sources
	209	nb_direct_targets, // number of local dests
	210	tgtid_memc); // Default target
[345]	211
[706]	212	////////////// vci_dspin wrappers
	213	std::ostringstream swtxbar;
	214	swtxbar << "wt_xbar_" << x_id << "_" << y_id;
	215	wt_xbar_d = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
	216	swtxbar.str().c_str(),
	217	x_width + y_width + l_width );
[345]	218
[706]	219	std::ostringstream swixbar;
	220	swixbar << "wi_xbar_" << x_id << "_" << y_id;
	221	wi_xbar_d = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
	222	swixbar.str().c_str(),
	223	x_width + y_width + l_width );
	224
[345]	225	/////////////////////////////////////////////////////////////////////////////
[396]	226	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
[379]	227	"xbar_m2p_c",
[345]	228	mtd, // mapping table
	229	x_id, y_id, // cluster coordinates
	230	x_width, y_width, l_width,
	231	1, // number of local sources
[435]	232	nb_procs, // number of local targets
[428]	233	2, 2, // fifo depths
[435]	234	true, // CMD
[345]	235	false, // don't use local routing table
[435]	236	true ); // broadcast
[345]	237
	238	/////////////////////////////////////////////////////////////////////////////
[396]	239	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
[379]	240	"xbar_p2m_c",
[345]	241	mtd, // mapping table
	242	x_id, y_id, // cluster coordinates
[379]	243	x_width, y_width, 0, // l_width unused on p2m network
[345]	244	nb_procs, // number of local sources
	245	1, // number of local dests
[428]	246	2, 2, // fifo depths
[435]	247	false, // RSP
[345]	248	false, // don't use local routing table
[435]	249	false ); // no broadcast
[345]	250
	251	/////////////////////////////////////////////////////////////////////////////
[468]	252	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
	253	"xbar_clack_c",
	254	mtd, // mapping table
	255	x_id, y_id, // cluster coordinates
	256	x_width, y_width, l_width,
	257	1, // number of local sources
	258	nb_procs, // number of local targets
	259	1, 1, // fifo depths
	260	true, // CMD
	261	false, // don't use local routing table
	262	false); // broadcast
	263
	264	/////////////////////////////////////////////////////////////////////////////
[396]	265	router_cmd = new VirtualDspinRouter<dspin_cmd_width>(
[379]	266	"router_cmd",
[345]	267	x_id,y_id, // coordinate in the mesh
	268	x_width, y_width, // x & y fields width
[468]	269	3, // nb virtual channels
[345]	270	4,4); // input & output fifo depths
	271
	272	/////////////////////////////////////////////////////////////////////////////
[396]	273	router_rsp = new VirtualDspinRouter<dspin_rsp_width>(
[379]	274	"router_rsp",
[345]	275	x_id,y_id, // coordinates in mesh
	276	x_width, y_width, // x & y fields width
[465]	277	2, // nb virtual channels
[345]	278	4,4); // input & output fifo depths
	279
	280	// IO cluster components
[508]	281	if (io)
[345]	282	{
	283	/////////////////////////////////////////////
[435]	284	brom = new VciSimpleRom<vci_param_int>(
[396]	285	"brom",
	286	IntTab(cluster_id, tgtid_brom),
	287	mtd,
	288	loader);
[345]	289
	290	/////////////////////////////////////////////
[396]	291	fbuf = new VciFrameBuffer<vci_param_int>(
	292	"fbuf",
	293	IntTab(cluster_id, tgtid_fbuf),
	294	mtd,
[428]	295	xfb, yfb);
[345]	296
	297	/////////////////////////////////////////////
[396]	298	bdev = new VciBlockDeviceTsar<vci_param_int>(
	299	"bdev",
	300	mtd,
[508]	301	IntTab(cluster_id, nb_procs + 1),
[396]	302	IntTab(cluster_id, tgtid_bdev),
	303	disk_name,
	304	block_size,
	305	64); // burst size
[345]	306
[548]	307	int mac = 0xBEEF0000;
	308	mnic = new VciMultiNic<vci_param_int>(
	309	"mnic",
	310	IntTab(cluster_id, tgtid_mnic),
	311	mtd,
	312	nic_channels,
[619]	313	mac, // mac_4 address
	314	0xBABE, // mac_2 address
[548]	315	nic_rx_name,
[619]	316	nic_tx_name);
[345]	317
	318
[706]	319
[345]	320	/////////////////////////////////////////////
[475]	321	chbuf = new VciChbufDma<vci_param_int>(
	322	"chbuf_dma",
	323	mtd,
	324	IntTab(cluster_id, nb_procs + 2),
	325	IntTab(cluster_id, tgtid_chbuf),
	326	64,
[485]	327	chbufdma_channels);
[475]	328
	329	/////////////////////////////////////////////
[345]	330	std::vector<std::string> vect_names;
[508]	331	for (size_t tid = 0; tid < nb_ttys; tid++)
[345]	332	{
	333	std::ostringstream term_name;
	334	term_name << "term" << tid;
	335	vect_names.push_back(term_name.str().c_str());
	336	}
[396]	337	mtty = new VciMultiTty<vci_param_int>(
	338	"mtty",
	339	IntTab(cluster_id, tgtid_mtty),
[428]	340	mtd,
[396]	341	vect_names);
[345]	342
[547]	343	simhelper = new VciSimhelper<vci_param_int>(
	344	"sim_helper",
	345	IntTab(cluster_id, tgtid_simh),
	346	mtd);
[345]	347	}
	348
	349	////////////////////////////////////
	350	// Connections are defined here
	351	////////////////////////////////////
	352
	353	//////////////////////// CMD ROUTER and RSP ROUTER
	354	router_cmd->p_clk (this->p_clk);
	355	router_cmd->p_resetn (this->p_resetn);
	356	router_rsp->p_clk (this->p_clk);
	357	router_rsp->p_resetn (this->p_resetn);
[465]	358
[508]	359	for (int i = 0; i < 4; i++)
[345]	360	{
[468]	361	for (int k = 0; k < 3; k++)
[345]	362	{
[465]	363	router_cmd->p_out[i][k] (this->p_cmd_out[i][k]);
	364	router_cmd->p_in[i][k] (this->p_cmd_in[i][k]);
[468]	365	}
	366
	367	for (int k = 0; k < 2; k++)
	368	{
[465]	369	router_rsp->p_out[i][k] (this->p_rsp_out[i][k]);
	370	router_rsp->p_in[i][k] (this->p_rsp_in[i][k]);
[345]	371	}
	372	}
	373
[465]	374	router_cmd->p_out[4][0] (signal_dspin_cmd_g2l_d);
	375	router_cmd->p_out[4][1] (signal_dspin_m2p_g2l_c);
[468]	376	router_cmd->p_out[4][2] (signal_dspin_clack_g2l_c);
[465]	377	router_cmd->p_in[4][0] (signal_dspin_cmd_l2g_d);
	378	router_cmd->p_in[4][1] (signal_dspin_m2p_l2g_c);
[468]	379	router_cmd->p_in[4][2] (signal_dspin_clack_l2g_c);
[345]	380
[465]	381	router_rsp->p_out[4][0] (signal_dspin_rsp_g2l_d);
	382	router_rsp->p_out[4][1] (signal_dspin_p2m_g2l_c);
	383	router_rsp->p_in[4][0] (signal_dspin_rsp_l2g_d);
	384	router_rsp->p_in[4][1] (signal_dspin_p2m_l2g_c);
[345]	385
[468]	386
[345]	387	std::cout << " - CMD & RSP routers connected" << std::endl;
	388
[706]	389	wi_xbar_d->p_clk (this->p_clk);
	390	wi_xbar_d->p_resetn (this->p_resetn);
	391	wi_xbar_d->p_vci (signal_vci_l2g_d);
	392	wi_xbar_d->p_dspin_cmd (signal_dspin_cmd_l2g_d);
	393	wi_xbar_d->p_dspin_rsp (signal_dspin_rsp_g2l_d);
[345]	394
[706]	395	std::cout << " - Wrapper Ini VCI2DSPIN Direct connected" << std::endl;
[345]	396
[706]	397	wt_xbar_d->p_clk (this->p_clk);
	398	wt_xbar_d->p_resetn (this->p_resetn);
	399	wt_xbar_d->p_vci (signal_vci_g2l_d);
	400	wt_xbar_d->p_dspin_cmd (signal_dspin_cmd_g2l_d);
	401	wt_xbar_d->p_dspin_rsp (signal_dspin_rsp_l2g_d);
[345]	402
[706]	403	std::cout << " - Wrapper Tgt VCI2DSPIN Direct connected" << std::endl;
[345]	404
[706]	405	///////////////////// CMD VCI local crossbar direct
	406	xbar_d->p_clk (this->p_clk);
	407	xbar_d->p_resetn (this->p_resetn);
	408	xbar_d->p_target_to_up (signal_vci_g2l_d);
	409	xbar_d->p_initiator_to_up (signal_vci_l2g_d);
[345]	410
[706]	411	xbar_d->p_to_target[tgtid_memc] (signal_vci_tgt_memc);
	412	xbar_d->p_to_target[tgtid_xicu] (signal_vci_tgt_xicu);
	413	xbar_d->p_to_target[tgtid_mdma] (signal_vci_tgt_mdma);
[345]	414
[706]	415	xbar_d->p_to_initiator[nb_procs] (signal_vci_ini_mdma);
[345]	416
	417	for (size_t p = 0; p < nb_procs; p++)
[706]	418	xbar_d->p_to_initiator[p] (signal_vci_ini_proc[p]);
[345]	419
[508]	420	if (io)
[345]	421	{
[706]	422	xbar_d->p_to_target[tgtid_mtty] (signal_vci_tgt_mtty);
	423	xbar_d->p_to_target[tgtid_brom] (signal_vci_tgt_brom);
	424	xbar_d->p_to_target[tgtid_bdev] (signal_vci_tgt_bdev);
	425	xbar_d->p_to_target[tgtid_fbuf] (signal_vci_tgt_fbuf);
	426	xbar_d->p_to_target[tgtid_mnic] (signal_vci_tgt_mnic);
	427	xbar_d->p_to_target[tgtid_chbuf] (signal_vci_tgt_chbuf);
	428	xbar_d->p_to_target[tgtid_simh] (signal_vci_tgt_simh);
[345]	429
[706]	430	xbar_d->p_to_initiator[nb_procs + 1] (signal_vci_ini_bdev);
	431	xbar_d->p_to_initiator[nb_procs + 2] (signal_vci_ini_chbuf);
[345]	432	}
	433
[706]	434	std::cout << " - Direct crossbar connected" << std::endl;
[345]	435
	436	////////////////////// M2P DSPIN local crossbar coherence
	437	xbar_m2p_c->p_clk (this->p_clk);
	438	xbar_m2p_c->p_resetn (this->p_resetn);
	439	xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c);
	440	xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c);
[360]	441	xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc);
[428]	442	for (size_t p = 0; p < nb_procs; p++)
[345]	443	xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]);
	444
	445	std::cout << " - M2P Coherence crossbar connected" << std::endl;
	446
[468]	447	////////////////////// CLACK DSPIN local crossbar coherence
	448	xbar_clack_c->p_clk (this->p_clk);
	449	xbar_clack_c->p_resetn (this->p_resetn);
	450	xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c);
	451	xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c);
	452	xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc);
	453	for (size_t p = 0; p < nb_procs; p++)
[508]	454	xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]);
[468]	455
	456	std::cout << " - Clack Coherence crossbar connected" << std::endl;
	457
[345]	458	////////////////////////// P2M DSPIN local crossbar coherence
	459	xbar_p2m_c->p_clk (this->p_clk);
	460	xbar_p2m_c->p_resetn (this->p_resetn);
	461	xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c);
	462	xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c);
[360]	463	xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc);
[428]	464	for (size_t p = 0; p < nb_procs; p++)
[345]	465	xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]);
	466
	467	std::cout << " - P2M Coherence crossbar connected" << std::endl;
	468
	469
	470	//////////////////////////////////// Processors
	471	for (size_t p = 0; p < nb_procs; p++)
	472	{
	473	proc[p]->p_clk (this->p_clk);
	474	proc[p]->p_resetn (this->p_resetn);
	475	proc[p]->p_vci (signal_vci_ini_proc[p]);
[468]	476	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
	477	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
	478	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
[624]	479
[706]	480	for ( size_t i = 0; i < irq_per_processor; i++)
[345]	481	{
[706]	482	proc[p]->p_irq[i] (signal_proc_it[p*irq_per_processor + i]);
[624]	483	}
[706]	484	for ( size_t j = irq_per_processor; j < 6; j++) // 6 = number of irqs in the MIPS
[624]	485	{
[345]	486	proc[p]->p_irq[j] (signal_false);
	487	}
	488
	489	}
	490
	491	std::cout << " - Processors connected" << std::endl;
	492
	493	///////////////////////////////////// XICU
[428]	494	xicu->p_clk (this->p_clk);
	495	xicu->p_resetn (this->p_resetn);
	496	xicu->p_vci (signal_vci_tgt_xicu);
[706]	497	for (size_t p = 0; p < nb_procs * irq_per_processor; p++)
[345]	498	{
[706]	499	xicu->p_irq[p] (signal_proc_it[p]);
[345]	500	}
[508]	501	for (size_t i = 0; i < 32; i++)
[345]	502	{
[508]	503	if (io) // I/O cluster
[345]	504	{
	505	if (i < 8) xicu->p_hwi[i] (signal_false);
[508]	506	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
[345]	507	else if (i < 16) xicu->p_hwi[i] (signal_false);
[508]	508	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i - 16]);
[602]	509	else if (i < 30) xicu->p_hwi[i] (signal_false);
	510	else if (i < 31) xicu->p_hwi[i] (signal_irq_memc);
[345]	511	else xicu->p_hwi[i] (signal_irq_bdev);
	512	}
	513	else // other clusters
	514	{
	515	if (i < 8) xicu->p_hwi[i] (signal_false);
[508]	516	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
[602]	517	else if (i < 30) xicu->p_hwi[i] (signal_false);
	518	else if (i < 31) xicu->p_hwi[i] (signal_irq_memc);
[428]	519	else xicu->p_hwi[i] (signal_false);
[345]	520	}
	521	}
	522
	523	std::cout << " - XICU connected" << std::endl;
	524
	525	//////////////////////////////////////////////// MEMC
[428]	526	memc->p_clk (this->p_clk);
	527	memc->p_resetn (this->p_resetn);
[602]	528	memc->p_irq (signal_irq_memc);
[428]	529	memc->p_vci_ixr (signal_vci_xram);
	530	memc->p_vci_tgt (signal_vci_tgt_memc);
[468]	531	memc->p_dspin_p2m (signal_dspin_p2m_memc);
	532	memc->p_dspin_m2p (signal_dspin_m2p_memc);
	533	memc->p_dspin_clack (signal_dspin_clack_memc);
[345]	534
	535	std::cout << " - MEMC connected" << std::endl;
	536
	537	/////////////////////////////////////////////// XRAM
[428]	538	xram->p_clk (this->p_clk);
	539	xram->p_resetn (this->p_resetn);
	540	xram->p_vci (signal_vci_xram);
[345]	541
	542	std::cout << " - XRAM connected" << std::endl;
	543
[360]	544	////////////////////////////////////////////// MDMA
[428]	545	mdma->p_clk (this->p_clk);
	546	mdma->p_resetn (this->p_resetn);
	547	mdma->p_vci_target (signal_vci_tgt_mdma);
	548	mdma->p_vci_initiator (signal_vci_ini_mdma);
[508]	549	for (size_t i = 0; i < nb_dmas; i++)
[345]	550	mdma->p_irq[i] (signal_irq_mdma[i]);
	551
	552	std::cout << " - MDMA connected" << std::endl;
	553
[428]	554	/////////////////////////////// Components in I/O cluster
[345]	555
[508]	556	if (io)
[428]	557	{
	558	// BDEV
	559	bdev->p_clk (this->p_clk);
[345]	560	bdev->p_resetn (this->p_resetn);
	561	bdev->p_irq (signal_irq_bdev);
	562	bdev->p_vci_target (signal_vci_tgt_bdev);
	563	bdev->p_vci_initiator (signal_vci_ini_bdev);
	564
	565	std::cout << " - BDEV connected" << std::endl;
	566
	567	// FBUF
	568	fbuf->p_clk (this->p_clk);
	569	fbuf->p_resetn (this->p_resetn);
	570	fbuf->p_vci (signal_vci_tgt_fbuf);
	571
	572	std::cout << " - FBUF connected" << std::endl;
	573
	574	// MNIC
	575	mnic->p_clk (this->p_clk);
	576	mnic->p_resetn (this->p_resetn);
	577	mnic->p_vci (signal_vci_tgt_mnic);
[508]	578	for (size_t i = 0; i < nic_channels; i++)
[345]	579	{
[548]	580	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
	581	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
[345]	582	}
	583
	584	std::cout << " - MNIC connected" << std::endl;
	585
[475]	586	// CHBUF
	587	chbuf->p_clk (this->p_clk);
	588	chbuf->p_resetn (this->p_resetn);
	589	chbuf->p_vci_target (signal_vci_tgt_chbuf);
	590	chbuf->p_vci_initiator (signal_vci_ini_chbuf);
[508]	591	for (size_t i = 0; i < chbufdma_channels; i++)
[475]	592	{
	593	chbuf->p_irq[i] (signal_irq_chbuf[i]);
	594	}
	595
	596	std::cout << " - CHBUF connected" << std::endl;
	597
[345]	598	// BROM
	599	brom->p_clk (this->p_clk);
	600	brom->p_resetn (this->p_resetn);
	601	brom->p_vci (signal_vci_tgt_brom);
	602
	603	std::cout << " - BROM connected" << std::endl;
	604
	605	// MTTY
	606	mtty->p_clk (this->p_clk);
	607	mtty->p_resetn (this->p_resetn);
	608	mtty->p_vci (signal_vci_tgt_mtty);
[508]	609	for (size_t i = 0; i < nb_ttys; i++)
[345]	610	{
[428]	611	mtty->p_irq[i] (signal_irq_mtty[i]);
[345]	612	}
	613
[706]	614	std::cout << " - MTTY connected" << std::endl;
[360]	615
[547]	616
	617	// Sim Helper
	618	simhelper->p_clk (this->p_clk);
	619	simhelper->p_resetn (this->p_resetn);
	620	simhelper->p_vci (signal_vci_tgt_simh);
	621
[706]	622	std::cout << " - SIMH connected" << std::endl;
[345]	623	}
	624	} // end constructor
	625
[508]	626
	627
	628	template<size_t dspin_cmd_width,
	629	size_t dspin_rsp_width,
	630	typename vci_param_int,
	631	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
	632	dspin_rsp_width,
	633	vci_param_int,
	634	vci_param_ext>::~TsarXbarCluster() {
	635
[512]	636	dealloc_elems<DspinInput<dspin_cmd_width> > (p_cmd_in, 4, 3);
	637	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cmd_out, 4, 3);
	638	dealloc_elems<DspinInput<dspin_rsp_width> > (p_rsp_in, 4, 2);
	639	dealloc_elems<DspinOutput<dspin_rsp_width> >(p_rsp_out, 4, 2);
	640
[508]	641	for (size_t p = 0; p < n_procs; p++)
	642	{
	643	delete proc[p];
	644	}
	645
	646	delete memc;
	647	delete xram;
	648	delete xicu;
	649	delete mdma;
[706]	650	delete xbar_d;
	651	delete wt_xbar_d;
	652	delete wi_xbar_d;
[508]	653	delete xbar_m2p_c;
	654	delete xbar_p2m_c;
	655	delete xbar_clack_c;
	656	delete router_cmd;
	657	delete router_rsp;
	658	if (brom != NULL)
	659	{
	660	delete brom;
	661	delete fbuf;
	662	delete bdev;
	663	delete mnic;
	664	delete chbuf;
	665	delete mtty;
[547]	666	delete simhelper;
[508]	667	}
	668	}
	669
	670
[396]	671	}}
[345]	672
	673	// Local Variables:
[508]	674	// tab-width: 4
	675	// c-basic-offset: 4
[345]	676	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	677	// indent-tabs-mode: nil
	678	// End:
	679
[508]	680	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
[345]	681
	682
	683

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
Plural-Forms: nplurals=2; plural=(n != 1)
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Generated-By: Babel 2.8.0