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source: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp @ 885

Last change on this file since 885 was 885, checked in by devigne, 9 years ago
platform: tsar_generic_xbar Replace virtual_dspin_router by dspin_router.
File size: 33.6 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_xbar_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : march 2011
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// This file define a TSAR cluster architecture with virtual memory:
9	// - It uses two virtual_dspin_router as distributed global interconnect
10	// - It uses four dspin_local_crossbar as local interconnect
11	// - It uses the vci_cc_vcache_wrapper
12	// - It uses the vci_mem_cache
13	// - It contains a private RAM with a variable latency to emulate the L3 cache
14	// - It can contains 1, 2 or 4 processors
15	// - Each processor has a private dma channel (vci_multi_dma)
16	// - It uses the vci_xicu interrupt controller
17	// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
18	// - The Multi-TTY component controls up to 15 terminals.
19	// - Each Multi-DMA component controls up to 8 DMA channels.
20	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
21	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
22	// - The BDEV IRQ is connected to IRQ_IN[31]
23	//////////////////////////////////////////////////////////////////////////////////
24
25	#include "../include/tsar_xbar_cluster.h"
26
27
28	namespace soclib {
29	namespace caba {
30
31	////////////////////////////////////////////////////////////////////////////////////
32	template<size_t dspin_cmd_width,
33	size_t dspin_rsp_width,
34	typename vci_param_int,
35	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
36	dspin_rsp_width,
37	vci_param_int,
38	vci_param_ext>::TsarXbarCluster(
39	////////////////////////////////////////////////////////////////////////////////////
40	sc_module_name insname,
41	size_t nb_procs,
42	size_t nb_ttys,
43	size_t nb_dmas,
44	size_t x_id,
45	size_t y_id,
46	size_t cluster_id,
47	const soclib::common::MappingTable &mtd,
48	const soclib::common::MappingTable &mtx,
49	size_t x_width,
50	size_t y_width,
51	size_t l_width,
52	size_t tgtid_memc,
53	size_t tgtid_xicu,
54	size_t tgtid_mdma,
55	size_t tgtid_fbuf,
56	size_t tgtid_mtty,
57	size_t tgtid_brom,
58	size_t tgtid_mnic,
59	size_t tgtid_chbuf,
60	size_t tgtid_bdev,
61	size_t tgtid_simh,
62	size_t memc_ways,
63	size_t memc_sets,
64	size_t l1_i_ways,
65	size_t l1_i_sets,
66	size_t l1_d_ways,
67	size_t l1_d_sets,
68	size_t irq_per_processor,
69	size_t xram_latency,
70	bool io,
71	size_t xfb,
72	size_t yfb,
73	char* disk_name,
74	size_t block_size,
75	size_t nic_channels,
76	char* nic_rx_name,
77	char* nic_tx_name,
78	uint32_t nic_timeout,
79	size_t chbufdma_channels,
80	const Loader & loader,
81	uint32_t frozen_cycles,
82	uint32_t debug_start_cycle,
83	bool memc_debug_ok,
84	bool proc_debug_ok)
85	: soclib::caba::BaseModule(insname),
86	p_clk("clk"),
87	p_resetn("resetn")
88
89	{
90
91	n_procs = nb_procs;
92
93	/////////////////////////////////////////////////////////////////////////////
94	// Vectors of ports definition and allocation
95	/////////////////////////////////////////////////////////////////////////////
96
97	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cmd_in", 4);
98	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cmd_out", 4);
99
100	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_rsp_in", 4);
101	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_rsp_out", 4);
102
103	p_m2p_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_m2p_in", 4);
104	p_m2p_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_m2p_out", 4);
105
106	p_p2m_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_p2m_in", 4);
107	p_p2m_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_p2m_out", 4);
108
109	p_cla_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cla_in", 4);
110	p_cla_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cla_out", 4);
111
112	/////////////////////////////////////////////////////////////////////////////
113	// Components definition
114	/////////////////////////////////////////////////////////////////////////////
115
116	for (size_t p = 0; p < nb_procs; p++)
117	{
118	std::ostringstream sproc;
119	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
120	proc[p] = new VciCcVCacheWrapper<vci_param_int,
121	dspin_cmd_width,
122	dspin_rsp_width,
123	GdbServer<Mips32ElIss> >(
124	sproc.str().c_str(),
125	cluster_id * nb_procs + p, // GLOBAL PROC_ID
126	mtd, // Mapping Table
127	IntTab(cluster_id,p), // SRCID
128	(cluster_id << l_width) + p, // CC_GLOBAL_ID
129	8, // ITLB ways
130	8, // ITLB sets
131	8, // DTLB ways
132	8, // DTLB sets
133	l1_i_ways,l1_i_sets, 16, // ICACHE size
134	l1_d_ways,l1_d_sets, 16, // DCACHE size
135	4, // WBUF nlines
136	4, // WBUF nwords
137	x_width,
138	y_width,
139	frozen_cycles, // max frozen cycles
140	debug_start_cycle,
141	proc_debug_ok);
142
143	}
144
145	/////////////////////////////////////////////////////////////////////////////
146	std::ostringstream smemc;
147	smemc << "memc_" << x_id << "_" << y_id;
148	memc = new VciMemCache<vci_param_int,
149	vci_param_ext,
150	dspin_rsp_width,
151	dspin_cmd_width>(
152	smemc.str().c_str(),
153	mtd, // Mapping Table direct space
154	mtx, // Mapping Table external space
155	IntTab(cluster_id), // SRCID external space
156	IntTab(cluster_id, tgtid_memc), // TGTID direct space
157	x_width, // Number of x bits in platform
158	y_width, // Number of y bits in platform
159	memc_ways, memc_sets, 16, // CACHE SIZE
160	3, // MAX NUMBER OF COPIES
161	4096, // HEAP SIZE
162	8, // TRANSACTION TABLE DEPTH
163	8, // UPDATE TABLE DEPTH
164	8, // INVALIDATE TABLE DEPTH
165	debug_start_cycle,
166	memc_debug_ok);
167
168
169	/////////////////////////////////////////////////////////////////////////////
170	std::ostringstream sxram;
171	sxram << "xram_" << x_id << "_" << y_id;
172	xram = new VciSimpleRam<vci_param_ext>(
173	sxram.str().c_str(),
174	IntTab(cluster_id),
175	mtx,
176	loader,
177	xram_latency);
178
179	/////////////////////////////////////////////////////////////////////////////
180	std::ostringstream sxicu;
181	sxicu << "xicu_" << x_id << "_" << y_id;
182	xicu = new VciXicu<vci_param_int>(
183	sxicu.str().c_str(),
184	mtd, // mapping table
185	IntTab(cluster_id, tgtid_xicu), // TGTID_D
186	nb_procs, // number of timer IRQs
187	32, // number of hard IRQs
188	32, // number of soft IRQs
189	nb_procs * irq_per_processor); // number of output IRQs
190
191
192	/////////////////////////////////////////////////////////////////////////////
193	std::ostringstream smdma;
194	smdma << "mdma_" << x_id << "_" << y_id;
195	mdma = new VciMultiDma<vci_param_int>(
196	smdma.str().c_str(),
197	mtd,
198	IntTab(cluster_id, nb_procs), // SRCID
199	IntTab(cluster_id, tgtid_mdma), // TGTID
200	64, // burst size
201	nb_dmas); // number of IRQs
202
203
204	/////////////////////////////////////////////////////////////////////////////
205	size_t nb_direct_initiators = nb_procs + 1;
206	size_t nb_direct_targets = 3;
207	if (io)
208	{
209	nb_direct_initiators = nb_procs + 3;
210	nb_direct_targets = 10;
211	}
212
213	std::ostringstream sxbar;
214	sxbar << "xbar_" << x_id << "_" << y_id;
215	xbar_d = new VciLocalCrossbar<vci_param_int>(
216	sxbar.str().c_str(),
217	mtd, // mapping table
218	//x_id, y_id, // cluster coordinates
219	cluster_id,
220	nb_direct_initiators, // number of local of sources
221	nb_direct_targets, // number of local dests
222	tgtid_memc); // Default target
223
224	////////////// vci_dspin wrappers
225	std::ostringstream swtxbar;
226	swtxbar << "wt_xbar_" << x_id << "_" << y_id;
227	wt_xbar_d = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
228	swtxbar.str().c_str(),
229	x_width + y_width + l_width);
230
231	std::ostringstream swixbar;
232	swixbar << "wi_xbar_" << x_id << "_" << y_id;
233	wi_xbar_d = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
234	swixbar.str().c_str(),
235	x_width + y_width + l_width );
236
237	/////////////////////////////////////////////////////////////////////////////
238	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
239	"xbar_m2p_c",
240	mtd, // mapping table
241	x_id, y_id, // cluster coordinates
242	x_width, y_width, l_width,
243	1, // number of local sources
244	nb_procs, // number of local targets
245	2, 2, // fifo depths
246	true, // CMD
247	false, // don't use local routing table
248	true ); // broadcast
249
250	/////////////////////////////////////////////////////////////////////////////
251	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
252	"xbar_p2m_c",
253	mtd, // mapping table
254	x_id, y_id, // cluster coordinates
255	x_width, y_width, 0, // l_width unused on p2m network
256	nb_procs, // number of local sources
257	1, // number of local dests
258	2, 2, // fifo depths
259	false, // RSP
260	false, // don't use local routing table
261	false ); // no broadcast
262
263	/////////////////////////////////////////////////////////////////////////////
264	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
265	"xbar_clack_c",
266	mtd, // mapping table
267	x_id, y_id, // cluster coordinates
268	x_width, y_width, l_width,
269	1, // number of local sources
270	nb_procs, // number of local targets
271	1, 1, // fifo depths
272	true, // CMD
273	false, // don't use local routing table
274	false); // broadcast
275
276	/////////////////////////////////////////////////////////////////////////////
277	std::ostringstream s_router_cmd;
278	s_router_cmd << "router_cmd_" << x_id << "_" << y_id;
279	router_cmd = new DspinRouter<dspin_cmd_width>(
280	s_router_cmd.str().c_str(),
281	x_id,y_id, // coordinate in the mesh
282	x_width, y_width, // x & y fields width
283	4,4); // input & output fifo depths
284
285	/////////////////////////////////////////////////////////////////////////////
286	std::ostringstream s_router_rsp;
287	s_router_rsp << "router_rsp_" << x_id << "_" << y_id;
288	router_rsp = new DspinRouter<dspin_rsp_width>(
289	s_router_rsp.str().c_str(),
290	x_id,y_id, // coordinates in mesh
291	x_width, y_width, // x & y fields width
292	4,4); // input & output fifo depths
293
294	/////////////////////////////////////////////////////////////////////////////
295	std::ostringstream s_router_m2p;
296	s_router_m2p << "router_m2p_" << x_id << "_" << y_id;
297	router_m2p = new DspinRouter<dspin_cmd_width>(
298	s_router_m2p.str().c_str(),
299	x_id,y_id, // coordinate in the mesh
300	x_width, y_width, // x & y fields width
301	4,4, // input & output fifo depths
302	true); // broadcast supported
303
304	/////////////////////////////////////////////////////////////////////////////
305	std::ostringstream s_router_p2m;
306	s_router_p2m << "router_p2m_" << x_id << "_" << y_id;
307	router_p2m = new DspinRouter<dspin_rsp_width>(
308	s_router_p2m.str().c_str(),
309	x_id,y_id, // coordinates in mesh
310	x_width, y_width, // x & y fields width
311	4,4); // input & output fifo depths
312
313	/////////////////////////////////////////////////////////////////////////////
314	std::ostringstream s_router_cla;
315	s_router_cla << "router_cla_" << x_id << "_" << y_id;
316	router_cla = new DspinRouter<dspin_cmd_width>(
317	s_router_cla.str().c_str(),
318	x_id,y_id, // coordinate in the mesh
319	x_width, y_width, // x & y fields width
320	4,4); // input & output fifo depths
321
322	// IO cluster components
323	if (io)
324	{
325	/////////////////////////////////////////////
326	brom = new VciSimpleRom<vci_param_int>(
327	"brom",
328	IntTab(cluster_id, tgtid_brom),
329	mtd,
330	loader);
331
332	/////////////////////////////////////////////
333	fbuf = new VciFrameBuffer<vci_param_int>(
334	"fbuf",
335	IntTab(cluster_id, tgtid_fbuf),
336	mtd,
337	xfb, yfb);
338
339	/////////////////////////////////////////////
340	bdev = new VciBlockDeviceTsar<vci_param_int>(
341	"bdev",
342	mtd,
343	IntTab(cluster_id, nb_procs + 1),
344	IntTab(cluster_id, tgtid_bdev),
345	disk_name,
346	block_size,
347	64); // burst size
348
349	int mac = 0xBEEF0000;
350	mnic = new VciMultiNic<vci_param_int>(
351	"mnic",
352	IntTab(cluster_id, tgtid_mnic),
353	mtd,
354	nic_channels,
355	mac, // mac_4 address
356	0xBABE, // mac_2 address
357	nic_rx_name,
358	nic_tx_name);
359
360
361
362	/////////////////////////////////////////////
363	chbuf = new VciChbufDma<vci_param_int>(
364	"chbuf_dma",
365	mtd,
366	IntTab(cluster_id, nb_procs + 2),
367	IntTab(cluster_id, tgtid_chbuf),
368	64,
369	chbufdma_channels);
370
371	/////////////////////////////////////////////
372	std::vector<std::string> vect_names;
373	for (size_t tid = 0; tid < nb_ttys; tid++)
374	{
375	std::ostringstream term_name;
376	term_name << "term" << tid;
377	vect_names.push_back(term_name.str().c_str());
378	}
379	mtty = new VciMultiTty<vci_param_int>(
380	"mtty",
381	IntTab(cluster_id, tgtid_mtty),
382	mtd,
383	vect_names);
384
385	simhelper = new VciSimhelper<vci_param_int>(
386	"sim_helper",
387	IntTab(cluster_id, tgtid_simh),
388	mtd);
389	}
390
391	////////////////////////////////////
392	// Connections are defined here
393	////////////////////////////////////
394
395	//////////////////////// ROUTERS
396	router_cmd->p_clk (this->p_clk);
397	router_cmd->p_resetn (this->p_resetn);
398	router_rsp->p_clk (this->p_clk);
399	router_rsp->p_resetn (this->p_resetn);
400	router_m2p->p_clk (this->p_clk);
401	router_m2p->p_resetn (this->p_resetn);
402	router_p2m->p_clk (this->p_clk);
403	router_p2m->p_resetn (this->p_resetn);
404	router_cla->p_clk (this->p_clk);
405	router_cla->p_resetn (this->p_resetn);
406
407	// loop on N/S/E/W ports
408	for (size_t i = 0; i < 4; i++)
409	{
410	router_cmd->p_out[i] (this->p_cmd_out[i]);
411	router_cmd->p_in[i] (this->p_cmd_in[i]);
412
413	router_rsp->p_out[i] (this->p_rsp_out[i]);
414	router_rsp->p_in[i] (this->p_rsp_in[i]);
415
416	router_m2p->p_out[i] (this->p_m2p_out[i]);
417	router_m2p->p_in[i] (this->p_m2p_in[i]);
418
419	router_p2m->p_out[i] (this->p_p2m_out[i]);
420	router_p2m->p_in[i] (this->p_p2m_in[i]);
421
422	router_cla->p_out[i] (this->p_cla_out[i]);
423	router_cla->p_in[i] (this->p_cla_in[i]);
424	}
425
426	router_cmd->p_out[4] (signal_dspin_cmd_g2l_d);
427	router_cmd->p_in[4] (signal_dspin_cmd_l2g_d);
428
429	router_rsp->p_out[4] (signal_dspin_rsp_g2l_d);
430	router_rsp->p_in[4] (signal_dspin_rsp_l2g_d);
431
432	router_m2p->p_out[4] (signal_dspin_m2p_g2l_c);
433	router_m2p->p_in[4] (signal_dspin_m2p_l2g_c);
434
435	router_p2m->p_out[4] (signal_dspin_p2m_g2l_c);
436	router_p2m->p_in[4] (signal_dspin_p2m_l2g_c);
437
438	router_cla->p_out[4] (signal_dspin_clack_g2l_c);
439	router_cla->p_in[4] (signal_dspin_clack_l2g_c);
440
441	std::cout << " - routers connected" << std::endl;
442
443	wi_xbar_d->p_clk (this->p_clk);
444	wi_xbar_d->p_resetn (this->p_resetn);
445	wi_xbar_d->p_vci (signal_vci_l2g_d);
446	wi_xbar_d->p_dspin_cmd (signal_dspin_cmd_l2g_d);
447	wi_xbar_d->p_dspin_rsp (signal_dspin_rsp_g2l_d);
448
449	std::cout << " - Wrapper Ini VCI2DSPIN Direct connected" << std::endl;
450
451	wt_xbar_d->p_clk (this->p_clk);
452	wt_xbar_d->p_resetn (this->p_resetn);
453	wt_xbar_d->p_vci (signal_vci_g2l_d);
454	wt_xbar_d->p_dspin_cmd (signal_dspin_cmd_g2l_d);
455	wt_xbar_d->p_dspin_rsp (signal_dspin_rsp_l2g_d);
456
457	std::cout << " - Wrapper Tgt VCI2DSPIN Direct connected" << std::endl;
458
459	///////////////////// CMD VCI local crossbar direct
460	xbar_d->p_clk (this->p_clk);
461	xbar_d->p_resetn (this->p_resetn);
462	xbar_d->p_target_to_up (signal_vci_g2l_d);
463	xbar_d->p_initiator_to_up (signal_vci_l2g_d);
464
465	xbar_d->p_to_target[tgtid_memc] (signal_vci_tgt_memc);
466	xbar_d->p_to_target[tgtid_xicu] (signal_vci_tgt_xicu);
467	xbar_d->p_to_target[tgtid_mdma] (signal_vci_tgt_mdma);
468
469	xbar_d->p_to_initiator[nb_procs] (signal_vci_ini_mdma);
470
471	for (size_t p = 0; p < nb_procs; p++)
472	xbar_d->p_to_initiator[p] (signal_vci_ini_proc[p]);
473
474	if (io)
475	{
476	xbar_d->p_to_target[tgtid_mtty] (signal_vci_tgt_mtty);
477	xbar_d->p_to_target[tgtid_brom] (signal_vci_tgt_brom);
478	xbar_d->p_to_target[tgtid_bdev] (signal_vci_tgt_bdev);
479	xbar_d->p_to_target[tgtid_fbuf] (signal_vci_tgt_fbuf);
480	xbar_d->p_to_target[tgtid_mnic] (signal_vci_tgt_mnic);
481	xbar_d->p_to_target[tgtid_chbuf] (signal_vci_tgt_chbuf);
482	xbar_d->p_to_target[tgtid_simh] (signal_vci_tgt_simh);
483
484	xbar_d->p_to_initiator[nb_procs + 1] (signal_vci_ini_bdev);
485	xbar_d->p_to_initiator[nb_procs + 2] (signal_vci_ini_chbuf);
486	}
487
488	std::cout << " - Direct crossbar connected" << std::endl;
489
490	////////////////////// M2P DSPIN local crossbar coherence
491	xbar_m2p_c->p_clk (this->p_clk);
492	xbar_m2p_c->p_resetn (this->p_resetn);
493	xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c);
494	xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c);
495	xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc);
496	for (size_t p = 0; p < nb_procs; p++)
497	xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]);
498
499	std::cout << " - M2P Coherence crossbar connected" << std::endl;
500
501	////////////////////// CLACK DSPIN local crossbar coherence
502	xbar_clack_c->p_clk (this->p_clk);
503	xbar_clack_c->p_resetn (this->p_resetn);
504	xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c);
505	xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c);
506	xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc);
507	for (size_t p = 0; p < nb_procs; p++)
508	xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]);
509
510	std::cout << " - Clack Coherence crossbar connected" << std::endl;
511
512	////////////////////////// P2M DSPIN local crossbar coherence
513	xbar_p2m_c->p_clk (this->p_clk);
514	xbar_p2m_c->p_resetn (this->p_resetn);
515	xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c);
516	xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c);
517	xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc);
518	for (size_t p = 0; p < nb_procs; p++)
519	xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]);
520
521	std::cout << " - P2M Coherence crossbar connected" << std::endl;
522
523
524	//////////////////////////////////// Processors
525	for (size_t p = 0; p < nb_procs; p++)
526	{
527	proc[p]->p_clk (this->p_clk);
528	proc[p]->p_resetn (this->p_resetn);
529	proc[p]->p_vci (signal_vci_ini_proc[p]);
530	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
531	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
532	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
533
534	for ( size_t i = 0; i < irq_per_processor; i++)
535	{
536	proc[p]->p_irq[i] (signal_proc_it[p*irq_per_processor + i]);
537	}
538	for ( size_t j = irq_per_processor; j < 6; j++) // 6 = number of irqs in the MIPS
539	{
540	proc[p]->p_irq[j] (signal_false);
541	}
542
543	}
544
545	std::cout << " - Processors connected" << std::endl;
546
547	///////////////////////////////////// XICU
548	xicu->p_clk (this->p_clk);
549	xicu->p_resetn (this->p_resetn);
550	xicu->p_vci (signal_vci_tgt_xicu);
551	for (size_t p = 0; p < nb_procs * irq_per_processor; p++)
552	{
553	xicu->p_irq[p] (signal_proc_it[p]);
554	}
555	for (size_t i = 0; i < 32; i++)
556	{
557	if (io) // I/O cluster
558	{
559	if (i < 8) xicu->p_hwi[i] (signal_false);
560	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
561	else if (i < 16) xicu->p_hwi[i] (signal_false);
562	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i - 16]);
563	else if (i < 30) xicu->p_hwi[i] (signal_false);
564	else if (i < 31) xicu->p_hwi[i] (signal_irq_memc);
565	else xicu->p_hwi[i] (signal_irq_bdev);
566	}
567	else // other clusters
568	{
569	if (i < 8) xicu->p_hwi[i] (signal_false);
570	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
571	else if (i < 30) xicu->p_hwi[i] (signal_false);
572	else if (i < 31) xicu->p_hwi[i] (signal_irq_memc);
573	else xicu->p_hwi[i] (signal_false);
574	}
575	}
576
577	std::cout << " - XICU connected" << std::endl;
578
579	//////////////////////////////////////////////// MEMC
580	memc->p_clk (this->p_clk);
581	memc->p_resetn (this->p_resetn);
582	memc->p_irq (signal_irq_memc);
583	memc->p_vci_ixr (signal_vci_xram);
584	memc->p_vci_tgt (signal_vci_tgt_memc);
585	memc->p_dspin_p2m (signal_dspin_p2m_memc);
586	memc->p_dspin_m2p (signal_dspin_m2p_memc);
587	memc->p_dspin_clack (signal_dspin_clack_memc);
588
589	std::cout << " - MEMC connected" << std::endl;
590
591	/////////////////////////////////////////////// XRAM
592	xram->p_clk (this->p_clk);
593	xram->p_resetn (this->p_resetn);
594	xram->p_vci (signal_vci_xram);
595
596	std::cout << " - XRAM connected" << std::endl;
597
598	////////////////////////////////////////////// MDMA
599	mdma->p_clk (this->p_clk);
600	mdma->p_resetn (this->p_resetn);
601	mdma->p_vci_target (signal_vci_tgt_mdma);
602	mdma->p_vci_initiator (signal_vci_ini_mdma);
603	for (size_t i = 0; i < nb_dmas; i++)
604	mdma->p_irq[i] (signal_irq_mdma[i]);
605
606	std::cout << " - MDMA connected" << std::endl;
607
608	/////////////////////////////// Components in I/O cluster
609
610	if (io)
611	{
612	// BDEV
613	bdev->p_clk (this->p_clk);
614	bdev->p_resetn (this->p_resetn);
615	bdev->p_irq (signal_irq_bdev);
616	bdev->p_vci_target (signal_vci_tgt_bdev);
617	bdev->p_vci_initiator (signal_vci_ini_bdev);
618
619	std::cout << " - BDEV connected" << std::endl;
620
621	// FBUF
622	fbuf->p_clk (this->p_clk);
623	fbuf->p_resetn (this->p_resetn);
624	fbuf->p_vci (signal_vci_tgt_fbuf);
625
626	std::cout << " - FBUF connected" << std::endl;
627
628	// MNIC
629	mnic->p_clk (this->p_clk);
630	mnic->p_resetn (this->p_resetn);
631	mnic->p_vci (signal_vci_tgt_mnic);
632	for (size_t i = 0; i < nic_channels; i++)
633	{
634	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
635	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
636	}
637
638	std::cout << " - MNIC connected" << std::endl;
639
640	// CHBUF
641	chbuf->p_clk (this->p_clk);
642	chbuf->p_resetn (this->p_resetn);
643	chbuf->p_vci_target (signal_vci_tgt_chbuf);
644	chbuf->p_vci_initiator (signal_vci_ini_chbuf);
645	for (size_t i = 0; i < chbufdma_channels; i++)
646	{
647	chbuf->p_irq[i] (signal_irq_chbuf[i]);
648	}
649
650	std::cout << " - CHBUF connected" << std::endl;
651
652	// BROM
653	brom->p_clk (this->p_clk);
654	brom->p_resetn (this->p_resetn);
655	brom->p_vci (signal_vci_tgt_brom);
656
657	std::cout << " - BROM connected" << std::endl;
658
659	// MTTY
660	mtty->p_clk (this->p_clk);
661	mtty->p_resetn (this->p_resetn);
662	mtty->p_vci (signal_vci_tgt_mtty);
663	for (size_t i = 0; i < nb_ttys; i++)
664	{
665	mtty->p_irq[i] (signal_irq_mtty[i]);
666	}
667
668	std::cout << " - MTTY connected" << std::endl;
669
670
671	// Sim Helper
672	simhelper->p_clk (this->p_clk);
673	simhelper->p_resetn (this->p_resetn);
674	simhelper->p_vci (signal_vci_tgt_simh);
675
676	std::cout << " - SIMH connected" << std::endl;
677	}
678	} // end constructor
679
680
681
682	template<size_t dspin_cmd_width,
683	size_t dspin_rsp_width,
684	typename vci_param_int,
685	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
686	dspin_rsp_width,
687	vci_param_int,
688	vci_param_ext>::~TsarXbarCluster() {
689
690	dealloc_elems<DspinInput<dspin_cmd_width> > (p_cmd_in, 4);
691	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cmd_out, 4);
692
693	dealloc_elems<DspinInput<dspin_rsp_width> > (p_rsp_in, 4);
694	dealloc_elems<DspinOutput<dspin_rsp_width> >(p_rsp_out, 4);
695
696	dealloc_elems<DspinInput<dspin_cmd_width> > (p_m2p_in, 4);
697	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_m2p_out, 4);
698
699	dealloc_elems<DspinInput<dspin_rsp_width> > (p_p2m_in, 4);
700	dealloc_elems<DspinOutput<dspin_rsp_width> >(p_p2m_out, 4);
701
702	dealloc_elems<DspinInput<dspin_cmd_width> > (p_cla_in, 4);
703	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cla_out, 4);
704
705	for (size_t p = 0; p < n_procs; p++)
706	{
707	delete proc[p];
708	}
709
710	delete memc;
711	delete xram;
712	delete xicu;
713	delete mdma;
714	delete xbar_d;
715	delete wt_xbar_d;
716	delete wi_xbar_d;
717	delete xbar_m2p_c;
718	delete xbar_p2m_c;
719	delete xbar_clack_c;
720	delete router_cmd;
721	delete router_rsp;
722	if (brom != NULL)
723	{
724	delete brom;
725	delete fbuf;
726	delete bdev;
727	delete mnic;
728	delete chbuf;
729	delete mtty;
730	delete simhelper;
731	}
732	}
733
734
735	template<size_t dspin_cmd_width,
736	size_t dspin_rsp_width,
737	typename vci_param_int,
738	typename vci_param_ext>
739	void TsarXbarCluster<dspin_cmd_width,
740	dspin_rsp_width,
741	vci_param_int,
742	vci_param_ext>::trace(sc_core::sc_trace_file * tf, const std::string & name) {
743
744	#define __trace(x) sc_core::sc_trace(tf, x, name + "_" + #x)
745	__trace(signal_vci_l2g_d);
746	__trace(signal_vci_g2l_d);
747	__trace(signal_vci_tgt_memc);
748	__trace(signal_vci_tgt_xicu);
749	__trace(signal_vci_tgt_mdma);
750	__trace(signal_vci_ini_mdma);
751
752	for (size_t p = 0; p < n_procs; p++) {
753	std::ostringstream signame;
754	signame << "vci_ini_proc_" << p;
755	sc_core::sc_trace(tf, signal_vci_ini_proc[p], signame.str());
756	}
757	__trace(signal_vci_tgt_mtty);
758	__trace(signal_vci_tgt_brom);
759	__trace(signal_vci_tgt_bdev);
760	__trace(signal_vci_tgt_fbuf);
761	__trace(signal_vci_tgt_simh);
762	__trace(signal_vci_ini_bdev);
763	__trace(signal_vci_tgt_memc);
764	__trace(signal_vci_xram);
765	#undef trace
766
767	}
768
769	}}
770
771	// Local Variables:
772	// tab-width: 4
773	// c-basic-offset: 4
774	// c-file-offsets:((innamespace . 0)(inline-open . 0))
775	// indent-tabs-mode: nil
776	// End:
777
778	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
779

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