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source: trunk/platforms/tsarv4_vgmn_generic_32/tsarv4_vgmn_generic_32_top.cpp @ 117

Last change on this file since 117 was 117, checked in by alain, 13 years ago

Introducing two generic hardware platforms:

tsarv4_vgmn_generic_32
tsarv4_dspin_generic_32

File size: 29.5 KB

Line
1	/////////////////////////////////////////////////////////////////////////
2	// File: tsarv4_vgmn_generic_32_top.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : november 5 2010
6	// This program is released under the GNU public license
7	/////////////////////////////////////////////////////////////////////////
8	// This file define a generic TSAR architecture without virtual memory.
9	// - It uses the vci_vgmn as global interconnect
10	// - It uses the vci_local_crossbar as local interconnect
11	// - It uses the vci_cc_xcache (No MMU)
12	// The physical address space is 32 bits.
13	// The number of clusters cannot be larger than 256.
14	// The three parameters are
15	// - xmax : number of clusters in a row
16	// - ymax : number of clusters in a column
17	// - nprocs : number of processor per cluster
18	//
19	// Each cluster contains nprocs processors, one Memory Cache,
20	// and one XICU component.
21	// The peripherals BDEV, CDMA, FBUF, MTTY and the boot BROM
22	// are in the cluster containing address 0xBFC00000.
23	// - The bdev_irq is connected to IRQ_IN[0]
24	// - The cdma_irq is connected to IRQ_IN[1]
25	// - The tty_irq[i] is connected to IRQ_IN[i+2]
26	// For all clusters, the XICU component contains nprocs timers.
27	//
28	// As we target up to 256 clusters, each cluster can contain
29	// at most 16 Mbytes (in a 4Gbytes address space).
30	// - Each memory cache contains 9 Mbytes.
31	// - The Frame buffer contains 2 Mbytes.
32	// - The Boot ROM contains 1 Mbytes.
33	//
34	// General policy for 32 bits address decoding:
35	// To simplifly, all segments base addresses are aligned
36	// on 1 Mbyte addresses. Therefore the 12 address MSB bits
37	// define the target in the direct address space.
38	// In these 12 bits, the (x_width + y_width) MSB bits define
39	// the cluster index, and the 4 LSB bits define the local index:
40	//
41	// \| X_ID \| Y_ID \|---\| L_ID \| OFFSET \|
42	// \|x_width\|y_width\|---\| 4 \| 20 \|
43	/////////////////////////////////////////////////////////////////////////
44
45	#include <systemc>
46	#include <sys/time.h>
47	#include <iostream>
48	#include <sstream>
49	#include <cstdlib>
50	#include <cstdarg>
51	#include <stdint.h>
52
53	#include "mapping_table.h"
54	#include "mips32.h"
55	#include "vci_simple_ram.h"
56	#include "vci_multi_tty.h"
57	#include "vci_mem_cache_v4.h"
58	#include "vci_cc_xcache_wrapper_v4.h"
59	#include "vci_xicu.h"
60	#include "vci_vgmn.h"
61	#include "vci_local_crossbar.h"
62	#include "vci_framebuffer.h"
63	#include "vci_dma_tsar_v2.h"
64	#include "vci_block_device_tsar_v2.h"
65	#include "gdbserver.h"
66
67	#define SECTOR_SIZE 2048
68
69	#define FBUF_XSIZE 960
70	#define FBUF_YSIZE 960
71
72	#define N_TTYS 4
73
74	//////////////////////////////////////////////
75	// segments definition in direct space.
76	// There is 16 Mbytes address space per cluster.
77	// The 8 MSB bits define the cluster index (x,y),
78	// even if the number of clusters is less than 256.
79	// Each memory cache contains up to 9 Mbytes.
80	// There is one MEMC segment and one XICU segment per cluster
81	// The peripherals BDEV, FBUF, MTTY, CDMA and the boot BROM
82	// are mapped in cluster containing address 0xBFC00000
83
84	#define MEMC_BASE 0x00000000
85	#define MEMC_SIZE 0x00900000
86
87	#define XICU_BASE 0x00900000
88	#define XICU_SIZE 0x00001000
89
90	#define FBUF_BASE 0xBFA00000
91	#define FBUF_SIZE 0x00200000
92
93	#define BROM_BASE 0xBFC00000
94	#define BROM_SIZE 0x00100000
95
96	#define BDEV_BASE 0xBFD00000
97	#define BDEV_SIZE 0x00000100
98
99	#define MTTY_BASE 0xBFE00000
100	#define MTTY_SIZE 0x00000100
101
102	#define CDMA_BASE 0xBFF00000
103	#define CDMA_SIZE 0x00000100
104
105	/* Pour ALMOS
106
107	#define BOOT_INFO_BLOCK 0xbfc08000
108	#define KERNEL_BIN_IMG 0xbfc10000
109
110	*/
111
112	////////////////////////////////////////////////////////////////////
113	// TGTID & SRCID definition in direct space
114	// For all components: global TGTID = global SRCID = cluster_index
115	// For processors, the local SRCID is between 0 & nprocs-1
116
117	#define MEMC_TGTID 0
118	#define XICU_TGTID 1
119	#define FBUF_TGTID 2
120	#define MTTY_TGTID 3
121	#define BROM_TGTID 4
122	#define BDEV_TGTID 5
123	#define CDMA_TGTID 6
124
125	#define PROC_SRCID 0
126	#define BDEV_SRCID nprocs
127	#define CDMA_SRCID (nprocs+1)
128
129	////////////////////////////////////////////////////////
130	// TGTID & SRCID definition in coherence space
131	// For all components: global TGTID = global SRCID = cluster_index
132	// For MEMC : local SRCID = local TGTID = nprocs
133	// For processors : local SRCID = local TGTID = PROC_ID
134
135	//////////////////////
136	// Router ports index
137
138	#define NORTH 0
139	#define SOUTH 1
140	#define EAST 2
141	#define WEST 3
142	#define LOCAL 4
143
144	///////////////
145	// VCI format
146	#define cell_width 4
147	#define address_width 32
148	#define plen_width 8
149	#define error_width 1
150	#define clen_width 1
151	#define rflag_width 1
152	#define srcid_width 14
153	#define pktid_width 4
154	#define trdid_width 4
155	#define wrplen_width 1
156
157	// cluster index (computed from x,y coordinates)
158	#define cluster(x,y) (y + ymax*x)
159
160	/////////////////////////////////
161	int _main(int argc, char *argv[])
162	{
163	using namespace sc_core;
164	using namespace soclib::caba;
165	using namespace soclib::common;
166
167	char soft_name[128] = "undefined_binary_code"; // pathname to binary code
168	char disk_name[128] = "undefined_disk_image"; // pathname to the disk image
169	size_t ncycles = 1000000000; // simulated cycles
170	size_t xmax = 2; // number of clusters in a row
171	size_t ymax = 2; // number of clusters in a column
172	size_t nprocs = 1; // number of processors per cluster
173	bool debug_ok = false; // debug activated
174	size_t from_cycle = 0; // debug start cycle
175	size_t to_cycle = 1000000000; // debug end cycle
176
177	////////////// command line arguments //////////////////////
178	if (argc > 1)
179	{
180	for( int n=1 ; n<argc ; n=n+2 )
181	{
182	if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
183	{
184	ncycles = atoi(argv[n+1]);
185	}
186	else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
187	{
188	nprocs = atoi(argv[n+1]);
189	assert( (nprocs <= 8) && "The number of processors per cluster cannot be larger than 8");
190	}
191	else if( (strcmp(argv[n],"-XMAX") == 0) && (n+1<argc) )
192	{
193	xmax = atoi(argv[n+1]);
194	assert( ((xmax >= 2) && (xmax <= 16))
195	&& "The XMAX parameter (number of clusters in a row) must be in the range [2,16]" );
196	}
197	else if( (strcmp(argv[n],"-YMAX") == 0) && (n+1<argc) )
198	{
199	ymax = atoi(argv[n+1]);
200	assert( ((ymax >= 2) && (ymax <= 16))
201	&& "The YMAX parameter (number of clusters in a column) must be in the range [2,16]" );
202	}
203	else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
204	{
205	strcpy(soft_name, argv[n+1]);
206	}
207	else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
208	{
209	strcpy(disk_name, argv[n+1]);
210	}
211	else if( (strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
212	{
213	debug_ok = true;
214	from_cycle = atoi(argv[n+1]);
215	}
216	else if( (strcmp(argv[n],"-TOCYCLE") == 0) && (n+1<argc) )
217	{
218	to_cycle = atoi(argv[n+1]);
219	}
220	else
221	{
222	std::cout << " Arguments on the command line are (key,value) couples." << std::endl;
223	std::cout << " The order is not important." << std::endl;
224	std::cout << " Accepted arguments are :" << std::endl << std::endl;
225	std::cout << " -SOFT elf_file_name" << std::endl;
226	std::cout << " -DISK disk_image_file_name" << std::endl;
227	std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
228	std::cout << " -NPROCS number_of_processors_per_cluster" << std::endl;
229	std::cout << " -XMAX number_of_clusters_in_a_row" << std::endl;
230	std::cout << " -YMAX number_of_clusters_in_a_column" << std::endl;
231	std::cout << " -DEBUG debug_start_cycle" << std::endl;
232	std::cout << " -TOCYCLE debug_end_cycle" << std::endl;
233	exit(0);
234	}
235	}
236	}
237
238	std::cout << std::endl << "********* TSAR ARCHITECTURE ************" << std::endl
239	<< " - Interconnect = VGMN & CROSSBAR" << std::endl
240	<< " - Number of clusters = " << xmax << " * " << ymax << std::endl
241	<< " - Number of processors per cluster = " << nprocs << std::endl
242	<< "**********************************************" << std::endl
243	<< std::endl;
244
245
246	// Define VCI parameters
247	typedef soclib::caba::VciParams<cell_width,
248	plen_width,
249	address_width,
250	error_width,
251	clen_width,
252	rflag_width,
253	srcid_width,
254	pktid_width,
255	trdid_width,
256	wrplen_width> vci_param;
257
258	size_t cluster_io_index;
259	size_t x_width;
260	size_t y_width;
261
262	if (xmax == 2) x_width = 1;
263	else if (xmax <= 4) x_width = 2;
264	else if (xmax <= 8) x_width = 3;
265	else x_width = 4;
266
267	if (ymax == 2) y_width = 1;
268	else if (ymax <= 4) y_width = 2;
269	else if (ymax <= 8) y_width = 3;
270	else y_width = 4;
271
272	cluster_io_index = 0xBF >> (8 - x_width - y_width);
273
274	/////////////////////
275	// Mapping Tables
276	/////////////////////
277
278	// direct network
279	MappingTable maptabd(address_width,
280	IntTab(x_width + y_width, 12 - x_width - y_width),
281	IntTab(x_width + y_width, srcid_width - x_width - y_width),
282	0x00F00000);
283	for ( size_t x = 0 ; x < xmax ; x++)
284	{
285	for ( size_t y = 0 ; y < ymax ; y++)
286	{
287	sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);
288	std::ostringstream sm;
289	sm << "d_seg_memc_" << x << "_" << y;
290	maptabd.add(Segment(sm.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
291	std::ostringstream si;
292	si << "d_seg_xicu_" << x << "_" << y;
293	maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
294	if ( cluster(x,y) == cluster_io_index )
295	{
296	maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
297	maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
298	maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
299	maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
300	maptabd.add(Segment("d_seg_cdma", CDMA_BASE, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
301	}
302	}
303	}
304	std::cout << maptabd << std::endl;
305
306	// coherence network
307	MappingTable maptabc(address_width,
308	IntTab(x_width + y_width, 12 - x_width - y_width),
309	IntTab(x_width + y_width, srcid_width - x_width - y_width),
310	0xF0000000);
311
312	for ( size_t x = 0 ; x < xmax ; x++)
313	{
314	for ( size_t y = 0 ; y < ymax ; y++)
315	{
316	sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);
317
318	std::ostringstream sm;
319	sm << "c_seg_memc_" << x << "_" << y;
320	maptabc.add(Segment(sm.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y), nprocs), false));
321	// the segment base and size will be modified
322	// when the segmentation of the coherence space will be simplified
323
324	if ( cluster(x,y) == cluster_io_index )
325	{
326	std::ostringstream sr;
327	sr << "c_seg_brom_" << x << "_" << y;
328	maptabc.add(Segment(sr.str(), BROM_BASE, BROM_SIZE, IntTab(cluster(x,y), nprocs), false));
329	}
330
331	sc_uint<address_width> avoid_collision = 0;
332	for ( size_t p = 0 ; p < nprocs ; p++)
333	{
334	sc_uint<address_width> base = MEMC_SIZE + (p*0x100000) + offset;
335	// the following test is to avoid a collision between the c_seg_brom segment
336	// and a c_seg_proc segment (all segments base addresses being multiple of 1Mbytes)
337	if ( base == BROM_BASE ) avoid_collision = 0x100000;
338	std::ostringstream sp;
339	sp << "c_seg_proc_" << x << "_" << y << "_" << p;
340	maptabc.add(Segment(sp.str(), base + avoid_collision, 0x20, IntTab(cluster(x,y), p), false,
341	true, IntTab(cluster(x,y), p)));
342	// the two last arguments will be removed
343	// when the segmentation of the coherence space will be simplified
344	}
345	}
346	}
347	std::cout << maptabc << std::endl;
348
349	// external network
350	MappingTable maptabx(address_width, IntTab(1), IntTab(10), 0xF0000000);
351
352	for ( size_t x = 0 ; x < xmax ; x++)
353	{
354	for ( size_t y = 0 ; y < ymax ; y++)
355	{
356	sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);
357	std::ostringstream sx;
358
359	sx << "seg_xram_" << x << "_" << y;
360	maptabx.add(Segment(sx.str(), MEMC_BASE + offset, MEMC_SIZE, IntTab(0), false));
361	}
362	}
363	std::cout << maptabx << std::endl;
364
365	////////////////////
366	// Signals
367	///////////////////
368
369	sc_clock signal_clk("clk");
370	sc_signal<bool> signal_resetn("resetn");
371	sc_signal<bool> signal_false;
372
373	// IRQ signals (one signal per proc)
374	sc_signal<bool>*** signal_proc_it =
375	alloc_elems<sc_signal<bool> >("signal_proc_it", xmax, ymax, nprocs);
376
377	sc_signal<bool>* signal_irq_mtty =
378	alloc_elems<sc_signal<bool> >("signal_irq_mtty", N_TTYS);
379
380	sc_signal<bool> signal_irq_bdev;
381	sc_signal<bool> signal_irq_cdma;
382
383	// Direct VCI signals
384
385	VciSignals<vci_param>*** signal_vci_ini_d_proc =
386	alloc_elems<VciSignals<vci_param> >("signal_vci_ini_d_proc", xmax, ymax, nprocs);
387
388	VciSignals<vci_param>** signal_vci_tgt_d_memc =
389	alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_d_memc", xmax, ymax);
390
391	VciSignals<vci_param>** signal_vci_tgt_d_xicu =
392	alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_d_xicu", xmax, ymax);
393
394	VciSignals<vci_param>** signal_vci_l2g_d =
395	alloc_elems<VciSignals<vci_param> >("signal_vci_l2g_d", xmax, ymax);
396
397	VciSignals<vci_param>** signal_vci_g2l_d =
398	alloc_elems<VciSignals<vci_param> >("signal_vci_g2l_d", xmax, ymax);
399
400	VciSignals<vci_param> signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty");
401	VciSignals<vci_param> signal_vci_tgt_d_brom("signal_vci_tgt_d_brom");
402	VciSignals<vci_param> signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev");
403	VciSignals<vci_param> signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf");
404	VciSignals<vci_param> signal_vci_tgt_d_cdma("signal_vci_tgt_d_cdma");
405
406	VciSignals<vci_param> signal_vci_ini_d_bdev("signal_vci_ini_d_bdev");
407	VciSignals<vci_param> signal_vci_ini_d_cdma("signal_vci_ini_d_cdma");
408
409	// Coherence VCI signals
410
411	VciSignals<vci_param>*** signal_vci_ini_c_proc =
412	alloc_elems<VciSignals<vci_param> >("signal_vci_ini_c_proc", xmax, ymax, nprocs);
413
414	VciSignals<vci_param>*** signal_vci_tgt_c_proc =
415	alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_c_proc", xmax, ymax, nprocs);
416
417	VciSignals<vci_param>** signal_vci_ini_c_memc =
418	alloc_elems<VciSignals<vci_param> >("signal_vci_ini_c_memc", xmax, ymax);
419
420	VciSignals<vci_param>** signal_vci_tgt_c_memc =
421	alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_c_memc", xmax, ymax);
422
423	VciSignals<vci_param>** signal_vci_l2g_c =
424	alloc_elems<VciSignals<vci_param> >("signal_vci_l2g_c", xmax, ymax);
425
426	VciSignals<vci_param>** signal_vci_g2l_c =
427	alloc_elems<VciSignals<vci_param> >("signal_vci_g2l_c", xmax, ymax);
428
429	// Xternal network VCI signals
430
431	VciSignals<vci_param> signal_vci_tgt_x_xram("signal_vci_tgt_x_xram");
432	VciSignals<vci_param>** signal_vci_ini_x_memc =
433	alloc_elems<VciSignals<vci_param> >("signal_vci_ini_x_memc", xmax, ymax);
434
435	////////////////////////////
436	// Components
437	////////////////////////////
438
439	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
440
441	soclib::common::Loader loader(soft_name);
442	proc_iss::set_loader(loader);
443
444	/* code specifique ALMOS pour chargement du binaire
445
446	#define _TO_STR(_str) #_str
447	#define TO_STR(_str) _TO_STR(_str)
448
449	soclib::common::Loader loader("bootloader.bin",
450	"arch-info.bin@"TO_STR(BOOT_INFO_BLOCK)":D",
451	"kernel-soclib.bin@"TO_STR(KERNEL_BIN_IMG)":D");
452	*/
453
454	// External RAM
455	VciSimpleRam<vci_param> xram(
456	"xram",
457	IntTab(0),
458	maptabx,
459	loader);
460
461	// Direct network
462	VciVgmn<vci_param> dnoc(
463	"dnoc",
464	maptabd,
465	xmax*ymax,
466	xmax*ymax,
467	2, 2);
468
469	// Coherence network
470	VciVgmn<vci_param> cnoc(
471	"cnoc",
472	maptabc,
473	xmax*ymax,
474	xmax*ymax,
475	2, 2);
476
477	// External network
478	VciVgmn<vci_param> xnoc(
479	"xnoc",
480	maptabx,
481	xmax*ymax,
482	1,
483	2, 2);
484
485	// Peripherals : TTY, Frame Buffer, Block Device, Boot ROM, & DMA
486	VciSimpleRam<vci_param> brom(
487	"brom",
488	IntTab(cluster_io_index, BROM_TGTID),
489	maptabd,
490	loader);
491
492	VciMultiTty<vci_param> mtty(
493	"mtty",
494	IntTab(cluster_io_index, MTTY_TGTID),
495	maptabd,
496	"tty0","tty1","tty2","tty3",NULL);
497
498	VciFrameBuffer<vci_param> fbuf(
499	"fbuf",
500	IntTab(cluster_io_index, FBUF_TGTID),
501	maptabd,
502	FBUF_XSIZE,
503	FBUF_YSIZE);
504
505	VciBlockDeviceTsarV2<vci_param> bdev(
506	"bdev",
507	maptabd,
508	IntTab(cluster_io_index, BDEV_SRCID), // SRCID_D
509	IntTab(cluster_io_index, BDEV_TGTID), // TGTID_D
510	disk_name,
511	SECTOR_SIZE);
512
513	VciDmaTsarV2<vci_param> cdma(
514	"cdma",
515	maptabd,
516	IntTab(cluster_io_index,CDMA_SRCID), // SRCID_D
517	IntTab(cluster_io_index,CDMA_TGTID), // TGTID_D
518	64);
519
520	// processors (nprocs per cluster)
521
522	VciCcXCacheWrapperV4<vci_param, proc_iss> *proc[xmax][ymax][nprocs];
523
524	for( size_t x = 0 ; x < xmax ; x++ )
525	{
526	for( size_t y = 0 ; y < ymax ; y++ )
527	{
528	for ( size_t p = 0 ; p < nprocs ; p++ )
529	{
530
531	std::ostringstream sp;
532	sp << "proc_" << x << "_" << y << "_" << p;
533
534	proc[x][y][p] = new VciCcXCacheWrapperV4<vci_param, proc_iss>(
535	sp.str().c_str(),
536	p+nprocs*cluster(x,y),
537	maptabd, maptabc,
538	IntTab(cluster(x,y), PROC_SRCID+p), // SRCID_D
539	IntTab(cluster(x,y), PROC_SRCID+p), // SRCID_C
540	IntTab(cluster(x,y), PROC_SRCID+p), // TGTID_C
541	4,64,16,4,64,16); // Icache and Dcache sizes
542	}
543	}
544	}
545
546	// memory caches (one per cluster)
547	VciMemCacheV4<vci_param>* memc[xmax][ymax];
548
549	for( size_t x = 0 ; x < xmax ; x++ )
550	{
551	for( size_t y = 0 ; y < ymax ; y++ )
552	{
553	std::ostringstream sm;
554	sm << "memc_" << x << "_" << y;
555
556	memc[x][y] = new VciMemCacheV4<vci_param>(
557	sm.str().c_str(),
558	maptabd, maptabc, maptabx,
559	IntTab(cluster(x,y)), // SRCID_X
560	IntTab(cluster(x,y), nprocs), // SRCID_C
561	IntTab(cluster(x,y), MEMC_TGTID), // TGTID_D
562	IntTab(cluster(x,y), nprocs), // TGTID_C
563	4,16,16, // CACHE SIZE
564	4096); // HEAP SIZE
565	}
566	}
567
568	// XICU (one per cluster)
569	VciXicu<vci_param> *xicu[xmax][ymax];
570
571	for( size_t x = 0 ; x < xmax ; x++ )
572	{
573	for( size_t y = 0 ; y < ymax ; y++ )
574	{
575	std::ostringstream si;
576	si << "xicu_" << x << "_" << y;
577	size_t nhwi;
578	if ( cluster(x,y) == cluster_io_index ) nhwi = N_TTYS + 2;
579	else nhwi = 0;
580	xicu[x][y] = new VciXicu<vci_param>(
581	si.str().c_str(),
582	maptabd,
583	IntTab(cluster(x,y), XICU_TGTID), // TGTID_D
584	nprocs, // number of TIMERS
585	nhwi, // number of hard IRQs
586	nprocs, // number of soft IRQs
587	nprocs); // number of output IRQ lines
588	}
589	}
590
591	// Local interconnects : one direct crossbar & one coherence crossbar per cluster
592	VciLocalCrossbar<vci_param>* dxbar[xmax][ymax];
593
594	VciLocalCrossbar<vci_param>* cxbar[xmax][ymax];
595
596	for( size_t x = 0 ; x < xmax ; x++ )
597	{
598	for( size_t y = 0 ; y < ymax ; y++ )
599	{
600	std::ostringstream sd;
601	sd << "dxbar_" << x << "_" << y;
602	size_t nb_direct_initiators = nprocs;
603	size_t nb_direct_targets = 2;
604	if ( cluster(x,y) == cluster_io_index )
605	{
606	nb_direct_initiators = nprocs + 2;
607	nb_direct_targets = 7;
608	}
609	dxbar[x][y] = new VciLocalCrossbar<vci_param>(
610	sd.str().c_str(),
611	maptabd,
612	IntTab(cluster(x,y)), // global initiator index
613	IntTab(cluster(x,y)), // global target index
614	nb_direct_initiators, // number of initiators
615	nb_direct_targets); // number of targets
616
617	std::ostringstream sc;
618	sc << "cxbar_" << x << "_" << y;
619	cxbar[x][y] = new VciLocalCrossbar<vci_param>(
620	sc.str().c_str(),
621	maptabc,
622	IntTab(cluster(x,y)), // global initiator index
623	IntTab(cluster(x,y)), // global target index
624	nprocs+1, // number of initiators
625	nprocs+1); // number of targets
626	}
627	}
628
629	std::cout << "all components created" << std::endl;
630
631	///////////////////////////////////////////////////////////////
632	// Net-list
633	///////////////////////////////////////////////////////////////
634
635	// External Ram (one instance)
636	xram.p_clk (signal_clk);
637	xram.p_resetn (signal_resetn);
638	xram.p_vci (signal_vci_tgt_x_xram);
639
640	// External Network (one instance)
641	xnoc.p_clk (signal_clk);
642	xnoc.p_resetn (signal_resetn);
643	xnoc.p_to_target[0] (signal_vci_tgt_x_xram);
644	for ( size_t x = 0 ; x < xmax ; x++ )
645	{
646	for ( size_t y = 0 ; y < ymax ; y++ )
647	{
648	xnoc.p_to_initiator[cluster(x,y)] (signal_vci_ini_x_memc[x][y]);
649	}
650	}
651
652	// Direct Network (one instance)
653	dnoc.p_clk (signal_clk);
654	dnoc.p_resetn (signal_resetn);
655	for ( size_t x = 0 ; x < xmax ; x++ )
656	{
657	for ( size_t y = 0 ; y < ymax ; y++ )
658	{
659	dnoc.p_to_initiator[cluster(x,y)] (signal_vci_l2g_d[x][y]);
660	dnoc.p_to_target[cluster(x,y)] (signal_vci_g2l_d[x][y]);
661	}
662	}
663
664	// Coherence Network (one instance)
665	cnoc.p_clk (signal_clk);
666	cnoc.p_resetn (signal_resetn);
667	for ( size_t x = 0 ; x < xmax ; x++ )
668	{
669	for ( size_t y = 0 ; y < ymax ; y++ )
670	{
671	cnoc.p_to_initiator[cluster(x,y)] (signal_vci_l2g_c[x][y]);
672	cnoc.p_to_target[cluster(x,y)] (signal_vci_g2l_c[x][y]);
673	}
674	}
675
676	// Distributed components (in clusters)
677
678	for ( size_t x = 0 ; x < xmax ; x++ )
679	{
680	for ( size_t y = 0 ; y < ymax ; y++ )
681	{
682	// direct local crossbar
683	dxbar[x][y]->p_clk (signal_clk);
684	dxbar[x][y]->p_resetn (signal_resetn);
685	dxbar[x][y]->p_initiator_to_up (signal_vci_l2g_d[x][y]);
686	dxbar[x][y]->p_target_to_up (signal_vci_g2l_d[x][y]);
687	dxbar[x][y]->p_to_target[MEMC_TGTID] (signal_vci_tgt_d_memc[x][y]);
688	dxbar[x][y]->p_to_target[XICU_TGTID] (signal_vci_tgt_d_xicu[x][y]);
689	for ( size_t p = 0 ; p < nprocs ; p++ )
690	{
691	dxbar[x][y]->p_to_initiator[p] (signal_vci_ini_d_proc[x][y][p]);
692	}
693
694	// coherence local crossbar
695	cxbar[x][y]->p_clk (signal_clk);
696	cxbar[x][y]->p_resetn (signal_resetn);
697	cxbar[x][y]->p_initiator_to_up (signal_vci_l2g_c[x][y]);
698	cxbar[x][y]->p_target_to_up (signal_vci_g2l_c[x][y]);
699	cxbar[x][y]->p_to_initiator[nprocs] (signal_vci_ini_c_memc[x][y]);
700	cxbar[x][y]->p_to_target[nprocs] (signal_vci_tgt_c_memc[x][y]);
701	for ( size_t p = 0 ; p < nprocs ; p++ )
702	{
703	cxbar[x][y]->p_to_initiator[p] (signal_vci_ini_c_proc[x][y][p]);
704	cxbar[x][y]->p_to_target[p] (signal_vci_tgt_c_proc[x][y][p]);
705	}
706
707	// Processors
708	for ( size_t p = 0 ; p < nprocs ; p++ )
709	{
710	proc[x][y][p]->p_clk (signal_clk);
711	proc[x][y][p]->p_resetn (signal_resetn);
712	proc[x][y][p]->p_vci_ini_rw (signal_vci_ini_d_proc[x][y][p]);
713	proc[x][y][p]->p_vci_ini_c (signal_vci_ini_c_proc[x][y][p]);
714	proc[x][y][p]->p_vci_tgt (signal_vci_tgt_c_proc[x][y][p]);
715	proc[x][y][p]->p_irq[0] (signal_proc_it[x][y][p]);
716	for ( size_t j = 1 ; j < 6 ; j++ )
717	{
718	proc[x][y][p]->p_irq[j] (signal_false);
719	}
720	}
721
722	// XICU
723	xicu[x][y]->p_clk (signal_clk);
724	xicu[x][y]->p_resetn (signal_resetn);
725	xicu[x][y]->p_vci (signal_vci_tgt_d_xicu[x][y]);
726	for ( size_t p = 0 ; p < nprocs ; p++ )
727	{
728	xicu[x][y]->p_irq[p] (signal_proc_it[x][y][p]);
729	}
730
731	// MEMC
732	memc[x][y]->p_clk (signal_clk);
733	memc[x][y]->p_resetn (signal_resetn);
734	memc[x][y]->p_vci_tgt (signal_vci_tgt_d_memc[x][y]);
735	memc[x][y]->p_vci_ini (signal_vci_ini_c_memc[x][y]);
736	memc[x][y]->p_vci_tgt_cleanup (signal_vci_tgt_c_memc[x][y]);
737	memc[x][y]->p_vci_ixr (signal_vci_ini_x_memc[x][y]);
738
739	// I/O peripherals
740	if ( cluster(x,y) == cluster_io_index )
741	{
742	bdev.p_clk (signal_clk);
743	bdev.p_resetn (signal_resetn);
744	bdev.p_irq (signal_irq_bdev);
745	bdev.p_vci_target (signal_vci_tgt_d_bdev);
746	bdev.p_vci_initiator (signal_vci_ini_d_bdev);
747
748	cdma.p_clk (signal_clk);
749	cdma.p_resetn (signal_resetn);
750	cdma.p_irq (signal_irq_cdma);
751	cdma.p_vci_target (signal_vci_tgt_d_cdma);
752	cdma.p_vci_initiator (signal_vci_ini_d_cdma);
753
754	fbuf.p_clk (signal_clk);
755	fbuf.p_resetn (signal_resetn);
756	fbuf.p_vci (signal_vci_tgt_d_fbuf);
757
758	brom.p_clk (signal_clk);
759	brom.p_resetn (signal_resetn);
760	brom.p_vci (signal_vci_tgt_d_brom);
761
762	mtty.p_clk (signal_clk);
763	mtty.p_resetn (signal_resetn);
764	mtty.p_vci (signal_vci_tgt_d_mtty);
765	for(size_t i=0 ; i<N_TTYS ; i++)
766	{
767	mtty.p_irq[i] (signal_irq_mtty[i]);
768	}
769
770	dxbar[x][y]->p_to_target[BROM_TGTID] (signal_vci_tgt_d_brom);
771	dxbar[x][y]->p_to_target[MTTY_TGTID] (signal_vci_tgt_d_mtty);
772	dxbar[x][y]->p_to_target[BDEV_TGTID] (signal_vci_tgt_d_bdev);
773	dxbar[x][y]->p_to_target[FBUF_TGTID] (signal_vci_tgt_d_fbuf);
774	dxbar[x][y]->p_to_target[CDMA_TGTID] (signal_vci_tgt_d_cdma);
775
776	dxbar[x][y]->p_to_initiator[BDEV_SRCID] (signal_vci_ini_d_bdev);
777	dxbar[x][y]->p_to_initiator[CDMA_SRCID] (signal_vci_ini_d_cdma);
778
779	xicu[x][y]->p_hwi[0] (signal_irq_bdev);
780	xicu[x][y]->p_hwi[1] (signal_irq_cdma);
781
782	for(size_t i=0 ; i<N_TTYS ; i++)
783	{
784	xicu[x][y]->p_hwi[2+i] (signal_irq_mtty[i]);
785	}
786	}
787	} // end for y
788	} // end for x
789
790	std::cout << "all components connected" << std::endl;
791
792	////////////////////////////////////////////////////////
793	// Simulation
794	///////////////////////////////////////////////////////
795
796	sc_start(sc_core::sc_time(0, SC_NS));
797	signal_resetn = false;
798
799	sc_start(sc_core::sc_time(1, SC_NS));
800	signal_resetn = true;
801
802	for(size_t i=1 ; i<ncycles ; i++)
803	{
804	sc_start(sc_core::sc_time(1, SC_NS));
805
806	if( debug_ok && (i > from_cycle) && (i < to_cycle) )
807	{
808	std::cout << std::dec << "************* cycle " << i << " *********************" << std::endl;
809	proc[0][0][0]->print_trace();
810	proc[0][1][0]->print_trace();
811	proc[1][0][0]->print_trace();
812	proc[1][1][0]->print_trace();
813	std::cout << std::endl;
814	dxbar[0][0]->print_trace();
815	dxbar[0][1]->print_trace();
816	dxbar[1][0]->print_trace();
817	dxbar[1][1]->print_trace();
818	std::cout << std::endl;
819	cxbar[0][0]->print_trace();
820	cxbar[0][1]->print_trace();
821	cxbar[1][0]->print_trace();
822	cxbar[1][1]->print_trace();
823	std::cout << std::endl;
824	memc[0][0]->print_trace();
825	memc[0][1]->print_trace();
826	memc[1][0]->print_trace();
827	memc[1][1]->print_trace();
828	std::cout << std::endl;
829	}
830	}
831
832	std::cout << "Hit ENTER to end simulation" << std::endl;
833	char buf[1];
834	std::cin.getline(buf,1);
835
836	return EXIT_SUCCESS;
837	}
838
839	int sc_main (int argc, char *argv[])
840	{
841	try {
842	return _main(argc, argv);
843	} catch (std::exception &e) {
844	std::cout << e.what() << std::endl;
845	} catch (...) {
846	std::cout << "Unknown exception occured" << std::endl;
847	throw;
848	}
849	return 1;
850	}

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