Ignore:
Timestamp:
Mar 9, 2011, 4:11:43 PM (13 years ago)
Author:
kane
Message:

yAjout du multi_cache : plusieurs processeur peuvent ce partager le même cache L1.
2 remarques, (1) deux nouveaux paramètres : nb_cpu, nb_cache. Pour avoir un cache dont le comportement est identique à la version d'avant, mettre ces paramètres à 1.
(2) le port d'interruption est maintenant un tableau dépendant du nombre de processeur.
Voir le fichier "platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp" pour plus de détails.

--Cette ligne, et les suivantes ci-dessous, seront ignorées--

M platforms/tsarv4_dspin_generic_32/tsarv4_dspin_generic_32_top.cpp
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/segmentation.h
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/gen_config.sh
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry21a.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/define.h
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/matrix_multiplication/matrix_multiplication.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/common/common.c
A platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying
A platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying/self_code_modifying.c
A platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying/self_code_modifying.h
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark.h
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_sort.c
A platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_self_code_modifying.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_matrix_multiplication.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/Makefile
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/Makefile
M platforms/tsarv4_vgmn_generic_32/tsarv4_vgmn_generic_32_top.cpp
M modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
M modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
M modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
M modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h
M modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp

File:
1 edited

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  • trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h

    r134 r140  
    3131
    3232#include <inttypes.h>
     33#include <fstream>
    3334#include <systemc>
    3435#include <queue>
    … …  
    7172 *     4    - one access with round robin priority
    7273 *
     74 * CC_XCACHE_WRAPPER_MULTI_CACHE :
     75 *     1    - icache static partitionnement
     76 *     2    - icache dedicated
     77 *
    7378 * CC_XCACHE_WRAPPER_STOP_SIMULATION :
    7479 *   stop simulation if processor is stall after a long time
    … …  
    8186 *   Number of cycle before to prinf debug message
    8287 *
    83  * CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
    84  *   Print transaction between the cpu and the cache
     88 * CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
     89 *   Print transaction between :
     90 *     - the cpu and the cache (icache and dcache)
     91 *     - vci
     92 *     - cleanup
     93 *     - coherency
    8594 */
    8695
    8796// implementation
    8897#ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM
    89 #define CC_XCACHE_WRAPPER_SELECT_VICTIM             0
     98#define CC_XCACHE_WRAPPER_SELECT_VICTIM               1
    9099#endif
    91100#ifndef CC_XCACHE_WRAPPER_FIFO_RSP
    92 #define CC_XCACHE_WRAPPER_FIFO_RSP                  0
     101#define CC_XCACHE_WRAPPER_FIFO_RSP                    1
    93102#endif
    94103#ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
    95 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE     1
     104#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE       1
    96105#endif
    97106#ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
    98 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1
     107#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT   1
    99108#endif
    100109#ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME
    101 #define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME        0
     110#define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME          2
    102111#endif
    103112#ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY
    104 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY          2
     113#define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY            4
     114#endif 
     115#ifndef CC_XCACHE_WRAPPER_MULTI_CACHE
     116#define CC_XCACHE_WRAPPER_MULTI_CACHE                 2
    105117#endif 
    106118// debugging
    107119#ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION
    108 #define CC_XCACHE_WRAPPER_STOP_SIMULATION           1
     120#define CC_XCACHE_WRAPPER_STOP_SIMULATION             1
    109121#endif
    110122#ifndef CC_XCACHE_WRAPPER_DEBUG
    111 #define CC_XCACHE_WRAPPER_DEBUG                     0
     123#define CC_XCACHE_WRAPPER_DEBUG                       0
    112124#endif
    113125#ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN
    114 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN           200000
    115 #endif
    116 #ifndef CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
    117 #define CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION  0
     126#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN             949900
     127#endif
     128#ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
     129#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION      0
     130#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log"
     131#endif
     132
     133// don't change
     134#if not CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
     135#undef  CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
     136#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT   0
    118137#endif
    119138
    … …  
    204223    enum cleanup_fsm_state_e {
    205224        CLEANUP_IDLE,
    206         CLEANUP_DCACHE,
    207         CLEANUP_ICACHE,
     225        CLEANUP_REQ,
     226        CLEANUP_RSP_DCACHE,
     227        CLEANUP_RSP_ICACHE,
    208228    };
    209229
    … …  
    231251    sc_in<bool>                             p_clk;
    232252    sc_in<bool>                             p_resetn;
    233     sc_in<bool>                             p_irq[iss_t::n_irq];
     253    sc_in<bool>                          ** p_irq;//[m_nb_cpu][iss_t::n_irq];
    234254    soclib::caba::VciInitiator<vci_param>   p_vci_ini_rw;
    235255    soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
    … …  
    241261    const soclib::common::AddressDecodingTable<vci_addr_t, bool>    m_cacheability_table;
    242262    const soclib::common::Segment                                   m_segment;
    243     iss_t               m_iss;
     263    iss_t            ** m_iss; //[m_nb_cpu]
    244264    const uint32_t      m_srcid_rw;   
    245265    const uint32_t      m_srcid_c;   
    246266   
     267    const size_t        m_nb_cpu;
     268    const size_t        m_nb_icache;
     269    const size_t        m_nb_dcache;
     270    const size_t        m_nb_cache;
    247271    const size_t        m_dcache_ways;
    248272    const size_t        m_dcache_words;
    … …  
    258282    bool                m_stop_simulation;
    259283    uint32_t            m_stop_simulation_nb_frz_cycles_max;
    260     uint32_t            m_stop_simulation_nb_frz_cycles;
     284    uint32_t          * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu]
    261285#endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
    262286
    263287    // REGISTERS
    264     sc_signal<int>          r_dcache_fsm;
    265     sc_signal<int>          r_dcache_fsm_save;
    266     sc_signal<addr_40>      r_dcache_addr_save;
    267     sc_signal<data_t>       r_dcache_wdata_save;
    268     sc_signal<data_t>       r_dcache_rdata_save;
    269     sc_signal<int>          r_dcache_type_save;
    270     sc_signal<be_t>         r_dcache_be_save;
    271     sc_signal<bool>         r_dcache_cached_save;
    272     sc_signal<bool>         r_dcache_cleanup_req;
    273     sc_signal<addr_40>      r_dcache_cleanup_line;
    274     sc_signal<bool>         r_dcache_miss_req;
    275     sc_signal<size_t>       r_dcache_miss_way;
    276     sc_signal<size_t>       r_dcache_miss_set;
    277     sc_signal<bool>         r_dcache_unc_req;
    278     sc_signal<bool>         r_dcache_sc_req;
    279     sc_signal<bool>         r_dcache_inval_rsp;
    280     sc_signal<size_t>       r_dcache_update_addr;
    281     sc_signal<data_64>      r_dcache_ll_data;
    282     sc_signal<addr_40>      r_dcache_ll_addr;
    283     sc_signal<bool>         r_dcache_ll_valid;
    284     sc_signal<bool>         r_dcache_previous_unc;
    285 
    286     sc_signal<int>          r_icache_fsm;
    287     sc_signal<int>          r_icache_fsm_save;
    288     sc_signal<addr_40>      r_icache_addr_save;
    289     sc_signal<bool>         r_icache_miss_req;
    290     sc_signal<size_t>       r_icache_miss_way;
    291     sc_signal<size_t>       r_icache_miss_set;
    292     sc_signal<bool>         r_icache_unc_req;
    293     sc_signal<bool>         r_icache_cleanup_req;
    294     sc_signal<addr_40>      r_icache_cleanup_line;
    295     sc_signal<bool>         r_icache_inval_rsp;
    296     sc_signal<size_t>       r_icache_update_addr;
     288    sc_signal<uint32_t>     r_cpu_prior;
     289    sc_signal<uint32_t>   * r_icache_lock;//[m_nb_icache]
     290    sc_signal<uint32_t>   * r_dcache_lock;//[m_nb_dcache]
     291    sc_signal<bool>       * r_dcache_sync;//[m_nb_dcache]
     292
     293    sc_signal<int>        * r_dcache_fsm;          //[m_nb_dcache]
     294    sc_signal<int>        * r_dcache_fsm_save;     //[m_nb_dcache]
     295    sc_signal<addr_40>    * r_dcache_addr_save;    //[m_nb_dcache]
     296    sc_signal<data_t>     * r_dcache_wdata_save;   //[m_nb_dcache]
     297    sc_signal<data_t>     * r_dcache_rdata_save;   //[m_nb_dcache]
     298    sc_signal<int>        * r_dcache_type_save;    //[m_nb_dcache]
     299    sc_signal<be_t>       * r_dcache_be_save;      //[m_nb_dcache]
     300    sc_signal<bool>       * r_dcache_cached_save;  //[m_nb_dcache]
     301    sc_signal<bool>       * r_dcache_cleanup_req;  //[m_nb_dcache]
     302    sc_signal<addr_40>    * r_dcache_cleanup_line; //[m_nb_dcache]
     303    sc_signal<bool>       * r_dcache_miss_req;     //[m_nb_dcache]
     304    sc_signal<size_t>     * r_dcache_miss_way;     //[m_nb_dcache]
     305    sc_signal<size_t>     * r_dcache_miss_set;     //[m_nb_dcache]
     306    sc_signal<bool>       * r_dcache_unc_req;      //[m_nb_dcache]
     307    sc_signal<bool>       * r_dcache_sc_req;       //[m_nb_dcache]
     308    sc_signal<bool>       * r_dcache_inval_rsp;    //[m_nb_dcache]
     309    sc_signal<size_t>     * r_dcache_update_addr;  //[m_nb_dcache]
     310    sc_signal<data_64>   ** r_dcache_ll_data;      //[m_nb_dcache][m_nb_cpu]
     311    sc_signal<addr_40>   ** r_dcache_ll_addr;      //[m_nb_dcache][m_nb_cpu]
     312    sc_signal<bool>      ** r_dcache_ll_valid;     //[m_nb_dcache][m_nb_cpu]
     313    sc_signal<uint32_t>   * r_dcache_num_cpu_save; //[m_nb_dcache]
     314    sc_signal<bool>       * r_dcache_previous_unc; //[m_nb_dcache]
     315                                                   
     316    sc_signal<int>        * r_icache_fsm;          //[m_nb_icache]
     317    sc_signal<int>        * r_icache_fsm_save;     //[m_nb_icache]
     318    sc_signal<addr_40>    * r_icache_addr_save;    //[m_nb_icache]
     319    sc_signal<bool>       * r_icache_miss_req;     //[m_nb_icache]
     320    sc_signal<size_t>     * r_icache_miss_way;     //[m_nb_icache]
     321    sc_signal<size_t>     * r_icache_miss_set;     //[m_nb_icache]
     322    sc_signal<bool>       * r_icache_unc_req;      //[m_nb_icache]
     323    sc_signal<bool>       * r_icache_cleanup_req;  //[m_nb_icache]
     324    sc_signal<addr_40>    * r_icache_cleanup_line; //[m_nb_icache]
     325    sc_signal<bool>       * r_icache_inval_rsp;    //[m_nb_icache]
     326    sc_signal<size_t>     * r_icache_update_addr;  //[m_nb_icache]
     327    sc_signal<bool>       * r_icache_buf_unc_valid;//[m_nb_icache]
    297328
    298329    sc_signal<int>          r_vci_cmd_fsm;
    … …  
    301332    sc_signal<size_t>       r_vci_cmd_cpt;       
    302333    sc_signal<bool>         r_vci_cmd_dcache_prior;
    303      
     334    sc_signal<uint32_t>     r_vci_cmd_num_cache;
     335
    304336    sc_signal<int>          r_vci_rsp_fsm;
    305     sc_signal<bool>         r_vci_rsp_ins_error;   
    306     sc_signal<bool>         r_vci_rsp_data_error;   
    307337    sc_signal<size_t>       r_vci_rsp_cpt; 
    308     sc_signal<bool>         r_vci_rsp_ack;
     338              bool          s_vci_rsp_ack;
     339    sc_signal<uint32_t>     r_vci_rsp_num_cache;
     340    sc_signal<bool>       * r_vci_rsp_ins_error;  //[m_nb_icache]
     341    sc_signal<bool>       * r_vci_rsp_data_error; //[m_nb_dcache]
    309342
    310343#if CC_XCACHE_WRAPPER_FIFO_RSP
    311     std::queue<data_t>      r_icache_miss_buf;
    312     std::queue<data_t>      r_dcache_miss_buf;
     344    std::queue<data_t>    * r_icache_miss_buf;    //[m_nb_icache]
     345    std::queue<data_t>    * r_dcache_miss_buf;    //[m_nb_dcache]
    313346#else
    314     bool                   *r_icache_miss_val;    //[m_icache_words]
    315     data_t                 *r_icache_miss_buf;    //[m_icache_words]
    316     bool                   *r_dcache_miss_val;    //[m_dcache_words]
    317     data_t                 *r_dcache_miss_buf;    //[m_dcache_words]
    318 #endif
    319     sc_signal<bool>         r_icache_buf_unc_valid;
    320 
    321     data_t                 *r_tgt_buf;            //[m_cache_words]
    322     be_t                   *r_tgt_be;             //[m_cache_words]
     347    bool                 ** r_icache_miss_val;    //[m_nb_icache][m_icache_words]
     348    data_t               ** r_icache_miss_buf;    //[m_nb_icache][m_icache_words]
     349    bool                 ** r_dcache_miss_val;    //[m_nb_dcache][m_dcache_words]
     350    data_t               ** r_dcache_miss_buf;    //[m_nb_dcache][m_dcache_words]
     351#endif
     352    data_t                * r_tgt_buf;            //[m_cache_words]
     353    be_t                  * r_tgt_be;             //[m_cache_words]
    323354#if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
    324355    sc_signal<uint32_t>     r_cache_word;
    … …  
    326357
    327358    sc_signal<int>          r_vci_tgt_fsm;
    328     sc_signal<addr_40>      r_tgt_addr;
     359    sc_signal<addr_40>      r_tgt_iaddr;
     360    sc_signal<addr_40>      r_tgt_daddr;
    329361    sc_signal<size_t>       r_tgt_word;
    330362    sc_signal<bool>         r_tgt_update;
    … …  
    335367    sc_signal<size_t>       r_tgt_trdid;
    336368  //sc_signal<size_t>       r_tgt_plen;
    337     sc_signal<bool>         r_tgt_icache_req;
    338     sc_signal<bool>         r_tgt_dcache_req;
    339     sc_signal<bool>         r_tgt_icache_rsp;
    340     sc_signal<bool>         r_tgt_dcache_rsp;
     369    sc_signal<uint32_t>     r_tgt_num_cache;
     370    sc_signal<bool>       * r_tgt_icache_req; //[m_nb_icache]
     371    sc_signal<bool>       * r_tgt_icache_rsp; //[m_nb_icache]
     372    sc_signal<bool>       * r_tgt_dcache_req; //[m_nb_dcache]
     373    sc_signal<bool>       * r_tgt_dcache_rsp; //[m_nb_dcache]
    341374
    342375    sc_signal<int>          r_cleanup_fsm;              // controls initiator port of the coherence network
    343 
    344     MultiWriteBuffer<addr_40>   r_wbuf;
    345     GenericCache<vci_addr_t>    r_icache;
    346     GenericCache<vci_addr_t>    r_dcache;
    347 
    348 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
    349     std::ofstream               log_dcache_transaction_file;
     376    sc_signal<uint32_t>     r_cleanup_num_cache;
     377    sc_signal<bool>         r_cleanup_icache;
     378
     379    MultiWriteBuffer<addr_40>** r_wbuf;
     380    GenericCache<vci_addr_t> ** r_icache;
     381    GenericCache<vci_addr_t> ** r_dcache;
     382
     383#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
     384    std::ofstream             * log_transaction_file_icache; //[m_nb_cpu]
     385    std::ofstream             * log_transaction_file_dcache; //[m_nb_cpu]
     386    std::ofstream               log_transaction_file_cmd;
     387    std::ofstream               log_transaction_file_tgt;
     388    std::ofstream               log_transaction_file_cleanup;
    350389#endif
    351390
    352391    // Activity counters
    353     uint32_t m_cpt_dcache_data_read;             // * DCACHE DATA READ
    354     uint32_t m_cpt_dcache_data_write;            // * DCACHE DATA WRITE
    355     uint32_t m_cpt_dcache_dir_read;              // * DCACHE DIR READ
    356     uint32_t m_cpt_dcache_dir_write;             // * DCACHE DIR WRITE
    357                                                  
    358     uint32_t m_cpt_icache_data_read;             // * ICACHE DATA READ
    359     uint32_t m_cpt_icache_data_write;            // * ICACHE DATA WRITE
    360     uint32_t m_cpt_icache_dir_read;              // * ICACHE DIR READ
    361     uint32_t m_cpt_icache_dir_write;             // * ICACHE DIR WRITE
    362 
    363     uint32_t m_cpt_cc_update_icache;             // number of coherence update packets (for icache)
    364     uint32_t m_cpt_cc_update_dcache;             // number of coherence update packets (for dcache)
    365     uint32_t m_cpt_cc_inval_broadcast;           // number of coherence inval packets
    366     uint32_t m_cpt_cc_inval_icache;              // number of coherence inval packets
    367     uint32_t m_cpt_cc_inval_dcache;              // number of coherence inval packets
    368     uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets
    369     uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets
    370 
    371     uint32_t m_cpt_frz_cycles;                   // * number of cycles where the cpu is frozen
    372     uint32_t m_cpt_total_cycles;                     // total number of cycles
    373 
    374     uint32_t m_cpt_data_read;                    //   number of data read
    375     uint32_t m_cpt_data_read_miss;               //   number of data read miss
    376     uint32_t m_cpt_data_read_uncached;           //   number of data read uncached
    377     uint32_t m_cpt_data_write;                   //   number of data write
    378     uint32_t m_cpt_data_write_miss;              //   number of data write miss
    379     uint32_t m_cpt_data_write_uncached;          //   number of data write uncached
    380     uint32_t m_cpt_ins_miss;                     // * number of instruction miss
    381 
    382     uint32_t m_cost_write_frz;                   // * number of frozen cycles related to write buffer         
    383     uint32_t m_cost_data_miss_frz;               // * number of frozen cycles related to data miss
    384     uint32_t m_cost_unc_read_frz;                // * number of frozen cycles related to uncached read
    385     uint32_t m_cost_ins_miss_frz;                // * number of frozen cycles related to ins miss
    386 
    387     uint32_t m_cpt_imiss_transaction;            // * number of VCI instruction miss transactions
    388     uint32_t m_cpt_dmiss_transaction;            // * number of VCI data miss transactions
    389     uint32_t m_cpt_unc_transaction;              // * number of VCI uncached read transactions
    390     uint32_t m_cpt_data_write_transaction;       // * number of VCI write transactions
    391 
    392     uint32_t m_cost_imiss_transaction;           // * cumulated duration for VCI IMISS transactions
    393     uint32_t m_cost_dmiss_transaction;           // * cumulated duration for VCI DMISS transactions
    394     uint32_t m_cost_unc_transaction;             // * cumulated duration for VCI UNC transactions
    395     uint32_t m_cost_write_transaction;           // * cumulated duration for VCI WRITE transactions
    396     uint32_t m_length_write_transaction;         // * cumulated length for VCI WRITE transactions
     392    uint32_t   m_cpt_dcache_data_read;             // * DCACHE DATA READ
     393    uint32_t   m_cpt_dcache_data_write;            // * DCACHE DATA WRITE
     394    uint32_t   m_cpt_dcache_dir_read;              // * DCACHE DIR READ
     395    uint32_t   m_cpt_dcache_dir_write;             // * DCACHE DIR WRITE
     396                                                   
     397    uint32_t   m_cpt_icache_data_read;             // * ICACHE DATA READ
     398    uint32_t   m_cpt_icache_data_write;            // * ICACHE DATA WRITE
     399    uint32_t   m_cpt_icache_dir_read;              // * ICACHE DIR READ
     400    uint32_t   m_cpt_icache_dir_write;             // * ICACHE DIR WRITE
     401               
     402    uint32_t   m_cpt_cc_update_icache;             // number of coherence update packets (for icache)
     403    uint32_t   m_cpt_cc_update_dcache;             // number of coherence update packets (for dcache)
     404    uint32_t   m_cpt_cc_inval_broadcast;           // number of coherence inval packets
     405    uint32_t   m_cpt_cc_inval_icache;              // number of coherence inval packets
     406    uint32_t   m_cpt_cc_inval_dcache;              // number of coherence inval packets
     407    uint32_t   m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets
     408    uint32_t   m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets
     409               
     410    uint32_t * m_cpt_frz_cycles;                       // * number of cycles where the cpu is frozen
     411    uint32_t   m_cpt_total_cycles;                     // total number of cycles
     412               
     413    uint32_t   m_cpt_data_read;                    //   number of data read
     414    uint32_t   m_cpt_data_read_miss;               //   number of data read miss
     415    uint32_t   m_cpt_data_read_uncached;           //   number of data read uncached
     416    uint32_t   m_cpt_data_write;                   //   number of data write
     417    uint32_t   m_cpt_data_write_miss;              //   number of data write miss
     418    uint32_t   m_cpt_data_write_uncached;          //   number of data write uncached
     419    uint32_t   m_cpt_ins_miss;                     // * number of instruction miss
     420               
     421    uint32_t   m_cost_write_frz;                   // * number of frozen cycles related to write buffer         
     422    uint32_t   m_cost_data_miss_frz;               // * number of frozen cycles related to data miss
     423    uint32_t   m_cost_unc_read_frz;                // * number of frozen cycles related to uncached read
     424    uint32_t   m_cost_ins_miss_frz;                // * number of frozen cycles related to ins miss
     425               
     426    uint32_t   m_cpt_imiss_transaction;            // * number of VCI instruction miss transactions
     427    uint32_t   m_cpt_dmiss_transaction;            // * number of VCI data miss transactions
     428    uint32_t   m_cpt_unc_transaction;              // * number of VCI uncached read transactions
     429    uint32_t   m_cpt_data_write_transaction;       // * number of VCI write transactions
     430               
     431    uint32_t   m_cost_imiss_transaction;           // * cumulated duration for VCI IMISS transactions
     432    uint32_t   m_cost_dmiss_transaction;           // * cumulated duration for VCI DMISS transactions
     433    uint32_t   m_cost_unc_transaction;             // * cumulated duration for VCI UNC transactions
     434    uint32_t   m_cost_write_transaction;           // * cumulated duration for VCI WRITE transactions
     435    uint32_t   m_length_write_transaction;         // * cumulated length for VCI WRITE transactions
     436
     437    uint32_t * m_cpt_icache_access; //[m_nb_icache]
     438    uint32_t * m_cpt_dcache_access; //[m_nb_dcache]
     439
     440    uint32_t ** m_cpt_fsm_dcache;  //[m_nb_dcache]
     441    uint32_t ** m_cpt_fsm_icache;  //[m_nb_icache]
     442    uint32_t  * m_cpt_fsm_cmd;
     443    uint32_t  * m_cpt_fsm_rsp;
     444    uint32_t  * m_cpt_fsm_tgt;
     445    uint32_t  * m_cpt_fsm_cleanup;
     446
     447    // Non blocking multi-cache
     448    typename iss_t::InstructionRequest  * ireq        ; //[m_nb_icache]
     449    typename iss_t::InstructionResponse * irsp        ; //[m_nb_icache]
     450    bool                                * ireq_cached ; //[m_nb_icache]
     451    uint32_t                            * ireq_num_cpu; //[m_nb_dcache]
     452    typename iss_t::DataRequest         * dreq        ; //[m_nb_dcache]
     453    typename iss_t::DataResponse        * drsp        ; //[m_nb_dcache]
     454    bool                                * dreq_cached ; //[m_nb_dcache]
     455    uint32_t                            * dreq_num_cpu; //[m_nb_dcache]
     456
     457    const uint32_t m_num_cache_LSB;
     458    const uint32_t m_num_cache_MSB;
     459          addr_40  m_num_cache_LSB_mask;
     460          addr_40  m_num_cache_mask;
    397461
    398462protected:
    … …  
    409473                       const soclib::common::IntTab &initiator_index_c,
    410474                       const soclib::common::IntTab &target_index,
     475                       size_t nb_cpu,
     476                       size_t nb_cache,
    411477                       size_t icache_ways,
    412478                       size_t icache_sets,
    … …  
    435501    void genMoore();
    436502
    437     soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
     503    uint32_t get_num_cache     (addr_40 & addr);
     504    uint32_t get_num_cache_only(addr_40   addr);
     505    void     set_num_cache     (addr_40 & addr, uint32_t num_cache);
     506    addr_40  set_num_cache_only(addr_40   addr, uint32_t num_cache);
     507
     508    soclib_static_assert((int)iss_t::SC_ATOMIC     == (int)vci_param::STORE_COND_ATOMIC);
    438509    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
    439510};
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