Ignore:
Timestamp:
Mar 9, 2011, 4:11:43 PM (13 years ago)
Author:
kane
Message:

yAjout du multi_cache : plusieurs processeur peuvent ce partager le même cache L1.
2 remarques, (1) deux nouveaux paramètres : nb_cpu, nb_cache. Pour avoir un cache dont le comportement est identique à la version d'avant, mettre ces paramètres à 1.
(2) le port d'interruption est maintenant un tableau dépendant du nombre de processeur.
Voir le fichier "platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp" pour plus de détails.

--Cette ligne, et les suivantes ci-dessous, seront ignorées--

M platforms/tsarv4_dspin_generic_32/tsarv4_dspin_generic_32_top.cpp
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/segmentation.h
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/gen_config.sh
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry21a.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/define.h
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/matrix_multiplication/matrix_multiplication.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/common/common.c
A platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying
A platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying/self_code_modifying.c
A platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying/self_code_modifying.h
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark.h
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_sort.c
A platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_self_code_modifying.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_matrix_multiplication.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/Makefile
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/Makefile
M platforms/tsarv4_vgmn_generic_32/tsarv4_vgmn_generic_32_top.cpp
M modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
M modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
M modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
M modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h
M modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp

Location:
trunk/modules/vci_mem_cache_v4/caba/source/include
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h

    r57 r140  
    66#include <cassert>
    77#include "arithmetics.h"
     8
     9#define L1_MULTI_CACHE      1
    810
    911namespace soclib { namespace caba {
    … …  
    3739      bool      inst;       // Is the owner an ICache ?
    3840      size_t    srcid;      // The SRCID of the owner
     41#if L1_MULTI_CACHE
     42      size_t    cache_id;   // In multi_cache configuration
     43#endif
    3944
    4045    ////////////////////////
    4146    // Constructors
    4247    ////////////////////////
    43       Owner(bool i_inst,size_t i_srcid){
     48      Owner(bool   i_inst
     49            ,size_t i_srcid
     50#if L1_MULTI_CACHE
     51            ,size_t i_cache_id
     52#endif
     53            ){
    4454        inst    = i_inst;
    4555        srcid   = i_srcid;
     56#if L1_MULTI_CACHE
     57        cache_id= i_cache_id;
     58#endif
    4659      }
    4760
    … …  
    4962        inst    = a.inst;
    5063        srcid   = a.srcid;
     64#if L1_MULTI_CACHE
     65        cache_id= a.cache_id;
     66#endif
    5167      }
    5268
    … …  
    5470        inst    = false;
    5571        srcid   = 0;
     72#if L1_MULTI_CACHE
     73        cache_id= 0;
     74#endif
    5675      }
    5776      // end constructors
    … …  
    89108      owner.inst    = 0;
    90109      owner.srcid   = 0;
     110#if L1_MULTI_CACHE
     111      owner.cache_id= 0;
     112#endif
    91113      ptr           = 0;
    92114    }
    … …  
    137159    {
    138160      std::cout << "Valid = " << valid << " ; IS COUNT = " << is_cnt << " ; Dirty = " << dirty << " ; Lock = "
    139         << lock << " ; Tag = " << std::hex << tag << std::dec << " ; Count = " << count << " ; Owner = " << owner.srcid << " " << owner.inst << " ; Pointer = " << ptr << std::endl;
     161                << lock
     162                << " ; Tag = " << std::hex << tag << std::dec
     163                << " ; Count = " << count
     164                << " ; Owner = " << owner.srcid
     165#if L1_MULTI_CACHE
     166                << "." << owner.cache_id
     167#endif
     168                << " " << owner.inst
     169                << " ; Pointer = " << ptr << std::endl;
    140170    }
    141171
    … …  
    346376    ////////////////////////
    347377      HeapEntry()
    348       :owner(false,0)
     378      :owner(false,0
     379#if L1_MULTI_CACHE
     380             ,0
     381#endif
     382             )
    349383      {
    350384        next = 0;
    … …  
    355389    ////////////////////////
    356390      HeapEntry(const HeapEntry &entry){
     391        owner.inst  = entry.owner.inst;
    357392        owner.srcid = entry.owner.srcid;
    358         owner.inst  = entry.owner.inst;
    359         next        = entry.next;
     393#if L1_MULTI_CACHE
     394        owner.cache_id = entry.owner.cache_id;
     395#endif       
     396        next           = entry.next;
    360397      } // end constructor
    361398
    … …  
    364401    /////////////////////////////////////////////////////////////////////
    365402      void copy(const HeapEntry &entry){
    366         owner.srcid = entry.owner.srcid;
    367         owner.inst  = entry.owner.inst;
    368         next        = entry.next;
     403        owner.inst     = entry.owner.inst;
     404        owner.srcid    = entry.owner.srcid;
     405#if L1_MULTI_CACHE
     406        owner.cache_id = entry.owner.cache_id;
     407#endif
     408        next           = entry.next;
    369409      } // end copy()
    370410
    … …  
    374414      void print(){
    375415        std::cout
    376         << " -- owner.srcid : " << std::dec << owner.srcid << std::endl
    377         << " -- owner.inst  : " << std::dec << owner.inst << std::endl
    378         << " -- next        : " << std::dec << next << std::endl;
     416        << " -- owner.inst     : " << std::dec << owner.inst << std::endl
     417        << " -- owner.srcid    : " << std::dec << owner.srcid << std::endl
     418#if L1_MULTI_CACHE
     419        << " -- owner.cache_id : " << std::dec << owner.cache_id << std::endl
     420#endif
     421        << " -- next           : " << std::dec << next << std::endl;
    379422
    380423      } // end print()

  • trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h

    r138 r140  
    405405      sc_signal<int>         r_read_fsm;        // FSM state
    406406      sc_signal<size_t>      r_read_copy;       // Srcid of the first copy
     407      sc_signal<size_t>      r_read_copy_cache; // Srcid of the first copy
    407408      sc_signal<bool>        r_read_copy_inst;  // Type of the first copy
    408409      sc_signal<tag_t>       r_read_tag;            // cache line tag (in directory)
    … …  
    450451      sc_signal<tag_t>     r_write_tag;             // cache line tag (in directory)
    451452      sc_signal<size_t>    r_write_copy;            // first owner of the line
     453      sc_signal<size_t>    r_write_copy_cache;      // first owner of the line
    452454      sc_signal<bool>      r_write_copy_inst;       // is this owner a ICache ?
    453455      sc_signal<size_t>    r_write_count;           // number of copies
    … …  
    483485      GenericFifo<bool>    m_write_to_init_cmd_inst_fifo;   // fifo for the L1 type
    484486      GenericFifo<size_t>  m_write_to_init_cmd_srcid_fifo;  // fifo for srcids
     487      GenericFifo<size_t>  m_write_to_init_cmd_cache_id_fifo;  // fifo for srcids
    485488
    486489      // Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
    … …  
    516519
    517520      sc_signal<copy_t>      r_cleanup_copy;        // first copy
     521      sc_signal<copy_t>      r_cleanup_copy_cache;  // first copy
    518522      sc_signal<size_t>      r_cleanup_copy_inst;   // type of the first copy
    519523      sc_signal<copy_t>      r_cleanup_count;       // number of copies
    … …  
    521525      sc_signal<size_t>      r_cleanup_prev_ptr;    // previous pointer to the heap
    522526      sc_signal<size_t>      r_cleanup_prev_srcid;  // srcid of previous heap entry
     527      sc_signal<size_t>      r_cleanup_prev_cache_id;  // srcid of previous heap entry
    523528      sc_signal<bool>        r_cleanup_prev_inst;   // inst bit of previous heap entry
    524529      sc_signal<size_t>      r_cleanup_next_ptr;    // next pointer to the heap
    … …  
    552557      sc_signal<size_t>    r_llsc_cpt;              // size of command
    553558      sc_signal<copy_t>    r_llsc_copy;             // Srcid of the first copy
     559      sc_signal<copy_t>    r_llsc_copy_cache;   // Srcid of the first copy
    554560      sc_signal<bool>      r_llsc_copy_inst;    // Type of the first copy
    555561      sc_signal<size_t>    r_llsc_count;            // number of copies
    … …  
    590596      GenericFifo<bool>    m_llsc_to_init_cmd_inst_fifo;    // fifo for the L1 type
    591597      GenericFifo<size_t>  m_llsc_to_init_cmd_srcid_fifo;   // fifo for srcids
     598      GenericFifo<size_t>  m_llsc_to_init_cmd_cache_id_fifo;// fifo for srcids
    592599
    593600      // Buffer between LLSC fsm and INIT_RSP fsm (Decrement UPT entry)
    … …  
    620627      sc_signal<addr_t>    r_xram_rsp_victim_nline;     // victim line index
    621628      sc_signal<copy_t>    r_xram_rsp_victim_copy;      // victim line first copy
     629      sc_signal<copy_t>    r_xram_rsp_victim_copy_cache;// victim line first copy
    622630      sc_signal<bool>      r_xram_rsp_victim_copy_inst; // victim line type of first copy
    623631      sc_signal<size_t>    r_xram_rsp_victim_count;         // victim line number of copies
    … …  
    644652      GenericFifo<bool>     m_xram_rsp_to_init_cmd_inst_fifo;       // fifo for the L1 type
    645653      GenericFifo<size_t>   m_xram_rsp_to_init_cmd_srcid_fifo;      // fifo for srcids
     654      GenericFifo<size_t>   m_xram_rsp_to_init_cmd_cache_id_fifo;      // fifo for srcids
    646655
    647656      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
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