Changeset 144 for trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include

Timestamp:

Mar 30, 2011, 6:30:22 PM (13 years ago)

Author:

kane

Message:

in vci_cc_xcache_wrapper_v4 : (1) Fix bug in MISS_VICTIM state, (2) add HIT after MISS, (3) add STORE after STORE

File:

• trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h (modified) (6 diffs)

trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h

@@ -74 +74 @@
  *     2    - icache dedicated
  *
+ * CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS
+ *   (In multi-cache) 
+ *   A dcache used by a cpu and in miss_wait state can be use by
+ *   an another cpu to make a load cached access.
+ * 
+ * CC_XCACHE_WRAPPER_STORE_AFTER_STORE
+ *   Store access in dcache (and hit) is make in two cycle :
+ *    - first read directory and read data
+ *    - second make a mask with old data and write new data.
+ *   If data part has a write enable per byte, read data access can be suppress
+ *   and we can pipeline consecutive store access.
+ *
  * CC_XCACHE_WRAPPER_STOP_SIMULATION :
  *   stop simulation if processor is stall after a long time
@@ -94 +106 @@
 // implementation
 #ifndef CC_XCACHE_WRAPPER_FIFO_RSP
-#define CC_XCACHE_WRAPPER_FIFO_RSP                    1
+#define CC_XCACHE_WRAPPER_FIFO_RSP                    2
 #endif
 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
@@ -107 +119 @@
 #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY
 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY            3
-#endif  
+#endif
 #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE
 #define CC_XCACHE_WRAPPER_MULTI_CACHE                 2
@@ -113 +125 @@
 // <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1
 // <soclib toplevel>/soclib/lib/multi_write_buffer/include/multi_write_buffer.h          : CC_XCACHE_MULTI_CACHE 1
+#endif
+#ifndef CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS
+#define CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS  1
+#endif
+#ifndef CC_XCACHE_WRAPPER_STORE_AFTER_STORE
+#define CC_XCACHE_WRAPPER_STORE_AFTER_STORE           1
 #endif
   
@@ -444 +462 @@
     uint32_t * m_cpt_icache_access; //[m_nb_icache]
     uint32_t * m_cpt_dcache_access; //[m_nb_dcache]
+    uint32_t * m_cpt_dcache_hit_after_miss_read;  //[m_nb_dcache]
+    uint32_t * m_cpt_dcache_hit_after_miss_write; //[m_nb_dcache]
+    uint32_t * m_cpt_dcache_store_after_store; //[m_nb_dcache]
+    uint32_t * m_cpt_icache_miss_victim_wait; //[m_nb_icache]
+    uint32_t * m_cpt_dcache_miss_victim_wait; //[m_nb_dcache]
 
     uint32_t ** m_cpt_fsm_dcache;  //[m_nb_dcache]
@@ -495 +518 @@
     ~VciCcXCacheWrapperV4();
 
-    void print_trace(size_t mode = 0);
-    void print_cpi();
-    void print_stats();
+  void print_trace(size_t mode = 0);
+  void print_cpi();
+  void print_stats(bool print_wbuf=true, bool print_fsm=true);
 
 // #if CC_XCACHE_WRAPPER_STOP_SIMULATION