Changeset 150
- Timestamp:
- May 2, 2011, 9:20:32 AM (13 years ago)
- Location:
- trunk/modules/vci_vdspin_initiator_wrapper/caba/source
- Files:
-
- 2 edited
-
include/vci_vdspin_initiator_wrapper.h (modified) (3 diffs)
-
src/vci_vdspin_initiator_wrapper.cpp (modified) (11 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h
r148 r150 66 66 CMD_IDLE, 67 67 CMD_BROADCAST, 68 CMD_RW, 68 CMD_READ, 69 CMD_WRITE, 69 70 CMD_WDATA, 70 71 }; … … 74 75 RSP_IDLE, 75 76 RSP_READ, 77 RSP_WRITE, 76 78 }; 77 79 … … 105 107 void genMoore(); 106 108 109 public: 110 void print_trace(); 111 107 112 }; 108 113 -
trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp
r148 r150 95 95 // - A single flit VCI broadcast packet is translated to 96 96 // a 2 flits DSPIN command. 97 // A DSPIN flit is written in the fifo_cmd in all states 98 // but a VCI flit is consumed only in the CMD_READ, 99 // CMD_BROACAST, and CMD_WDATA states. 97 100 ////////////////////////////////////////////////////////////// 98 101 … … 101 104 102 105 // r_cmd_fsm, cmd_fifo_write and cmd_fifo_data 106 cmd_fifo_write = false; // default value 107 103 108 switch(r_cmd_fsm) { 104 109 case CMD_IDLE: // write first DSPIN flit into fifo_cmd … … 110 115 sc_uint<dspin_cmd_width> srcid = (sc_uint<dspin_cmd_width>)p_vci.srcid.read(); 111 116 sc_uint<dspin_cmd_width> trdid = (sc_uint<dspin_cmd_width>)p_vci.trdid.read(); 112 if ( address & 0x3 ) // VCI broacast command 117 sc_uint<dspin_cmd_width> cmd = (sc_uint<dspin_cmd_width>)p_vci.cmd.read(); 118 119 bool is_broadcast = ( (address & 0x3) != 0); 120 bool is_read = ((cmd == vci_param::CMD_READ) || (cmd == vci_param::CMD_LOCKED_READ)); 121 122 if ( vci_param::N == 40 ) address = address >> 1; 123 else address = address << (39 - vci_param::N); 124 125 if ( is_broadcast ) // VCI broacast command 113 126 { 114 127 r_cmd_fsm = CMD_BROADCAST; 115 cmd_fifo_data = ((address & 0xFFFFF00000) >> 1) | 116 (srcid << 5) | (trdid << 1) | 0x0000000001; 128 cmd_fifo_data = (address & 0x7FFFF80000) | 129 ((srcid << 5) & 0x000007FFE0) | 130 ((trdid << 1) & 0x000000001E) | 131 0x0000000001; 117 132 } 118 else // VCI READ or WRITE command 119 { 120 r_cmd_fsm = CMD_RW; 121 cmd_fifo_data = (address >> 1) & 0x788888888E; 133 else if (is_read ) // VCI READ command 134 { 135 r_cmd_fsm = CMD_READ; 136 cmd_fifo_data = address & 0x7FFFFFFFFE; 137 } 138 else // VCI WRITE command 139 { 140 r_cmd_fsm = CMD_WRITE; 141 cmd_fifo_data = address & 0x7FFFFFFFFE; 122 142 } 123 143 } 124 else125 {126 cmd_fifo_write = false;127 }128 144 break; 129 145 } … … 135 151 sc_uint<dspin_cmd_width> data = (sc_uint<dspin_cmd_width>)p_vci.wdata.read(); 136 152 sc_uint<dspin_cmd_width> be = (sc_uint<dspin_cmd_width>)p_vci.be.read(); 137 cmd_fifo_data = (data & 0x00FFFFFFFF) | ((be & 0x3) << 32) | 0x8000000000; 153 cmd_fifo_data = (data & 0x00FFFFFFFF) | 154 ((be << 32) & 0x0300000000) | 155 0x8000000000; 138 156 r_cmd_fsm = CMD_IDLE; 139 157 } 140 else141 {142 cmd_fifo_write = false;143 }144 158 break; 145 159 } 146 case CMD_RW: // write second DSPIN flit in case of read/write 160 case CMD_READ: // write second DSPIN flit in case of read/write 161 case CMD_WRITE: 147 162 { 148 163 if( p_vci.cmdval && r_fifo_cmd.wok() ) … … 154 169 sc_uint<dspin_cmd_width> plen = (sc_uint<dspin_cmd_width>)p_vci.plen.read(); 155 170 sc_uint<dspin_cmd_width> be = (sc_uint<dspin_cmd_width>)p_vci.be.read(); 156 cmd_fifo_data = ((be & 0xF) << 1) | 157 ((trdid & 0xFF) << 5) | 158 ((plen & 0xFF) << 13) | 159 ((cmd & 0x3) << 23) | 160 ((srcid & 0x3FFF) << 25) | 161 0x1000000000; 162 if( (cmd == vci_param::CMD_READ) || 163 (cmd == vci_param::CMD_LOCKED_READ) ) r_cmd_fsm = CMD_IDLE; 164 else r_cmd_fsm = CMD_WDATA; 171 cmd_fifo_data = ((be << 1 ) & 0x000000001E) | 172 ((trdid << 5 ) & 0x0000001FE0) | 173 ((plen << 13) & 0x00001FE000) | 174 ((cmd << 23) & 0x0001800000) | 175 ((srcid << 25) & 0x7FFE000000) ; 176 if ( p_vci.contig.read() ) cmd_fifo_data = cmd_fifo_data | 0x0000400000 ; 177 if ( p_vci.cons.read() ) cmd_fifo_data = cmd_fifo_data | 0x0000200000 ; 178 179 if( r_cmd_fsm == CMD_READ ) // read command 180 { 181 r_cmd_fsm = CMD_IDLE; 182 cmd_fifo_data = cmd_fifo_data | 0x8000000000 ; 183 } 184 else // write command 185 { 186 r_cmd_fsm = CMD_WDATA; 187 } 165 188 } 166 else167 {168 cmd_fifo_write = false;169 }170 189 break; 171 190 } … … 177 196 sc_uint<dspin_cmd_width> data = (sc_uint<dspin_cmd_width>)p_vci.wdata.read(); 178 197 sc_uint<dspin_cmd_width> be = (sc_uint<dspin_cmd_width>)p_vci.be.read(); 179 cmd_fifo_data = (data & 0xFFFFFFFF) | ((be & 0xF) << 32); 198 cmd_fifo_data = (data & 0x00FFFFFFFF) | 199 ((be << 32) & 0x0F00000000) ; 200 180 201 if ( p_vci.eop.read() ) 181 202 { … … 184 205 } 185 206 } 186 else187 {188 cmd_fifo_write = false;189 }190 207 break; 191 208 } … … 202 219 // The FIFO output is analysed and translated to a VCI packet 203 220 ////////////////////////////////////////////////////////////// 204 // - A N+ 2flits DSPIN read response packet is translated221 // - A N+1 flits DSPIN read response packet is translated 205 222 // to a N flits VCI response. 206 223 // - A single flit DSPIN write response packet is translated 207 224 // to a single flit VCI response. 225 // A valid DSPIN flit in the fifo_rsp is always consumed 226 // in the CMD_IDLE state, but no VCI flit is transmitted. 227 // The VCI flits are sent in the RSP_READ & RSP_WRITE states. 208 228 ////////////////////////////////////////////////////////////// 209 229 … … 213 233 214 234 // r_rsp_fsm, rsp_fifo_read 235 rsp_fifo_read = false; // default value 236 215 237 switch(r_rsp_fsm) { 216 238 case RSP_IDLE: 217 239 { 218 if( r_fifo_rsp.rok() && p_vci.rspack)240 if( r_fifo_rsp.rok() ) 219 241 { 220 242 rsp_fifo_read = true; 221 if ( (r_fifo_rsp.read() & 0x000020000) == 0 ) // read response 222 { 223 r_rsp_buf = r_fifo_rsp.read(); 224 r_rsp_fsm = RSP_READ; 225 } 243 r_rsp_buf = r_fifo_rsp.read(); 244 if ( (r_fifo_rsp.read() & 0x000020000) == 0 ) r_rsp_fsm = RSP_READ; 245 else r_rsp_fsm = RSP_WRITE; 226 246 } 227 else228 {229 rsp_fifo_read = false;230 }231 232 247 break; 233 248 } 234 249 case RSP_READ: 235 250 { 236 if( r_fifo_rsp.rok() && p_vci.rspack )251 if( r_fifo_rsp.rok() && p_vci.rspack.read() ) 237 252 { 238 253 rsp_fifo_read = true; 239 254 if ( (r_fifo_rsp.read() & 0x100000000) ) r_rsp_fsm = RSP_IDLE; 240 255 } 241 else242 {243 rsp_fifo_read = false;244 }245 256 break; 257 } 258 case RSP_WRITE: 259 { 260 if ( p_vci.rspack.read() ) r_rsp_fsm = RSP_IDLE; 246 261 } 247 262 } // end switch r_rsp_fsm … … 258 273 { 259 274 // VCI CMD interface 260 if ( r_cmd_fsm.read() == CMD_IDLE ) p_vci.cmdack = false; 261 else p_vci.cmdack = r_fifo_cmd.wok(); 275 if ( ( r_cmd_fsm.read() == CMD_IDLE ) || ( r_cmd_fsm.read() == CMD_WRITE ) ) 276 { 277 p_vci.cmdack = false; 278 } 279 else 280 { 281 p_vci.cmdack = r_fifo_cmd.wok(); 282 } 262 283 263 284 // VCI RSP interface 264 285 if ( r_rsp_fsm.read() == RSP_IDLE ) 265 286 { 266 if ( r_fifo_rsp.rok() && (r_fifo_rsp.read() & 0x000020000) ) // valid RSP WRITE 267 { 268 p_vci.rspval = true; 269 p_vci.rdata = 0; 270 p_vci.rsrcid = (sc_uint<vci_param::S>)((r_fifo_rsp.read() & 0x0FFFC0000) >> 18); 271 p_vci.rtrdid = (sc_uint<vci_param::T>)((r_fifo_rsp.read() & 0x00000FF00) >> 8); 272 p_vci.rpktid = 0; 273 p_vci.rerror = (sc_uint<vci_param::E>)((r_fifo_rsp.read() & 0x000030000) >> 16); 274 p_vci.reop = true; 275 } 276 else 277 { 278 p_vci.rspval = false; 279 } 280 } 281 else // Next flit of a RSP READ 282 { 283 if ( r_fifo_rsp.rok() ) // valid RSP READ 284 { 285 p_vci.rspval = true; 286 p_vci.rdata = (sc_uint<4*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFF); 287 p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000) >> 18); 288 p_vci.rtrdid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x00000FF00) >> 8); 289 p_vci.rpktid = 0; 290 p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000) >> 16); 291 p_vci.reop = ((r_fifo_rsp.read() & 0x100000000) == 0x100000000); 292 } 293 else 294 { 295 p_vci.rspval = false; 296 } 297 } 287 p_vci.rspval = false; 288 } 289 else if ( r_rsp_fsm.read() == RSP_WRITE ) 290 { 291 p_vci.rspval = true; 292 p_vci.rdata = 0; 293 p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000) >> 18); 294 p_vci.rtrdid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x00000FF00) >> 8); 295 p_vci.rpktid = 0; 296 p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000) >> 16); 297 p_vci.reop = true; 298 } 299 else if ( r_rsp_fsm.read() == RSP_READ ) 300 { 301 p_vci.rspval = true; 302 p_vci.rdata = (sc_uint<8*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFF); 303 p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000) >> 18); 304 p_vci.rtrdid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x00000FF00) >> 8); 305 p_vci.rpktid = 0; 306 p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000) >> 16); 307 p_vci.reop = ((r_fifo_rsp.read() & 0x100000000) == 0x100000000); 308 } 298 309 299 310 // DSPIN_OUT interface … … 305 316 306 317 }; // end genMoore 318 319 ///////////////////////// 320 tmpl(void)::print_trace() 321 { 322 const char* cmd_str[] = { 323 "CMD_IDLE ", 324 "CMD_BROADCAST", 325 "CMD_READ ", 326 "CMD_WRITE ", 327 "CMD_WDATA ", 328 }; 329 const char* rsp_str[] = { 330 "RSP_IDLE ", 331 "RSP_READ ", 332 "RSP_WRITE ", 333 }; 334 335 std::cout << name() << " : " << cmd_str[r_cmd_fsm.read()] 336 << " | " << rsp_str[r_rsp_fsm.read()] 337 << " | fifo_cmd = " << r_fifo_cmd.filled_status() 338 << " | fifo_rsp = " << r_fifo_rsp.filled_status() 339 << std::endl; 340 } 307 341 308 342 }} // end namespace
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