Changeset 238


Ignore:
Timestamp:
Jul 16, 2012, 5:52:01 PM (12 years ago)
Author:
fraga
Message:

Changing ICACHE TLB MISS requests priority in DCACHE_IDLE. Now, the data is treated first. This solves the following livelock problem: A processor's simultaneous request of instruction and data that generates miss on PTE1 and PTE2 in the instruction address, PTE1 and PTE2 in the data address and on the data itself. In the case where all these data occupy the same set and the DCACHE contains 4 ways, the instruction page table entry may be overwritten producing a new TLB MISS request to the DCACHE. The cycle then restarts.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp

    r237 r238  
    21652165        }       
    21662166
    2167         // itlb miss request
    2168         else if ( r_icache_tlb_miss_req.read() )
    2169         {
    2170             r_dcache_tlb_ins    = true;
    2171             r_dcache_tlb_vaddr  = r_icache_vaddr_save.read();
    2172             r_dcache_fsm        = DCACHE_TLB_MISS;
    2173             r_dcache_p0_valid = false;
    2174         }
    2175 
    21762167        // processor request
    21772168        else if ( m_dreq.valid and not write_pipe_frozen )
     
    27162707            }  // end if read/write/ll/sc request       
    27172708        } // end dreq.valid
     2709       
     2710        // itlb miss request
     2711        else if ( r_icache_tlb_miss_req.read() )
     2712        {
     2713            r_dcache_tlb_ins    = true;
     2714            r_dcache_tlb_vaddr  = r_icache_vaddr_save.read();
     2715            r_dcache_fsm        = DCACHE_TLB_MISS;
     2716            r_dcache_p0_valid = false;
     2717        }
    27182718        else
    27192719        {
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