- Timestamp:
- Aug 9, 2012, 11:26:59 AM (12 years ago)
- File:
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trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp
r247 r249 8 8 ////////////////////////////////////////////////////////////////////////// 9 9 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> 10 TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterMmu( 11 sc_module_name insname, 12 size_t nprocs, 13 size_t x_id, 14 size_t y_id, 15 size_t cluster_id, 16 const soclib::common::MappingTable &mtd, 17 const soclib::common::MappingTable &mtc, 18 const soclib::common::MappingTable &mtx, 19 size_t x_width, 20 size_t y_width, 21 size_t tgtid_memc, 22 size_t tgtid_xicu, 23 size_t tgtid_fbuf, 24 size_t tgtid_mtty, 25 size_t tgtid_brom, 26 size_t tgtid_bdev, 27 size_t tgtid_mdma, 28 size_t memc_ways, 29 size_t memc_sets, 30 size_t l1_i_ways, 31 size_t l1_i_sets, 32 size_t l1_d_ways, 33 size_t l1_d_sets, 34 size_t xram_latency, 35 bool io, 36 size_t xfb, 37 size_t yfb, 38 char* disk_name, 39 size_t block_size, 40 const Loader &loader, 41 uint32_t frozen_cycles, 42 uint32_t debug_start_cycle, 43 bool debug_ok) 44 : soclib::caba::BaseModule(insname), 45 p_clk("clk"), 46 p_resetn("resetn"), 47 48 signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"), 49 signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"), 50 signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"), 51 signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"), 52 signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"), 53 signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"), 54 signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"), 55 signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"), 56 57 signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"), 58 signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"), 59 60 signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"), 61 signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"), 62 signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"), 63 signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"), 64 signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"), 65 signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"), 66 signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"), 67 68 signal_vci_ini_c_memc("signal_vci_ini_c_memc"), 69 signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"), 70 71 signal_vci_xram("signal_vci_xram") 72 73 { 74 // Vectors of ports definition 75 76 p_cmd_in = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4); 77 p_cmd_out = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4); 78 p_rsp_in = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4); 79 p_rsp_out = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4); 80 81 // Components definition 82 83 // on direct network : local srcid[proc] in [0...nprocs-1] 84 // on direct network : local srcid[mdma] = nprocs 85 // on direct network : local srcid[bdev] = nprocs + 1 86 87 // on coherence network : local srcid[proc] in [0...nprocs-1] 88 // on coherence network : local srcid[memc] = nprocs 89 90 std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; 91 92 for ( size_t p=0 ; p<nprocs ; p++ ) 93 { 94 std::ostringstream sproc; 95 sproc << "proc_" << x_id << "_" << y_id << "_" << p; 96 proc[p] = new VciCcVCacheWrapperV4<vci_param, iss_t>( 97 sproc.str().c_str(), 98 cluster_id*nprocs + p, 99 mtd, // Mapping Table Direct 100 mtc, // Mapping Table Coherence 101 IntTab(cluster_id,p), // SRCID_D 102 IntTab(cluster_id,p), // SRCID_C 103 IntTab(cluster_id,p), // TGTID_C 104 8, // ITLB ways 105 8, // ITLB sets 106 8, // DTLB ways 107 8, // DTLB sets 108 l1_i_ways,l1_i_sets,16, // ICACHE size 109 l1_d_ways,l1_d_sets,16, // DCACHE size 110 4, // WBUF width 111 4, // WBUF depth 112 x_width, // X Width 113 y_width, // Y Width 114 nprocs, // Memory Cache Local Id (coherence) 115 frozen_cycles, // max frozen cycles 116 debug_start_cycle, 117 debug_ok); 118 } 119 120 std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; 121 122 std::ostringstream smemc; 123 smemc << "memc_" << x_id << "_" << y_id; 124 memc = new VciMemCacheV4<vci_param>( 125 smemc.str().c_str(), 126 mtd, mtc, mtx, 127 IntTab(cluster_id), // SRCID_X 128 IntTab(cluster_id, nprocs), // SRCID_C 129 IntTab(cluster_id, tgtid_memc), // TGTID_D 130 IntTab(cluster_id, nprocs), // TGTID_C 131 memc_ways, memc_sets, 16, // CACHE SIZE 132 4096, // HEAP SIZE 133 8, // TRANSACTION TABLE DEPTH 134 8, // UPDATE TABLE DEPTH 135 debug_start_cycle, 136 debug_ok); 137 138 139 std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; 140 141 std::ostringstream sxram; 142 sxram << "xram_" << x_id << "_" << y_id; 143 xram = new VciSimpleRam<vci_param>( 144 sxram.str().c_str(), 145 IntTab(cluster_id), 146 mtx, 147 loader, 148 xram_latency); 149 150 std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; 151 152 size_t nhwi = 4; // always 4 (or 9) ports, even if 153 if( io == true ) nhwi = 9; // there if less than 4 processors 154 std::ostringstream sicu; 155 sicu << "xicu_" << x_id << "_" << y_id; 156 xicu = new VciXicu<vci_param>( 157 sicu.str().c_str(), 158 mtd, // mapping table 159 IntTab(cluster_id, tgtid_xicu), // TGTID_D 160 0, // number of timer IRQs 161 nhwi, // number of hard IRQs 162 0, // number of soft IRQs 163 nprocs); // number of output IRQs 164 165 std::cout << " - building dma_" << x_id << "_" << y_id << std::endl; 166 167 // dma multi-canaux 168 std::ostringstream sdma; 169 sdma << "dma_" << x_id << "_" << y_id; 170 mdma = new VciMultiDma<vci_param>( 171 sdma.str().c_str(), 172 mtd, 173 IntTab(cluster_id, nprocs), // SRCID 174 IntTab(cluster_id, tgtid_mdma), // TGTID 175 64, // burst size 176 nprocs); // number of IRQs 177 178 std::cout << " - building xbard_" << x_id << "_" << y_id << std::endl; 179 180 // direct local crossbar 181 size_t nb_direct_initiators = nprocs + 1; 182 size_t nb_direct_targets = 3; 183 if( io == true ) 184 { 185 nb_direct_initiators = nprocs + 2; 186 nb_direct_targets = 7; 187 } 188 std::ostringstream sd; 189 sd << "xbard_" << x_id << "_" << y_id; 190 xbard = new VciLocalCrossbar<vci_param>( 191 sd.str().c_str(), 192 mtd, 193 IntTab(cluster_id), // cluster initiator index 194 IntTab(cluster_id), // cluster target index 195 nb_direct_initiators, // number of initiators 196 nb_direct_targets); // number of targets 197 198 std::cout << " - building xbarc_" << x_id << "_" << y_id << std::endl; 199 200 // coherence local crossbar 201 std::ostringstream sc; 202 sc << "xbarc_" << x_id << "_" << y_id; 203 xbarc = new VciLocalCrossbar<vci_param>( 204 sc.str().c_str(), 205 mtc, 206 IntTab(cluster_id), // cluster initiator index 207 IntTab(cluster_id), // cluster target index 208 nprocs + 1, // number of initiators 209 nprocs + 1); // number of targets 210 211 std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; 212 213 // direct initiator wrapper 214 std::ostringstream wid; 215 wid << "iniwrapperd_" << x_id << "_" << y_id; 216 iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 217 wid.str().c_str(), 218 4, // cmd fifo depth 219 4); // rsp fifo depth 220 221 // direct target wrapper 222 std::ostringstream wtd; 223 wtd << "tgtwrapperd_" << x_id << "_" << y_id; 224 tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 225 wtd.str().c_str(), 226 4, // cmd fifo depth 227 4); // rsp fifo depth 228 229 // coherence initiator wrapper 230 std::ostringstream wic; 231 wic << "iniwrapperc_" << x_id << "_" << y_id; 232 iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 233 wic.str().c_str(), 234 4, // cmd fifo depth 235 4); // rsp fifo depth 236 237 // coherence target wrapper 238 std::ostringstream wtc; 239 wtc << "tgtwrapperc_" << x_id << "_" << y_id; 240 tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 241 wtc.str().c_str(), 242 4, // cmd fifo depth 243 4); // rsp fifo depth 244 245 std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl; 246 247 // CMD router 248 std::ostringstream scmd; 249 scmd << "cmdrouter_" << x_id << "_" << y_id; 250 cmdrouter = new VirtualDspinRouter<cmd_width>( 251 scmd.str().c_str(), 252 x_id,y_id, // coordinate in the mesh 253 x_width, y_width, // x & y fields width 254 4,4); // input & output fifo depths 255 256 std::cout << " - building rsprouter_" << x_id << "_" << y_id << std::endl; 257 258 // RSP router 259 std::ostringstream srsp; 260 srsp << "rsprouter_" << x_id << "_" << y_id; 261 rsprouter = new VirtualDspinRouter<rsp_width>( 262 srsp.str().c_str(), 263 x_id,y_id, // coordinates in mesh 264 x_width, y_width, // x & y fields width 265 4,4); // input & output fifo depths 266 267 // IO cluster components 268 if ( io == true ) 269 { 270 brom = new VciSimpleRam<vci_param>( 271 "brom", 272 IntTab(cluster_id, tgtid_brom), 273 mtd, 274 loader); 275 276 fbuf = new VciFrameBuffer<vci_param>( 277 "fbuf", 278 IntTab(cluster_id, tgtid_fbuf), 279 mtd, 280 xfb, yfb); 281 282 bdev = new VciBlockDeviceTsarV4<vci_param>( 283 "bdev", 284 mtd, 285 IntTab(cluster_id, nprocs+1), 286 IntTab(cluster_id, tgtid_bdev), 287 disk_name, 288 block_size); 289 290 mtty = new VciMultiTty<vci_param>( 291 "mtty", 292 IntTab(cluster_id, tgtid_mtty), 293 mtd, 294 "tty0", "tty1", "tty2", "tty3", NULL); 295 } 296 297 std::cout << " - all components constructed" << std::endl; 298 299 //////////////////////////////////// 300 // Connections are defined here 301 //////////////////////////////////// 302 303 // CMDROUTER and RSPROUTER 304 cmdrouter->p_clk (this->p_clk); 305 cmdrouter->p_resetn (this->p_resetn); 306 rsprouter->p_clk (this->p_clk); 307 rsprouter->p_resetn (this->p_resetn); 308 for(int x = 0; x < 2; x++) 309 { 310 for(int y = 0; y < 4; y++) 311 { 312 cmdrouter->p_out[x][y] (this->p_cmd_out[x][y]); 313 cmdrouter->p_in[x][y] (this->p_cmd_in[x][y]); 314 rsprouter->p_out[x][y] (this->p_rsp_out[x][y]); 315 rsprouter->p_in[x][y] (this->p_rsp_in[x][y]); 316 } 317 } 318 319 cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d); 320 cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c); 321 cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d); 322 cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c); 323 324 rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d); 325 rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c); 326 rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d); 327 rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c); 328 329 // VCI/DSPIN WRAPPERS 330 iniwrapperd->p_clk (this->p_clk); 331 iniwrapperd->p_resetn (this->p_resetn); 332 iniwrapperd->p_vci (signal_vci_l2g_d); 333 iniwrapperd->p_dspin_out (signal_dspin_cmd_l2g_d); 334 iniwrapperd->p_dspin_in (signal_dspin_rsp_g2l_d); 335 336 tgtwrapperd->p_clk (this->p_clk); 337 tgtwrapperd->p_resetn (this->p_resetn); 338 tgtwrapperd->p_vci (signal_vci_g2l_d); 339 tgtwrapperd->p_dspin_out (signal_dspin_rsp_l2g_d); 340 tgtwrapperd->p_dspin_in (signal_dspin_cmd_g2l_d); 341 342 iniwrapperc->p_clk (this->p_clk); 343 iniwrapperc->p_resetn (this->p_resetn); 344 iniwrapperc->p_vci (signal_vci_l2g_c); 345 iniwrapperc->p_dspin_out (signal_dspin_cmd_l2g_c); 346 iniwrapperc->p_dspin_in (signal_dspin_rsp_g2l_c); 347 348 tgtwrapperc->p_clk (this->p_clk); 349 tgtwrapperc->p_resetn (this->p_resetn); 350 tgtwrapperc->p_vci (signal_vci_g2l_c); 351 tgtwrapperc->p_dspin_out (signal_dspin_rsp_l2g_c); 352 tgtwrapperc->p_dspin_in (signal_dspin_cmd_g2l_c); 353 354 // CROSSBAR direct 355 xbard->p_clk (this->p_clk); 356 xbard->p_resetn (this->p_resetn); 357 xbard->p_initiator_to_up (signal_vci_l2g_d); 358 xbard->p_target_to_up (signal_vci_g2l_d); 359 360 xbard->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc); 361 xbard->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu); 362 xbard->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma); 363 364 xbard->p_to_initiator[nprocs] (signal_vci_ini_d_mdma); 365 366 for ( size_t p=0 ; p<nprocs ; p++) 367 { 368 xbard->p_to_initiator[p] (signal_vci_ini_d_proc[p]); 369 } 370 371 if ( io == true ) 372 { 373 xbard->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty); 374 xbard->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom); 375 xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); 376 xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); 377 378 xbard->p_to_initiator[nprocs+1] (signal_vci_ini_d_bdev); 379 } 380 381 // CROSSBAR coherence 382 xbarc->p_clk (this->p_clk); 383 xbarc->p_resetn (this->p_resetn); 384 xbarc->p_initiator_to_up (signal_vci_l2g_c); 385 xbarc->p_target_to_up (signal_vci_g2l_c); 386 xbarc->p_to_initiator[nprocs] (signal_vci_ini_c_memc); 387 xbarc->p_to_target[nprocs] (signal_vci_tgt_c_memc); 388 for ( size_t p=0 ; p<nprocs ; p++) 389 { 390 xbarc->p_to_target[p] (signal_vci_tgt_c_proc[p]); 391 xbarc->p_to_initiator[p] (signal_vci_ini_c_proc[p]); 392 } 393 394 // Processors 395 for ( size_t p=0 ; p<nprocs ; p++) 396 { 397 proc[p]->p_clk (this->p_clk); 398 proc[p]->p_resetn (this->p_resetn); 399 proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); 400 proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); 401 proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); 402 proc[p]->p_irq[0] (signal_proc_it[p]); 403 for ( size_t j = 1 ; j < 6 ; j++ ) 10 TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterMmu( 11 sc_module_name insname, 12 size_t nprocs, 13 size_t x_id, 14 size_t y_id, 15 size_t cluster_id, 16 const soclib::common::MappingTable &mtd, 17 const soclib::common::MappingTable &mtc, 18 const soclib::common::MappingTable &mtx, 19 size_t x_width, 20 size_t y_width, 21 size_t tgtid_memc, 22 size_t tgtid_xicu, 23 size_t tgtid_fbuf, 24 size_t tgtid_mtty, 25 size_t tgtid_brom, 26 size_t tgtid_bdev, 27 size_t tgtid_mdma, 28 size_t memc_ways, 29 size_t memc_sets, 30 size_t l1_i_ways, 31 size_t l1_i_sets, 32 size_t l1_d_ways, 33 size_t l1_d_sets, 34 size_t xram_latency, 35 bool io, 36 size_t xfb, 37 size_t yfb, 38 char* disk_name, 39 size_t block_size, 40 const Loader &loader, 41 uint32_t frozen_cycles, 42 uint32_t debug_start_cycle, 43 bool debug_ok) 44 : soclib::caba::BaseModule(insname), 45 p_clk("clk"), 46 p_resetn("resetn"), 47 48 signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"), 49 signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"), 50 signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"), 51 signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"), 52 signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"), 53 signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"), 54 signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"), 55 signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"), 56 57 signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"), 58 signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"), 59 60 signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"), 61 signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"), 62 signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"), 63 signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"), 64 signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"), 65 signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"), 66 signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"), 67 68 signal_vci_ini_c_memc("signal_vci_ini_c_memc"), 69 signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"), 70 71 signal_vci_xram("signal_vci_xram") 72 404 73 { 405 proc[p]->p_irq[j] (signal_false); 406 } 407 } 408 409 // XICU 410 xicu->p_clk (this->p_clk); 411 xicu->p_resetn (this->p_resetn); 412 xicu->p_vci (signal_vci_tgt_d_xicu); 413 for ( size_t p=0 ; p<nprocs ; p++) 414 { 415 xicu->p_irq[p] (signal_proc_it[p]); 416 } 417 for ( size_t p=0 ; p<nprocs ; p++) 418 { 419 xicu->p_hwi[p] (signal_irq_mdma[p]); 420 } 421 for ( size_t x=nprocs ; x<4 ; x++) 422 { 423 xicu->p_hwi[x] (signal_false); 424 } 425 if ( io == true ) 426 { 427 xicu->p_hwi[4] (signal_irq_tty0); 428 xicu->p_hwi[5] (signal_irq_tty1); 429 xicu->p_hwi[6] (signal_irq_tty2); 430 xicu->p_hwi[7] (signal_irq_tty3); 431 xicu->p_hwi[8] (signal_irq_bdev); 432 } 433 434 // MEMC 435 memc->p_clk (this->p_clk); 436 memc->p_resetn (this->p_resetn); 437 memc->p_vci_ixr (signal_vci_xram); 438 memc->p_vci_tgt (signal_vci_tgt_d_memc); 439 memc->p_vci_ini (signal_vci_ini_c_memc); 440 memc->p_vci_tgt_cleanup (signal_vci_tgt_c_memc); 441 442 // XRAM 443 xram->p_clk (this->p_clk); 444 xram->p_resetn (this->p_resetn); 445 xram->p_vci (signal_vci_xram); 446 447 // CDMA 448 mdma->p_clk (this->p_clk); 449 mdma->p_resetn (this->p_resetn); 450 mdma->p_vci_target (signal_vci_tgt_d_mdma); 451 mdma->p_vci_initiator (signal_vci_ini_d_mdma); 452 for (size_t p=0 ; p<nprocs ; p++) 453 { 454 mdma->p_irq[p] (signal_irq_mdma[p]); 455 } 456 457 // Components in IO cluster 458 459 if ( io == true ) 460 { 461 // BDEV 462 bdev->p_clk (this->p_clk); 463 bdev->p_resetn (this->p_resetn); 464 bdev->p_irq (signal_irq_bdev); 465 bdev->p_vci_target (signal_vci_tgt_d_bdev); 466 bdev->p_vci_initiator (signal_vci_ini_d_bdev); 467 468 // FBUF 469 fbuf->p_clk (this->p_clk); 470 fbuf->p_resetn (this->p_resetn); 471 fbuf->p_vci (signal_vci_tgt_d_fbuf); 472 473 // BROM 474 brom->p_clk (this->p_clk); 475 brom->p_resetn (this->p_resetn); 476 brom->p_vci (signal_vci_tgt_d_brom); 477 478 // MTTY 479 mtty->p_clk (this->p_clk); 480 mtty->p_resetn (this->p_resetn); 481 mtty->p_vci (signal_vci_tgt_d_mtty); 482 mtty->p_irq[0] (signal_irq_tty0); 483 mtty->p_irq[1] (signal_irq_tty1); 484 mtty->p_irq[2] (signal_irq_tty2); 485 mtty->p_irq[3] (signal_irq_tty3); 486 } 487 } // end constructor 74 // Vectors of ports definition 75 76 p_cmd_in = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4); 77 p_cmd_out = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4); 78 p_rsp_in = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4); 79 p_rsp_out = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4); 80 81 // Components definition 82 83 // on direct network : local srcid[proc] in [0...nprocs-1] 84 // on direct network : local srcid[mdma] = nprocs 85 // on direct network : local srcid[bdev] = nprocs + 1 86 87 // on coherence network : local srcid[proc] in [0...nprocs-1] 88 // on coherence network : local srcid[memc] = nprocs 89 90 std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; 91 92 for (size_t p = 0; p < nprocs; p++){ 93 std::ostringstream sproc; 94 sproc << "proc_" << x_id << "_" << y_id << "_" << p; 95 proc[p] = new VciCcVCacheWrapperV4<vci_param, iss_t>( 96 sproc.str().c_str(), 97 cluster_id*nprocs + p, 98 mtd, // Mapping Table Direct 99 mtc, // Mapping Table Coherence 100 IntTab(cluster_id,p), // SRCID_D 101 IntTab(cluster_id,p), // SRCID_C 102 IntTab(cluster_id,p), // TGTID_C 103 8, // ITLB ways 104 8, // ITLB sets 105 8, // DTLB ways 106 8, // DTLB sets 107 l1_i_ways,l1_i_sets,16, // ICACHE size 108 l1_d_ways,l1_d_sets,16, // DCACHE size 109 4, // WBUF width 110 4, // WBUF depth 111 x_width, // X Width 112 y_width, // Y Width 113 nprocs, // Memory Cache Local Id (coherence) 114 frozen_cycles, // max frozen cycles 115 debug_start_cycle, 116 debug_ok); 117 } 118 119 std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; 120 121 std::ostringstream smemc; 122 smemc << "memc_" << x_id << "_" << y_id; 123 memc = new VciMemCacheV4<vci_param>( 124 smemc.str().c_str(), 125 mtd, mtc, mtx, 126 IntTab(cluster_id), // SRCID_X 127 IntTab(cluster_id, nprocs), // SRCID_C 128 IntTab(cluster_id, tgtid_memc), // TGTID_D 129 IntTab(cluster_id, nprocs), // TGTID_C 130 memc_ways, memc_sets, 16, // CACHE SIZE 131 4096, // HEAP SIZE 132 8, // TRANSACTION TABLE DEPTH 133 8, // UPDATE TABLE DEPTH 134 debug_start_cycle, 135 debug_ok); 136 137 138 std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; 139 140 std::ostringstream sxram; 141 sxram << "xram_" << x_id << "_" << y_id; 142 xram = new VciSimpleRam<vci_param>( 143 sxram.str().c_str(), 144 IntTab(cluster_id), 145 mtx, 146 loader, 147 xram_latency); 148 149 std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; 150 151 size_t nhwi = 4; // always 4 (or 9) ports, even if 152 if (io){ 153 nhwi = 9; // there if less than 4 processors 154 } 155 std::ostringstream sicu; 156 sicu << "xicu_" << x_id << "_" << y_id; 157 xicu = new VciXicu<vci_param>( 158 sicu.str().c_str(), 159 mtd, // mapping table 160 IntTab(cluster_id, tgtid_xicu), // TGTID_D 161 0, // number of timer IRQs 162 nhwi, // number of hard IRQs 163 0, // number of soft IRQs 164 nprocs); // number of output IRQs 165 166 std::cout << " - building dma_" << x_id << "_" << y_id << std::endl; 167 168 // dma multi-canaux 169 std::ostringstream sdma; 170 sdma << "dma_" << x_id << "_" << y_id; 171 mdma = new VciMultiDma<vci_param>( 172 sdma.str().c_str(), 173 mtd, 174 IntTab(cluster_id, nprocs), // SRCID 175 IntTab(cluster_id, tgtid_mdma), // TGTID 176 64, // burst size 177 nprocs); // number of IRQs 178 179 std::cout << " - building xbard_" << x_id << "_" << y_id << std::endl; 180 181 // direct local crossbar 182 size_t nb_direct_initiators = nprocs + 1; 183 size_t nb_direct_targets = 3; 184 if (io){ 185 nb_direct_initiators = nprocs + 2; 186 nb_direct_targets = 7; 187 } 188 std::ostringstream sd; 189 sd << "xbard_" << x_id << "_" << y_id; 190 xbard = new VciLocalCrossbar<vci_param>( 191 sd.str().c_str(), 192 mtd, 193 IntTab(cluster_id), // cluster initiator index 194 IntTab(cluster_id), // cluster target index 195 nb_direct_initiators, // number of initiators 196 nb_direct_targets); // number of targets 197 198 std::cout << " - building xbarc_" << x_id << "_" << y_id << std::endl; 199 200 // coherence local crossbar 201 std::ostringstream sc; 202 sc << "xbarc_" << x_id << "_" << y_id; 203 xbarc = new VciLocalCrossbar<vci_param>( 204 sc.str().c_str(), 205 mtc, 206 IntTab(cluster_id), // cluster initiator index 207 IntTab(cluster_id), // cluster target index 208 nprocs + 1, // number of initiators 209 nprocs + 1); // number of targets 210 211 std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; 212 213 // direct initiator wrapper 214 std::ostringstream wid; 215 wid << "iniwrapperd_" << x_id << "_" << y_id; 216 iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 217 wid.str().c_str(), 218 4, // cmd fifo depth 219 4); // rsp fifo depth 220 221 // direct target wrapper 222 std::ostringstream wtd; 223 wtd << "tgtwrapperd_" << x_id << "_" << y_id; 224 tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 225 wtd.str().c_str(), 226 4, // cmd fifo depth 227 4); // rsp fifo depth 228 229 // coherence initiator wrapper 230 std::ostringstream wic; 231 wic << "iniwrapperc_" << x_id << "_" << y_id; 232 iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 233 wic.str().c_str(), 234 4, // cmd fifo depth 235 4); // rsp fifo depth 236 237 // coherence target wrapper 238 std::ostringstream wtc; 239 wtc << "tgtwrapperc_" << x_id << "_" << y_id; 240 tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 241 wtc.str().c_str(), 242 4, // cmd fifo depth 243 4); // rsp fifo depth 244 245 std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl; 246 247 // CMD router 248 std::ostringstream scmd; 249 scmd << "cmdrouter_" << x_id << "_" << y_id; 250 cmdrouter = new VirtualDspinRouter<cmd_width>( 251 scmd.str().c_str(), 252 x_id,y_id, // coordinate in the mesh 253 x_width, y_width, // x & y fields width 254 4,4); // input & output fifo depths 255 256 std::cout << " - building rsprouter_" << x_id << "_" << y_id << std::endl; 257 258 // RSP router 259 std::ostringstream srsp; 260 srsp << "rsprouter_" << x_id << "_" << y_id; 261 rsprouter = new VirtualDspinRouter<rsp_width>( 262 srsp.str().c_str(), 263 x_id,y_id, // coordinates in mesh 264 x_width, y_width, // x & y fields width 265 4,4); // input & output fifo depths 266 267 // IO cluster components 268 if (io){ 269 brom = new VciSimpleRam<vci_param>( 270 "brom", 271 IntTab(cluster_id, tgtid_brom), 272 mtd, 273 loader); 274 275 fbuf = new VciFrameBuffer<vci_param>( 276 "fbuf", 277 IntTab(cluster_id, tgtid_fbuf), 278 mtd, 279 xfb, yfb); 280 281 bdev = new VciBlockDeviceTsarV4<vci_param>( 282 "bdev", 283 mtd, 284 IntTab(cluster_id, nprocs+1), 285 IntTab(cluster_id, tgtid_bdev), 286 disk_name, 287 block_size); 288 289 mtty = new VciMultiTty<vci_param>( 290 "mtty", 291 IntTab(cluster_id, tgtid_mtty), 292 mtd, 293 "tty0", "tty1", "tty2", "tty3", NULL); 294 } 295 296 std::cout << " - all components constructed" << std::endl; 297 298 //////////////////////////////////// 299 // Connections are defined here 300 //////////////////////////////////// 301 302 // CMDROUTER and RSPROUTER 303 cmdrouter->p_clk (this->p_clk); 304 cmdrouter->p_resetn (this->p_resetn); 305 rsprouter->p_clk (this->p_clk); 306 rsprouter->p_resetn (this->p_resetn); 307 for (int x = 0; x < 2; x++){ 308 for(int y = 0; y < 4; y++){ 309 cmdrouter->p_out[x][y] (this->p_cmd_out[x][y]); 310 cmdrouter->p_in[x][y] (this->p_cmd_in[x][y]); 311 rsprouter->p_out[x][y] (this->p_rsp_out[x][y]); 312 rsprouter->p_in[x][y] (this->p_rsp_in[x][y]); 313 } 314 } 315 316 cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d); 317 cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c); 318 cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d); 319 cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c); 320 321 rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d); 322 rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c); 323 rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d); 324 rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c); 325 326 // VCI/DSPIN WRAPPERS 327 iniwrapperd->p_clk (this->p_clk); 328 iniwrapperd->p_resetn (this->p_resetn); 329 iniwrapperd->p_vci (signal_vci_l2g_d); 330 iniwrapperd->p_dspin_out (signal_dspin_cmd_l2g_d); 331 iniwrapperd->p_dspin_in (signal_dspin_rsp_g2l_d); 332 333 tgtwrapperd->p_clk (this->p_clk); 334 tgtwrapperd->p_resetn (this->p_resetn); 335 tgtwrapperd->p_vci (signal_vci_g2l_d); 336 tgtwrapperd->p_dspin_out (signal_dspin_rsp_l2g_d); 337 tgtwrapperd->p_dspin_in (signal_dspin_cmd_g2l_d); 338 339 iniwrapperc->p_clk (this->p_clk); 340 iniwrapperc->p_resetn (this->p_resetn); 341 iniwrapperc->p_vci (signal_vci_l2g_c); 342 iniwrapperc->p_dspin_out (signal_dspin_cmd_l2g_c); 343 iniwrapperc->p_dspin_in (signal_dspin_rsp_g2l_c); 344 345 tgtwrapperc->p_clk (this->p_clk); 346 tgtwrapperc->p_resetn (this->p_resetn); 347 tgtwrapperc->p_vci (signal_vci_g2l_c); 348 tgtwrapperc->p_dspin_out (signal_dspin_rsp_l2g_c); 349 tgtwrapperc->p_dspin_in (signal_dspin_cmd_g2l_c); 350 351 // CROSSBAR direct 352 xbard->p_clk (this->p_clk); 353 xbard->p_resetn (this->p_resetn); 354 xbard->p_initiator_to_up (signal_vci_l2g_d); 355 xbard->p_target_to_up (signal_vci_g2l_d); 356 357 xbard->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc); 358 xbard->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu); 359 xbard->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma); 360 361 xbard->p_to_initiator[nprocs] (signal_vci_ini_d_mdma); 362 363 for (size_t p = 0; p < nprocs; p++){ 364 xbard->p_to_initiator[p] (signal_vci_ini_d_proc[p]); 365 } 366 367 if (io){ 368 xbard->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty); 369 xbard->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom); 370 xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); 371 xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); 372 373 xbard->p_to_initiator[nprocs+1] (signal_vci_ini_d_bdev); 374 } 375 376 // CROSSBAR coherence 377 xbarc->p_clk (this->p_clk); 378 xbarc->p_resetn (this->p_resetn); 379 xbarc->p_initiator_to_up (signal_vci_l2g_c); 380 xbarc->p_target_to_up (signal_vci_g2l_c); 381 xbarc->p_to_initiator[nprocs] (signal_vci_ini_c_memc); 382 xbarc->p_to_target[nprocs] (signal_vci_tgt_c_memc); 383 for (size_t p = 0; p < nprocs; p++) { 384 xbarc->p_to_target[p] (signal_vci_tgt_c_proc[p]); 385 xbarc->p_to_initiator[p] (signal_vci_ini_c_proc[p]); 386 } 387 388 // Processors 389 for (size_t p = 0; p < nprocs; p++){ 390 proc[p]->p_clk (this->p_clk); 391 proc[p]->p_resetn (this->p_resetn); 392 proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); 393 proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); 394 proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); 395 proc[p]->p_irq[0] (signal_proc_it[p]); 396 for ( size_t j = 1 ; j < 6 ; j++){ 397 proc[p]->p_irq[j] (signal_false); 398 } 399 } 400 401 // XICU 402 xicu->p_clk (this->p_clk); 403 xicu->p_resetn (this->p_resetn); 404 xicu->p_vci (signal_vci_tgt_d_xicu); 405 for (size_t p = 0; p < nprocs; p++){ 406 xicu->p_irq[p] (signal_proc_it[p]); 407 } 408 for (size_t p = 0; p < nprocs; p++){ 409 xicu->p_hwi[p] (signal_irq_mdma[p]); 410 } 411 for (size_t x = nprocs; x < 4; x++){ 412 xicu->p_hwi[x] (signal_false); 413 } 414 415 if (io){ 416 xicu->p_hwi[4] (signal_irq_tty0); 417 xicu->p_hwi[5] (signal_irq_tty1); 418 xicu->p_hwi[6] (signal_irq_tty2); 419 xicu->p_hwi[7] (signal_irq_tty3); 420 421 xicu->p_hwi[8] (signal_irq_bdev); 422 } 423 424 // MEMC 425 memc->p_clk (this->p_clk); 426 memc->p_resetn (this->p_resetn); 427 memc->p_vci_ixr (signal_vci_xram); 428 memc->p_vci_tgt (signal_vci_tgt_d_memc); 429 memc->p_vci_ini (signal_vci_ini_c_memc); 430 memc->p_vci_tgt_cleanup (signal_vci_tgt_c_memc); 431 432 // XRAM 433 xram->p_clk (this->p_clk); 434 xram->p_resetn (this->p_resetn); 435 xram->p_vci (signal_vci_xram); 436 437 // CDMA 438 mdma->p_clk (this->p_clk); 439 mdma->p_resetn (this->p_resetn); 440 mdma->p_vci_target (signal_vci_tgt_d_mdma); 441 mdma->p_vci_initiator (signal_vci_ini_d_mdma); 442 for (size_t p = 0; p < nprocs; p++){ 443 mdma->p_irq[p] (signal_irq_mdma[p]); 444 } 445 446 // Components in IO cluster 447 448 if (io){ 449 // BDEV 450 bdev->p_clk (this->p_clk); 451 bdev->p_resetn (this->p_resetn); 452 bdev->p_irq (signal_irq_bdev); 453 bdev->p_vci_target (signal_vci_tgt_d_bdev); 454 bdev->p_vci_initiator (signal_vci_ini_d_bdev); 455 456 // FBUF 457 fbuf->p_clk (this->p_clk); 458 fbuf->p_resetn (this->p_resetn); 459 fbuf->p_vci (signal_vci_tgt_d_fbuf); 460 461 // BROM 462 brom->p_clk (this->p_clk); 463 brom->p_resetn (this->p_resetn); 464 brom->p_vci (signal_vci_tgt_d_brom); 465 466 // MTTY 467 mtty->p_clk (this->p_clk); 468 mtty->p_resetn (this->p_resetn); 469 mtty->p_vci (signal_vci_tgt_d_mtty); 470 mtty->p_irq[0] (signal_irq_tty0); 471 mtty->p_irq[1] (signal_irq_tty1); 472 mtty->p_irq[2] (signal_irq_tty2); 473 mtty->p_irq[3] (signal_irq_tty3); 474 } 475 } // end constructor 488 476 489 477 /////////////////////////////////////////////////////////////////////////// … … 491 479 /////////////////////////////////////////////////////////////////////////// 492 480 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> 493 TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterMmu() {} 494 495 }} 481 TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterMmu() {} 482 483 } 484 } 485 486 487 // Local Variables: 488 // tab-width: 3 489 // c-basic-offset: 3 490 // c-file-offsets:((innamespace . 0)(inline-open . 0)) 491 // indent-tabs-mode: nil 492 // End: 493 494 // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 495 496 497
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