- Timestamp:
- Aug 16, 2012, 7:36:04 PM (12 years ago)
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trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h
r234 r255 6 6 // This program is released under the GNU public license 7 7 ////////////////////////////////////////////////////////////////////////////// 8 // This file define a TSAR cluster architecture with virtual memory:9 // - It uses the virtual_dspin_router as distributed global interconnect10 // - It uses the vci_local_crossbar as local interconnect11 // - It uses the vci_cc_vcache_wrapper_v412 // - It uses the vci_mem_cache_v413 // - It contains a private RAM with a variable latency to emulate the L3 cache14 // - It can contains 1, 2 or 4 processors15 // - Each processor has a private dma channel (vci_multi_dma)16 // - It uses the vci_xicu interrupt controller17 // - The peripherals MTTY, BDEV, FBUF, and the boot BROM are in the cluster18 // containing address 0xBFC00000.19 // - The Multi-TTY component controls 4 terminals.20 // - The nprocs dma irqs are connected to IRQ_IN[0]...IRQ_IN[3]21 // - The four tty irqs are connected to IRQ_IN[4]...IRQ_IN[7]22 // - The bdev irq is connected to IRQ_IN[8]23 //////////////////////////////////////////////////////////////////////////////////24 8 25 9 #ifndef SOCLIB_CABA_TSAR_CLUSTER_V4_MMU_H … … 62 46 63 47 // Ports 64 65 48 sc_in<bool> p_clk; 49 sc_in<bool> p_resetn; 66 50 soclib::caba::DspinOutput<cmd_width> **p_cmd_out; 67 51 soclib::caba::DspinInput<cmd_width> **p_cmd_in; 68 soclib::caba::DspinOutput<rsp_width>**p_rsp_out;69 soclib::caba::DspinInput<rsp_width>**p_rsp_in;52 soclib::caba::DspinOutput<rsp_width> **p_rsp_out; 53 soclib::caba::DspinInput<rsp_width> **p_rsp_in; 70 54 71 // interrupt signals 72 sc_signal<bool> signal_false; 73 sc_signal<bool> signal_proc_it[4]; 74 sc_signal<bool> signal_irq_mdma[4]; 75 sc_signal<bool> signal_irq_tty0; 76 sc_signal<bool> signal_irq_tty1; 77 sc_signal<bool> signal_irq_tty2; 78 sc_signal<bool> signal_irq_tty3; 55 // interrupt signals 56 sc_signal<bool> signal_false; 57 sc_signal<bool> signal_proc_it[8]; 58 sc_signal<bool> signal_irq_mdma[8]; 59 sc_signal<bool> signal_irq_mtty[23]; 79 60 sc_signal<bool> signal_irq_bdev; 80 61 … … 117 98 VciSignals<vci_param> signal_vci_xram; 118 99 119 100 // Components 120 101 121 VciCcVCacheWrapperV4<vci_param, iss_t>* proc[4];122 123 124 VciLocalCrossbar<vci_param>*xbard;125 VciLocalCrossbar<vci_param>*xbarc;126 VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*tgtwrapperd;127 VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*iniwrapperd;128 VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*tgtwrapperc;129 VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*iniwrapperc;130 VirtualDspinRouter<cmd_width>*cmdrouter;131 132 VciSimpleRam<vci_param>*brom;133 VciMultiTty<vci_param>*mtty;134 VciFrameBuffer<vci_param>*fbuf;135 VciBlockDeviceTsarV4<vci_param>*bdev;136 VciMultiDma<vci_param>*mdma;137 VciSimpleRam<vci_param>*xram;102 VciCcVCacheWrapperV4<vci_param, iss_t>* proc[8]; 103 VciMemCacheV4<vci_param>* memc; 104 VciXicu<vci_param>* xicu; 105 VciLocalCrossbar<vci_param>* xbard; 106 VciLocalCrossbar<vci_param>* xbarc; 107 VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>* tgtwrapperd; 108 VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* iniwrapperd; 109 VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>* tgtwrapperc; 110 VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* iniwrapperc; 111 VirtualDspinRouter<cmd_width>* cmdrouter; 112 VirtualDspinRouter<rsp_width>* rsprouter; 113 VciSimpleRam<vci_param>* brom; 114 VciMultiTty<vci_param>* mtty; 115 VciFrameBuffer<vci_param>* fbuf; 116 VciBlockDeviceTsarV4<vci_param>* bdev; 117 VciMultiDma<vci_param>* mdma; 118 VciSimpleRam<vci_param>* xram; 138 119 139 TsarV4ClusterMmu(sc_module_name insname, 140 size_t nprocs, // number of processors 141 size_t n_x, // x coordinate 142 size_t n_y, // y coordinate 143 size_t n_cluster, // y + ymax*x 144 const soclib::common::MappingTable &mtd, // direct mapping table 145 const soclib::common::MappingTable &mtc, // coherence mapping table 146 const soclib::common::MappingTable &mtx, // xram mapping table 147 size_t x_width, // x field number of bits 148 size_t y_width, // y field number of bits 149 size_t tgtid_memc, 150 size_t tgtid_xicu, 151 size_t tgtid_fbuf, 152 size_t tgtid_mtty, 153 size_t tgtid_brom, 154 size_t tgtid_bdev, 155 size_t tgtid_mdma, 156 size_t memc_ways, // number of ways for MEMC 157 size_t memc_sets, // number of sets for MEMC 158 size_t l1_i_ways, // number of ways for L1 ICACHE 159 size_t l1_i_sets, // number of sets for L1 ICACHE 160 size_t l1_d_ways, // number of ways for L1 DCACHE 161 size_t l1_d_sets, // number of sets for L1 DCACHE 162 size_t xram_latency, // external ram latency 163 bool io, // I/O cluster if true 164 size_t xfb, // frame buffer pixels 165 size_t yfb, // frame buffer lines 166 char* disk_name, // virtual disk name for BDEV 167 size_t block_size, // block size for BDEV 168 const Loader &loader, // loader for BROM 169 uint32_t frozen_cycles, // max frozen cycles 170 uint32_t start_debug_cycle, 171 bool debug_ok); 120 TsarV4ClusterMmu(sc_module_name insname, 121 size_t nb_procs, // number of processors 122 size_t nb_ttys, // number of TTY terminals 123 size_t nb_dmas, // number of DMA channels 124 size_t x, // x coordinate 125 size_t y, // y coordinate 126 size_t cluster, // y + ymax*x 127 const soclib::common::MappingTable &mtd, // direct mapping table 128 const soclib::common::MappingTable &mtc, // coherence mapping table 129 const soclib::common::MappingTable &mtx, // xram mapping table 130 size_t x_width, // x field number of bits 131 size_t y_width, // y field number of bits 132 size_t tgtid_memc, 133 size_t tgtid_xicu, 134 size_t tgtid_fbuf, 135 size_t tgtid_mtty, 136 size_t tgtid_brom, 137 size_t tgtid_bdev, 138 size_t tgtid_mdma, 139 size_t memc_ways, 140 size_t memc_sets, 141 size_t l1_i_ways, 142 size_t l1_i_sets, 143 size_t l1_d_ways, 144 size_t l1_d_sets, 145 size_t xram_latency, // external ram latency 146 bool io, // I/O cluster if true 147 size_t xfb, // frame buffer pixels 148 size_t yfb, // frame buffer lines 149 char* disk_name, // virtual disk name for BDEV 150 size_t block_size, // block size for BDEV 151 const Loader &loader, // loader for BROM 152 uint32_t frozen_cycles, // max frozen cycles 153 uint32_t start_debug_cycle, 154 bool memc_debug_ok, 155 bool proc_debug_ok); 172 156 173 157 ~TsarV4ClusterMmu();
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