Changeset 291 for trunk/modules/vci_mem_cache_v4/caba/source/include

Timestamp:

Jan 28, 2013, 1:59:32 PM (11 years ago)

Author:

joannou

Message:

Introducing new generic_llsc_local_table and generic_llsc_global_table components :
These two tables implement the new scalable LL/SC mechanism for TSAR.

• generic_llsc_local_table, integrated in the vci_cc_vache_wrapper_v4 component. The table is accessed by the DCACHE_FSM. A two step registration (LL cmd/ LL rsp) sets a signature allocated by the global table for the pending LL/SC operation. An SC operation consumes the registration.
• generic_llsc_global_table, integrated in the vci_mem_cache_v4 component. The table is accessed by the READ_FSM, WRITE_FSM, CAS_FSM, when accessing the directory. It generates a signature for LL registrations and performs SC operation by checking registration's valididty with that signature. SW operations simply invalidate a registrations.

N.B. :

• The sizes of the tables are parameters, and are NOT a function of the architecture's size (scalable mechanism).
• The LL are handled by the MEMCACHE in the READ_FSM.
• The SC are handled by the MEMCACHE in the WRITE_FSM, and are no longer CAS emulated. CAS operation is now only performed by hardware mechanisms.
• An extra field is added to the xram transaction table to save a pending LL's signature.

Location:

trunk/modules/vci_mem_cache_v4/caba/source/include

Files:

• vci_mem_cache_v4.h (modified) (6 diffs)
• xram_transaction_v4.h (modified) (5 diffs)

trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h

@@ -54 +54 @@
 #include "mapping_table.h"
 #include "int_tab.h"
+#include "generic_llsc_global_table.h"
 #include "mem_cache_directory_v4.h"
 #include "xram_transaction_v4.h"
@@ -422 +423 @@
       CacheData       m_cache_data;       // data array[set][way][word]
       HeapDirectory   m_heap;             // heap for copies
+      GenericLLSCGlobalTable
+      <
+        32  ,   // desired number of slots
+        4096,   // number of processors in the system
+        8000,   // registratioçn life span (in # of LL operations)
+        typename vci_param::fast_addr_t // address type
+      >
+      m_llsc_table;       // ll/sc global registration table
 
       // adress masks
@@ -491 +500 @@
       sc_signal<size_t>   r_read_next_ptr;   // Next entry to point to
       sc_signal<bool>     r_read_last_free;  // Last free entry
+      sc_signal<typename vci_param::fast_addr_t>
+                          r_read_ll_key;     // LL key returned by the llsc_global_table
 
       // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
@@ -505 +516 @@
       sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
       sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
+      sc_signal<typename vci_param::fast_addr_t>
+                          r_read_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
 
       ///////////////////////////////////////////////////////////////
@@ -533 +546 @@
       sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
       sc_signal<size_t>   r_write_upt_index;  // index in Update Table
+      sc_signal<bool>     r_write_sc_fail;    // sc command failed
+      sc_signal<bool>     r_write_pending_sc; // sc command pending in WRITE fsm
 
       // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
-      sc_signal<bool>     r_write_to_tgt_rsp_req;   // valid request
-      sc_signal<size_t>   r_write_to_tgt_rsp_srcid; // transaction srcid
-      sc_signal<size_t>   r_write_to_tgt_rsp_trdid; // transaction trdid
-      sc_signal<size_t>   r_write_to_tgt_rsp_pktid; // transaction pktid
+      sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
+      sc_signal<size_t>   r_write_to_tgt_rsp_srcid;   // transaction srcid
+      sc_signal<size_t>   r_write_to_tgt_rsp_trdid;   // transaction trdid
+      sc_signal<size_t>   r_write_to_tgt_rsp_pktid;   // transaction pktid
+      sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
 
       // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
@@ -721 +737 @@
       sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
       sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
+      sc_signal<typename vci_param::fast_addr_t>
+                          r_xram_rsp_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
 
       // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)

trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h

@@ -32 +32 @@
     std::vector<be_t>   wdata_be;       // be for each data in the write buffer
     bool                rerror;         // error returned by xram
+    data_t              ll_key;         // LL key returned by the llsc_global_table
 
     /////////////////////////////////////////////////////////////////////
@@ -127 +128 @@
         wdata.assign(source.wdata.begin(),source.wdata.end());  
         rerror      = source.rerror;
+        ll_key      = source.ll_key;
     }
 
@@ -325 +327 @@
     // - data : the data to write (in case of write)
     // - data_be : the mask of the data to write (in case of write)
+    // - ll_key  : the ll key (if any) returned by the llsc_global_table
     /////////////////////////////////////////////////////////////////////
     void set(const size_t index,
@@ -336 +339 @@
             const size_t word_index,
             const std::vector<be_t> &data_be,
-            const std::vector<data_t> &data) 
+            const std::vector<data_t> &data, 
+            const data_t ll_key = 0) 
     {
         assert( (index < size_tab) 
@@ -354 +358 @@
         tab[index].read_length      = read_length;
         tab[index].word_index       = word_index;
+        tab[index].ll_key           = ll_key;
         for(size_t i=0; i<tab[index].wdata.size(); i++) 
         {