Ignore:
Timestamp:
Jun 16, 2010, 12:24:08 PM (14 years ago)
Author:
guthmull
Message:

Fix a bug in SC, add start cycle debug

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp

    r53 r55  
    3232namespace caba {
    3333
    34 #define SOCLIB_MODULE_DEBUG
     34//#define SOCLIB_MODULE_DEBUG
     35#define DEBUG_START_CYCLE 33069000
    3536#ifdef SOCLIB_MODULE_DEBUG
    3637namespace {
     
    611612
    612613#ifdef SOCLIB_MODULE_DEBUG
    613 std::cout << name() << "cycle = " << m_cpt_total_cycles 
     614if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){
     615std::cout << name() << " cycle = " << std::dec << m_cpt_total_cycles 
    614616          << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
    615617          << " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm]
     
    619621          << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm]
    620622          << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl;
     623}
    621624#endif
    622625
     
    632635
    633636#ifdef SOCLIB_MODULE_DEBUG
     637if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){
    634638    std::cout << name() << " Instruction Request: " << ireq << std::endl;
    635639    std::cout << name() << " Data Request: " << dreq << std::endl;
     640}
    636641#endif
    637642
     
    20532058
    20542059#ifdef SOCLIB_MODULE_DEBUG
     2060if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){
    20552061    std::cout << name() << " Instruction Response: " << irsp << std::endl;
     2062}
    20562063#endif
    20572064
     
    43974404            if(dreq.type == iss_t::DATA_SC)
    43984405            {
     4406                if(r_dcache_cleanup_req) break;
    43994407                size_t way = 0;
    44004408                size_t set = 0;
    44014409                // Simulate an invalidate request
    4402                 r_dcache_cleanup_req = r_dcache.inval(r_dcache_paddr_save, &way, &set);
     4410                r_dcache_cleanup_req = r_dcache.inval(r_dcache_paddr_save, &way, &set);        //   !!!!!!!!!
    44034411                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2);
    44044412                m_cpt_cc_cleanup_data++;
     
    49935001
    49945002#ifdef SOCLIB_MODULE_DEBUG
     5003if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){
    49955004    std::cout << name() << " Data Response: " << drsp << std::endl;
     5005}
    49965006#endif
    49975007
     
    59095919
    59105920#ifdef SOCLIB_MODULE_DEBUG
     5921if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){
    59115922   std::cout << name()
    5912              << "Moore R/W:" << std::hex
     5923             << " Moore R/W:" << std::hex
    59135924             << " p_vci_ini_rw.cmdval: " << p_vci_ini_rw.cmdval
    59145925             << " p_vci_ini_rw.address: " << p_vci_ini_rw.address
     
    59195930
    59205931   std::cout << name()
    5921              << "Moore TGT:" << std::hex
     5932             << " Moore TGT:" << std::hex
    59225933             << " p_vci_tgt.rspval: " << p_vci_tgt.rspval
    59235934             << std::endl;
    59245935
    59255936   std::cout << name()
    5926              << "Moore Cleanup:" << std::hex
     5937             << " Moore Cleanup:" << std::hex
    59275938             << " p_vci_ini_c.cmdval: " << p_vci_ini_c.cmdval
    59285939             << " p_vci_ini_c.address: " << p_vci_ini_c.address
     
    59315942             << " p_vci_ini_c.eop: " << p_vci_ini_c.eop
    59325943             << std::endl;
    5933 
     5944}
    59345945#endif
    59355946}
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