Ignore:
Timestamp:
Nov 17, 2013, 4:02:23 PM (11 years ago)
Author:
bouyer
Message:

Make sure MOSI data changes on SPI clock falling edge,
not one system clock cycle later. With a dividor of 0, this would
delay the MOSI change to the SPI clock rising edge.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_spi/caba/source/src/vci_spi.cpp

    r565 r575  
    633633        break;
    634634    case S_XMIT:
     635      {
     636        bool s_clk_sample = r_spi_clk ^ r_ctrl_cpha;
    635637        p_spi_clk = r_spi_clk ^ r_ctrl_cpol;
    636         p_spi_mosi = r_spi_out;
    637         break;
     638        if (s_clk_sample == 0) {
     639            // clock low: get data directly from shift register
     640            // as r_spi_out may be delayed by one clock cycle
     641            p_spi_mosi = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL;
     642        } else {
     643            // clock high: get data from saved value, as the shift register
     644            // may have changed
     645            p_spi_mosi = r_spi_out;
     646        }
     647        break;
     648      }
    638649    }
    639650
Note: See TracChangeset for help on using the changeset viewer.