Changeset 594


Ignore:
Timestamp:
Dec 5, 2013, 7:39:57 PM (9 years ago)
Author:
bouyer
Message:

In VHDL, as r_dma_count is shared between 2 FSMs we can't update it in
the same cycle as going back idle. So spend an extra cycle when resetting it
to 0.

Location:
trunk/modules/vci_spi/caba/source
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_spi/caba/source/include/vci_spi.h

    r579 r594  
    122122    M_READ_CMD          = 2,
    123123    M_READ_RSP          = 3,
    124     M_WRITE_WAIT        = 4,
    125     M_WRITE_CMD         = 5,
    126     M_WRITE_RSP         = 6,
    127     M_WRITE_END         = 7
     124    M_READ_END          = 4,
     125    M_WRITE_WAIT        = 5,
     126    M_WRITE_CMD         = 6,
     127    M_WRITE_RSP         = 7,
     128    M_WRITE_END         = 8
    128129    };
    129130
  • trunk/modules/vci_spi/caba/source/src/vci_spi.cpp

    r592 r594  
    417417                r_dma_count = 0;
    418418                r_dma_error = true;
    419                 r_initiator_fsm = M_IDLE;
     419                r_initiator_fsm = M_READ_END;
    420420#ifdef SOCLIB_MODULE_DEBUG
    421421                std::cout << "vci_bd M_READ_ERROR" << std::endl;
     
    425425            {
    426426                r_dma_count = 0;
    427                 r_initiator_fsm = M_IDLE;
     427                r_initiator_fsm = M_READ_END;
    428428                r_dma_error = false;
    429429#ifdef SOCLIB_MODULE_DEBUG
     
    439439        break;
    440440    }
     441    ///////////////////
     442    case M_READ_END:
     443        // wait one cycle because VHDL can't update r_dma_count
     444        // in the same cycle as going back IDLE
     445        r_initiator_fsm = M_IDLE;
     446        break;
    441447    ///////////////////
    442448    case M_WRITE_WAIT:  // wait for the FIFO to be empty
     
    733739                "M_READ_CMD",
    734740                "M_READ_RSP",
     741                "M_READ_END",
    735742
    736743                "M_WRITE_WAIT",
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