Ignore:
Timestamp:
Jun 23, 2014, 3:43:33 PM (10 years ago)
Author:
cfuguet
Message:

vci_io_bridge:

  • erasing XICU base and size registers. There registers are not used anymore because routing through INT network is done by using special attribute of IOX mapping segments.
  • bugfix: adding config_cmd_to_config_rsp registers for transmitting SRCID, TRDID and PKTID. Before, r_config_cmd registers were used for transmitting these informations to CONFIG_RSP FSM, but these registers can be simultaneously modified by the CONFIG_CMD FSM.
  • adding a masking table for SRCID in the DMA_CMD FSM. This masking table is used to replace SRCID global bits of commands coming from external DMA peripherals by the IOB cluster global bits. This way, the responses for DMA peripheral commands, will come through the same IOB. In the same manner, the DMA_RSP FSM masks the global bits of RSRCID before sending to DMA external peripherals.
  • introduction of an IO transaction table in the CONFIG_CMD FSM. This table is used to store SRCID and TRDID of incoming commands from the INT network. The SRCID and TRDID of these commands is replaced by the IOB IOX SRCID and table index respectively. The goal is to force that responses to these commands come back trough the same IOB. The CONFIG_RSP FSM restores both SRCID and TRDID by reading the table.
File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_io_bridge/caba/metadata/vci_io_bridge.sd

    r434 r715  
    55
    66Module('caba:vci_io_bridge',
    7         classname = 'soclib::caba::VciIoBridge',
     7    classname = 'soclib::caba::VciIoBridge',
    88
    9         tmpl_parameters = [
     9    tmpl_parameters = [
    1010        parameter.Module('vci_param_int',
    1111                          default = 'caba:vci_param',
    1212                          cell_size = parameter.Reference('iob_cell_size_int')),
    13             parameter.Module('vci_param_ext',
     13        parameter.Module('vci_param_ext',
    1414                          default = 'caba:vci_param',
    1515                          cell_size = parameter.Reference('iob_cell_size_ext')),
    1616    ],
    1717
    18         header_files =         [
     18    header_files =         [
    1919        '../source/include/vci_io_bridge.h',
    20             '../source/include/transaction_tab_io.h'
     20        '../source/include/transaction_tab_io.h'
    2121    ],
    2222
    23         implementation_files = [ '../source/src/vci_io_bridge.cpp' ],
     23    implementation_files = [ '../source/src/vci_io_bridge.cpp' ],
    2424
    25         uses = [ Uses('caba:base_module'),
    26             Uses('common:mapping_table'),
    27             Uses('caba:generic_fifo'),
    28             Uses('caba:generic_tlb',
    29               addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 
     25    uses = [ Uses('caba:base_module'),
     26        Uses('common:mapping_table'),
     27        Uses('caba:generic_fifo'),
     28        Uses('caba:generic_tlb',
     29              addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ',
    3030              parameter.Reference('addr_size'))),
    31             Uses('common:address_decoding_table',
     31        Uses('common:address_decoding_table',
    3232              input_t  = 'unsigned long',
    3333              output_t = 'bool'),
    34             Uses('common:address_decoding_table',
     34        Uses('common:address_decoding_table',
    3535              input_t  = 'unsigned long',
    3636              output_t = 'int'),
    3737    ],
    3838
    39         ports = [
    40               Port('caba:vci_initiator', 'p_vci_ini_ram'),
    41                   Port('caba:vci_target',    'p_vci_tgt_iox'),
    42               Port('caba:vci_initiator', 'p_vci_ini_iox'),
    43                   Port('caba:vci_target',    'p_vci_tgt_int'),
    44               Port('caba:vci_initiator', 'p_vci_ini_int'),
    45                   Port('caba:bit_in','p_irq', 32),
    46                   Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
    47                   Port('caba:clock_in', 'p_clk', auto = 'clock'),
     39    ports = [
     40        Port('caba:vci_initiator', 'p_vci_ini_ram'),
     41        Port('caba:vci_target',    'p_vci_tgt_iox'),
     42        Port('caba:vci_initiator', 'p_vci_ini_iox'),
     43        Port('caba:vci_target',    'p_vci_tgt_int'),
     44        Port('caba:vci_initiator', 'p_vci_ini_int'),
     45        Port('caba:bit_in','p_irq', 32),
     46        Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
     47        Port('caba:clock_in', 'p_clk', auto = 'clock'),
    4848    ],
    4949
    50     instance_parameters = [ 
     50    instance_parameters = [
    5151        parameter.Module('mt_ext', 'common:mapping_table'),
    5252        parameter.Module('mt_int', 'common:mapping_table'),
Note: See TracChangeset for help on using the changeset viewer.