Changeset 73 for trunk


Ignore:
Timestamp:
Aug 7, 2010, 12:42:20 AM (14 years ago)
Author:
bouyer
Message:

Fix several issues regarding management of the r_dcache_in_itlb/r_dcache_in_dtlb
arrays:

  • fix convertion from cache line number to physical address in various place
  • ICACHE_TLB_CC_INVAL: add ICACHE_TLB1_WRITE and ICACHE_TLB2_WRITE to the list of cases where r_icache_inval_tlb_rsp should be set to true. Otherwise, the fsm will go to ICACHE_TLB1_WRITE the ICACHE_TLB1_UPD once the ICACHE_TLB_CC_INVAL is done, and the TLB entry being dealt with will be entered, while it's not registered any more with the dcache.
  • add a check in ICACHE_IDLE and DCACHE_IDLE that a tlb hit] should imply the correspoding PTE entry being in the dcache, and the r_dcache_in_itlb/r_dcache_in_dtlb arrray. abort() if an inconsistency is found.
File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp

    r72 r73  
    10071007        else                                                                // MMU activated
    10081008        {
     1009            size_t c_way, c_set;
    10091010            m_cpt_ins_tlb_read++;
    10101011            icache_hit_t  = icache_tlb.cctranslate(ireq.addr, &tlb_ipaddr, &icache_pte_info,
     
    10141015            spc_ipaddr    = ((paddr_t)r_icache_ppn_save << PAGE_K_NBITS) | (paddr_t)(ireq.addr & PAGE_K_MASK);
    10151016            icache_cached = icache_pte_info.c;
     1017            if (icache_hit_t) {
     1018               if (!r_dcache.read(icache_tlb_nline << (uint32_log2(m_dcache_words) + 2), &icache_ins, &c_way, &c_set)) {
     1019                std::cout << "itlb PTE " << std::hex << icache_tlb_nline << " " << (icache_tlb_nline << (uint32_log2(m_dcache_words) + 2)) << " not in cache" << std::endl;
     1020                abort();
     1021              }
     1022              if (!r_dcache_in_itlb[m_dcache_sets*c_way+c_set]) {
     1023                std::cout << "itlb PTE " << std::hex << icache_tlb_nline << " "
     1024                    << (icache_tlb_nline << (uint32_log2(m_dcache_words) + 2)) <<
     1025                    " " << c_way << "," << c_set << " @" << &r_dcache_in_itlb[m_dcache_sets*c_way+c_set] << " not in_itlb" << std::endl;
     1026                abort();
     1027              }
     1028           }
    10161029        }
    10171030
     
    20312044        // invalidate cache
    20322045        if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ )  ||
    2033           /* ( r_icache_fsm_save == ICACHE_TLB1_WRITE )|| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||*/
     2046          ( r_icache_fsm_save == ICACHE_TLB1_WRITE )|| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
    20342047             ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) &&
    20352048            (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2) ) == r_dcache_itlb_inval_line.read()) )
     
    25562569            else                                                            // MMU activated
    25572570            {
     2571                size_t c_way, c_set;
    25582572                m_cpt_data_tlb_read++;
    25592573                dcache_hit_t  = dcache_tlb.cctranslate(dreq.addr, &tlb_dpaddr, &dcache_pte_info,
     
    25652579                                ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
    25662580                                 (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));   
     2581               if (dcache_hit_t) {
     2582                   if (!r_dcache.read(dcache_tlb_nline << (uint32_log2(m_dcache_words) + 2), &dcache_rdata, &c_way, &c_set)) {
     2583                    std::cout << "dtlb PTE " << std::hex << dcache_tlb_nline << " " << (dcache_tlb_nline << (uint32_log2(m_dcache_words) + 2)) << " not in cache" << std::endl;
     2584                    abort();
     2585                  }
     2586                  if (!r_dcache_in_dtlb[m_dcache_sets*c_way+c_set]) {
     2587                    std::cout << "dtlb PTE " << std::hex << dcache_tlb_nline <<
     2588                        " " << c_way << "," << c_set << " not in_dtlb" <<
     2589                        std::endl;
     2590                    abort();
     2591                  }
     2592              }
    25672593            }
    25682594
     
    35563582            if (dcache_tlb.update(r_dcache_pte_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
    35573583            {
    3558                 r_dcache.setinbit((paddr_t)victim_index*m_dcache_words*2, r_dcache_in_dtlb, false);
     3584                r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words) + 2), r_dcache_in_dtlb, false);
    35593585            }
    35603586            r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
     
    40134039            if (dcache_tlb.update(r_dcache_pte_update,r_dcache_ppn_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
    40144040            {
    4015                 r_dcache.setinbit((paddr_t)victim_index*m_dcache_words*2, r_dcache_in_dtlb, false);
     4041                r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words) + 2), r_dcache_in_dtlb, false);
    40164042            }
    40174043            r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
     
    40364062        if ( r_dcache_itlb_cleanup_req )
    40374063        {   
    4038             r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false);
     4064            r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read() << (uint32_log2(m_dcache_words) + 2)), r_dcache_in_itlb, false);
    40394065            r_dcache_itlb_cleanup_req = false;
    40404066        }
     
    40464072                if(dcache_tlb.checkcleanup(way, set, &victim_index))
    40474073                {
    4048                     r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false);
     4074                    /*
     4075                     * this is correct because checkcleanup returns true only
     4076                     * if none of the PTE entries of the line is global.
     4077                     */
     4078                    r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words) + 2), r_dcache_in_dtlb, false);
    40494079                }
    40504080            }
     
    41434173        if ( dcache_tlb.inval(r_dcache_wdata_save, &victim_index) )
    41444174        { 
    4145             r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false);
     4175            r_dcache.setinbit((paddr_t)(victim_index << (uint32_log2(m_dcache_words) + 2)), r_dcache_in_dtlb, false);
    41464176        }
    41474177        r_dtlb_translation_valid = false;
     
    49544984        if ( dreq.valid ) m_cost_data_miss_frz++;
    49554985
    4956         r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false);
     4986        r_dcache.setinbit((paddr_t)r_dcache_itlb_cleanup_line.read() << (uint32_log2(m_dcache_words) + 2), r_dcache_in_itlb, false);
    49574987        r_dcache_itlb_cleanup_req = false;
    49584988        r_dcache_fsm = DCACHE_IDLE;
Note: See TracChangeset for help on using the changeset viewer.