Changeset 92 for trunk


Ignore:
Timestamp:
Sep 14, 2010, 2:30:25 PM (14 years ago)
Author:
choichil
Message:

Platform with DMA VHDL

Location:
trunk/platforms/dsx/v1_1cluster_phys
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • trunk/platforms/dsx/v1_1cluster_phys/cluster.py

    r30 r92  
    4141            ('data', 0x10000000, 0x00100000),
    4242            ] )
    43         tty  = self.create_tty( addr = 0xc0200000, tty_count = proc_count )
     43        tty  = self.create_tty( addr = 0xc0200000, tty_count = 1 )
     44        xicu = self.create_xicu( addr = 0xd2200000, pti_count = 1,
     45                                                    hwi_count = 1,
     46                                                    wti_count = 4,
     47                                                    irq_count = 4)
     48        tty.irq[0] // xicu.hwi[0]
     49        for i in range(proc_count):
     50            self.cpu[i].irq[0] // xicu.irq[i]
    4451
    4552    def create_tty(self, addr, tty_count = 1):
     
    5158        return tty
    5259   
     60    def create_xicu(self, addr, pti_count, hwi_count, wti_count, irq_count):
     61        name = 'xicu'
     62        xicu = self.pf.create('caba:vci_xicu_vhdl', name, pti_count = pti_count,
     63                                                          hwi_count = hwi_count,
     64                                                          wti_count = wti_count,
     65                                                          irq_count = irq_count)
     66        self.ringp.to_target.new() // xicu.vci
     67        xicu.addSegment(name, address = addr, size = 0x1000, cacheable = False)
     68        return xicu
     69
    5370
    5471class ClusterV3(Cluster):
  • trunk/platforms/dsx/v1_1cluster_phys/dsx.conf

    r30 r92  
    1 soclib_type = "systemc_64"
     1soclib_type = "modelsim"
  • trunk/platforms/dsx/v1_1cluster_phys/v1_1cluster_phys.py

    r30 r92  
    55import soclib.component
    66import os
     7
     8import platform_handlers
    79
    810class Platform:
     
    9597    hard = Platform(ClusterV3, cpus, binaries = ["bin.soft"])
    9698    hard.simulator('.')
    97 #    hard.dts(os.path.basename(__file__)[:-2]+'dts')
    98 #    hard.dtb(os.path.basename(__file__)[:-2]+'dtb')
     99    hard.dts(os.path.basename(__file__)[:-2]+'dts')
     100    hard.dtb(os.path.basename(__file__)[:-2]+'dtb')
    99101
    100102if __name__ == '__main__':
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