Changeset 94


Ignore:
Timestamp:
Sep 14, 2010, 3:30:46 PM (14 years ago)
Author:
choichil
Message:

Deleting work directory

Location:
trunk/platforms/dsx/v1_1cluster_phys_dma
Files:
1 deleted
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/platforms/dsx/v1_1cluster_phys_dma/topcell_/topcell_.cpp

    r93 r94  
    55 ** your changes will be lost !
    66 **
    7  ** Generated by DSX on 2010-09-14 14:36:17.463123
     7 ** Generated by DSX on 2010-09-14 15:19:49.691098
    88 ** by choichil@hop
    99 ** MARKER_END
     
    12121212{
    12131213    // Segment configure;
    1214     mtc.add(proc_0_1_seg);
    12151214    mtc.add(ram_c_reset_seg);
    12161215    mtc.add(ram_c_excep_seg);
    12171216    mtc.add(ram_c_text_seg);
    12181217    mtc.add(ram_c_data_seg);
     1218    mtc.add(proc_0_3_seg);
    12191219    mtc.add(proc_0_0_seg);
     1220    mtc.add(proc_0_1_seg);
    12201221    mtc.add(proc_0_2_seg);
    1221     mtc.add(proc_0_3_seg);
     1222    mtp.add(xicu_seg);
    12221223    mtp.add(tty0_seg);
     1224    mtp.add(dma0_seg);
    12231225    mtp.add(ram_p_reset_seg);
    12241226    mtp.add(ram_p_excep_seg);
    12251227    mtp.add(ram_p_text_seg);
    12261228    mtp.add(ram_p_data_seg);
    1227     mtp.add(xicu_seg);
    1228     mtp.add(dma0_seg);
    12291229    mtx.add(ram_x_reset_seg);
    12301230    mtx.add(ram_x_excep_seg);
  • trunk/platforms/dsx/v1_1cluster_phys_dma/topcell_/topcell_.sd

    r93 r94  
    55# your changes will be lost !
    66#
    7 ## Generated by DSX on 2010-09-14 14:36:17.024238
     7## Generated by DSX on 2010-09-14 15:19:49.271489
    88## by choichil@hop
    99## MARKER_END
     
    2929                Uses('common:plain_file_loader', )],
    3030        header_files = ['topcell_.h'],
    31         ports = [Port("caba:bit_in", "p_resetn", addr_size = 64, cell_size = 4, clen_size = 1, pktid_size = 4, plen_size = 8, rerror_size = 1, rflag_size = 1, srcid_size = 14, trdid_size = 4, wrplen_size = 1),
    32                 Port("caba:clock_in", "p_clock", addr_size = 64, cell_size = 4, clen_size = 1, pktid_size = 4, plen_size = 8, rerror_size = 1, rflag_size = 1, srcid_size = 14, trdid_size = 4, wrplen_size = 1)],
     31        ports = [Port("caba:clock_in", "p_clock", addr_size = 64, cell_size = 4, clen_size = 1, pktid_size = 4, plen_size = 8, rerror_size = 1, rflag_size = 1, srcid_size = 14, trdid_size = 4, wrplen_size = 1),
     32                Port("caba:bit_in", "p_resetn", addr_size = 64, cell_size = 4, clen_size = 1, pktid_size = 4, plen_size = 8, rerror_size = 1, rflag_size = 1, srcid_size = 14, trdid_size = 4, wrplen_size = 1)],
    3333        implementation_files = ['topcell_.cpp']
    3434)
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