Changes between Version 15 and Version 16 of AtomicOperations

Timestamp:

Dec 7, 2015, 8:51:32 PM (8 years ago)

Author:

alain

Comment:

--

AtomicOperations

@@ -8 +8 @@
  * The '''LL/SC''' (Linked Load / Store Conditional) operation is implemented as two specific VCI transactions. As the LL/SC instructions are implemented in the MIPS32 instruction set, these instructions can be used by both the kernel code and by the application code to read a data at address X, test this data, and write the (possibly modified) data at the same address X, with the guaranty that no other access to this address was done between the read and write access.
  
- * The '''CAS''' (Compare and Swap) operation is implemented as a specific VCI transaction. As there is no CAS instruction in the MIPS32 instruction set, this operation cannot be used by the software. It is only used by some hardware components such as the L1 cache controller (to allow the MMU to update the DIRTY bit in the page tables), or by some DMA peripheral such as the vci_mwmr_dma component (to atomically access the lock protecting a shared communication channel).
+ * The '''CAS''' (Compare and Swap) operation is implemented as a specific VCI transaction. As there is no CAS instruction in the MIPS32 instruction set, this operation cannot be used by the software. It is only used by some hardware components such as the L1 cache controller (to allow the MMU to update the DIRTY bit in the page tables), or by some DMA peripheral such as the vci_mwmr_dma component (to atomically access the lock protecting a shared hardware/software communication channel).
 
 For both types of operation, the addresses a supposed to be aligned on 32 bits word boundaries, and the data are supposed to be 32 bits words.