Changes between Version 17 and Version 18 of AtomicOperations
- Timestamp:
- Dec 8, 2015, 1:31:00 PM (8 years ago)
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AtomicOperations
v17 v18 17 17 As the atomic access can be used to implement spin-locks, the address must be cacheable in order to benefit from the general coherence protocol, and avoid unnecessary transactions on the interconnection network. 18 18 19 === 2.1 General principle ===19 === 2.1 General Principle === 20 20 21 21 From a conceptual point of view, the atomicity is handled on the memory controller side, that is actually the L2 cache controller in the TSAR architecture. Each L2 cache controller contains a list of all pending LL/SC atomic operations in an associative ''reservation table'', that contains 32 entries. … … 98 98 == 3. CAS operation == 99 99 100 === 3.1 general principle ===100 === 3.1 General Principle === 101 101 102 102 The semantic of the '''CAS(X,D_old,D_new)''' VCI transaction (three arguments in the VCI command) is the following:
