Changes between Version 8 and Version 9 of AtomicOperations
- Timestamp:
- Oct 12, 2010, 3:58:10 PM (14 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
AtomicOperations
v8 v9 13 13 14 14 The TSAR memory sub-system supports the LL/SC mechanism. The LL & SC commands are defined in the VCI/OCP protocol, and the LL and SC instructions must be defined in the processor Instructon Set Architecture. This is natively the case for the MIPS32 & PowerPC processors. 15 On the direct network, the VCI CMD field can take four values : READ, WRITE, LINKED_LOAD (LL), and STORE_CONDITIONAL (SC). From a conceptual point of view, the atomicity his handled on the memory controller side (actually the memory cache controller s), as the memory controllers must maintain a list of all pending atomic operations in a ''reservation table'' :15 On the direct network, the VCI CMD field can take four values : READ, WRITE, LINKED_LOAD (LL), and STORE_CONDITIONAL (SC). From a conceptual point of view, the atomicity his handled on the memory controller side (actually the memory cache controller), as the memory controllers must maintain a list of all pending atomic operations in a ''reservation table'' : 16 16 17 * When a processor, identified by its SRCID, executes the LL(X) instruction to an address X, the memory controller registers an entry (SRCID, X) in the reservation table, and returns the memory value stored at address X in the VCI RDATA field. If there was another reservation for the same processor SRCID, but for another address X’, the previous reservation for X’ is lost (it means that the previous reservation can becancelled).17 * When a processor, identified by its SRCID, executes the LL(X) instruction to an address X, the memory controller registers an entry (SRCID, X) in the reservation table, and returns the memory value stored at address X in the VCI RDATA field. If there was another reservation for the same processor SRCID, but for another address X’, the previous reservation for X’ is lost (it means that the previous reservation is cancelled). 18 18 * When a processor, identified by its SRCID, executes the SC(X) instruction, there is two possibilities. If there is a valid reservation entry (SRCID, X) indicating that no other access to the X address has been received, the atomic operation is a success : the write is done, the memory cache controller returns a “true” value in he RDATA VCI field, and all entries in the reservation table for the X address are cancelled. If there is no valid reservation entry (SRCID, X) in the reservation table, the atomic operation is a failure : The write is not done, and the memory cache returns a “false” value in the RDATA field. 19 19 20 20 Clearly, in case of concurrent access, the winner is defined by the first SC instruction received by the memory controller. 21 21 22 As described below , this mechanism can be used to implement a spin-lock, using any memory address :22 As described below (using MIPS32 instruction set), this mechanism can be used to implement a spin-lock, using any memory address : 23 23 * The lock acquisition is done by an atomic LL/SC operation. 24 24 * The lock release is done by a simple WRITE instruction. … … 27 27 _itmask # enter critical section 28 28 # lock acquisition 29 loop LL Reg1 @ # Reg1 <= M[@] 30 BNE Reg1 loop # continue if lock not taken (Reg1 == 0) 31 SC 1 @ # M[@] <= 1 / Reg2 <= KO 32 BNE Reg2 loop # retry if not atomic (Reg2 != 0) 29 loop LL r1, 0(r4) # r1 <= M[r4] 30 BNEZ r1, loop # retry if lock already taken (r1 != 0) 31 ORI r1, r0, 1 # r1 <= 1 32 SC r1, 0(r4) # if atomic (M[r4] <= 1 / r1 <= 1) else (r1 <= 0) 33 BEQZ r1, loop # retry if not atomic (r1 == 0) 33 34 ... 34 35 # lock release 35 SW 0 @ # M[@] <= 0 36 ORI r1, r0, 0 # r1 <= 0 37 SW r1, 0(r4) # M[r4] <= 0 36 38 _itunmask # exit critical section 37 39 }}} … … 39 41 == 3. Cachable atomic operations == 40 42 41 In order to support cachable spin-locks and a better scalability, the memory cache controller, and the L1 cache controller must cooperate to implement the LL/SC mechanism. But the previoussemantic of the LL/SC mechanism has to be modified.43 In order to support cachable spin-locks and a better scalability, the memory cache controller, and the L1 cache controller must cooperate to implement the LL/SC mechanism. But the standard semantic of the LL/SC mechanism has to be modified. 42 44 43 45 Furthermore, the LL/SC mechanism is extended to support both 32 and 64 bits atomic accesses.
