Changes between Version 17 and Version 18 of CacheCoherence


Ignore:
Timestamp:
Dec 18, 2012, 11:15:50 AM (11 years ago)
Author:
joannou
Comment:

updated information about the use of the pktid and trdid fields in the direct network

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  • CacheCoherence

    v17 v18  
    5959the target is a memory cache controller, acting as a physical memory bank, or another VCI target peripheral. This target can be located in any cluster.
    6060
    61 The L1 cache controller can issue several simultaneous VCI transactions, that must be distinguished by the VCI TRDID field value. The VCI PKTID field is not used.
     61The L1 cache controller can issue several simultaneous VCI transactions, that must be distinguished by the VCI TRDID field value. The VCI PKTID field is also used to distinguish transaction types.
    6262
    63  * A '''READ''' transaction can be a single word request (in case of uncached access), or a burst, corresponding to a complete cache line (16 words). A READ burst transaction initiated by any DMA controller must respect the same 16 words cache line format. For all READ transaction, the VCI command packet contains one single VCI flit. The  VCI CMD field contains the VCI_READ code. The VCI PLEN field is used to define the burst length (number of bytes). A READ transaction has a type, encoded in the two LSB bits of the VCI PKTID field, and the the MSB bit must be 0.
     63 * A '''READ''' transaction can be a single word request (in case of uncached access), or a burst, corresponding to a complete cache line (16 words). A READ burst transaction initiated by any DMA controller must respect the same 16 words cache line format. For all READ transaction, the VCI command packet contains one single VCI flit. The  VCI CMD field contains the VCI_READ code. The VCI PLEN field is used to define the burst length (number of bytes). A READ transaction has a type, encoded in the three LSB bits of the VCI PKTID field (the MSB bit is ignored).
    6464
    65 || TRDID for Uncached Data        ||0...00||
    66 || TRDID for Cached Data          ||0...01||
    67 || TRDID for Uncached Instruction ||0...10||
    68 || TRDID for Cached Instruction   ||0...11||
     65|| PKTID for Uncached Data        ||X000||
     66|| PKTID for Cached Data          ||X001||
     67|| PKTID for Uncached Instruction ||X010||
     68|| PKTID for Cached Instruction   ||X011||
    6969
    70  * A '''WRITE''' transaction can be a single word request or a variable length burst request. In case of burst, the VCI command packet contains at most 8 VCI flits, with consecutive addresses. All words belong to the same half cache line, and the VCI BE field can have different values for each flit (including the zero value). The VCI response packet contains one VCI flit. A WRITE burst transaction initiated by any DMA controller must respect the same 8 aligned words constraint. The VCI CMD field contains the VCI_WRITE code. The MSB bit of the TRDID field must be 1. The other bits in the TRDID field are used to code the slot index in the write buffer. If the modified cache line is replicated in one or several other L1 caches, the memory cache must guaranty that all copies have been updated or invalidated before the WRITE transaction is acknowledged.
     70 * A '''WRITE''' transaction can be a single word request or a variable length burst request. In case of burst, the VCI command packet contains at most 8 VCI flits, with consecutive addresses. All words belong to the same half cache line, and the VCI BE field can have different values for each flit (including the zero value). The VCI response packet contains one VCI flit. A WRITE burst transaction initiated by any DMA controller must respect the same 8 aligned words constraint. The VCI CMD field contains the VCI_WRITE code. The PKTID field contains the TYPE_WRITE code (X100, MSB bit is ignored). The TRDID field is used to code the slot index in the write buffer. If the modified cache line is replicated in one or several other L1 caches, the memory cache must guaranty that all copies have been updated or invalidated before the WRITE transaction is acknowledged.
    7171
    72 || TRDID for Write burst       ||1 wbuf_index||
     72|| TRDID for Write burst       ||wbuf_index||
     73|| PKTID for Write burst       ||      X100||
    7374
    7475 * The TSAR architecture supports the '''LL/SC''' mechanism for atomic operations (see AtomicOperations).
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