Changes between Version 21 and Version 22 of CacheCoherence
- Timestamp:
- Nov 17, 2019, 8:34:24 PM (4 years ago)
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CacheCoherence
v21 v22 49 49 AS the L1 cache controller can issue several simultaneous direct transactions, that are distinguished by the VCI TRDID and PKTID values. 50 50 51 51 * A '''READ''' transaction can have four sub-types: It can be instruction or data, and it can be cacheable or uncacheable. In case of a burst transaction the burst must be included in a 16 words cache line. This constraint applies for both the L1 cache controllers and the I/O controllers with a DMA capability. For all READ transaction, the VCI command packet contains one single VCI flit, and the VCI response packet contains at most 16 flits. 52 52 53 53 * A '''WRITE''' transaction can be a single word request or a variable length burst request. In case of burst, all words must belong to the same cache line. and the BE field can have different values for each flit (including the zero value). The VCI command packet contains at most 16 flits and the VCI response packet contains one VCI flit. A WRITE burst transaction initiated by a DMA controller must respect the same constraint. 54 54 55 55 * A '''LL (Linked Load)''' transaction can target any single word contained in a memory cache. The response returns two 32 bits values that are the addressed data value, and a signature that has been allocated by the memory cache to this LL reservation. This means that the VCI command packet contains one flit and the VCI response packet contains two flits. 56 56 57 57 * A '''SC (Store Conditionnal)''' transaction can target any single word contained in a memory cache. The command must transport both the new data value and the signature obtained after the LL transaction. The response returns only a Boolean indicating failure/success for the SC transaction. This means that the VCI command packet contains two flits and the VCI response packet contains one flit. 58 58 59 59 * A '''CAS (Compare & Swap)''' transaction can target any single word contained in a memory cache. The command must transport both the old data value and the new data value. The response returns only a Boolean indicating failure/success for the CAS transaction. This means that the VCI command packet contains two flits and the VCI response packet contains one flit. 60 60 61 61 === 2.2 Coherence transactions === … … 66 66 Depending on the transaction type, a coherence transaction can require two or three packets. 67 67 68 68 * A '''CLEANUP''' transaction is initiated by the L1 cache when it must evict a line L for replacement, to signal to the owner L2 cache that it does not contains anymore a copy of L. This transaction requires two packet types: 69 69 1. The L1 cache send a ''cleanup(L)'' packet to the owner L2 cache. 70 70 1. The L2 cache returns a ''clack(L)'' packet to signal that its list of copies for L has been updated. 71 For the L1 cache, the '''CLEANUP'''transaction is completed when the L1 cache receive the ''clack'' packet.71 For the L1 cache, the CLEANUP transaction is completed when the L1 cache receive the ''clack'' packet. 72 72 73 73 * A '''MULTI_UPDATE''' transaction is a multi-cast transaction initiated by the L2 cache when it receives a WRITE request to a replicated cache line, and the number of copies does not exceeds the DHCCP threshold. This transaction requires two packet types: 74 74 1. The L2 send as many ''update(L,DATA)'' packets as the number of registered copies (but the writer). 75 75 1. Each L1 cache returns an ''update_ack(L)'' packet to the L2 cache to signal that the local copy has been updated. 76 76 For the L2 cache, the '''MULTICAST_UPDATE''' transaction is completed when the L2 cache received all expected ''update_ack'' packets. 77 77 78 78 * A '''MULTI_INVAL''' transaction is a multi-cast transaction, initiated by the L2 cache, when it must evict a given line L, and the number of copies does not exceeds the DHCCP threshold. To keep the inclusion property, all copies in L1 caches must be invalidated. This transaction requires three types of packets: 79 79 1. The L2 cache send as many ''inval(L)'' packets as the number of registered copies to all registered L1 caches. 80 80 1. Each L1 cache send a ''cleanup(L)'' packet to the L2 cache to signal that the local copy has been invalidated. 81 81 1. The L2 cache returns to each L1 cache a ''clack(L) packet to signal that its list of copies for L has been updated. 82 For the L2 cache, the '''MULTI_INVAL'''transaction is completed when the last ''cleanup''82 For the L2 cache, the MULTI_INVAL transaction is completed when the last ''cleanup'' 83 83 packet has been received. 84 84 85 85 * A '''BROADCAST_INVAL''' transaction is a broadcast transaction initiated by a L2 cache when a line L has been modified by a WRITE, or when the line L must be evicted for replacement, and the number of copies exceeds the DHCCP threshold. This transaction request three types of packets: 86 86 1. The L2 cache send to all L1 caches controller a ''bc_inval(L)'' broadcast packet. 87 87 1. Each L1 cache that contains a copy of L send a ''cleanup(L)'' packet to the L2 cache to signal that the local copy has been invalidated. 88 88 1. The L2 cache returns to each L1 cache that made a cleanup, a ''clack(L)'' packet to signal that its list of copies for L has been updated. 89 For the L2 cache, it simply decrement the counter of copies for each received ''cleanup'', and the '''MULTI_BROADCAST'''transaction is completed when the last ''cleanup'' packet has been received.89 For the L2 cache, it simply decrement the counter of copies for each received ''cleanup'', and the BROADCAST_INVAL transaction is completed when the last ''cleanup'' packet has been received. 90 90 91 91 As the '''MULTI_INVAL''' and '''BROADCAST_INVAL''' transactions require three packets, the coherence transactions require three separated physical networks
